Datasheet AD9240EB Datasheet (Analog Devices)

Page 1

REV. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Complete 14-Bit, 10 MSPS

Monolithic A/D Converter

AD9240

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998

FUNCTIONAL BLOCK DIAGRAM

VINA

CAPT CAPB

SENSE

OTR BIT 1

(MSB) BIT 14

(LSB)

VREF

DVSSAVSS

AD9240

SHA

DIGITAL CORRECTION LOGIC

OUTPUT BUFFERS

VINB

REFCOM

DVDDAVDD

CLK

MODE

SELECT

MDAC3

GAIN = 8

MDAC2

GAIN = 8

MDAC1

GAIN = 16

A/DA/DA/D

DRVDD

DRVSS

CML

BIAS

A/D

FEATURES Monolithic 14-Bit, 10 MSPS A/D Converter Low Power Dissipation: 285 mW Single +5 V Supply Integral Nonlinearity Error: 2.5 LSB Differential Nonlinearity Error: 0.6 LSB Input Referred Noise: 0.36 LSB Complete: On-Chip Sample-and-Hold Amplifier and

Voltage Reference Signal-to-Noise and Distortion Ratio: 77.5 dB Spurious-Free Dynamic Range: 90 dB Out-of-Range Indicator Straight Binary Output Data 44-Lead MQFP

PRODUCT HIGHLIGHTS

The AD9240 offers a complete single-chip sampling 14-bit, analog-to-digital conversion function in a 44-lead Metric Quad Flatpack.

Low Power and Single Supply

The AD9240 consumes only 280 mW on a single +5 V power supply.

Excellent DC Performance Over Temperature

The AD9240 provides no missing codes, and excellent temperature drift performance over the full operating temperature range.

Excellent AC Performance and Low Noise

The AD9240 provides nearly 13 ENOB performance and has an input referred noise of 0.36 LSB rms.

Flexible Analog Input Range

The versatile onboard sample-and-hold (SHA) can be configured for either single ended or differential inputs of varying input spans.

Flexible Digital Outputs

The digital outputs can be configured to interface with +3 V and +5 V CMOS logic families.

Excellent Undersampling Performance

The full power bandwidth and dynamic range of the AD9240 make it well suited for Direct-IF Down Conversion extending to 45 MHz.

PRODUCT DESCRIPTION

The AD9240 is a 10 MSPS, single supply, 14-bit analog-todigital converter (ADC). It combines a low cost, high speed CMOS process and a novel architecture to achieve the resolution and speed of existing hybrid implementations at a fraction of the power consumption and cost. It is a complete, monolithic ADC with an on-chip, high performance, low noise sample-and-hold amplifier and programmable voltage reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. The device uses a multistage differential pipelined architecture with digital output error correction logic to guarantee no missing codes over the full operating temperature range.

The input of the AD9240 is highly flexible, allowing for easy interfacing to imaging, communications, medical and dataacquisition systems. A truly differential input structure allows for both single-ended and differential input interfaces of varying input spans. The sample-and-hold amplifier (SHA) is equally suited for multiplexed systems that switch full-scale voltage levels in successive channels as well as sampling single-channel inputs at frequencies up to and beyond the Nyquist rate. The AD9240 also performs well in communication systems employing Direct-IF Down Conversion, since the SHA in the differential input mode can achieve excellent dynamic performance well beyond its specified Nyquist frequency of 5 MHz.

A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range (OTR) signal indicates an overflow condition which can be used with the most significant bit to determine low or high overflow.

Page 2

REV. A

–2–

AD9240–SPECIFICATIONS

DC SPECIFICATIONS

Parameter AD9240 Units

RESOLUTION 14 Bits min

MAX CONVERSION RATE 10 MHz min

INPUT REFERRED NOISE

VREF = 1 V 0.9 LSB rms typ VREF = 2.5 V 0.36 LSB rms typ

ACCURACY

Integral Nonlinearity (INL) ±2.5 LSB typ Differential Nonlinearity (DNL) ±0.6 LSB typ

±1.0 LSB max

INL

±2.5 LSB typ

DNL

±0.7 LSB typ

No Missing Codes 14 Bits Guaranteed

Zero Error (@ +25°C) 0.3 % FSR max Gain Error (@ +25°C)

1.5 % FSR max

Gain Error (@ +25°C)

0.75 % FSR max

TEMPERATURE DRIFT

Zero Error 3.0 ppm/°C typ

Gain Error

20.0 ppm/°C typ

Gain Error

5.0 ppm/°C typ

POWER SUPPLY REJECTION 0.1 % FSR max

ANALOG INPUT

Input Span (with VREF = 1.0 V) 2 V p-p min

Input Span (with VREF = 2.5 V) 5 V p-p max

Input (VINA or VINB) Range 0 V min

AVDD V max

Input Capacitance 16 pF typ

INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode) 1 Volts typ

Output Voltage Tolerance (1 V Mode) ±14 mV max

Output Voltage (2.5 V Mode) 2.5 Volts typ

Output Voltage Tolerance (2.5 V Mode) ±35 mV max

Load Regulation

5.0 mV max

REFERENCE INPUT RESISTANCE 5 kΩ typ

POWER SUPPLIES

Supply Voltages

AVDD +5 V (±5% AVDD

Operating)

DVDD +5 V (±5% DVDD

Operating)

DRVDD +5 V (±5% DRVDD

Operating)

Supply Current

IAVDD 50 mA max (46 mA typ) IDRVDD 1 mA max (0.1 mA typ) IDVDD 15 mA max (11 mA typ)

POWER CONSUMPTION 330 mW max (285 mW typ)

NOTES

VREF = 1 V.

Including internal reference.

Excluding internal reference.

Load regulation with 1 mA load current (in addition to that required by the AD9240).

Specification subject to change without notice.

(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f

SAMPLE

= 10 MSPS, R

BIAS

= 2 k⍀, VREF = 2.5 V, VINB = 2.5 V,

MIN

to T

MAX

unless otherwise noted)

Page 3

AC SPECIFICATIONS

Parameter AD9240 Units

SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D)

INPUT

= 500 kHz 75.0 dB min

77.5 dB typ

INPUT

= 1.0 MHz 77.5 dB typ

INPUT

= 5.0 MHz 75.0 dB typ

EFFECTIVE NUMBER OF BITS (ENOB)

INPUT

= 500 kHz 12.2 Bits min

12.6 Bits typ

INPUT

= 1.0 MHz 12.6 Bits typ

INPUT

= 5.0 MHz 12.2 Bits typ

SIGNAL-TO-NOISE RATIO (SNR)

INPUT

= 500 kHz 76.0 dB min

78.5 dB typ

INPUT

= 1.0 MHz 78.5 dB typ

INPUT

= 5.0 MHz 78.5 dB typ

TOTAL HARMONIC DISTORTION (THD)

INPUT

= 500 kHz –78.0 dB max

–85.0 dB typ

INPUT

= 1.0 MHz –85.0 dB typ

INPUT

= 5.0 MHz –77.0 dB typ

SPURIOUS FREE DYNAMIC RANGE

INPUT

= 500 kHz 90.0 dB typ

INPUT

= 1.0 MHz 90.0 dB typ

INPUT

= 5.0 MHz 80.0 dB typ

DYNAMIC PERFORMANCE

Full Power Bandwidth 70 MHz typ Small Signal Bandwidth 70 MHz typ Aperture Delay 1 ns typ Aperture Jitter 4 ps rms typ Acquisition to Full-Scale Step (0.0025%) 45 ns typ Overvoltage Recovery Time 167 ns typ

Specifications subject to change without notice.

DIGITAL SPECIFICATIONS

Parameters Symbol AD9240 Units

CLOCK INPUT

High Level Input Voltage V

+3.5 V min

Low Level Input Voltage V

+1.0 V max

High Level Input Current (V

= DVDD) I

±10 µA max

Low Level Input Current (V

= 0 V) I

±10 µA max

Input Capacitance C

5 pF typ

LOGIC OUTPUTS (with DRVDD = 5 V)

High Level Output Voltage (I

= 50 µA) V

+4.5 V min

High Level Output Voltage (I

= 0.5 mA) V

+2.4 V min

Low Level Output Voltage (I

= 1.6 mA) V

+0.4 V max

Low Level Output Voltage (I

= 50 µA) V

+0.1 V max

Output Capacitance C

OUT

5 pF typ

LOGIC OUTPUTS (with DRVDD = 3 V)

High Level Output Voltage (I

= 50 µA) V

+2.4 V min

Low Level Output Voltage (I

= 50 µA) V

+0.7 V max

Specifications subject to change without notice.

AD9240

REV. A

–3–

(AVDD = +5 V, DVDD= +5 V, DRVDD = +5 V, f

SAMPLE

= 10 MSPS, R

BIAS

= 2 k⍀, VREF = 2.5 V, AIN = –0.5 dBFS,

AC Coupled/Differential Input, T

MIN

to T

MAX

unless otherwise noted)

(AVDD = +5 V, DVDD = +5 V, T

MIN

to T

MAX

unless otherwise noted)

Page 4

AD9240

REV. A

–4–

ABSOLUTE MAXIMUM RATINGS*

With Respect

Parameter to Min Max Units

AVDD AVSS –0.3 +6.5 V DVDD DVSS –0.3 +6.5 V AVSS DVSS –0.3 +0.3 V AVDD DVDD –6.5 +6.5 V DRVDD DRVSS –0.3 +6.5 V DRVSS AVSS –0.3 +0.3 V REFCOM AVSS –0.3 +0.3 V CLK AVSS –0.3 AVDD

+ 0.3 V

Digital Outputs DRVSS –0.3 DRVDD

+ 0.3 V

VINA, VINB AVSS –0.3 AVDD

+ 0.3 V

VREF AVSS –0.3 AVDD

+ 0.3 V

SENSE AVSS –0.3 AVDD

+ 0.3 V

CAPB, CAPT AVSS –0.3 AVDD

+ 0.3 V

BIAS AVSS –0.3 AVDD

+ 0.3 V

Junction Temperature +150 °C Storage Temperature –65 +150 °C

Lead Temperature

(10 sec) +300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.

SWITCHING SPECIFICATIONS

Parameters Symbol AD9240 Units

Clock Period

100 ns min

CLOCK Pulsewidth High t

45 ns min

CLOCK Pulsewidth Low t

45 ns min

Output Delay t

8ns min 13 ns typ 19 ns max

Pipeline Delay (Latency) 3 Clock Cycles

NOTES

The clock period may be extended to 1 ms without degradation in specified performance @ +25 °C.

Specifications subject to change without notice.

MIN

to T

MAX

with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, R

BIAS

= 2 k⍀, CL = 20 pF)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9240 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

DATA 1

DATA

OUTPUT

INPUT

CLOCK

ANALOG

INPUT

Figure 1. Timing Diagram

THERMAL CHARACTERISTICS

Thermal Resistance 44-Lead MQFP

= 53.2°C/W

= 19°C/W

ORDERING GUIDE

Temperature Package Package

Model Range Description Option*

AD9240AS –40

C to +85oC 44-Lead MQFP S-44

AD9240EB Evaluation Board

*S = Metric Quad Flatpack.

PIN CONFIGURATION

3 4 5 6 7

1 2

10 11

8 9

40 39 3841

4344 36 35 3437

PIN 1 IDENTIFIER

TOP VIEW

(Not to Scale)

AD9240

121314 15 16 17 18 19 20 21 22

NC = NO CONNECT

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

DVSS AVSS DVDD AVDD

DRVSS

DRVDD

CLK

NC NC NC

(LSB) BIT 14

REFCOM VREF SENSE NC AVSS AVDD NC NC OTR BIT 1 (MSB) BIT 2

CML

CAPT

CAPB

BIAS

VINB

VINA

WARNING!

ESD SENSITIVE DEVICE

Page 5

AD9240

REV. A

–5–

OVERVOLTAGE RECOVERY TIME

Overvoltage recovery time is defined as that amount of time required for the ADC to achieve a specified accuracy after an overvoltage (50% greater than full-scale range), measured from the time the overvoltage signal reenters the converter’s range.

TEMPERATURE DRIFT

The temperature drift for zero error and gain error specifies the

maximum change from the initial (+25°C) value to the value at

MIN

or T

MAX

POWER SUPPLY REJECTION

The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit.

APERTURE JITTER

Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D.

APERTURE DELAY

Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion.

SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD) RATIO

S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.

EFFECTIVE NUMBER OF BITS (ENOB)

For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,

N = (SINAD – 1.76)/6.02

it is possible to get a measure of performance expressed as N, the effective number of bits.

Thus, an effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD.

TOTAL HARMONIC DISTORTION (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels.

SIGNAL-TO-NOISE RATIO (SNR)

SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.

SPURIOUS FREE DYNAMIC RANGE (SFDR)

SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.

TWO-TONE SFDR

The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Two-tone SFDR may be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale).

PIN FUNCTION DESCRIPTIONS

Pin Number Name Description

1 DVSS Digital Ground 2, 29 AVSS Analog Ground 3 DVDD +5 V Digital Supply 4, 28 AVDD +5 V Analog Supply 5 DRVSS Digital Output Driver Ground 6 DRVDD Digital Output Driver Supply 7 CLK Clock Input Pin 8–10 NC No Connect 11 BIT 14 Least Significant Data Bit (LSB) 12–23 BIT 13–BIT 2 Data Output Bits 24 BIT 1 Most Significant Data Bit (MSB) 25 OTR Out of Range 26, 27, 30 NC No Connect 31 SENSE Reference Select 32 VREF Reference I/O 33 REFCOM Reference Common 34, 38, 40, 43, 44 NC No Connect 35 BIAS* Power/Speed Programming 36 CAPB Noise Reduction Pin 37 CAPT Noise Reduction Pin 39 CML Common-Mode Level (Midsupply) 41 VINA Analog Input Pin (+) 42 VINB Analog Input Pin (–)

*See Speed/Power Programmability section.

DEFINITIONS OF SPECIFICATION

INTEGRAL NONLINEARITY (INL)

INL refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as “negative full scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.

DIFFERENTIAL NONLINEARITY (DNL, NO MISSING CODES)

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16384 codes, respectively, must be present over all operating ranges.

ZERO ERROR

The major carry transition should occur for an analog value 1/2 LSB below VINA = VINB. Zero error is defined as the deviation of the actual transition from that point.

GAIN ERROR

The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.

Page 6

AD9240

REV. A

–6–

Typical Differential AC Characterization Curves/Plots

(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f

SAMPLE

10 MSPS, R

BIAS

= 2 k⍀, TA = +25ⴗC, Differential Input)

INPUT FREQUENCY – MHz

0.1 1 20

55 50

SINAD – dB

–0.5dBFS

–6.0dBFS

–20.0dBFS

Figure 2. SINAD vs. Input Frequency (Input Span = 5 V, V

= 2.5 V)

INPUT FREQUENCY – MHz

0.1 1 20

55 50

SINAD – dB

–0.5dBFS

–6.0dBFS

–20.0dBFS

Figure 5. SINAD vs. Input Frequency (Input Span = 2 V, V

= 2.5 V)

SAMPLE RATE – MHz

–60

–65

0.1 1 10

–95

–100

–85

–90

–70

–80

–75

THD – dB

5V SPAN

2V SPAN

Figure 8. THD vs. Sample Rate (f

= 5.0 MHz, AIN = –0.5 dBFS,

= 2.5 V)

INPUT FREQUENCY – MHz

–40

–100

0.1 1 20

–90

–80

–70

–50

–60

THD – dB

–0.5dBFS

–6.0dBFS

–20.0dBFS

Figure 3. THD vs. Input Frequency (Input Span = 5 V, V

= 2.5 V)

INPUT FREQUENCY – MHz

–40

–100

0.1 1 20

–90

–80

–70

–50

–60

THD – dB

–20.0dBFS

–6.0dBFS

–0.5dBFS

Figure 6. THD vs. Input Frequency (Input Span = 2 V, V

= 2.5 V)

AIN – dB

SFDR – dBc AND dBFS

110

60 50 40

80 70

–60 –50 0

–40 –30 –20 –10

5V SPAN – dBc

2V SPAN – dBFS

5V SPAN – dBFS

100

2V SPAN – dBc

Figure 9. Single Tone SFDR (f

= 5.0 MHz, VCM = 2.5 V)

FREQUENCY – MHz

AMPLITUDE – dB

–70

–100

0 5.0

–10

–60

–80 –90

–40 –50

–20 –30

–110 –120

1st

9th

8th

2nd

3rd

7th

6th

4th

5th

Figure 4. Typical FFT, fIN = 1.0 MHz (Input Span = 5 V, V

= 2.5 V)

FREQUENCY – MHz

AMPLITUDE – dB

0 –15 –30 –45 –60 –75 –90

–105 –120 –135

–150

0 5.0

Figure 7. Typical FFT, fIN = 5.0 MHz (Input Span = 2 V, V

= 2.5 V)

INPUT POWER LEVEL (

) – dBFS

WORST CASE SPURIOUS – dBc AND dBFS

110

–40 –35

–30 –25 –20 –15 –10 –5

105

90 85

100

5V SPAN – dBFS

5V SPAN – dBc

2V SPAN – dBFS

2V SPAN – dBc

Figure 10. Dual Tone SFDR (f

= 0.95 MHz, f2 = 1.04 MHz,

= 2.5 V)

Page 7

AD9240

REV. A

–7–

Other Characterization Curves/Plots

(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f

SAMPLE

= 10 MSPS, R

BIAS

= 2 k⍀,

TA = +25ⴗC, Single-Ended Input)

CODE

INL – LSB

3.0

–0.5

–2.0

0 16863

2.5

0.0

–1.0 –1.5

2.0

1.0

1.5

0.5

–2.5 –3.0

Figure 11. Typical INL (Input Span = 5 V)

INPUT FREQUENCY – MHz

90 85

0.1 1 20

65 60

SINAD – dB

–0.5dBFS

–6.0dBFS

–20.0dBFS

Figure 14. SINAD vs. Input Frequency (Input Span = 2 V, V

= 2.5 V)

INPUT FREQUENCY – MHz

0.1 1 20

55 50

SINAD – dB

–0.5dBFS

–6.0dBFS

–20.0dBFS

Figure 17. SINAD vs. Input Frequency (Input Span = 5 V, V

= 2.5 V)

CODE

DNL – LSB

1.0

–0.4

–1.0

0 16383

0.8

–0.2

–0.6 –0.8

0.6

0.2

0.4

0.0

Figure 12. Typical DNL (Input Span = 5 V)

INPUT FREQUENCY – MHz

–40

–100

0.1 1 20

–90

–80

–70

–50

–60

THD – dB

–0.5dBFS

–6.0dBFS

–20.0dBFS

Figure 15. THD vs. Input Frequency (Input Span = 2 V, V

= 2.5 V)

INPUT FREQUENCY – MHz

–40

–100

0.1 1 20

–90

–80

–70

–50

–60

THD – dB

–0.5dBFS

–6.0dBFS

–20dBFS

Figure 18. THD vs. Input Frequency (Input Span = 5 V, V

= 2.5 V)

N–1

13484335

1414263

1482053

N N+1

HITS

CODE

Figure 13. “Grounded-Input” Histogram (Input Span = 5 V)

FREQUENCY – MHz

–10

1 10 100

–70 –80

–50

–60

–20

–40

–30

AMPLITUDE – dB

Figure 16. CMR vs. Input Frequency

(Input Span = 2 V, V

= 2.5 V)

TEMPERATURE – 8C

REF

ERROR – V

0.01

–0.004

–0.01

–60 –40 140–20 0 20 40 60 80 100 120

0.008

–0.002

–0.006 –0.008

0.002 0

0.006

0.004

Figure 19. Typical Voltage Reference Error vs. Temperature

Page 8

AD9240

REV. A

–8–

CLOCK FREQUENCY – MHz

SINAD – dB

12010

BIAS

= 10kV

BIAS

= 20kV

BIAS

= 200kV

BIAS

4kV

BIAS

2kV

Figure 21. SINAD vs. Clock Frequency for Varying R

BIAS

Values (VCM = 2.5 V, AIN = –0.5 dB, 5 V Span, fIN = f

CLK

/2)

CLOCK FREQUENCY – MHz

POWER – mW

400

100

2204 6 8 10 12 14 16 18

350

300

250

200

150

BIAS

= 1.7kV

BIAS

= 2kV

BIAS

= 2.5kV

BIAS

= 3.3kV

BIAS

= 5kV

BIAS

= 10kV

BIAS

= 100kV

Figure 22. Power Dissipation vs. Clock Frequency for Varying R

BIAS

Values

ANALOG INPUT AND REFERENCE OVERVIEW

Figure 23, a simplified model of the AD9240, highlights the relationship between the analog inputs, VINA, VINB, and the reference voltage, VREF. Like the voltage applied to the top of the resistor ladder in a flash A/D converter, the value VREF defines the maximum input voltage to the A/D core. The minimum input voltage to the A/D core is automatically defined to be –VREF.

CORE

VINA

VINB

+VREF

–VREF

A/D

CORE

AD9240

Figure 23. Equivalent Functional Input Circuit

INTRODUCTION

The AD9240 uses a four-stage pipeline architecture with a wideband input sample-and-hold amplifier (SHA) implemented on a cost-effective CMOS process. Each stage of the pipeline, excluding the last, consists of a low resolution flash A/D connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier amplifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash A/D.

The pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. This means that while the converter is capable of capturing a new input sample every clock cycle, it actually takes three clock cycles for the conversion to be fully processed and appear at the output. This latency is not a concern in most applications. The digital output, together with the out-of-range indicator (OTR), is latched into an output buffer to drive the output pins. The output drivers can be configured to interface with +5 V or +3.3 V logic families.

The AD9240 uses both edges of the clock in its internal timing circuitry (see Figure 1 and specification page for exact timing requirements). The A/D samples the analog input on the rising edge of the clock input. During the clock low time (between the falling edge and rising edge of the clock), the input SHA is in the sample mode; during the clock high time it is in the hold mode. System disturbances just prior to the rising edge of the clock and/or excessive clock jitter may cause the input SHA to acquire the wrong value, and should be minimized.

Speed/Power Programmability

The AD9240’s maximum conversion rate and associated power dissipation can be set using the part’s BIAS pin. A simplified diagram of the on-chip circuitry associated with the BIAS pin is shown in Figure 20.

AD9240

BIAS

FIXED

ADC

BIAS

Figure 20.

The value of R

BIAS

can be varied over a limited range to set the maximum sample rate and power dissipation of the AD9240. A typical plot of S/(N+D) @ f

= Nyquist vs. f

CLK

at varying

BIAS

is shown in Figure 21. A similar plot of power vs. f

CLK

at varying R

BIAS

is shown in Figure 22. These plots indicate

typical performance vs. R

BIAS

. Note that all other plots and specifications in this data sheet reflect performance at a fixed R

BIAS

= 2 kΩ.

Page 9

AD9240

REV. A

–9–

The addition of a differential input structure gives the user an additional level of flexibility that is not possible with traditional flash converters. The input stage allows the user to easily configure the inputs for either single-ended operation or differential operation. The A/D’s input structure allows the dc offset of the input signal to be varied independently of the input span of the converter. Specifically, the input to the A/D core is the difference of the voltages applied at the VINA and VINB input pins.

Therefore, the equation,

CORE

= VINA – VINB (1)

defines the output of the differential input stage and provides the input to the A/D core.

The voltage, V

CORE

, must satisfy the condition,

–VREF

≤

CORE

≤ VREF

(2)

where VREF is the voltage at the VREF pin.

While an infinite combination of VINA and VINB inputs exist that satisfy Equation 2, there is an additional limitation placed on the inputs by the power supply voltages of the AD9240. The power supplies bound the valid operating range for VINA and VINB. The condition,

AVSS – 0.3 V < VINA < AVDD + 0.3 V

(3)

AVSS – 0.3 V < VINB < AVDD + 0.3 V

where AVSS is nominally 0 V and AVDD is nominally +5 V, defines this requirement. Thus, the range of valid inputs for VINA and VINB is any combination that satisfies both Equations 2 and 3.

For additional information showing the relationship between VINA, VINB, VREF and the digital output of the AD9240, see Table IV.

Refer to Table I and Table II for a summary of the various analog input and reference configurations.

ANALOG INPUT OPERATION

Figure 24 shows the equivalent analog input of the AD9240 which consists of a differential sample-and-hold amplifier (SHA). The differential input structure of the SHA is highly flexible, allowing the devices to be easily configured for either a differential or single-ended input. The dc offset, or common-mode voltage, of the input(s) can be set to accommodate either singlesupply or dual supply systems. Note also that the analog inputs, VINA and VINB, are interchangeable with the exception that reversing the inputs to the VINA and VINB pins results in a polarity inversion.

VINA

VINB

PAR

–

PAR

Figure 24. Simplified Input Circuit

The input SHA of the AD9240 is optimized to meet the performance requirements for some of the most demanding communication, imaging, and data acquisition applications while maintaining low power dissipation. Figure 25 is a graph of the full-power bandwidth of the AD9240, typically 60 MHz. Note that the small signal bandwidth is the same as the full-power bandwidth. The settling time response to a full-scale stepped input is shown in Figure 26 and is typically less than 40 ns to

0.0025%. The low input referred noise of 0.36 LSB’s rms is displayed via a grounded histogram and is shown in Figure 13.

FREQUENCY – MHz

1 0

–7

1 10 100

–3 –4 –5 –6

–1 –2

–8 –9

–10

AMPLITUDE – dB

Figure 25. Full-Power Bandwidth

SETTLING TIME – ns

CODE

16000

12000

6010 20 30 40 50

8000

4000

70 80

Figure 26. Settling Time

The SHA’s optimum distortion performance for a differential or single-ended input is achieved under the following two conditions: (1) the common-mode voltage is centered around midsupply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input signal voltage span of the SHA is set at its lowest (i.e., 2 V input span). This is due to the sampling switches, Q

, being CMOS

switches whose R

resistance is very low but has some signal dependency which causes frequency dependent ac distortion while the SHA is in the track mode. The R

resistance of a CMOS switch is typically lowest at its midsupply but increases symmetrically as the input signal approaches either AVDD or AVSS. A lower input signal voltage span centered at midsupply reduces the degree of R

modulation.

Page 10

AD9240

REV. A

–10–

Figure 27 compares the AD9240’s THD vs. frequency performance for a 2 V input span with a common-mode voltage of 1 V and 2.5 V. Note the difference in the amount of degradation in THD performance as the input frequency increases. Similarly, note how the THD performance at lower frequencies becomes less sensitive to the common-mode voltage. As the input frequency approaches dc, the distortion will be dominated by static nonlinearities such as INL and DNL. It is important to note that these dc static nonlinearities are independent of any R

modulation.

–50

–80

0.1 1 20

–70

–60

–90

THD – dB

FREQUENCY – MHz

VCM = 1.0V

VCM = 2.5V

Figure 27. THD vs. Frequency for VCM = 2.5 V and 1.0 V (A

= –0.5 dB, Input Span = 2.0 V p-p)

Due to the high degree of symmetry within the SHA topology, a significant improvement in distortion performance for differential input signals with frequencies up to and beyond Nyquist can be realized. This inherent symmetry provides excellent cancellation of both common-mode distortion and noise. Also, the required input signal voltage span is reduced a factor of two which further reduces the degree of R

modulation and its

effects on distortion.

The optimum noise and dc linearity performance for either differential or single-ended inputs is achieved with the largest input signal voltage span (i.e., 5 V input span) and matched input impedance for VINA and VINB. Note that only a slight degradation in dc linearity performance exists between the 2 V and 5 V input span as specified in the AD9240 DC SPECIFICATIONS.

Referring to Figure 24, the differential SHA is implemented using a switched-capacitor topology. Hence, its input impedance and its subsequent effects on the input drive source should be understood to maximize the converter’s performance. The combination of the pin capacitance, C

, parasitic capacitance

PAR,

and the sampling capacitance, CS, is typically less than 16 pF. When the SHA goes into track mode, the input source must charge or discharge the voltage stored on C

to the new

input voltage. This action of charging and discharging C

which is approximately 4 pF, averaged over a period of time and for a given sampling frequency, F

, makes the input impedance ap-

pear to have a benign resistive component (i.e., 83 kΩ at F

= 10 MSPS). However, if this action is analyzed within a sampling period (i.e., T = <1/F

), the input impedance is dynamic due to the instantaneous requirement of charging and discharging C

. A series resistor inserted between the input drive source and the SHA input as shown in Figure 28 provides effective isolation.

10mF

VINA

VINB

SENSE

AD9240

0.1mF

RS*

VREF

REFCOM

*OPTIONAL SERIES RESISTOR

Figure 28. Series Resistor Isolates Switched-Capacitor SHA Input from Op Amp. Matching Resistors Improve SNR Performance

The optimum size of this resistor is dependent on several factors, which include the AD9240 sampling rate, the selected op amp and the particular application. In most applications, a

30 Ω to 50 Ω resistor is sufficient; however, some applications

may require a larger resistor value to reduce the noise bandwidth or possibly limit the fault current in an overvoltage condition. Other applications may require a larger resistor value as part of an antialiasing filter. In any case, since the THD performance is dependent on the series resistance and the above mentioned factors, optimizing this resistor value for a given application is encouraged.

A slight improvement in SNR performance and dc offset performance is achieved by matching the input resistance connected to VINA and VINB. The degree of improvement is dependent on the resistor value and the sampling rate. For series

resistor values greater than 100 Ω, the use of a matching resis-

tor is encouraged.

The noise or small-signal bandwidth of the AD9240 is the same as its full-power bandwidth. For noise sensitive applications, the excessive bandwidth may be detrimental and the addition of a series resistor and/or shunt capacitor can help limit the wideband noise at the A/D’s input by forming a low-pass filter. Note, however, that the combination of this series resistance with the equivalent input capacitance of the AD9240 should be evaluated for those time-domain applications that are sensitive to the input signal’s absolute settling time. In applications where harmonic distortion is not a primary concern, the series resistance may be selected in combination with the SHA’s nominal 16 pF of input capacitance to set the filter’s 3 dB cutoff frequency.

A better method of reducing the noise bandwidth, while possibly establishing a real pole for an antialiasing filter, is to add some additional shunt capacitance between the input (i.e., VINA and/or VINB) and analog ground. Since this additional shunt capacitance combines with the equivalent input capacitance of the AD9240, a lower series resistance can be selected to establish the filter’s cutoff frequency while not degrading the distortion performance of the device. The shunt capacitance also acts as a charge reservoir, sinking or sourcing the additional charge required by the hold capacitor, C

, further reducing

current transients seen at the op amp’s output.

The effect of this increased capacitive load on the op amp driving the AD9240 should be evaluated. To optimize performance when noise is the primary consideration, increase the shunt capacitance as much as the transient response of the input signal will allow. Increasing the capacitance too much may adversely affect the op amp’s settling time, frequency response and distortion performance.

Page 11

AD9240

REV. A

–11–

Table I. Analog Input Configuration Summary

Input Input Input Range (V) Figure Connection Coupling Span (V) VINA

VINB

# Comments

Single-Ended DC 2 0 to 2 1 32, 33 Best for stepped input response applications, suboptimum THD

and noise performance, requires ±5 V op amp.

2 × VREF 0 to VREF 32, 33 Same as above but with improved noise performance due to

2 × VREF increase in dynamic range. Headroom/settling time requirements

of ±5 V op amp should be evaluated.

5 0 to 5 2.5 32, 33 Optimum noise performance, excellent THD performance. Requires

op amp with VCC > +5 V due to insufficient headroom @ 5 V.

2 × VREF 2.5 – VREF 2.5 39 Optimum THD performance with VREF = 1, noise performance

to improves while THD performance degrades as VREF increases

2.5 + VREF to 2.5 V. Single supply operation (i.e., +5 V) for many op amps.

Single-Ended AC 2 or 0 to 1 or 1 or VREF 34 Suboptimum ac performance due to input common-mode level

2 × VREF 0 to 2 × VREF not biased at optimum midsupply level (i.e., 2.5 V).

5 0 to 5 2.5 34 Optimum noise performance, excellent THD performance. 2 × VREF 2.5 – VREF 2.5 35 Flexible input range, Optimum THD performance with VREF = 1.

to Noise performance improves while THD performance degrades as

2.5 + VREF VREF increases to 2.5 V.

Differential AC or 2 2 to 3 3 to 2 29–31 Optimum full-scale THD and SFDR performance well beyond the

DC A/Ds Nyquist frequency.

2 × VREF 2.5 – VREF/2 2.5 + VREF/2 29–31 Same as 2 V to 3 V input range with the exception that full-scale

to to THD and SFDR performance can be traded off for better noise

2.5 + VREF/2 2.5 – VREF/2 performance.

5 1.25 to 3.75 3.75 to 1.25 29–31 Widest dynamic range (i.e., ENOBs) due to optimum noise

performance.

VINA and VINB can be interchanged if signal inversion is required.

Table II. Reference Configuration Summary

Reference Input Span (VINA–VINB) Operating Mode (V p-p) Required VREF (V) Connect To

INTERNAL 2 1 SENSE VREF INTERNAL 5 2.5 SENSE REFCOM

INTERNAL 2 ≤ SPAN ≤ 5 AND 1 ≤ VREF ≤ 2.5 AND R1 VREF AND SENSE

SPAN = 2 × VREF VREF = (1 + R1/R2) R2 SENSE AND REFCOM

EXTERNAL 2 ≤ SPAN ≤ 51 ≤ VREF ≤ 2.5 SENSE AVDD

(NONDYNAMIC) VREF EXT. REF.

EXTERNAL 2 ≤ SPAN ≤ 5 CAPT and CAPB SENSE AVDD

(DYNAMIC) Externally Driven VREF REFCOM

EXT. REF. 1 CAPT EXT. REF. 2 CAPB

Page 12

AD9240

REV. A

–12–

REFERENCE OPERATION

The AD9240 contains an onboard bandgap reference that provides a pin-strappable option to generate either a 1 V or 2.5 V output. With the addition of two external resistors, the user can generate reference voltages other than 1 V and 2.5 V. Another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance. See Table II for a summary of the pin-strapping options for the AD9240 reference configurations.

Figure 29 shows a simplified model of the internal voltage reference of the AD9240. A pin-strappable reference amplifier buffers a 1 V fixed reference. The output from the reference amplifier, A1, appears on the VREF pin. The voltage on the VREF pin determines the full-scale input span of the A/D. This input span equals,

Full-Scale Input Span = 2

VREF

The voltage appearing at the VREF pin as well as the state of the internal reference amplifier, A1, are determined by the voltage appearing at the SENSE pin. The logic circuitry contains two comparators which monitor the voltage at the SENSE pin. The comparator with the lowest set point (approximately 0.3 V) controls the position of the switch within the feedback path of A1. If the SENSE pin is tied to REFCOM, the switch is connected to the internal resistor network thus providing a VREF of

2.5 V. If the SENSE pin is tied to the VREF pin via a short or resistor, the switch is connected to the SENSE pin. A short will provide a VREF of 1.0 V while an external resistor network will provide an alternative VREF between 1.0 V and 2.5 V.

The second comparator controls internal circuitry that will disable the reference amplifier if the SENSE pin is tied AVDD. Disabling the reference amplifier allows the VREF pin to be driven by an external voltage reference.

5kV

LOGIC

DISABLE

7.5kV

LOGIC

5kV

DISABLE

A/D

AD9240

CAPT

CAPB

VREF

SENSE

REFCOM

Figure 29. Equivalent Reference Circuit

The actual reference voltages used by the internal circuitry of the AD9240 appear on the CAPT and CAPB pins. For proper operation when using the internal or an external reference, it is necessary to add a capacitor network to decouple these pins. Figure 30 shows the recommended decoupling network. This capacitive network performs the following three functions: (1) along with the reference amplifier, A2, it provides a low source impedance over a large frequency range to drive the A/D internal circuitry, (2) it provides the necessary compensation for A2 and (3) it bandlimits the noise contribution from the reference. The turn-on time of the reference voltage appearing between CAPT and CAPB is approximately 15 ms and should be evaluated in any power-down mode of operation.

0.1mF

10mF

0.1mF

CAPT

CAPB

AD9240

Figure 30. Recommended CAPT/CAPB Decoupling Network

The A/D’s input span may be varied dynamically by changing the differential reference voltage appearing across CAPT and CAPB symmetrically around 2.5 V (i.e., midsupply). To change the reference at speeds beyond the capabilities of A2, it will be necessary to drive CAPT and CAPB with two high speed, low noise amplifiers. In this case, both internal amplifiers (i.e., A1 and A2) must be disabled by connecting SENSE to AVDD and VREF to REFCOM and the capacitive decoupling network removed. The external voltages applied to CAPT and CAPB must be 2.5 V + Input Span/4 and 2.5 V – Input Span/4, respectively, where the input span can be varied between 2 V and 5 V. Note that those samples within the pipeline A/D during any reference transition will be corrupted and should be discarded.

Page 13

AD9240

REV. A

–13–

DRIVING THE ANALOG INPUTS

INTRODUCTION

The AD9240 has a highly flexible input structure allowing it to interface with single-ended or differential input interface circuitry. The applications shown in sections Driving the Analog Inputs and Reference Configurations, along with the information presented in the Input and Reference Overview section of this data sheet, give examples of both single-ended and differential operation. Refer to Tables I and II for a list of the different possible input and reference configurations and their associated figures in the data sheet.

The optimum mode of operation, analog input range and associated interface circuitry will be determined by the particular applications performance requirements as well as power supply options. For example, a dc coupled single-ended input may be appropriate for many data acquisition and imaging applications. Also, many communication applications which require a dc coupled input for proper demodulation can take advantage of the excellent single-ended distortion performance of the AD9240. The input span should be configured such that the system’s performance objectives and the headroom requirements of the driving op amp are simultaneously met.

Alternatively, the differential mode of operation provides the best THD and SFDR performance over a wide frequency range. A transformer coupled differential input should be considered for the most demanding spectral-based applications which allow ac coupling (e.g., Direct IF to Digital Conversion). The dccoupled differential mode of operation also provides an enhancement in distortion and noise performance at higher input spans. Furthermore, it allows the AD9240 to be configured for a 5 V

span using op amps specified for +5 V or ±5 V operation.

Single-ended operation requires that VINA be ac or dc coupled to the input signal source while VINB of the AD9240 be biased to the appropriate voltage corresponding to a midscale code transition. Note that signal inversion may be easily accomplished by transposing VINA and VINB.

Differential operation requires that VINA and VINB be simultaneously driven with two equal signals that are in and out of phase versions of the input signal. Differential operation of the AD9240 offers the following benefits: (1) Signal swings are smaller and therefore linearity requirements placed on the input signal source may be easier to achieve, (2) Signal swings are smaller and therefore may allow the use of op amps which may otherwise have been constrained by headroom limitations, (3) Differential operation minimizes even-order harmonic products and (4) Differential operation offers noise immunity based on the device’s common-mode rejection as shown in Figure 16.

As is typical of most CMOS devices, exceeding the supply limits will turn on internal parasitic diodes resulting in transient currents within the device. Figure 31 shows a simple means of clamping a dc coupled input with the addition of two series resistors and two diodes. Note that a larger series resistor could be used to limit the fault current through D1 and D2 but should be evaluated since it can cause a degradation in overall performance.

AVDD

30V

D2 1N4148

D1 1N4148

20V

AD9240

Figure 31. Simple Clamping Circuit

DIFFERENTIAL MODE OF OPERATION

Since not all applications have a signal preconditioned for differential operation, there is often a need to perform a single-ended-to-differential conversion. A single-ended-todifferential conversion can be realized with an RF transformer or a dual op amp differential driver. The optimum method depends on whether the application requires the input signal to be ac or dc coupled to AD9240.

AC Coupling via an RF Transformer

An RF transformer with a center tap can be used to generate differential inputs for the AD9240. It provides all of the benefits of operating the ADC in the differential mode while contributing no additional noise and minimal distortion. As a result, an RF transformer is recommended in high frequency applications, especially undersampling, in which the performance of a dual op amp differential driver may not be adequate. An RF transformer has the added benefit of providing electrical isolation between the signal source and the ADC. However, since the lower cutoff frequency of most RF transformers is nominally a few 100 kHz, a dual op amp differential driver may be more suitable in ac-coupling applications, where the spectral content of the input signal falls below the cutoff frequency of a suitable RF transformer.

Figure 32 is a suggested transformer circuit using a MiniCircuits RF transformer, model #T4-6T, which has an impedance ratio of four (turns ratio of 2). The 1:4 impedance ratio

requires the 200 Ω secondary termination for optimum power

transfer and VSWR. The centertap of the transformer provides a convenient means of level-shifting the input signal to a desired common-mode voltage. Optimum performance can be realized when the centertap is tied to CML of the AD9240 which is the common-mode bias level of the internal SHA.

VINA

CML

VINB

AD9240

0.1mF

200V

MINI-CIRCUITS

T4-6T

50V

Figure 32. Transformer Coupled Input

Transformers with other turns ratios may also be selected to optimize the performance of a given application. For example, a given input signal source or amplifier may realize an improvement in distortion performance at reduced output power levels and signal swings. Hence, selecting a transformer with a higher impedance ratio (i.e., Mini-Circuits T16-6T with a 1:16 impedance ratio) effectively “steps up” the signal level, further reducing the driving requirements of the signal source.

Page 14

AD9240

REV. A

–14–

AC Coupling with Op Amps

As previously stated, a dual op amp differential driver may be more suitable in applications in which the spectral content of the input signal falls below the cutoff frequency of a suitable RF transformer and/or the cost of an RF transformer and a low distortion driver for the transformer is prohibitive.

The ac-coupled differential driver shown in Figure 33 is best

suited for ±5 V systems in which the input signal is ground

referenced. In this case, V

will be 0 V. This driver circuit can achieve performance similar to an RF transformer over the AD9240’s full Nyquist bandwidth of 5 MHz. However, unlike the RF transformer, the lower cutoff frequency can be arbitrarily set low by adjusting the RC time constant formed by C

and

/2. CN, in combination with RS, can be used to limit the con-

tribution of op amp-generated noise at higher frequencies. Low

cost, high performance dual op amps operating from ±5 V such

as the AD8056 and AD8058, are excellent choices for this application and are capable of maintaining 78 dB SNR and 83 dB THD at 1 MHz (5 V span). An optional resistor R

can be added to U1B to achieve a similar group delay as U1A, potentially improving overall distortion performance. A resistor divider network formed by R

centers the inputs of the AD9240 around

AVDD/2 to achieve its optimum distortion performance.

SOURCE

5kV

0.1mF

5kV

0.1mF

U1A

U1B

5kV

Figure 33. AC Coupling of Op Amps

DC Coupling with Op Amps

The dc-coupled differential driver in Figure 34 is best suited for

±5 V systems in which the input signal is ground referenced and

optimum distortion performance is desired. This driver circuit provides the ability to level-shift the input signal to within the common-mode range of the AD9240. The two op amps are configured as matched differential amps with the input signal applied to opposing inputs to provide the differential output. The common-mode offset voltage is applied to the noninverting resistor network, which provides the proper level shifting. The AD9631 is given as the amplifier of choice in this application due to its superior distortion performance for relatively large output swings and wide bandwidth. If cost or space are factors, the AD8056 dual op amp will save on both, but at the cost of slightly increased distortion with large signal levels. Figure 34 also illustrates the use of protection diodes, which are used to protect the AD9240 from any fault condition in which the op amps outputs inadvertently go above V

or below GND.

VINA

VINB

CML

AD9240

390V

CML

–VIN

CML

+VIN

AVDD

390V

220V

390V

AVDD

390V

220V

390V

AD9631

2.5kV

33V

100V

0.1mF

1mF

0.1mF

OP113

33V

390V

0.1mF

Figure 34. Differential Driver with Level-Shifting

Single Supply DC-Coupled Driver

The circuit of Figure 33 can be easily modified for a single supply, dc-coupled application. This is done by biasing V

to AVDD/2, the normal common-mode level in a single supply system. Since the outputs of the op amps are centered at AVDD/2, the ac coupling network of C

and RB can be removed. With this done, the differential driving pair can now be run from a single supply.

SINGLE-ENDED MODE OF OPERATION

The AD9240 can be configured for single-ended operation using dc or ac coupling. In either case, the input of the A/D must be driven from an operational amplifier that will not degrade the A/D’s performance. Because the A/D operates from a single supply, it will be necessary to level-shift ground-based bipolar signals to comply with its input requirements. Both dc and ac coupling provide this necessary function, but each method results in different interface issues which may influence the system design and performance.

DC COUPLING AND INTERFACE ISSUES

Many applications require the analog input signal to be dc coupled to the AD9240. An operational amplifier can be configured to rescale and level-shift the input signal so it is compatible with the selected input range of the A/D. The input range to the A/D should be selected on the basis of system performance objectives as well as the analog power supply availability since this will place certain constraints on the op amp selection.

Many of the new high performance op amps are specified for

only ±5 V operation and have limited input/output swing capa-

bilities. Hence, the selected input range of the AD9240 should be sensitive to the headroom requirements of the particular op amp to prevent clipping of the signal. Also, since the output of a dual supply amplifier can swing below –0.3 V, clamping its output should be considered in some applications.

In some applications, it may be advantageous to use an op amp specified for single supply +5 V operation since it will inherently limit its output swing to within the power supply rails. Rail-torail output amplifiers such as the AD8041 allow the AD9240 to be configured with larger input spans which improves the noise performance.

Page 15

AD9240

REV. A

–15–

If the application requires the largest single-ended input range (i.e., 0 V to 5 V) of the AD9240, the op amp will require larger supplies to drive it. Various high speed amplifiers in the Op Amp Selection Guide of this data sheet can be selected to accommodate a wide range of supply options. Once again, clamping the output of the amplifier should be considered for these applications. Alternatively, a single-ended to differential op amp driver circuit using the AD8042 could be used to achieve the 5 V input span while operating from a single +5 V supply as discussed in the previous section.

Two dc coupled op amp circuits using a noninverting and inverting topology are discussed below. Although not shown, the noninverting and inverting topologies can be easily configured as part of an antialiasing filter by using a Sallen-Key or Multiple-Feedback topology, respectively. An additional R-C network can be inserted between the op amp’s output and the AD9240 input to provide a real pole.

Simple Op Amp Buffer

In the simplest case, the input signal to the AD9240 will already be biased at levels in accordance with the selected input range. It is simply necessary to provide an adequately low source impedance for the VINA and VINB analog input pins of the A/D. Figure 35 shows the recommended configuration for a singleended drive using an op amp. In this case, the op amp is shown in a noninverting unity gain configuration driving the VINA pin. The internal reference drives the VINB pin. Note that the addi-

tion of a small series resistor of 30 Ω to 50 Ω connected to VINA

and VINB will be beneficial in nearly all cases. Refer to the Analog Input Operation section for a discussion on resistor selection. Figure 35 shows the proper connection for a 0 V to 5 V input range. Alternative single ended input ranges of 0 V to

2 × VREF can also be realized with the proper configuration of

VREF (refer to the section, Using the Internal Reference).

10mF

VINA

VINB

SENSE

AD9240

0.1mF

–V

VREF

5V 0V

2.5V

Figure 35. Single-Ended AD9240 Op Amp Drive Circuit

Op Amp with DC Level-Shifting

Figure 36 shows a dc-coupled level-shifting circuit employing an op amp, A1, to sum the input signal with the desired dc offset. Configuring the op amp in the inverting mode with the given resistor values results in an ac signal gain of –1. If the signal inversion is undesirable, interchange the VINA and VINB connections to reestablish the original signal polarity. The dc voltage at VREF sets the common-mode voltage of the AD9240. For example, when VREF = 2.5 V, the output level from the op amp will also be centered around 2.5 V. The use of ratio matched, thin-film resistor networks will minimize gain and offset errors. An optional pull-up resistor, R

, may also be used to reduce the

output load on VREF to ±1 mA.

+VREF –VREF

VINA

VINB

AD9240

0.1mF

500V*

0.1mF

500V*

VREF

500V*

RP**

AVDD

*OPTIONAL RESISTOR NETWORK-OHMTEK ORNA500D **OPTIONAL PULL-UP RESISTOR WHEN USING INTERNAL REFERENCE

Figure 36. Single-Ended Input With DC-Coupled Level-Shift

AC COUPLING AND INTERFACE ISSUES

For applications where ac coupling is appropriate, the op amp’s output can be easily level-shifted to the common-mode voltage, V

, of the AD9240 via a coupling capacitor. This has the advantage of allowing the op amps common-mode level to be symmetrically biased to its midsupply level (i.e., (V

+ VEE)/

2). Op amps that operate symmetrically with respect to their power supplies typically provide the best ac performance as well as greatest input/output span. Hence, various high speed/ performance amplifiers that are restricted to +5 V/–5 V operation and/or specified for +5 V single-supply operation can be easily configured for the 5 V or 2 V input span of the AD9240, respectively. The best ac distortion performance is achieved when the A/D is configured for a 2 V input span and commonmode voltage of 2.5 V. Note that differential transformer coupling, which is another form of ac coupling, should be considered for optimum ac performance.

Simple AC Interface

Figure 37 shows a typical example of an ac-coupled, singleended configuration. The bias voltage shifts the bipolar, ground-referenced input signal to approximately VREF. The value for C1 and C2

will depend on the size of the resistor, R.

The capacitors, C1 and C2, are typically a 0.1 µF ceramic and 10 µF tantalum capacitor in parallel to achieve a low cutoff

frequency while maintaining a low impedance over a wide frequency range. The combination of the capacitor and the resistor form a high-pass filter with a high-pass –3 dB frequency determined by the equation,

–3 dB

= 1/(2 × π × R × (C1 + C2))

VINA

VINB

SENSE

AD9240

+5V

–5V

VREF

+VREF

–VREF

Figure 37. AC-Coupled Input

The low impedance VREF voltage source biases both the VINB input and provides the bias voltage for the VINA input. Figure 37 shows the VREF configured for 2.5 V. Thus the input range of the A/D is 0 V to 5 V. Other input ranges could be selected by changing VREF but the A/D’s distortion performance will

Page 16

AD9240

REV. A

–16–

degrade slightly as the input common-mode voltage deviates from its optimum level of 2.5 V.

Alternative AC Interface

Figure 38 shows a flexible ac-coupled circuit which can be configured for different input spans. Since the common-mode voltage of VINA and VINB are biased to midsupply independent of VREF, VREF can be pin-strapped or reconfigured to achieve input spans between 2 V and 5 V p-p. The AD9240’s CMRR along with the symmetrical coupling R-C networks will reject both power supply variations and noise. The resistors, R, establish the common-mode voltage. They may have a high value

(e.g., 5 kΩ) to minimize power consumption and establish a low

cutoff frequency. The capacitors, C1

and C2, are typically a

0.1 µF ceramic and 10 µF tantalum capacitor in parallel to

achieve a low cutoff frequency while maintaining a low impedance over a wide frequency range. R

isolates the buffer amplifier from the A/D input. The optimum performance is achieved when VINA and VINB are driven via symmetrical networks. The high pass f

–3 dB

point can be approximated by the equation,

–3 dB

= 1/(2 × π × R/2 × (C1 + C2))

VINA

VINB

AD9240

+5V

–5V

+5V

Figure 38. AC-Coupled Input-Flexible Input Span,

= 2.5 V

OP AMP SELECTION GUIDE

Op amp selection for the AD9240 is highly dependent on a particular application. In general, the performance requirements of any given application can be characterized by either time domain or frequency domain parameters. In either case, one should carefully select an op amp that preserves the performance of the A/D. This task becomes challenging when one considers the AD9240’s high performance capabilities coupled with other external system level requirements such as power consumption and cost.

The ability to select the optimal op amp may be further complicated by limited power supply availability and/or limited acceptable supplies for a desired op amp. Newer, high performance op amps typically have input and output range limitations in accordance with their lower supply voltages. As a result, some op amps will be more appropriate in systems where ac-coupling is allowable. When dc-coupling is required, op amps without headroom constraints such as rail-to-rail op amps or ones where larger supplies can be used should be considered. The following section describes some op amps currently available from Analog Devices. The system designer is always encouraged to contact the factory or local sales office to be updated on Analog Devices’ latest amplifier product offerings. Highlights of the areas where the op amps excel and where they may limit the performance of the AD9240 are also included.

AD9631: 220 MHz Unity GBW, 16 ns Settling to 0.01%,

±5 V Supplies

Best Applications: Best AC Specs, Low Noise, AC-Coupled Limits: Usable Input/Output Range, Power Consumption

AD8047: 130 MHz Unity GBW, 30 ns Settling to 0.01%,

±5 V Supplies

Best Applications: Good AC Specs, Low Noise, AC-Coupled Limits: THD > 5 MHz, Usable Input Range

AD8042: Dual AD8041

Best Applications: Differential and/or Low Impedance Input Drivers Limits: Noise with 2 V Input Range

REFERENCE CONFIGURATIONS

For the purpose of simplicity, the figures associated with this section on internal and external reference operation do not show recommended matching series resistors for VINA and VINB. Please refer to section Driving the Analog Inputs, Introduction, for a discussion of this topic. The figures do not show the decoupling network associated with the CAPT and CAPB pins. Please refer to the Reference Operation section for a discussion of the internal reference circuitry and the recommended decoupling network shown in Figure 30.

USING THE INTERNAL REFERENCE Single-Ended Input with 0 to 2 ⴛ VREF Range

Figure 39 shows how to connect the AD9240 for a 0 V to 2 V or 0 V to 5 V input range via pin strapping the SENSE pin. An

intermediate input range of 0 to 2 × VREF can be established

using the resistor programmable configuration in Figure 41 and connecting VREF to VINB.

10mF

VINA

VREF

AD9240

0.1mF

VINB

2xVREF

SHORT FOR 0 TO 2V

INPUT SPAN

SENSE

SHORT FOR 0 TO 5V

INPUT SPAN

REFCOM

Figure 39. Internal Reference (2 V p-p Input Span, V

= 1 V, or 5 V p-p Input Span, VCM = 2.5 V)

In either case, both the common-mode voltage and input span are directly dependent on the value of VREF. More specifically, the common-mode voltage is equal to VREF while the input

span is equal to 2 × VREF. Thus, the valid input range extends from 0 to 2 × VREF. When VINA is ≤ 0 V, the digital output will be 0000 Hex; when VINA is ≥ 2 × VREF, the digital output

will be 3FFF Hex.

Shorting the VREF pin directly to the SENSE pin places the internal reference amplifier in unity-gain mode and the resultant VREF output is 1 V. The valid input range is, therefore, 0 V to 2 V. Shorting the SENSE pin directly to the REFCOM pin configures the internal reference amplifier for a gain of 2.5 and

Page 17

AD9240

REV. A

–17–

the resultant VREF output is 2.5 V. The valid input range thus becomes 0 V to 5 V. The VREF pin should be bypassed to the

REFCOM pin with a 10 µF tantalum capacitor in parallel with a low-inductance 0.1 µF ceramic capacitor.

Single-Ended or Differential Input, VCM = 2.5 V

Figure 37 shows the single-ended configuration that gives the best SINAD performance. To optimize dynamic specifications, center the common-mode voltage of the analog input at approximately by 2.5 V by connecting VINB to VREF, a lowimpedance 2.5 V source. As described above, shorting the SENSE pin directly to the REFCOM pin results in a 2.5 V reference voltage and a 5 V p-p input span. The valid range for input signals is 0 V to 5 V. The VREF pin should be by-

passed to the REFCOM pin with a 10 µF tantalum capacitor in parallel with a low inductance 0.1 µF ceramic capacitor.

This reference configuration could also be used for a differential input in which VINA and VINB are driven via a transformer as shown in Figure 32. In this case, the common-mode voltage, V

, is set at midsupply by connecting the transformer’s center tap to CML of the AD9240. VREF can be configured for 1 V or 2.5 V by connecting SENSE to either VREF or REFCOM respectively. Note that the valid input range for each of the differential inputs is one half of the single-ended input and thus becomes V

– VREF/2 to VCM + VREF/2.

0.1mF

10mF

VINA VINB

VREF SENSE

REFCOM

AD9240

5V 0V

2.5V

Figure 40. Internal Reference—5 V p-p Input Span, V

= 2.5 V

Resistor Programmable Reference

Figure 41 shows an example of how to generate a reference voltage other than 1 V or 2.5 V with the addition of two external resistors and a bypass capacitor. Use the equation,

VREF = 1 V × (1 + R1/R2),

to determine appropriate values for R1 and R2. These resistors

should be in the 2 kΩ to 100 kΩ range. For the example shown, R1 equals 2.5 kΩ and R2 equals 5 kΩ. From the equa-

tion above, the resultant reference voltage on the VREF pin is

1.5 V. This sets the input span to be 3 V p-p. To assure stabil-

ity, place a 0.1 µF ceramic capacitor in parallel with R1.

The common-mode voltage can be set to VREF by connecting

VINB to VREF to provide an input span of 0 to 2 × VREF.

Alternatively, the common-mode voltage can be set to 2.5 V by connecting VINB to a low impedance 2.5 V source. For

the example shown, the valid input signal range for VINA is 1 V to 4 V since VINB is set to an external, low impedance 2.5 V source. The VREF pin should be bypassed to the REFCOM pin

with a 10 µF tantalum capacitor in parallel with a low inductance 0.1 µF ceramic capacitor.

1.5V

0.1mF

10mF

VINA

VINB VREF

SENSE

REFCOM

AD9240

2.5V

2.5kV R2

5kV

0.1mF

Figure 41. Resistor Programmable Reference (3 V p-p Input Span, V

= 2.5 V)

USING AN EXTERNAL REFERENCE

Using an external reference may enhance the dc performance of the AD9240 by improving drift and accuracy. Figures 42 through 44 show examples of how to use an external reference with the A/D. Table III is a list of suitable voltage references from Analog Devices. To use an external reference, the user must disable the internal reference amplifier and drive the VREF pin. Connecting the SENSE pin to AVDD disables the internal reference amplifier.

Table III. Suitable Voltage References

Initial Operating

Output Drift Accuracy Current Voltage (ppm/ⴗC) % (max) (␮A)

Internal 1.00 26 1.4 N/A REF191 2.048 5–25 0.1–0.5 45 Internal 2.50 26 1.4 N/A REF192 2.50 5–25 0.08–0.4 45 AD780 2.50 3–7 0.04–0.2 1000

The AD9240 contains an internal reference buffer, A2 (see Figure 29), that simplifies the drive requirements of an external

reference. The external reference must be able to drive a ≈5 kΩ (±20%) load. Note that the bandwidth of the reference buffer is

deliberately left small to minimize the reference noise contribution. As a result, it is not possible to change the reference voltage rapidly in this mode without the removal of the CAPT/ CAPB Decoupling Network, and driving these pins directly.

Page 18

AD9240

REV. A

–18–

Variable Input Span with V

= 2.5 V

Figure 42 shows an example of the AD9240 configured for an

input span of 2 × VREF centered at 2.5 V. An external 2.5 V

reference drives the VINB pin thus setting the common-mode voltage at 2.5 V. The input span can be independently set by a voltage divider consisting of R1 and R2, which generates the VREF signal. A1 buffers this resistor network and drives VREF. Choose this op amp based on accuracy requirements. It is

essential that a minimum of a 10 µF capacitor in parallel with a

0.1 µF low inductance ceramic capacitor decouple the reference

output to ground.

2.5V+VREF

2.5V–VREF

2.5V

+5V

0.1mF

22mF

VINA

VINB

VREF

SENSE

AD9240

+5V

0.1mF

2.5V REF

Figure 42. External Reference, VCM = 2.5 V (2.5 V on VINB, Resistor Divider to Make VREF)

Single-Ended Input with 0 to 2 ⴛ VREF Range

Figure 43 shows an example of an external reference driving both VINB and VREF. In this case, both the common mode voltage and input span are directly dependent on the value of VREF. More specifically, the common-mode voltage is equal to

VREF while the input span is equal to 2 × VREF. Thus, the valid input range extends from 0 to 2 × VREF. If, for example,

the REF191, a 2.048 external reference, were selected, the valid input range extends from 0 V to 4.096 V. In this case, 1 LSB of the AD9240 corresponds to 0.250 mV. It is essential that a

minimum of a 10 µF capacitor in parallel with a 0.1 µF low induc-

tance ceramic capacitor decouple the reference output to ground.

2xREF

+5V

10mF

VINA

VINB

VREF

SENSE

AD9240

+5V

0.1mF

VREF

0.1mF

Figure 43. Input Range = 0 V to 2 × VREF

Low Cost/Power Reference

The external reference circuit shown in Figure 44 uses a low cost

1.225 V external reference (e.g., AD580 or AD1580) along with an op amp and transistor. The 2N2222 transistor acts in conjunction with 1/2 of an OP282 to provide a very low impedance drive for VINB. The selected op amp need not be a high speed op amp and may be selected based on cost, power and accuracy.

3.75V

1.25V

+5V

10mF

VINA

VINB

VREF

SENSE

AD9240

+5V

0.1mF

316V

1kV

0.1mF

1/2

OP282

10mF

0.1mF

7.5kV

AD1580

1kV

820V

+5V

2N2222

1.225V

Figure 44. External Reference Using the AD1580 and Low Impedance Buffer

DIGITAL INPUTS AND OUTPUTS Digital Outputs

The AD9240 output data is presented in positive true straight binary for all input ranges. Table IV indicates the output data formats for various input ranges regardless of the selected input range. A twos complement output data format can be created by inverting the MSB.

Table IV. Output Data Format

Input (V) Condition (V) Digital Output OTR

VINA – VINB < –VREF 00 0000 0000 0000 1 VINA – VINB = –VREF 00 0000 0000 0000 0 VINA – VINB = 0 10 0000 0000 0000 0 VINA – VINB = +VREF – 1 LSB 11 1111 1111 1111 0

VINA – VINB ≥ +VREF 11 1111 1111 1111 1

Out Of Range (OTR)

An out-of-range condition exists when the analog input voltage is beyond the input range of the converter. OTR is a digital output that is updated along with the data output corresponding to the particular sampled analog input voltage. Hence, OTR has the same pipeline delay (latency) as the digital data. It is LOW when the analog input voltage is within the analog input range. It is HIGH when the analog input voltage exceeds the input range as shown in Figure 45. OTR will remain HIGH until the analog input returns within the input range and another conversion is completed. By logical ANDing OTR with the MSB and its complement, overrange high or underrange low conditions can be detected. Table V is a truth table for the over/ underrange circuit in Figure 46 which uses NAND gates. Systems requiring programmable gain conditioning of the AD9240 input signal can immediately detect an out-of-range condition, thus eliminating gain selection iterations. Also, OTR can be used for digital offset and gain calibration.

111111 1111 1111 111111 1111 1111 111111 1111 1110

OTR

–FS

+FS

–FS+1/2 LSB

+FS –1/2 LSB–FS –1/2 LSB

+FS –1 1/2 LSB

000000 0000 0001 000000 0000 0000 000000 0000 0000

1 0 0

0 0 1

OTR DATA OUTPUTS

Figure 45. Output Data Format

Page 19

AD9240

REV. A

–19–

Table V. Out-of-Range Truth Table

OTR MSB Analog Input Is

0 0 In Range 0 1 In Range 1 0 Underrange 1 1 Overrange

OVER = “1”

UNDER = “1”

MSB

OTR

MSB

Figure 46. Overrange or Underrange Logic

Digital Output Driver Considerations (DRVDD)

The AD9240 output drivers can be configured to interface with +5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3 V respectively. The AD9240 output drivers are sized to provide sufficient output current to drive a wide variety of logic families; large drive currents tend to cause glitches on the supplies and may affect SINAD performance. Applications requiring the AD9240 to drive large capacitive loads or large fanout may require additional decoupling capacitors on DRVDD. In extreme cases, external buffers or latches may be required.

Clock Input and Considerations

The AD9240 internal timing uses the two edges of the clock input to generate a variety of internal timing signals. The clock input must meet or exceed the minimum specified pulsewidth high and low (t

and tCL) specifications for the given A/D, as defined in the Switching Specifications at the beginning of the data sheet, to meet the rated performance specifications. For example, the clock input to the AD9240 operating at 10 MSPS may have a duty cycle between 45% to 55% to meet this timing requirement since the minimum specified t

and tCL is 45 ns. For clock rates below 10 MSPS, the duty cycle may deviate from this range to the extent that both t

and tCL are satisfied.

All high speed high resolution A/Ds are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (f

), due only to aperture jitter (tA), can be

calculated with the following equation:

SNR = 20 log

[1/(2 π f

IN tA

)]

In the equation, the rms aperture jitter, t

, represents the rootsum square of all the jitter sources, which include the clock input, analog input signal and A/D aperture jitter specification. For example, if a 5.0 MHz full-scale sine wave is sampled by an A/D with a total rms jitter of 15 ps, the SNR performance of the A/D will be limited to 66.5 dB. Undersampling applications are particularly sensitive to jitter.

The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9240. As such, supplies for clock drivers should be separated from the A/D output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing or other method), it should be retimed by the original clock at the last step.

Most of the power dissipated by the AD9240 is from the analog power supply; however, lower clock speeds will reduce digital current slightly. Figure 47 shows the relationship between power and clock rate.

CLOCK FREQUENCY – MHz

400

200

2204 6 8 1012141618

380

300

260

240 220

360

340

280

320

POWER – mW

Figure 47. Power Consumption vs. Clock Frequency (R

BIAS

= 2 kΩ)

GROUNDING AND DECOUPLING Analog and Digital Grounding

Proper grounding is essential in any high speed, high resolution system. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power schemes. The use of ground and power planes offers distinct advantages:

1. The minimization of the loop area encompassed by a signal and its return path.

2. The minimization of the impedance associated with ground and power paths.

3. The inherent distributed capacitor formed by the power plane, PCB insulation and ground plane.

These characteristics result in both a reduction of electromagnetic interference (EMI) and an overall improvement in performance.

It is important to design a layout that prevents noise from coupling onto the input signal. Digital signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. While the AD9240 features separate analog and digital ground pins, it should be treated as an analog component. The AVSS, DVSS and DRVSS pins must be joined together directly under the AD9240. A solid ground plane under the A/D is acceptable if the power and ground return currents are carefully managed. Alternatively, the ground plane under the A/D may contain serrations to steer currents in predictable directions where cross-coupling between analog and digital would otherwise be unavoidable. The AD9240/EB ground layout, shown in Figure 57, depicts the serrated type of arrangement. The analog and digital grounds are connected by a jumper below the A/D.

Page 20

AD9240

REV. A

–20–

Analog and Digital Supply Decoupling

The AD9240 features separate analog and digital supply and ground pins, helping to minimize digital corruption of sensitive analog signals.

FREQUENCY – kHz

120

PSRR – dBFS

100

1000

100101

AVDD

DVDD

Figure 48. PSRR vs. Frequency

Figure 48 shows the power supply rejection ratio vs. frequency for a 200 mV p-p ripple applied to both AVDD and DVDD.

In general, AVDD, the analog supply, should be decoupled to AVSS, the analog common, as close to the chip as physically possible. Figure 49 shows the recommended decoupling for the

analog supplies; 0.1 µF ceramic chip capacitors should provide

adequately low impedance over a wide frequency range. Note that the AVDD and AVSS pins are co-located on the AD9240 to simplify the layout of the decoupling capacitors and provide the shortest possible PCB trace lengths. The AD9240/EB power plane layout, shown in Figure 58, depicts a typical arrangement using a multilayer PCB.

0.1mF

AVDD

AVSS

AD9240

0.1mF

AVDD

AVSS

Figure 49. Analog Supply Decoupling

The CML is an internal analog bias point used internally by the

AD9240. This pin must be decoupled with at least a 0.1 µF

capacitor as shown in Figure 50. The dc level of CML is approximately AVDD/2. This voltage should be buffered if it is to be used for any external biasing.

0.1mF

CML

AD9240

Figure 50. CML Decoupling

The digital activity on the AD9240 chip falls into two general categories: correction logic and output drivers. The internal correction logic draws relatively small surges of current, mainly during the clock transitions. The output drivers draw large current impulses while the output bits are changing. The size and duration of these currents are a function of the load on the

output bits: large capacitive loads are to be avoided. Note that the internal correction logic of the AD9240 is referenced DVDD while the output drivers are referenced to DRVDD.

The decoupling shown in Figure 51, a 0.1 µF ceramic chip

capacitor, is appropriate for a reasonable capacitive load on the digital outputs (typically 20 pF on each pin). Applications involving greater digital loads should consider increasing the digital decoupling proportionally and/or using external buffers/ latches.

0.1mF

DVDD

DVSS

AD9240

DRVDD

DRVSS

0.1mF

Figure 51. Digital Supply Decoupling

A complete decoupling scheme will also include large tantalum or electrolytic capacitors on the PCB to reduce low-frequency ripple to negligible levels. For more information regarding the placement of decoupling capacitors, refer to the AD9240/EB schematic and layouts in Figures 54–58.

APPLICATIONS Direct IF Down Conversion Using the AD9240

Sampling IF signals above an ADC’s baseband region (i.e., dc to F

/2) is becoming increasingly popular in communication applications. This process is often referred to as Direct IF Down Conversion or Undersampling. There are several potential benefits in using the ADC to alias (or mix) down a narrowband or wideband IF signal. First and foremost is the elimination of a complete mixer stage with its associated amplifiers and filters reducing cost and power dissipation. Second is the ability to apply various DSP techniques to perform such functions as filtering, channel selection, quadrature demodulation, data reduction, detection, etc. A detailed discussion on using this technique in digital receivers can be found in Analog Devices Application Notes AN-301 and AN-302.

In Direct IF Down Conversion applications, one exploits the inherent sampling process of an ADC in which an IF signal lying outside the baseband region can be aliased back into the baseband region in a similar manner that a mixer will downconvert an IF signal. Similar to the mixer topology, an image rejection filter is required to limit other potential interfering signals from also aliasing back into the ADC’s baseband region. A tradeoff exists between the complexity of this image rejection filter and the sample rate as well as dynamic range of the ADC.

Until recently, the actual implementation of Direct IF Down Conversion has been limited by the lack of cost-effective ADCs with sufficiently wide dynamic range and high sample rates for IFs beyond 10.7 MHz. Since the performance of the AD9240 in the differential mode of operation extends well beyond its baseband region, it may be well suited as a mix-down converter in narrowband as well as some wideband applications. Also, with the full-power bandwidth of the AD9240 extending beyond 60 MHz, various IF frequencies exist over this frequency range in which the AD9240 maintains excellent dynamic performance.

Figure 52 shows the AD9240 configured in an IF sampling application at 37.5 MHz. To reduce the complexity of the digital demodulator in many quadrature demodulation applications, the IF frequency and/or sample rate are selected such that

Page 21

AD9240

REV. A

–21–

the bandlimited IF signal aliases back into the center of the ADC’s baseband region (i.e. F

/4). At a sample rate of 10 MSPS, an image of the IF signal centered at 37.5 MHz will be aliased back to 2.5 MHz which corresponds to one quarter of the sample rate (i.e. F

/4). Note, the IF signal in this case will have undergone a frequency inversion that may easily be corrected for in the digital domain.

200V

0.1mF

AD9240

VINA CML

VINB

50V

AD8009

50V

280V

93.1V

AD8009

200V

22.1V

50V

SAW FILTER OUTPUT

= 20dB

= 12dB

MINI-CIRCUITS

T4-6T

Figure 52. Simplified AD9240 IF Sampling Circuit

To maximize its distortion performance, the AD9240 is configured in the differential mode using a transformer. Preceding the AD9240 is a bandpass filter and a 32 dB gain stage. A large gain stage may be required to compensate for the high insertion losses of a SAW filter used for image rejection. The gain stage will also provide adequate isolation for the SAW filter from the transient currents associated with AD9240’s input stage.

The gain stage can be realized using one or two cascaded AD8009 op amps. The AD8009 is a low cost current-feedback op amp having a third order intercept of 33 dB for a gain of +10 MHz at 37.5 MHz. A passive bandpass filter is required after the AD8009 to reduce the resulting second order distortion products and limit its out-of-band noise. The specifications of this filter are application dependent and will affect both the total distortion and noise performance of this circuit.

Figure 53 shows the single-tone SNR and SFDR performance of the AD9240 configured in the 2 V and 5 V span without using the AD8009 gain stage. Only a slight degradation in SNR performance (i.e., 1 dB) was noted with the inclusion of the AD8009 gain stage and a bandpass filter. Note, the tradeoff in SNR and SFDR (dBFS) performance between the 5 V and 2 V spans at different signal levels.

INPUT POWER LEVEL – dBFS

–30–80 –70 –60 –40

WORST CASE SPURIOUS AND SNR – dBc

–50 –20 –10 0

SFDR w/5V SPAN

SFDR w/2V SPAN

SNR w/5V SPAN

SNR w/2V SPAN

Figure 53. Single-Tone SNR/SFDR vs. Input Amplitude @ 37.45 MHz

Figure 54 compares the two tone SFDR performance of the AD9240 in the 2 V span with and without the use of the AD8009 gain stage. No degradation in distortion performance was noted with the inclusion of the AD8009 gain stage provided that the AD8009 2nd order distortion products are sufficiently attenuated by the bandpass filter.

INPUT POWER LEVEL (f1 = f2) – dBFS

–90 –30–80 –70 –60 –40

100

90 80

WORST CASE SPURIOUS – dBc AND dBFS

–50 –20 –10 0

w/o AD8009 – dBFS

w/AD8009 – dBFS

w/o AD8009 – dBc

w/AD8009 – dBc

85 dB REFERENCE LINE

Figure 54. Two Tone SFDR vs. Input Amplitude @ f

= 36.40 MHz and f2 = 38.60 MHz

Page 22

AD9240

REV. A

–22–

AD817

1kV

C16

0.1mF

316V

2N2222

C17

10mF

16V

C18

0.1mF

820V

+5VA

TP25

50V

JP10

15kV

C12

0.1mF

10kV

C13

10mF

16V

OUT

GND

REF43

EXTERNAL REFERENCE DRIVE

C14

0.1mF

C15

0.1mF

74HC541N

TPD

C19

0.1mF

AD845

C21

0.1mF V

R11

500V

C20

0.1mF

R14

10kV

R13

10kV

BUFFER

JP23

R10

500V

JP24

DIRECT COUPLE OPTION

C38

AC COUPLE OPTION

JP14

JP13

50V

VIN

R12

33V

R15

33V

+5VA

1N5711

AC COUPLE OPTION

+5VA

1N5711

R39

4J8

6J88

12J814J816J818

20 J8

22J824 J8

39 J8

28 J8

30 J8

32J834J835 J8

36J837J838

+5VA

DECOUPLING

+5VD

DECOUPLING

SPARE GATES

JP18

JP17

R20

22.1V

13 J8

TP10

R21

22.1V

TP11

R22

22.1V

TP12

R23

22.1V

7J8

TP13

R24

22.1V

TP14

R25

22.1V

TP15

R26

22.1V

TP16

R27

22.1V

TP3

R28

22.1V

27 J8

TP4

R29

22.1V

25 J8

TP5

R30

22.1V

TP17

R31

22.1V

TP6

R32

22.1V

19 J8

TP7

R33

22.1V

TP8

R34

22.1V

TP9

C24

0.1mF

+DRVDD

74HC541N

CLKIN

13 12

JP15

CLKB

JP16

CLK

11 10

C23

0.1mF

TP2

R19

50V

R40

R41

R16

5kV

+5VA

R18

5kV

R17

1kV

D13

ADC_CLK

Y7Y6Y5Y4Y3Y2Y1

+5VD

G1G2A7A6A5A4A3A2A1A0GND

+DRVDD 20

Y7Y6Y5Y4Y3Y2Y1

+5VD

G1G2A7A6A5A4A3A2A1A0GND

BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

BIT8

BIT9

BIT10

BIT11

BIT12

BIT13

BIT14

OTR

VREF

SENSE

REFCOM

CAPT

CAPB

CML

VINA

VINB

AD9240MQFP

AVDD2

394142

TP24

0.1mF

JP7

+5VA

0.1mF

24 D13

23 D12

22 D11

21 D10

20 D9

19 D8

18 D7

17 D6

16 D5

15 D4

14 D3

13 D2

12 D1

11 D0

C43

0.1mF

C10

0.1mF

C11

0.1mF

+DRVDD

0.1mF

10mF

16V

JP6

JP3

+5VA

JP4

JP5

10kV

C41

0.1mF

JP2

TPC

TPD

0.1mF

10mF

16V

0.1mF

CML

VINA2

VINA1

JP11

321

VINB2

VINB1

JP12

321

JP8

+5VD

DRVSS

DVSS

DRVDD

DVDD

TP1

CLK

0.1

AVDD1

AVSS2

AVSS1

ADC_CLK

PRI SEC

R36

200V

C36

15pF

R37

33V

R38

33V

VINA1

VINB1

C37

15pF

JP21

TPC

JP22

TPD

JP1

CML

R35

50V

J10

AIN

TP26

SJ6

C28

22mF

25V

C32

0.1mF

TP18

J2+5A

C29

22mF

25V

C33

0.1mF

TP19

J3+5D

C30

22mF

25V

C34

0.1mF

TP20

J4+V

C31

22mF

25V

C35

0.1mF

TP21

J5–V

C39

22mF

25V

C40

0.1mF

TP27

J11

+5_OR _+3

+DRVDD

+5VD

+5VA

TP23

JG1-WIRE

ETCH

CKT SIDE

5 SETS OF

PADS TO

CONNECT

GROUNDS

JG1

SJ1

SJ2

SJ3

SJ4

SJ5

AGND

DGND

TP22

VINA2

VINB2

TPD

TPC

74HC14

74HC04

D7 9

D8 8

D9 7

D10 6

D11 5

D12 4

D13 3

11121314151617

CLK 9

D0 8

D1 7

D2 6

D3 5

D4 4

D5 3

C25

0.1mF C22

0.1mF

C26

0.1mF

C42

0.1mF

BIAS

D6 2

Figure 55. Evaluation Board Schematic

Page 23

AD9240

REV. A

–23–

Figure 56. Evaluation Board Component Side Layout (Not to Scale)

Figure 57. Evaluation Board Solder Side Layout (Not to Scale)

Figure 58. Evaluation Board Ground Plane Layout (Not to Scale)

Figure 59. Evaluation Board Power Plane Layout (Not to Scale)

Page 24

C2937a–0–11/98

PRINTED IN U.S.A.

–24–

OUTLINE DIMENSIONS

Dimensions shown in mm and (inches).

44-Lead MQFP (S-44)

TOP VIEW

(PINS DOWN)

0.45 (0.018)

0.3 (0.012)

13.45 (0.529)

12.95 (0.510)

10.1 (0.398)

9.90 (0.390)

0.8 (0.031) BSC

2.1 (0.083)

1.95 (0.077)

0.23 (0.009)

0.13 (0.005)

SEATING

PLANE

MIN

2.45 (0.096) MAX

1.03 (0.041)

0.73 (0.029)

0.25 (0.01) MIN

8.45 (0.333)

8.3 (0.327)

AD9240

REV. A