Page 1
11-Bit, 200 MSPS,
A
FEATURES
SNR = 62.5 dBFS @ fIN up to 70 MHz @ 200 MSPS
ENOB of 10.2 @ f
SFDR = −77 dBc @ f
Excellent linearity
DNL = ±0.15 LSB typical
INL = ±0.5 LSB typical
LVDS at 200 MSPS (ANSI-644 levels)
700 MHz full power analog bandwidth
On-chip reference, no external decoupling required
Integrated input buffer and track-and-hold amplifier
Low power dissipation
373 mW @ 200 MSPS (LVDS SDR mode)
328 mW @ 200 MSPS (LVDS DDR mode)
Programmable input voltage range
1.0 V to 1.5 V, 1.25 V nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
complement, gray code)
Clock duty cycle stabilizer
Integrated data capture clock
up to 70 MHz @ 200 MSPS (−1.0 dBFS)
IN
up to 70 MHz @ 200 MSPS (−1.0 dBFS)
IN
1.8 V Analog-to-Digital Converter
AD9230-11
FUNCTIONAL BLOCK DIAGRAM
REFERENCE
CML
VIN+
VIN–
CLK+
CLK–
TRACK-AND-HO LD
CLOCK
MANAGEM ENT
RESET
AGNDPWDNRBIAS
12 11
ADC
12-BIT
CORE
SERIAL PORT
SCLK SDIO CSB
Figure 1.
VDD
AD9230-11
OUTPUT
STAGING
LVDS
DRVDD
DRGND
D10 TO D0
OR+
OR–
DCO+
DCO–
07101-001
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
GENERAL DESCRIPTION
The AD9230-11 is an 11-bit monolithic sampling analog-todigital converter (ADC) optimized for high performance,
low power, and ease of use. The product operates at up to a
200 MSPS conversion rate and is optimized for outstanding
dynamic performance in wideband carrier and broadband
systems. All necessary functions, including a track-and-hold
(T/H) amplifier and voltage reference, are included on the
chip to provide a complete signal conversion solution.
The ADC requires a 1.8 V analog voltage supply and a
differential clock for full performance operation. The digital
outputs are LVDS (ANSI-644) compatible and support twos
complement, offset binary format, or Gray code. A data clock
output is available for proper output data timing.
Fabricated on an advanced CMOS process, the AD9230-11 is
available in a 56-lead lead frame chip scale package, specified
over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. High Performance. Maintains 62.5 dBFS SNR
@ 200 MSPS with a 70 MHz input.
2. Low Power. Consumes only 373 mW @ 200 MSPS.
3. Ease of Use. LVDS output data and output clock signal
allow interface to current FPGA technology. The on-chip
reference and sample-and-hold provide flexibility in
system design. Use of a single 1.8 V supply simplifies
system power supply design.
4. Serial Port Control. Standard serial port interface (SPI)
supports various product functions, such as data formatting,
disabling the clock duty cycle stabilizer, power-down, gain
adjust, and output test pattern generation.
5. Pin-Compatible Family. 10-bit and 12-bit pin-compatible
family offered as AD9211 and AD9230.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
Page 2
AD9230-11
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications .......................................................................... 4
Digital Specifications ................................................................... 5
Switching Specifications .............................................................. 6
Timing Diagrams .......................................................................... 7
Absolute Maximum Ratings ............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 13
Equivalent Circuits ......................................................................... 15
Theory of Operation ...................................................................... 16
Analog Input and Voltage Reference ....................................... 16
Clock Input Considerations ...................................................... 17
Power Dissipation and Power-Down Mode ........................... 18
Digital Outputs ........................................................................... 18
Timing ......................................................................................... 19
RBIAS ........................................................................................... 19
Configuration Using the SPI ..................................................... 19
Hardware Interface ..................................................................... 20
Configuration Without the SPI ................................................ 20
Memory Map .................................................................................. 22
Reading the Memory Map Table .............................................. 22
Reserved Locations .................................................................... 22
Default Values ............................................................................. 22
Logic Levels ................................................................................. 22
Transfer Register Map ................................................................ 22
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Page 3
AD9230-11
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, T
= −40°C, T
MIN
= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
MAX
Table 1.
1
Parameter
Temp Min Typ Max Unit
RESOLUTION 11 Bits
ACCURACY
No Missing Codes Full Guaranteed
Offset Error 25°C 4.2 mV
Full −12 +12 mV
Gain Error 25°C 0.89 % FS
Full −2.2 +4.3 % FS
Differential Nonlinearity (DNL) 25°C ±0.15 LSB
Full −0.4 +0.4 LSB
Integral Nonlinearity (INL) 25°C ±0.5 LSB
Full −0.5 +0.5 LSB
TEMPERATURE DRIFT
Offset Error Full ±9 μV/°C
Gain Error Full 0.019 %/°C
ANALOG INPUTS (VIN+, VIN−)
Differential Input Voltage Range
2
Full 0.98 1.25 1.5 V p-p
Input Common-Mode Voltage Full 1.4 V
Input Resistance (Differential) Full 4.3 kΩ
Input Capacitance 25°C 2 pF
POWER SUPPLY
AVDD Full 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 V
Supply Currents
3
I
Full 152 164 mA
AVDD
I
DRVDD
I
DRVDD
3
/SDR Mode
3
/DDR Mode
4
Full 55 58 mA
5
Full 36 mA
Power Dissipation3 Full
SDR Mode
DDR Mode
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were
completed.
2
The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the section. Memory Map
3
I
and I
AVDD
4
Single data rate mode; this is the default mode of the AD9230-11.
5
Double data rate mode; user-programmable feature. See the section.
4
Full 373 400 mW
5
Full 338 mW
are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate.
DRVDD
Memory Map
Rev. 0 | Page 3 of 28
Page 4
AD9230-11
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, T
Table 2.
Parameter2 Temp Min Typ Max Unit
SNR
fIN = 10 MHz 25°C 62.4 62.9 dB
Full 62.2 dB
fIN = 70 MHz 25°C 62.2 62.5 dB
Full 62.0 dB
fIN = 170 MHz 25°C 61.8 dB
SINAD
fIN = 10 MHz 25°C 62.3 62.8 dB
Full 62.1 dB
fIN = 70 MHz 25°C 62.0 62.3 dB
Full 61.8 dB
fIN = 170 MHz 25°C 61.5 dB
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz 25°C 10.3 Bits
fIN = 70 MHz 25°C 10.2 Bits
fIN = 170 MHz 25°C 10.1 Bits
WORST HARMONIC (SECOND OR THIRD)
fIN = 10 MHz 25°C −86 −77 dBc
Full −77 dBc
fIN = 70 MHz 25°C −79 −77 dBc
Full −76 dBc
fIN = 170 MHz 25°C −76 dBc
WORST OTHER (SFDR EXCLUDING SECOND AND THIRD)
fIN = 10 MHz 25°C −88 −84 dBc
Full −79 dBc
fIN = 70 MHz 25°C −84 −82 dBc
Full −81 dBc
fIN = 170 MHz 25°C −82 dBc
ANALOG INPUT BANDWIDTH 25°C 700 MHz
1
All ac specifications tested by driving CLK+ and CLK− differentially.
2
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were
completed.
= −40°C, T
MIN
= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.1
MAX
Rev. 0 | Page 4 of 28
Page 5
AD9230-11
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, T
Table 3.
Parameter1 Temp Min Typ Max Unit
CLOCK INPUTS
Logic Compliance Full CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 1.2 V
Differential Input Voltage Full 0.2 6 V p-p
Input Voltage Range Full AGND − 0.3 AVDD + 1.6 V
Input Common-Mode Range Full 1.1 AVDD V
High Level Input Voltage (VIH) Full 1.2 3.6 V
Low Level Input Voltage (VIL) Full 0 0.8 V
High Level Input Current (IIH) Full −10 +10 μA
Low Level Input Current (IIL) Full −10 +10 μA
Input Resistance (Differential) Full 16 20 24 kΩ
Input Capacitance Full 4 pF
LOGIC INPUTS
Logic 1 Voltage Full 0.8 × AVDD V
Logic 0 Voltage Full 0.2 × AVDD V
Logic 1 Input Current (SDIO) Full 0 μA
Logic 0 Input Current (SDIO) Full −60 μA
Logic 1 Input Current (SCLK, PWDN, CSB, RESET) Full 55 μA
Logic 0 Input Current (SCLK, PWDN, CSB, RESET) Full 0 μA
Input Capacitance 25°C 4 pF
LOGIC OUTPUTS2
VOD Differential Output Voltage Full 247 454 mV
VOS Output Offset Voltage Full 1.125 1.375 V
Output Coding Twos complement, gray code, or offset binary (default)
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were
completed.
2
LVDS R
TERMINATION
= 100 Ω.
= −40°C, T
MIN
= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
MAX
Rev. 0 | Page 5 of 28
Page 6
AD9230-11
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, T
Table 4.
Parameter Temp Min Typ Max Unit
CONVERSION RATE
Maximum Conversion Rate Full 200
Minimum Conversion Rate Full
PULSE WIDTH
CLK+ Pulse Width High (tCH) Full 2.25 2.5 ns
CLK+ Pulse Width Low (tCL) Full 2.25 2.5 ns
OUTPUT (LVDS, SDR MODE)
1
Data Propagation Delay (tPD) Full 3.8 ns
Rise Time (tR) (20% to 80%) 25°C 0.2 ns
Fall Time (tF) (20% to 80%) 25°C 0.2 ns
DCO Propagation Delay (t
Data to DCO Skew (t
CPD
) Full −0.3 0.1 0.5 ns
SKEW
Latency Full 6 Cycles
OUTPUT (LVDS, DDR MODE)
2
Data Propagation Delay (tPD) Full 3.8 ns
Rise Time (tR) (20% to 80%) 25°C 0.2 ns
Fall Time (tF) (20% to 80%) 25°C 0.2 ns
DCO Propagation Delay (t
Data to DCO Skew (t
CPD
) Full −0.5 0.1 0.3 ns
SKEW
Latency Full 6 Cycles
APERTURE UNCERTAINTY (JITTER, tJ) 25°C 0.2 ps rms
1
See Figure 2.
2
See Figure 3.
= −40°C, T
MIN
= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
MAX
40 MSPS
MSPS
) Full 3.9 ns
) Full 3.9 ns
Rev. 0 | Page 6 of 28
Page 7
AD9230-11
TIMING DIAGRAMS
VIN
CLK+
CLK–
DCO+
DCO–
Dx+
Dx–
VIN
N – 1
t
CH
N – 1
t
A
N
N + 3
N + 1
t
CL
t
CPD
1/
f
S
t
SKEW
t
PD
N – 6 N – 5 N – 4 N – 3 N – 2
N + 2
N + 4
N + 5
07101-002
Figure 2. Single Data Rate Mode
t
A
N
N + 3
N + 1
N + 2
N + 4
N + 5
t
CLK+
CLK–
DCO+
DCO–
D5+
D5–
D4/D10+
D4/D10–
t
CH
CL
t
CPD
1/
f
S
t
SKEW
t
PD
D5
N – 7NODATAD5N – 6NODATAD5N – 5NODATAD5N – 4NODATAD5N – 3NODATA
D10
N – 7D4N – 6
6 MSBs
5 LSBs
D10
N – 6D4N – 5
D10
N – 5D4N – 4
D10
N – 4D4N – 3
D10
N – 3D4N – 2
07101-003
Figure 3. Double Data Rate Mode
Rev. 0 | Page 7 of 28
Page 8
AD9230-11
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Electrical
AVDD to AGND −0.3 V to +2.0 V
DRVDD to DRGND −0.3 V to +2.0 V
AGND to DRGND −0.3 V to +0.3 V
AVDD to DRVDD −2.0 V to +2.0 V
D0+/D0− through D10+/D10−
to DRGND
DCO+/DCO− to DRGND −0.3 V to DRVDD + 0.3 V
OR+/OR− to DGND −0.3 V to DRVDD + 0.3 V
CLK+ to AGND −0.3 V to +3.9 V
CLK− to AGND −0.3 V to +3.9 V
VIN+ to AGND −0.3 V to AVDD + 0.2 V
VIN− to AGND −0.3 V to AVDD + 0.2 V
SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V
PWDN to AGND −0.3 V to +3.9 V
CSB to AGND −0.3 V to +3.9 V
SCLK/DFS to AGND −0.3 V to +3.9 V
Environmental
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature
(Soldering, 10 sec)
Junction Temperature 150°C
−0.3 V to DRVDD + 0.3 V
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
The exposed paddle must be soldered to the ground plane
for the LFCSP package. Soldering the exposed paddle to the
customer board increases the reliability of the solder joints,
maximizing the thermal capability of the package.
Table 6.
Package Type θJA θ
56-Lead LFCSP (CP-56-2) 30.4 2.9 °C/W
Unit
JC
Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θ
JA
. In
addition, metal that is in direct contact with the package leads
reduces the θ
.
JA
ESD CAUTION
Rev. 0 | Page 8 of 28
Page 9
AD9230-11
2
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
D1–
D1+
55
56
DCO+
DNC
DNC
D0– (LSB)
D0+ (LSB)
52
53
54
50
51
CLK–
AVDD
DRVDD
DRGND
DCO–
48
49
CLK+
AVDD
44
43
45
46
47
1D2–
2D2+
3D3–
4D3+
5D4–
6D4+
7DRVDD
8DRGND
9D5–
10D5+
11D6–
12D6+
13D7–
14D7+
NOTES
1. DNC = DO NOT CONNECT.
. PIN 0 (EXPOSED PADDLE) = AGND.
PIN 1
INDICATO R
16
15
D8–
D8+
AD9230-11
TOP VIEW
(Not to Scale)
17
19
20
18
D9–
D9+
(MSB) D10–
(MSB) D10+
42 AVDD
41 AVDD
40 CML
39 AVDD
38 AVDD
37 AVDD
36 VIN–
35 VIN+
34 AVDD
33 AVDD
32 AVDD
31 RBIAS
30 AVDD
29 PWDN
21
22
23
24
25
26
27
28
OR–
OR+
DRGND
CSB
RESET
DRVDD
SDIO/DCS
SCLK/DFS
7101-004
Figure 4. Single Data Rate Mode Pin Configuration
Table 7. Single Data Rate Mode Pin Function Descriptions
Pin No. Mnemonic Description
30, 32 to 34, 37 to 39, 41 to
AVDD 1.8 V Analog Supply.
43, 46
7, 24, 47 DRVDD 1.8 V Digital Output Supply.
0 AGND
8, 23, 48 DRGND
1
Analog Ground. The exposed paddle should be connected to the analog ground.
1
Digital Output Ground.
35 VIN+ Analog Input (True).
36 VIN− Analog Input (Complement).
40 CML
Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
44 CLK+ Clock Input (True).
45 CLK− Clock Input (Complement).
31 RBIAS Set Pin for Chip Bias Current. Place 1% 10 kΩ resistor terminated to ground. Nominally 0.5 V.
28 RESET CMOS-Compatible Chip Reset (Active Low).
25 SDIO/DCS
Serial Port Interface (SPI) Data Input/Output (Serial Port Mode). Duty Cycle Stabilizer Select
(External Pin Mode).
26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode). Data Format Select Pin (External Pin Mode).
27 CSB Serial Port Chip Select (Active Low).
29 PWDN Chip Power-Down.
49 DCO− Data Clock Output (Complement).
50 DCO+ Data Clock Output Input (True).
51, 52 DNC Do No Connect.
53 D0− (LSB) D0 Complement Output Bit (LSB).
54 D0+ (LSB) D0 True Output Bit (LSB).
55 D1− D1 Complement Output Bit.
56 D1+ D1 True Output Bit.
1 D2− D2 Complement Output Bit.
2 D2+ D2 True Output Bit.
Rev. 0 | Page 9 of 28
Page 10
AD9230-11
Pin No. Mnemonic Description
3 D3− D3 Complement Output Bit.
4 D3+ D3 True Output Bit.
5 D4− D4 Complement Output Bit.
6 D4+ D4 True Output Bit.
9 D5− D5 Complement Output Bit.
10 D5+ D5 True Output Bit.
11 D6− D6 Complement Output Bit.
12 D6+ D6 True Output Bit.
13 D7− D7 Complement Output Bit.
14 D7+ D77 True Output Bit.
15 D8− D8 Complement Output Bit.
16 D8+ D8 True Output Bit.
17 D9− D9 Complement Output Bit.
18 D9+ D9 True Output Bit.
19 D10− (MSB) D10 Complement Output Bit (MSB).
20 D10+ (MSB) D10 True Output Bit (MSB).
21 OR− Overrange Complement Output Bit.
22 OR+ Overrange True Output Bit.
1
AGND and DRGND should be tied to a common quiet ground plane.
Rev. 0 | Page 10 of 28
Page 11
AD9230-11
+
C
2
7+
D1/D7–
D1/D
D0/D6+ (LSB)
55
56
54
1D2/D8–
2D2/D8+
3D3/D9–
4D3/D9+
5(MSB) D4/D10–
6(MSB) D4/D10
7DRVDD
8DRGND
9OR–
10OR+
11DNC
12DNC
13DNC
14DNC
NOTES
1. DNC = DO NOT CONNE
. PIN 0 (EXPOSED PADDLE) = AGND.
PIN 1
INDICATO R
16
15
DNC
DNC
T.
17
DNC
DCO–
DCO+
ND/D5–
ND/D5+
D0/D6– (LSB)
52
53
49
50
51
AD9230-11
TOP VIEW
(Not to Scale)
21
19
20
22
18
DNC
DNC
DNC
DNC/(OR–)
DNC/(OR+)
LK–
AVDD
C
DRVDD
DRGND
48
23
DRGND
AVDD
CLK+
44
43
46
47
45
42 AVDD
41 AVDD
40 CML
39 AVDD
38 AVDD
37 AVDD
36 VIN–
35 VIN+
34 AVDD
33 AVDD
32 AVDD
31 RBIAS
30 AVDD
29 PWDN
24
25
26
27
28
CSB
RESET
DRVDD
SDIO/DCS
SCLK/DFS
07101-005
Figure 5. Double Data Rate Mode Pin Configuration
Table 8. Double Data Rate Mode Pin Function Descriptions
Pin No. Mnemonic Description
30, 32 to 34, 37 to 39,
AVDD 1.8 V Analog Supply.
41 to 43, 46
7, 24, 47 DRVDD 1.8 V Digital Output Supply.
0 AGND
8, 23, 48 DRGND
1
Analog Ground. The exposed paddle should be connected to the analog ground.
1
Digital Output Ground.
35 VIN+ Analog Input Input (True).
36 VIN− Analog Input (Complement).
40 CML
Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
44 CLK+ Clock Input Input (True).
45 CLK− Clock Input (Complement).
31 RBIAS Set Pin for Chip Bias Current. Place 1% 10 kΩ resistor terminated to ground. Nominally 0.5 V.
28 RESET CMOS-Compatible Chip Reset (Active Low).
25 SDIO/DCS Serial Port Interface (SPI) Data Input/Output (Serial Port Mode).
Duty Cycle Stabilizer Select (External Pin Mode).
26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode).
Data Format Select Pin (External Pin Mode).
27 CSB Serial Port Chip Select (Active Low).
29 PWDN Chip Power-Down.
49 DCO− Data Clock Output (Complement).
50 DCO+ Data Clock Output Input (True).
51 ND/D5− ND/D5 Complement Output Bit.
52 ND/D5+ ND/D5 True Output Bit.
53 D0/D6− (LSB) D0/D6 Complement Output Bit (LSB).
54 D0/D6+ (LSB) D0/D6 True Output Bit (LSB).
55 D1/D7− D1/D7 Complement Output Bit.
56 D1/D7+ D1/D7 True Output Bit.
1 D2/D8− D2/D8 Complement Output Bit.
2 D2/D8+ D2/D8 True Output Bit.
Rev. 0 | Page 11 of 28
Page 12
AD9230-11
Pin No. Mnemonic Description
3 D3/D9− D3/D9 Complement Output Bit.
4 D3/D9+ D3/D9 True Output Bit.
5 D4/D10− (MSB) D4/D10 Complement Output Bit (MSB).
6 D4/D10+ (MSB) D4/D10 True Output Bit (MSB).
9 OR−
10 OR+ OR True Output Bit. This pin is disabled if Pin 22 is reconfigured through the SPI to be OR+.
11 to 20 DNC Do Not Connect.
21 DNC/(OR−)
22 DNC/(OR+)
1
AGND and DRGND should be tied to a common quiet ground plane.
OR Complement Output Bit. This pin is disabled if Pin 21 is reconfigured through the SPI to be
OR−.
Do Not Connect. This pin can be reconfigured as the Overrange Complement Output Bit
through the serial port register.
Do Not Connect. This pin can be reconfigured as the Overrange True Output Bit through the
serial port register.
Rev. 0 | Page 12 of 28
Page 13
AD9230-11
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, TA = 25°C, 1.25 V p-p differential input, AIN = −1 dBFS, unless
otherwise noted.
–20
–40
0
200MSPS
10.3MHz @ –1.0d BFS
SNR: 62.9dB
ENOB: 10.3 BI TS
SFDR: 86dBc
85
80
75
SNR (dB) +85°C
–60
–80
AMPLITUDE ( dBFS)
–100
–120
–140
0 10010 20 30 40 50 60 70 80 90
FREQUENCY (MHz )
Figure 6. 64k Point Single-Tone FFT; 200 MSPS, 10.3 MHz
0
200MSPS
70.3MHz @ –1.0dBFS
–20
SNR: 62.5dB
ENOB: 10.2 BITS
SFDR: 77d Bc
–40
–60
–80
AMPLITUDE ( dBFS)
–100
–120
–140
0 10010 20 30 40 50 60 70 80 90
FREQUENCY (MHz )
Figure 7. 64k Point Single-Tone FFT; 200 MSPS, 70.3 MHz
70
SFDR (dBc) +25°C
65
SNR/SFDR (dB)
60
SNR (dB) –40°C
55
50
0 450
50 100 150 200 250 300 350 400
07101-028
SNR (dB) +25°C
ANALOG INPUT FREQUENCY (MHz)
Figure 9. Single-Tone SNR/SFDR vs. Input Frequency (f
SFDR (dBc) –40° C
07101-031
)
IN
with 1.25 V p-p Full-Scale; 200 MSPS
100
90
80
70
60
50
40
SNR/SFDR (dB)
30
20
10
0
–90 0
07101-029
SFDR (dBFS)
SNR (dBFS)
SNR (dB)SFDR (dBc)
–80 –70 –60 –50 –40 –30 –20 –10
AMPLITUDE ( dBFS)
07101-032
Figure 10. SNR/SFDR vs. Input Amplitude; 140.3 MHz
AMPLITUDE ( dBFS)
–20
–40
–60
–80
–100
–120
–140
0
0
10 20 30 40 50 60 70 80 90
FREQUENCY (MHz )
200MSPS
170.3MHz @ –1.0dBF S
SNR: 61.3dB
ENOB: 10.1 BITS
SFDR: 73d Bc
Figure 8. 64k Point Single-Tone FFT; 170 MSPS, 140.3 MHz
100
07101-030
Rev. 0 | Page 13 of 28
6.0
5.5
5.0
4.5
4.0
OFFSET (mV)
3.5
3.0
2.5
2.0
–40 –30 –20 –10 0 908070605040302010
Figure 11. Offset vs. Temperature
TEMPERATURE ( °C)
7101-012
Page 14
AD9230-11
1.0
0.8
0.6
0.4
0.2
0
DNL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
0 2048
2.5
2.0
1.5
512 1024 1536
OUTPUT CODE
Figure 12. DNL
1.0
0.8
0.6
0.4
0.2
0
INL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
0 2048
07101-034
512 1024 1536
OUTPUT CODE
07101-033
Figure 14. INL
1.0
GAIN (%FS)
0.5
0
–0.5
–60 120100806040200–20–40
TEMPERATURE ( °C)
7101-013
Figure 13. Gain vs. Temperature
Rev. 0 | Page 14 of 28
Page 15
AD9230-11
V
EQUIVALENT CIRCUITS
CLK+
AVDD
1.2V
10kΩ 10kΩ
Figure 15. Clock Inputs
CSB
CLK–
07101-006
Figure 18. Equivalent CSB Input Circuit
AVDD
25kΩ
1kΩ
07101-009
AVDD
BUF
1kΩ
= ~1.4 V)
CML
AVDD
V
CML
~1.4V
7101-007
07101-008
IN+
AVDD
VIN–
Figure 16. Analog Inputs (V
SCLK/DFS
RESET
PWDN
BUF
2kΩ
2kΩ
BUF
AVDD
25kΩ
Figure 17. Equivalent SCLK/DFS, RESET, PWDN Input Circuit
DRVDD
V+
Dx–
V–
V–
Dx+
V+
7101-010
Figure 19. LVDS Outputs (Dx+, Dx−, OR+, OR−, DCO+, DCO−)
DRVDD
SDIO/DCS
25kΩ
1kΩ
07101-011
Figure 20. Equivalent SDIO/DCS Input Circuit
Rev. 0 | Page 15 of 28
Page 16
AD9230-11
V
A
A
THEORY OF OPERATION
The AD9230-11 architecture consists of a front-end sampleand-hold amplifier (SHA) followed by a pipelined switched
capacitor ADC. The quantized outputs from each stage are
combined into a final 11-bit result in the digital correction
logic. The pipelined architecture permits the first stage to
operate on a new input sample, while the remaining stages operate
on preceding samples. Sampling occurs on the rising edge of the
clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a buffered differential SHA that can
be ac- or dc-coupled. The output staging block aligns the data,
carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate
supply, allowing adjustment of the output voltage swing. During
power-down, the output buffers go into a high impedance state.
ANALOG INPUT AND VOLTAGE REFERENCE
The analog input to the AD9230-11 is a differential buffer. For
best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched such that common-mode
settling errors are symmetrical. The analog input is optimized
to provide superior wideband performance and requires that
the analog inputs be driven differentially. SNR and SINAD
performance degrades significantly if the analog input is driven
with a single-ended signal.
A wideband transformer, such as Mini-Circuits® ADT1-1WT, can
provide the differential analog inputs for applications that require a
single-ended-to-differential conversion. Both analog inputs are selfbiased by an on-chip resistor divider to a nominal 1.4 V. An
internal differential voltage reference creates positive and negative
reference voltages that define the 1.25 V p-p fixed span of the ADC
core. This internal voltage reference can be adjusted by means of
SPI control. See the Configuration Using the SPI section.
CC
Differential Input Configurations
Optimum performance is achieved while driving the AD9230-11
in a differential input configuration. For baseband applications,
the AD8138 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
49.9Ω1V p-p
499Ω
0.1µF
523Ω
Figure 21. Differential Input Configuration Using the AD8138
499Ω
AD8138
499Ω
33Ω
33Ω
20pF
AVDD
VIN+
AD9230-11
VIN–
CML
7101-014
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers may not be adequate to achieve the
true performance of the AD9230-11. This is especially true in IF
undersampling applications where frequencies in the 70 MHz to
100 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration.
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies below a
few megahertz and excessive signal power can also cause core
saturation, leading to distortion. In any configuration, the value of
the shunt capacitor, C, is dependent on the input frequency and
may need to be reduced or removed.
15Ω
50Ω1.25V p-p
0.1µF
2pF
15Ω
Figure 22. Differential Transformer—Coupled Configuration
VIN+
AD9230-11
VIN–
07101-015
As an alternative to using a transformer-coupled input at frequencies in the second Nyquist zone, the AD8352 differential driver can
be used (see Figure 23).
NALOG I NPUT
C
NALOG I NPUT
0.1µF
0Ω
DRDRG
0Ω
0.1µF
16
1
2
3
4
5
8, 13
AD8352
14
0.1µF
0.1µF
11
10
0.1µF
0.1µF
200Ω
200Ω
R
C
R
0.1µF
VIN+
AD9230-11
CML
VIN–
07101-016
Figure 23. Differential Input Configuration Using the AD8352
Rev. 0 | Page 16 of 28
Page 17
AD9230-11
A
A
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9230-11 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ pin and the
CLK− pin via a transformer or capacitors. These pins are biased
internally and require no additional bias.
Figure 24 shows a preferred method for clocking the AD9230-11.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9230-11 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9230-11 and preserves the
fast rise and fall times of the signal, which are critical to low
jitter performance.
MINI-CIRCUITS
ADT1–1WT, 1:1Z
CLOCK
INPUT
50Ω
100Ω
Figure 24. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac couple
a differential PECL signal to the sample clock input pins as
shown in Figure 25. The AD9510/AD9511/AD9512/AD9513/
AD9514/AD9515 family of clock drivers offers excellent jitter
performance.
CLOCK
INPUT
CLOCK
INPUT
*50Ω RESISTORS ARE OPTIONAL.
0.1µF
CLK
PECL DRIVER
0.1µF
50Ω* 50Ω*
CLK
Figure 25. Differential PECL Sample Clock
CLOCK
INPUT
CLOCK
INPUT
50Ω* 50Ω*
*50Ω RESISTORS ARE OPTIO NAL.
0.1µF
CLK
LVDS DRIVER
0.1µF
CLK
Figure 26. Differential LVDS Sample Clock
0.1µF0.1µF
XFMR
0.1µF
0.1µF
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
SCHOTT KY
DIODES:
HSM2812
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
240Ω240Ω
100Ω
0.1µF
100Ω
0.1µF
0.1µF
0.1µF
CLK+
ADC
AD9230-11
CLK–
CLK+
ADC
AD9230-11
CLK–
CLK+
ADC
AD9230-11
CLK–
07101-017
07101-018
07101-019
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 F capacitor
in parallel with a 39 kΩ resistor (see Figure 27). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages up to 3.3 V (as shown in
Figure 28), making the selection of the drive logic voltage very
flexible.
D9510/AD9511/
AD9512/AD9513/
CLOCK
INPUT
*50Ω RESISTOR IS OPTIONAL.
0.1µF
50Ω*
0.1µF
AD9514/AD9515
CLK
CMOS DRIVER
CLK
0.1µF
OPTIONAL
100Ω
39kΩ
0.1µF
CLK+
ADC
AD9230-11
CLK–
Figure 27. Single-Ended 1.8 V CMOS Sample Clock
D9510/AD9511/
AD9512/AD9513/
CLOCK
INPUT
*50Ω RESISTOR IS OPTIONAL.
0.1µF
50Ω*
0.1µF
AD9514/AD9515
CLK
CMOS DRIVER
CLK
OPTIONAL
100Ω
0.1µF
0.1µF
CLK+
ADC
AD9230-11
CLK–
Figure 28. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9230-11 contains a duty cycle stabilizer
(DCS) that retimes the nonsampling edge, providing an internal
clock signal with a nominal 50% duty cycle. This allows a wide
range of clock input duty cycles without affecting the performance of the AD9230-11. When the DCS is on, noise and distortion
performance are nearly flat for a wide range of duty cycles.
However, some applications may require the DCS function to
be off. If so, keep in mind that the dynamic range performance can
be affected when operated in this mode. See the Configuration
Using the SPI section for more details on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
07101-020
07101-021
Rev. 0 | Page 17 of 28
Page 18
AD9230-11
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(f
) due only to aperture jitter (tJ) can be calculated by
A
SNR Degradation = 20 × log
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 29).
Treat the clock as an analog signal in cases where aperture jitter
may affect the dynamic range of the AD9230-11. Power supplies
for clock drivers should be separated from the ADC output
driver supplies to avoid modulating the clock signal with digital
noise. Low jitter, crystal-controlled oscillators make the best
clock sources. If the clock is generated from another type of
source (by gating, dividing, or other methods), it should be
retimed by the original clock at the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs (visit www.analog.com).
130
RMS CLOCK JIT TER REQUIREM ENT
120
110
100
90
80
SNR (dB)
70
10 BITS
60
8 BITS
50
40
30
1 10 100 1000
Figure 29. Ideal SNR vs. Input Frequency and Jitter
ANALOG INPUT FREQUENCY (MHz)
POWER DISSIPATION AND POWER-DOWN MODE
The power dissipated by the AD9230-11 is proportional to its
sample rate. The digital power dissipation does not vary much
because it is determined primarily by the DRVDD supply and
bias current of the LVDS output drivers.
By asserting PWDN (Pin 29) high, the AD9230-11 is placed in
standby mode or full power-down mode, as determined by the
contents of Register 0x08. Reasserting the PWDN pin low
returns the AD9230-11 to its normal operational mode.
An additional standby mode is supported by means of varying
the clock input. When the clock rate falls below 20 MHz, the
AD9230-11 assumes a standby state. In this case, the biasing
network and internal reference remain on, but digital circuitry
is powered down. Upon reactivating the clock, the AD9230-11
resumes normal operation after allowing for the pipeline
latency.
[1/2 × π × fA × tJ]
10
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
16 BITS
14 BITS
12 BITS
07101-022
DIGITAL OUTPUTS
Digital Outputs and Timing
The AD9230-11 differential outputs conform to the ANSI-644
LVDS standard on default power-up. This can be changed to a
low power, reduced signal option similar to the IEEE 1596.3
standard using the SPI. This LVDS standard can further reduce
the overall power dissipation of the device, which reduces the
power by ~39 mW. See the Memory Map section for more
information. The LVDS driver current is derived on-chip and
sets the output current at each output equal to a nominal
3.5 mA. A 100 Ω differential termination resistor placed at the
LVDS receiver inputs results in a nominal 350 mV swing at the
receiver.
The AD9230-11 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments.
Single point-to-point net topologies are recommended with a
100 Ω termination resistor placed as close to the receiver as
possible. No far-end receiver termination and poor differential
trace routing may result in timing errors. It is recommended
that the trace length is no longer than 24 inches and that the
differential output traces are kept close together and at equal
lengths.
An example of the LVDS output using the ANSI standard (default)
data eye and a time interval error (TIE) jitter histogram with
trace lengths less than 24 inches on regular FR-4 material is
shown in Figure 30. Figure 31 shows an example of when the
trace lengths exceed 24 inches on regular FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position. It is up to
the user to determine if the waveforms meet the timing budget
of the design when the trace lengths exceed 24 inches.
14
500
400
300
200
100
0
–100
VOLTAGE (mV)
–200
–300
–400
–500
–3–2–10123
Figure 30. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less
TIME (ns)
than 24 Inches on Standard FR-4
12
10
8
6
4
TIE JIT TER HIST OGRAM (Hi ts)
2
0
–40 –20 0 20 40
TIME (ps)
07101-023
Rev. 0 | Page 18 of 28
Page 19
AD9230-11
600
400
200
0
VOLTAGE (mV)
–200
–400
–600
–3–2–10123
Figure 31. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths
TIME (ns)
Greater than 24 Inches on Standard FR-4
12
10
8
6
4
TIE JITTER HISTOGRAM (Hits)
2
0
–100 0 100
TIME (ps)
07101-024
The format of the output data is offset binary by default. An
example of the output coding format can be found in Tabl e 12.
If it is desired to change the output data format to twos complement, see the Configuration Using the SPI section.
An output clock signal is provided to assist in capturing data
from the AD9230-11. The DCO is used to clock the output
data and is equal to the sampling clock (CLK) rate. In single
data rate mode (SDR), data is clocked out of the AD9230-11
and must be captured on the rising edge of the DCO. In double
data rate mode (DDR), data is clocked out of the AD9230-11
and must be captured on the rising and falling edges of the
DCO See the timing diagrams shown in Figure 2 and Figure 3
for more information.
Output Data Rate and Pinout Configuration
The output data of the AD9230-11 can be configured to drive
12 pairs of LVDS outputs at the same rate as the input clock
signal (single data rate, or SDR, mode), or six pairs of LVDS
outputs at 2× the rate of the input clock signal (double data rate,
or DDR, mode). SDR is the default mode; the device can be
reconfigured for DDR by setting Bit 3 in Register 14 (see Table 13).
Out-of-Range (OR)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR is a digital output
that is updated along with the data output corresponding to the
particular sampled input voltage. Thus, OR has the same
pipeline latency as the digital data. OR is low when the analog
input voltage is within the analog input range and high when
the analog input voltage exceeds the input range, as shown in
Figure 32. OR remains high until the analog input returns to
within the input range and another conversion is completed. By
logically AND-ing OR with the MSB and its complement, overrange high or underrange low conditions can be detected.
OR DATA OUTPUTS
1
1111
1111
0
1111
1111
0
1111
1111
0
0000
0000
0
0000
0000
1
0000
0000
Figure 32. OR Relation to Input Voltage and Output Data
OR
–FS + 1/2 L SB
–FS – 1/2 LSB
+FS – 1 LSB
+FS–FS
+FS – 1/2 L SB
07101-025
TIMING
The AD9230-11 provides latched data outputs with a pipeline
delay of seven clock cycles. Data outputs are available one
propagation delay (t
) after the rising edge of the clock signal.
PD
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9230-11.
These transients can degrade the dynamic performance of the
converter. The AD9230-11 also provides data clock output (DCO)
intended for capturing the data in an external register. The data
outputs are valid on the rising edge of DCO.
The lowest typical conversion rate of the AD9230-11 is 40 MSPS.
At clock rates below 1 MSPS, the AD9230-11 assumes the
standby mode.
RBIAS
The AD9230-11 requires the user to place a 10 k resistor
between the RBIAS pin and ground. This resister should have
a 1% tolerance and is used to set the master current reference
of the ADC core.
CONFIGURATION USING THE SPI
The AD9230-11 SPI allows the user to configure the converter for
specific functions or operations through a structured register space
inside the ADC. This gives the user added flexibility to customize
device operation depending on the application. Addresses are
accessed (programmed or readback) serially in 1-byte words. Each
byte may be further divided down into fields, which are
documented in the Memory Map section.
There are three pins that define the serial port interface (SPI) to this
particular ADC. They are the SCLK/DFS, SDIO/DCS, and CSB
pins. The SCLK/DFS (serial clock) is used to synchronize the read
and write data presented to the ADC. The SDIO/DCS (serial data
input/output) is a dual-purpose pin that allows data to be sent and
read from the internal ADC memory map registers. The CSB pin is
an active low control that enables or disables the read and write
cycles (see Tabl e 9 ).
Rev. 0 | Page 19 of 28
Page 20
AD9230-11
Table 9. Serial Port Interface Pins
Mnemonic Function
SCLK
SDIO
CSB
RESET
The falling edge of CSB, in conjunction with the rising edge of
the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 33
and Tabl e 11 .
During an instruction phase, a 16-bit instruction is transmitted.
Data then follows the instruction phase and is determined by
the W0 and W1 bits, which is 1 or more bytes of data. All data is
composed of 8-bit words. The first bit of each individual byte of
serial data indicates whether this is a read or write command.
This allows the serial data input/output (SDIO) pin to change
direction from an input to an output.
Data can be sent in MSB or in LSB first mode. MSB first is
default on power-up and can be changed by changing the
configuration register. For more information about this feature
and others, see the AN-877 Application Note, Inter facing to
High Speed ADCs via SPI, at www.analog.com.
CSB
SCLK (serial clock) is the serial shift clock in.
SCLK is used to synchronize serial interface
reads and writes.
SDIO (serial data input/output) is a dual-purpose
pin. The typical role for this pin is an input and
output depending on the instruction being sent
and the relative position in the timing frame.
CSB (chip select bar) is an active low control that
gates the read and write cycles.
Master Device Reset. When asserted, device
assumes default settings. Active low.
t
DS
t
S
t
DH
t
HI
t
CLK
t
LO
HARDWARE INTERFACE
The pins described in Ta b l e 9 comprise the physical interface
between the user’s programming device and the serial port
of the AD9230-11. All serial pins are inputs, which is an opendrain output and should be tied to an external pull-up or
pull-down resistor (suggested value of 10 kΩ).
This interface is flexible enough to be controlled by either PROMS
or PIC microcontrollers as well. This provides the user with an
alternate method to program the ADC other than using an SPI
controller.
If the user chooses not to use the SPI interface, some pins serve
a dual function and are associated with a specific function when
strapped externally to AVDD or ground during device power
on. The Configuration Without the SPI section describes the
strappable functions supported on the AD9230-11.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS and SCLK/DFS pins can alternately serve as
standalone CMOS-compatible control pins. When the device is
powered up, it is assumed that the user intends to use the pins
as static control lines for the duty cycle stabilizer. In this mode,
the CSB pin should be connected to AVDD, which disables the
serial port interface.
Table 10. Mode Selection
Mnemonic External Voltage Configuration
SDIO/DCS AVDD Duty cycle stabilizer enabled
AGND Duty cycle stabilizer disabled
SCLK/DFS AVDD Twos complement enabled
AGND Offset binary enabled
t
H
SCLK
SDIO
DON’T CARE
DON’T CARE
R/W W1 W0 A12 A11 A10
Figure 33. Serial Port Interface Timing Diagram
A9 A8 A7
Rev. 0 | Page 20 of 28
D5 D4 D3 D2 D1 D0
DON’T CARE
DON’T CARE
07101-027
Page 21
AD9230-11
Table 11. Serial Timing Definitions
Parameter Timing (minimum, ns) Description
tDS 5 Setup time between the data and the rising edge of SCLK
tDH 2 Hold time between the data and the rising edge of SCLK
t
40 Period of the clock
CLK
tS 5 Setup time between CSB and SCLK
tH 2 Hold time between CSB and SCLK
tHI 16 Minimum period that SCLK should be in a logic high state
tLO 16 Minimum period that SCLK should be in a logic low state
t
1
EN_SDIO
t
5
DIS_SDIO
Table 12. Output Data Format
Input (V) Condition (V)
VIN+ − VIN− < 0.62 0000 0000 000 1000 0000 000 1
VIN+ − VIN− = 0.62 0000 0000 000 1000 0000 000 0
VIN+ − VIN− = 0 0000 0000 000 0000 0000 000 0
VIN+ − VIN− = 0.62 1111 1111 111 0111 1111 111 0
VIN+ − VIN− > 0.62 + 0.5 LSB 1111 1111 111 0111 1111 111 1
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 33)
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 33)
Offset Binary Output Mode
D10 to D0
Twos Complement Mode
D10 to D0 OR
Rev. 0 | Page 21 of 28
Page 22
AD9230-11
MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map table has eight address locations.
The memory map is roughly divided into three sections: chip
configuration register map (Address 0x00 to Address 0x02),
transfer register map (Address 0xFF), and ADC functions map
(Address 0x08 to Address 0x2A).
The Addr. (Hex) column of the memory map indicates the
register address in hexadecimal, and the Default Value (Hex)
column shows the default hexadecimal value that is already
written into the register. The Bit 7 (MSB) column is the start of
the default hexadecimal value given. For example, Hexadecimal
Address 0x09, the clock register, has a hexadecimal default value
of 0x01. This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0,
Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. The
default value enables the duty cycle stabilizer. Overwriting this
default so that Bit 0 = 0 disables the duty cycle stabilizer. For more
information on this and other functions, consult the AN-877
Application Note, Interfacing to High Speed ADCs via SPI, at
www.analog.com.
RESERVED LOCATIONS
Undefined memory locations should not be written to other
than their default values suggested in this data sheet. Addresses
that have values marked as 0 should be considered reserved and
have a 0 written into their registers during power-up.
DEFAULT VALUES
Coming out of reset, critical registers are preloaded with default
values. These values are indicated in Tab le 1 3 . Other registers
do not have default values and retain the previous value when
exiting reset.
LOGIC LEVELS
An explanation of logic level terminology follows: “bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
TRANSFER REGISTER MAP
Address 0x08 to Address 0x18 are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer
bit. This allows these registers to be updated internally and
simultaneously when the transfer bit is set. The internal update
takes place when the transfer bit is set, and the bit autoclears.
Table 13. Memory Map Register
Addr.
(Hex)
Chip Configuration Registers
0x00 chip_port_config 0 LSB
0x01 chip_id 8-bit chip ID, Bits[7:0]
0x02 chip_grade 0 0 0 Speed grade:
Transfer Register
0xFF device_update 0 0 0 0 0 0 0 SW
Register Name
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
first
Soft
reset
1 1 Soft
reset
AD9230-11 = 0x0C
X X X Read-
11 = 200 MSPS
LSB first 0 0x18 The nibbles should
Bit 0
(LSB)
transfer
Default
Value
(Hex)
Readonly
only
0x00 Synchronously
Notes/
Comments
be mirrored by the
user so that LSB-or
MSB-first mode
registers correctly,
regardless of shift
mode.
Default is unique
chip ID, different
for each device.
This is a read-only
register.
Child ID used to
differentiate
graded devices.
transfers data from
the master shift
register to the
slave.
Rev. 0 | Page 22 of 28
Page 23
AD9230-11
Default
Addr.
(Hex) Register Name
ADC Functions
0x08 modes 0 0 PWDN:
0x09 clock 0 0 0 0 0 0 0 Duty
0x0D test_io 0 0 Reset
0x0F ain_config 0 0 0 0 0 Analog
0x14 output_mode 0 0 0 Output
0x15 output_adjust 0 0 0 0 LVDS
16 output_phase Output
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
0 0 Internal power-down mode:
000 = normal (power-up, default)
001 = full power-down
010 = standby
011 = normal (power-up)
Note: external PWDN pin
overrides this setting
Output test mode:
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checker board output
0101 = PN 23 sequence
0110 = PN 9
0111 = one/zero word toggle
1000 = unused
1001 = unused
1010 = unused
1011 = unused
1100 = unused
(Format determined by output_mode)
CML
input
disable:
1 = on
0 = off
(default)
Output
invert:
1 = on
0 = off
(default)
enable:
1 = on
0 = off
(default)
Data format select:
00 = offset binary
(default)
01 = twos
complement
10 = gray code
LVDS fine adjust:
001 = 3.50 mA
010 = 3.25 mA
011 = 3.00 mA
100 = 2.75 mA
101 = 2.50 mA
110 = 2.25 mA
111 = 2.00 mA
clock
polarity
1 =
inverted
0 =
normal
(default)
0 = full
(default)
1 =
standby
Reset
PN23
gen:
1 = on
0 = off
(default)
0 0 0 0 0 0 0x03
PN9 gen:
1 = on
0 = off
(default)
enable:
0 =
enable
(default)
1 =
disable
DDR:
1 =
enabled
0 =
disabled
(default)
course
adjust:
0 =
3.5 mA
(default)
1 =
2.0 mA
Bit 0
(LSB)
cycle
stabilizer:
0 =
disabled
1 =
enabled
(default)
0 0x00
Value
(Hex)
0x00 Determines various
0x01
0x00 When this register
0x00
0x00
Notes/
Comments
generic modes of
chip operation.
is set, the test data
is placed on the
output pins in
place of normal
data.
Rev. 0 | Page 23 of 28
Page 24
AD9230-11
Addr.
(Hex) Register Name
0x17 flex_output_delay Output
0x18 flex_vref 0 0 0 Input voltage range setting:
0x2A ovr_config 0 0 0 0 0 0 OR
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
delay
enable:
0 =
enable
1 =
disable
0 0 Output clock delay:
00000 = 0.1 ns
00001 = 0.2 ns
00010 = 0.3 ns
…
11101 = 3.0 ns
11110 = 3.1 ns
11111 = 3.2 ns
10000 = 0.98 V
10001 =1.00 V
10010 = 1.02 V
10011 =1.04 V
…
11111 = 1.23 V
00000 = 1.25 V
00001 = 1.27 V
…
01110 = 1.48 V
01111 = 1.50 V
position
(DDR
mode
only):
0 = Pin 9,
Pin 10
1 =
Pin 21,
Pin 22
Bit 0
(LSB)
OR
enable:
1 = on
(default)
0 = off
Default
Value
(Hex)
0
0
0x01
Notes/
Comments
Rev. 0 | Page 24 of 28
Page 25
AD9230-11
0
0
OUTLINE DIMENSIONS
0.30
0.23
0.18
PIN 1
56
INDICATOR
1
BSC SQ
PIN 1
INDICATO R
8.00
0.60 MAX
0.60 MAX
43
42
4.45
4.30 SQ
4.15
14
15
0.30 MIN
100808-A
1.00
.85
.80
SEATING
PLANE
12° MAX
TOP
VIEW
0.80 MAX
0.65 TYP
0.50 BSC
COMPLIANT TO JEDEC STANDARDS MO-220-VLL D-2
7.75
BSC SQ
0.20 REF
0.50
0.40
0.30
0.05 MAX
0.02 NOM
COPLANARITY
0.08
(BOTTOM VIEW)
29
28
EXPOSED
PAD
6.50
REF
FOR PROPER CONNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DES CRIPTIONS
SECTION O F THIS DAT A SHEET.
Figure 34. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
8 mm × 8 mm Body, Very Thin Quad
(CP-56-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9230BCPZ11-200
AD923011-200EBZ
1
Z = RoHS Compliant Part.
1
−40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-2
1
LVDS Evaluation Board
Rev. 0 | Page 25 of 28
Page 26
AD9230-11
NOTES
Rev. 0 | Page 26 of 28
Page 27
AD9230-11
NOTES
Rev. 0 | Page 27 of 28
Page 28
AD9230-11
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07101-0-10/08(0)
Rev. 0 | Page 28 of 28
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