Datasheet AD9229 Datasheet (Analog Devices)

Bit, 50/65 MSPS

Serial LVDS 3V A/D Converter

Rev. PrF 10/06/2003

Quad 12-

Preliminary Technical Data AD9229

FEATURES

• Four ADCs in one package

• Serial LVDS digital output data rates (ANSI-644)

• Data clock output provided

• On Chip Reference and SHA

• SNR = 70 dB at Fin up to Nyquist

• Excellent Linearity:

− DNL = ±0.3 LSB (Typical)

− INL = ±0.6 LSB (Typical)

• 500 MHz full power analog bandwidth

• Per Channel Core Power Dissipation = 270mW at 65MSPS /

200mW at 50MSPS

• 1 Vpp – 2 Vpp input voltage range

• +3.0 V supply operation

• Power down mode

APPLICATIONS

• Digital beam forming systems in ultrasound

• Wireless and wired broadband communications

• Communications test equipment

• Radar and satellite imaging sub-systems

PRODUCT DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

AVDD

VIN+A

VIN-A

VIN+B

VIN-B

VIN+C

VIN-C

VIN+D

VIN-D

VREF

SENSE

REFT

REFB

Ref

Select

Figure 1. Functional Block Diagram

signal a new output byte. Power down is supported and consumes
less than 3mW when enabled.

PDWN

AD9229

SHA

SHA

SHA

SHA

+

0.5 V

-

AGND

Pipeline

ADC

Pipeline

ADC

Pipeline

ADC

Pipeline

ADC

LVDSBIAS

DRVDD

12

12

12

12

Data Rate

Multiplier

Serial
LVDS

Serial
LVDS

Serial
LVDS

Serial
LVDS

CLK

DRGND

D1+A
D1-A

D1+B
D1-B

D1+C
D1-C

D1+D
D1-D

FCO+
FCO-

DCO+

DCO+
DCO-

DCO-

The AD9229 is a quad 12-bit monolithic sampling analog–to–
digital converter with an on–chip track–and–hold circuit and is
designed for low cost, low power, small size and ease of use. The
product operates up to a 65 MSPS conversion rate and is optimized
for outstanding dynamic performance where a small package size is
critical.

The ADC requires a single+3.0 V power supply and a TTL/CMOS
compatible sample rate clock for full performance operation. No
external reference or driver components are required for many
applications. A separate output power supply pin supports LVDS
compatible serial digital output levels.

The ADC automatically multiplies up the sample rate clock for the
appropriate LVDS serial data rate. An MSB trigger is provided to

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its
use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices. Trademarks and registered trademarks are the property
of their respective companies.

Fabricated on an advanced CMOS process, the AD9229 is available
in a 48-LFCSP package specified over the industrial temperature
range (–40°C to +85°C).

PRODUCT HIGHLIGHTS

1. Four analog-to-digital converters are contained in one small,
space saving package.

2. A Data Clock Output (DCO) is provided which operates up to
390 MHz.

3. The outputs of each ADC are serialized with a maximum data
output rate of 780 Mbps (12-bits x 65 MSPS).

4. The AD9229 operates from a single +3.0 V analog power
supply.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD9229 Preliminary Technical Data

TABLE OF CONTENTS

AD9229—Specifications ........................................................................3

DIGITAL SPECIFICATIONS...........................................................4

AC SPECIFICATIONS.......................................................................4

SWITCHING SPECIFICATIONS....................................................5

EXPLANATION OF TEST LEVELS................................................5

Absolute Maximum Ratings..................................................................6

EQuivalent circuits..................................................................................7

TYPICAL PERFORMANCE CHARACTERISTICS.........................8

Theory of Operation.............................................................................11

REVISION HISTORY

Revision PrA: Initial Version

Analog Inputs....................................................................................11

Voltage Reference..............................................................................11

Digital Outputs..................................................................................11

Timing ................................................................................................11

PLL......................................................................................................11

Pin Function Descriptions ...................................................................12

Pin Configurations................................................................................13

Timing Diagram....................................................................................14

Ordering Guide.................................................................................15

Revision PrB: Added Definition and Theory of Operation sections, updated Pin Configurations

Revision PrC: Deleted demux outputs

Revision PrD: Added Pin Info, Package Info

Revision PrE: Ch. 3.3V to 3.0V for supply, Updated Sinad spec typo, Added analog typical Cin, Overange Recovery Time, Latency

Revision PrF: Added 50MSPS Grade, Removed Clk-, Updated Power, SNR,LVDS Rset, Tpd Estimates, Added Equiv Ckts, Added FFT, VREF
figure, Corrected FCO, DCO polarity timing

Rev. PrF | Page 2 of 15 Oct. 6, 2003

Preliminary Technical Data AD9229

AD9229—SPECIFICATIONS1

AVDD = 3.0V, DRVDD = 3.0V; INTERNAL REFERENCE; DIFFERENTIAL ANALOG INPUTS,MAXIMUM SAMPLE RATE,T
T

, UNLESS OTHERWISE NOTED

MAX

Parameter

Temp Test

Level

AD9229BCP-50

Min Typ Max

AD9229BCP-65

Min Typ Max

MIN

TO

Unit

RESOLUTION 12 12 Bits

ACCURACY

No Missing Codes Full VI Guaran

teed
Offset Error
Gain Error

Offset Matching
Gain Matching2
Differential Nonlinearity (DNL)

25°C
25°C
25°C
25°C
25°C

I
I

± 0.5

± 0.5

I mV
I % FS
I

± 0.3

Guaran

teed

± 0.5
± 0.5

± 0.3

mV
%FS

LSB
Full VI LSB
Integral Nonlinearity (INL)

25°C

I

± 0.6

± 0.6

LSB
Full VI LSB

TEMPERATURE
DRIFT

REFERENCE

Offset Error Full V
Gain Error2 Full V
Reference Full V
Internal Reference Voltage

25°C

I 0.5 0.5 V

Output Current Full V uA
Input Current Full V uA
Input Resistance Full V

ppm/°C
ppm/°C
ppm/°C

kΩ

Differential Input Voltage Range 1 –2 1 –2 Vpp

ANALOG INPUTS

Common Mode Voltage Full V 1.5 1.5 V
Input Capacitance Full V 7 7 pF
Analog Bandwidth, Full Power Full V 500 500 MHz
AVDD Full IV 2.7

DRVDD Full IV 2.7

3.0

3.0

3.6 2.7

3.6 2.7

3.0

3.0

3.6 V

3.6 V

Power Dissipation3 Full VI 940 1250 mW

POWER SUPPLY

Power Down Dissipation Full VI <3 <3 mW
Power Supply Rejection Ratio (PSRR)

25°C

I mV/V

IAVDD3 Full VI 268 367 mA
IDRVDD3 Full VI 28 30 mA

IPLLVDD3 Full VI 18 19

Table 1: DC Specifications

1

Specifications subject to change without notice

2

Gain error and gain temperature coefficients are based on the ADC only (with a fixed 0.5 V external reference and a 1 V p-p differential analog input).

3

Power dissipation measured with rated encode and a dc analog input (Outputs Static, I

Rev. PrF | Page 3 of 15 Oct. 6, 2003

VDD

= 0.). I

VCC

and I

measured with TBD MHz analog input @ 0.5dBFS.

VDD

AD9229 Preliminary Technical Data

DIGITAL SPECIFICATIONS

AVDD = 3.0V, DRVDD = 3.0V

Parameter

VIH Full IV 2.0 2.0 V

CLOCK INPUT

PDWN INPUT

DIGITAL OUTPUTS
(LVDS Mode)*

*

LVDS Rset resistor = 3.6K, LVDS Output Termination Resistor= 100 Ohms.

VIL Full IV 0.8 0.8 V
Input Capacitance

Logic ‘1’ Voltage Full IV 2.0 2.0 V
Logic ‘0’ Voltage Full IV 0.8 0.8 V
Input Capacitance Full IV 2 2 PF
Differential Output Voltage

(VOD)
Output Offset Voltage (VOS) Full IV 1.125 1.375 1.125 1.375 V
Output Coding Full IV Offset Binary Offset Binary

Temp Test

25°C

Full IV 247 454 247 454 mV

Table 2: Digital Specifications

AC SPECIFICATIONS1

AD9229BCP-50

Level

IV 2 2 pF

Min Typ Max

AD9229BCP-65

Min Typ Max

Unit

AVDD = 3.0 V, DRVDD = 3.0V; INTERNAL REFERENCE; DIFFERENTIAL ANALOG INPUTS,MAXIMUM SAMPLE RATE,T
T

, UNLESS OTHERWISE NOTED

MAX

Parameter Temp Test

Level

SIGNAL TO NOISE
RATIO (SNR) –
Without
Harmonics

SIGNAL TO NOISE
RATIO (SINAD) –
With Harmonics

EFFECTIVE
NUMBER OF BITS
(ENOB)

SPURIOUS FREE
DYNAMIC RANGE
(SFDR)

SECOND AND
THIRD
HARMONIC
DISTORTION

INTERMOD
DISTORTION
(IMD)

1

SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 1 Vpp full-scale input range.

fIN= 10.3 MHz
fIN= 19.6 MHz
fIN= 32.5 MHz
fIN= 51 MHz
fIN= 10.3 MHz
fIN= 19.6 MHz
fIN= 32.5 MHz
fIN= 51 MHz
fIN= 10.3 MHz
fIN= 19.6 MHz
fIN= 32.5 MHz
fIN= 51 MHz
fIN= 10.3 MHz
fIN= 19.6 MHz
fIN= 32.5 MHz
fIN= 51 MHz
fIN= 10.3 MHz
fIN= 19.6 MHz
fIN= 32.5 MHz
fIN= 51 MHz
f

= 19 MHz, f

IN1

f

= xx MHz, f

IN1

= 20 MHz

IN2

= xx MHz

IN2

25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C

V 70.5 70.5 dB
V dB

I 69.7 69.7 dB
V dB
V 70.3 70.3 dB
V dB

I 69.5 69.5 dB
V dB
V Bits
V Bits

I Bits
V Bits
V dB
V 85 85 dB

I dB
V dB
V dBc
V -85 -85 dBc

I dBc
V dBc
V -85 -85 dBc TWO TONE
V dBc

AD9229BCP-50

Min Typ Max

AD9229BCP-65

Min Typ Max

TO

MIN

Unit

Rev. PrF | Page 4 of 15 Oct. 6, 2003

Preliminary Technical Data AD9229

Parameter Temp Test

Level

CROSSTALK Full V -80 -80 dB

Table 3: AC Specifications

SWITCHING SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V; DIFFERENTIAL ENCODE INPUT

AD9229BCP-50

Min Typ Max

AD9229BCP-65

Min Typ Max

Unit

Parameter Temp Test

Clock Rate Full VI 10 50 10 65 MSPS

CLOCK

OUTPUT
PARAMETERS IN
LVDS MODE

APERTURE
Out of Range

Recovery Time

Clock Pulse Width High (tEH) Full IV ns
Clock Pulse Width Low (tEL) Full IV ns
Valid Time (tV)1 Full VI ns
Propagation Delay (tPD) 1 Full VI 5 5 ns
MSB Propagation Delay (t
Rise Time (tR) (20% to 80%) Full V ns
Fall Time (tF) (20% to 80%) Full V ns
DCO Propagation Delay (t
Data to DCO Skew (tPD – t
Pipeline Latency Full VI 9 9 cycles
Aperture Delay (tA)

Aperture Uncertainty (Jitter)
Full IV 2 2 cycles

) 1 Full VI 5 5 ns

MSB

) Full VI 5 5 ns

CPD

) Full IV ns

CPD

EXPLANATION OF TEST LEVELS

TEST LEVEL

I 100% production tested.

AD9229BCP-50

Level

25°C
25°C

Table 4: Switching Specifications

V ps
V <1 <1 ps rms

Min Typ Max

AD9229BCP-65

Min Typ Max

Unit

II 100% production tested at +25°C and guaranteed by design and characterization at specified temperatures.

III Sample tested only.

IV Parameter is guaranteed by design and characterization testing.

V Parameter is a typical value only.

VI 100% production tested at +25°C and guaranteed by design and characterization for industrial temperature range.

1

t

and t

are measured from the transition points of the CLK input to the 50%/50% levels of the digital outputs swing. The digital output load during test is

V

PD

not to exceed an ac load of 5 pF or a dc current of ±40 µA. Rise and fall times measured from 20% to 80%.

Rev. PrF | Page 5 of 15 Oct. 6, 2003

AD9229 Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

Parameter Rating

AVDD Voltage 3.9V
DRVDD Voltage 3.9V
Analog Input Voltage

Electrical

Environmental

Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Analog Input Current
Digital Input Voltage
Digital Output Current
VREF Input Voltage
Operating Temperature Range (Ambient)

Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
Maximum Case Temperature
Storage Temperature Range (Ambient)

Table 5: Absolute Maximum Ratings

-40°C to +85°C
150°C

Rev. PrF | Page 6 of 15 Oct. 6, 2003

Preliminary Technical Data AD9229

EQUIVALENT CIRCUITS

AVDD

ANALOG IN

V-

DATAOUT-,
DCO-,FCO-

V+

DRVDD

3.5MA

V+

DATAOUT+,
DCO+,FCO+

V-

Figure 2 Analog Inputs

3.5MA

AVDDAVDD

Figure 4 LVDS Outputs

AVDDAVDD

CLK

Figure 3 Clock Input

PDWN

Figure 5 PDWN Input

Rev. PrF | Page 7 of 15 Oct. 6, 2003

TYPICAL PERFORMANCE CHARACTERISTICS

0

-20

-40

-60

dB

-80

-100

-120
0 5 10 15 20 25 30

SNR = 68.7 dB
SINAD = 68.5 dB
SFDR = 88.6 dB

MHz

Measured FFT Performance 32MHz Ain at 65MSPS

Preliminary Technical Data AD9229

02.6

−

−

Definitions

ANALOG BANDWIDTH

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.

APERTURE DELAY

The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input is
sampled.

APERTURE UNCERTAINTY (JITTER)

The sample-to-sample variation in aperture delay.

CROSSTALK

Coupling onto one channel being driven by a low level (-40 dBFS)
signal when the adjacent interfering channel is driven by a full­scale signal.

DIFFERENTIAL ANALOG INPUT RESISTANCE,
DIFFERENTIAL ANALOG INPUT CAPACITANCE, AND
DIFFERENTIAL ANALOG INPUT IMPEDANCE

ENCODE PULSE WIDTH/DUTY CYCLE

Pulse width high is the minimum amount of time that the
ENCODE pulse should be left in logic “1” state to achieve rated
performance; pulse width low is the minimum time ENCODE
pulse should be left in low state. See timing implications of
changing tENCH in text. At a give clock rate, these specs define an
acceptable Encode duty cycle.

FULL SCALE INPUT POWER

Expressed in dBm. Computed using the following equation:

2



V

Fullscale




Power

Fullscale

=

log10

Z



001.






GAIN ERROR

Gain error is the difference between the measured and ideal full
scale input voltage range of the worst ADC.

Input



rms









The real and complex impedances measured at each analog input
port. The resistance is measured statically and the capacitance and
differential input impedances are measured with a network
analyzer.

DIFFERENTIAL ANALOG INPUT VOLTAGE RANGE

The peak to peak differential voltage that must be applied to the
converter to generate a full scale response. Peak differential voltage
is computed by observing the voltage on a single pin and
subtracting the voltage from the other pin, which is 180 degrees out
of phase. Peak to peak differential is computed by rotating the
inputs phase 180 degrees and taking the peak measurement again.
Then the difference is computed between both peak measurements.

DIFFERENTIAL NONLINEARITY

The deviation of any code width from an ideal 1 LSB step.

EFFECTIVE NUMBER OF BITS

The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:

ENOB

=

MEASURED

76.1 dBSNR

GAIN MATCHING

Expressed in %FSR. Computed using the following equation:

minmax

=

ngGainMatchi






where FSR
FSR

min

HARMONIC DISTORTION, SECOND

The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.

HARMONIC DISTORTION, THIRD

The ratio of the rms signal amplitude to the rms value of the third
harmonic component, reported in dBc.

INTEGRAL NONLINEARITY

The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.

is the most positive gain error of the ADCs and

max

is the most negative gain error of the ADCs.

FSRFSR

+

2

minmax

FSRFSR






%100*

Rev. PrF | Page 9 of 15 Oct. 6, 2003

AD9229 Preliminary Technical Data

−

=

MINIMUM CONVERSION RATE

The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.

the rms value of the sum of all other spectral components,
including harmonics but excluding dc.

SIGNAL-TO-NOISE RATIO (WITHOUT HARMONICS)

MAXIMUM CONVERSION RATE

The encode rate at which parametric testing is performed.

OFFSET ERROR

Offset error is the difference between the measured and ideal
voltage at the analog input that produces the midscale code at the
outputs. Offset error is given for the worst ADC.

OFFSET MATCHING

Expressed in mV. Computed using the following equation:

minmax OFFOFFhingOffsetMatc

where OFF
most negative offset error.

is the most positive offset error and OFF

max

min

is the

OUTPUT PROPAGATION DELAY

The delay between a differential crossing of CLK+ and CLK- and
the time when all output data bits are within valid logic levels.

NOISE (FOR ANY RANGE WITHIN THE ADC)

The ratio of the rms signal amplitude (set at 1 dB below full scale)
to the rms value of the sum of all other spectral components,
excluding the first five harmonics and dc.

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

The ratio of the rms signal amplitude to the rms value of the peak
spurious spectral component. The peak spurious component may
or may not be a harmonic. It also may be reported in dBc (i.e.,
degrades as signal level is lowered) or dBFS (i.e., always related back
to converter full scale).

TWO-TONE INTERMODULATION DISTORTION
REJECTION

The ratio of the rms value of either input tone to the rms value of
the worst third order intermodulation product; reported in dBc.

TWO-TONE SFDR

The ratio of the rms value of either input tone to the rms value of
the peak spurious component. The peak spurious component may
or may not be an IMD product. It also may be reported in dBc (i.e.,
degrades as signal level is lowered) or in dBFS (i.e., always relates
back to converter full scale).

−−




=

noise

Where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value for the particular
input level and Signal is the signal level within the ADC reported in
dB below full scale. This value includes both thermal and
quantization noise.

ZV



10*001.*

SignalSNRFS

10



dBFSdBcdBm




POWER SUPPLY REJECTION RATIO

The ratio of a change in input offset voltage to a change in power
supply voltage.

SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)

The ratio of the rms signal amplitude (set 1 dB below full scale) to

WORST OTHER SPUR

The ratio of the rms signal amplitude to the rms value of the worst
spurious component (excluding the second and third harmonic)
reported in dBc.

TRANSIENT RESPONSE TIME

Transient response time is defined as the time it takes for the ADC
to reacquire the analog input after a transient from 10% above
negative full scale to 10% below positive full scale.

OUT-OF-RANGE RECOVERY TIME

Out of range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above positive
full scale to 10% above negative full scale, or from 10% below
negative full scale to 10% below positive full scale.

Rev. PrF | Page 10 of 15 Oct. 6, 2003

Preliminary Technical Data AD9229

AD9229

10 uF

uF 10

uF

THEORY OF OPERATION

Analog Inputs

recommended to keep the trace length no longer than 1–2 inches
and to keep differential output trace lengths as equal as possible.

For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors will be reduced by the
common-mode rejection of the A/D.

Voltage Reference

The AD9229 has a stable and accurate reference voltage on chip,
which sets the full-scale voltage at the analog input channels.
Internal reference mode is established by grounding the SENSE pin.
(Recommended decoupling capacitors shown below) The internal
reference can be bypassed by setting SENSE to AVDD and driving
VREF with an external 1V reference.

VINA

0.1 u F

SENSE

VINB

VREF

SELECT

LOGIC

CORE

ADC

REFT

0.1 uF

0.1

REFB

0.1 uF

0.5V

The format of the output data is offset binary.

Timing

Data from each A/D is serialized and provided on a separate
channel.

Two output clocks are provided to assist in capturing data from the
AD9229. The data clock out (DCO) is used to clock the output
data and is equal to 6 times the sample clock frequency. ( 390MHz
for 65MHz input clock) Data is clocked out of the AD9229 on the
rising and falling edges of DCO. The FCO clock signals the start of
a new serial word, the rising edge of FCO occurs at the start of an
MSB.

PLL

The AD9229 contains an internal PLL that is used to generate
internal clocking signals, if the PLL is unlocked, the data outputs
are static.

Internal Reference Mode Connection

Digital Outputs

The AD9229’s differential outputs conform to the ANSI-644 LVDS
standard. To set the LVDS bias current, place a resistor (RSET is
nominally equal to 3.6 kΩ) to ground at the LVDSBIAS pin. The
RSET resistor current (~ 1.2/RSET) is ratioed on-chip setting the
output current at each output equal to a nominal 3.5 mA. A 100 Ω
differential termination resistor placed at the LVDS receiver inputs
results in a nominal 350 mV swing at the receiver.

The AD9229’s LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments. Single
point-to-point net topologies are recommended with a 100 Ω
termination resistor as close to the receiver as possible. It is

Rev. PrF | Page 11 of 15 Oct. 6, 2003

AD9229 Preliminary Technical Data

PIN FUNCTION DESCRIPTIONS

Pin No. Name Description Pin No. Name Description

8,16,21,

29

9,12,15,

22,25,28,

31

2,35 DRVDD
1,36 DRGND Digital Ground 41 D-B ADC B Complement Digital Output

32 PLLVDD
33 PLLGND PLL Ground 39 D-C ADC C Complement Digital Output

30 CLK Input Clock 38 D+D ADC D True Digital Output
18 VREF Voltage Reference Input/Output 37 D1-D ADC D Complement Digital Output
17 SENSE Reference Mode Selection 48 DCO+ Data Clock Output – True
20 REFT Differential Reference (Positive) 47 DCO- Data Clock Output – Complement
19 REFB Differential Reference (Negative) 46 FCO+ Frame Clock Indicator – True Output
10 VIN+A ADC A Analog Input – True 45 FCO- Frame Clock Indicator – Complement Output
11 VIN-A ADC A Analog Input – Complement 34 LVDSBIAS LVDS Output Current Set Resistor Pin
14 VIN+B ADC B Analog Input – True 7 PDWN Power Down Selection ( Logic ‘1’ = Power Down )
13 VIN-B ADC B Analog Input – Complement 3,4,5,6 DNC Do Not Connect
23 VIN+C ADC C Analog Input – True
24 VIN-C ADC C Analog Input – Complement
27 VIN+D ADC D Analog Input – True
26 VIN-D ADC D Analog Input – Complement

AVDD

AGND Analog Ground 43 D-A ADC A Complement Digital Output

3.0 V Analog Supply

3.0 V Digital Output Supply

PLL 3.0V Supply

Table 6: Pin Function Descriptions

44 D+A ADC A True Digital Output

42 D+B ADC B True Digital Output

40 D+C ADC C True Digital Output

Rev. PrF | Page 12 of 15 Oct. 6, 2003

Preliminary Technical Data AD9229

PIN CONFIGURATIONS

DCO+

DCO-

FCO+

FCO-

D+A

D-A

D+B

D-B

D+C

D-C

D+D

D-D

DRGND
DRVDD

DNC
DNC
DNC
DNC

PDWN

AVDD
AGND
VIN+A

VIN-A
AGND

1

12

13

3748

36

AD9229

25

DRGND
DRVDD

LVDSBIAS

PLLGND
PLLVDD

AGND

CLK
AVDD
AGND
VIN+D

VIN-D
AGND

24

VIN-B

AGND

VIN+B

VREF

AVDD

SENSE

REFT

REFB

AVDD

VIN-C

AGND

VIN+C

Rev. PrF | Page 13 of 15 Oct. 6, 2003

AD9229 Preliminary Technical Data

TIMING DIAGRAM

N-1

AIN

CLK

Data

Out

DCO+

DCO-

FCO-

FCO+

t

A

t

EH

t

PD

MSB

LSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1

t

CPD

t

FPD

t

EL

LSB

N

MSB

Figure 6: Serial LVDS Outputs

NOTE : Latency = 9 cycles

Rev. PrF | Page 14 of 15 Oct. 6, 2003

Preliminary Technical Data AD9229

OUTLINE DIMENSIONS

Figure 7

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprietary
ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges.
Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Ordering Guide

Model Temperature Range Description

AD9229BCP-50
AD9229BCP-65
AD9229/PCB 25°C (Ambient) Evaluation Board ( Supplied with –65 Grade )

© 2002 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
Printed in the U.S.A. C02959-0-11/02(0)

-40°C to +85°C (Ambient)

-40°C to +85°C (Ambient)

48-LFCSP
48-LFCSP

Table 7: Ordering Guide

Rev. PrF | Page 15 of 15 Oct. 6, 2003