Datasheet AD9225 Datasheet (Analog Devices)

Page 1
Complete 12-Bit, 25 MSPS
a
FEATURES Monolithic 12-Bit, 25 MSPS A/D Converter Low Power Dissipation: 280 mW Single +5 V Supply No Missing Codes Guaranteed Differential Nonlinearity Error: 0.4 LSB Complete On-Chip Sample-and-Hold Amplifier and
Voltage Reference Signal-to-Noise and Distortion Ratio: 71 dB Spurious-Free Dynamic Range: –85 dB Out-of-Range Indicator Straight Binary Output Data 28-Lead SOIC 28-Lead SSOP Compatible with 3 V Logic
PRODUCT DESCRIPTION
The AD9225 is a monolithic, single supply, 12-bit, 25 MSPS, analog-to-digital converter with an on-chip, high performance sample-and-hold amplifier and voltage reference. The AD9225 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 25 MSPS data rates, and guarantees no missing codes over the full operat­ing temperature range.
The AD9225 combines a low cost high speed CMOS process and a novel architecture to achieve the resolution and speed of existing bipolar implementations at a fraction of the power consumption and cost.
The input of the AD9225 allows for easy interfacing to both imaging and communications systems. With a truly differential input structure, the user can select a variety of input ranges and offsets including single-ended applications. The dynamic perfor­mance is excellent.
The sample-and-hold (SHA) amplifier is well suited for both multiplexed systems that switch full-scale voltage levels in suc­cessive channels and sampling single-channel inputs at frequen­cies up to and well beyond the Nyquist rate.
The AD9225’s wideband input combined with the power and cost savings over previously available monolithics, is suitable for applications in communications, imaging and medical ultrasound.
The AD9225 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application.
Monolithic A/D Converter
AD9225
FUNCTIONAL BLOCK DIAGRAM
AVDDCLK
SHA
VINA VINB
CAPT CAPB
VREF
SENSE
MODE
SELECT
MDAC1
GAIN = 16
5
5
REFCOM
MDAC2
GAIN = 4
A/DA/D
3
DIGITAL CORRECTION LOGIC
OUTPUT BUFFERS
1V
AVSS
A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range signal indicates an overflow condition that can be used with the most significant bit to deter­mine low or high overflow.
PRODUCT HIGHLIGHTS
The AD9225 is fabricated on a very cost effective CMOS process. High-speed precision analog circuits are now combined with high density logic circuits.
The AD9225 offers a complete single-chip sampling 12-bit, 25 MSPS analog-to-digital conversion function in 28-lead SOIC and SSOP packages.
Low Power—The AD9225 at 280 mW consumes a fraction of the power of presently available in existing monolithic solutions.
On-Board Sample-and-Hold (SHA)—The versatile SHA input can be configured for either single-ended or differential inputs.
Out of Range (OTR)—The OTR output bit indicates when the input signal is beyond the AD9225’s input range.
Single Supply—The AD9225 uses a single +5 V power supply simplifying system power supply design. It also features a sepa­rate digital driven supply line to accommodate 3 V and 5 V logic families.
Pin Compatibility—The AD9225 is pin compatible with the AD9220, AD9221, AD9223 and AD9224 ADCs.
DRVDD
MDAC3
GAIN = 4
3
12
A/D
AD9225
DRVSS
3
3
CML
A/D
4
OTR BIT 1
(MSB) BIT 12
(LSB)
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998
Page 2
AD9225–SPECIFICATIONS
DC SPECIFICATIONS
(AVDD = +5 V, DRVDD = +5 V, f
= 25 MSPS, VREF = 2.0 V, VINB = 2.5 V dc, T
SAMPLE
MIN
to T
unless otherwise noted)
MAX
Parameter Min Typ Max Units
RESOLUTION 12 Bits
MAX CONVERSION RATE 25 MHz
INPUT REFERRED NOISE
VREF = 1.0 V 0.35 LSB rms VREF = 2.0 V 0.17 LSB rms
ACCURACY
Integral Nonlinearity (INL) ±1.0 ±2.5 LSB Differential Nonlinearity (DNL) ±0.4 ±1.0 LSB
No Missing Codes 12 Bits Guaranteed
Zero Error (@ +25°C) ±0.3 ±0.6 % FSR Gain Error (@ +25°C) Gain Error (@ +25°C)
1
2
±0.5 ±2.2 % FSR ±0.4 ±1.7 % FSR
TEMPERATURE DRIFT
Zero Error ±2 ppm/°C
Gain Error Gain Error
1
2
±26 ppm/°C ±0.4 ppm/°C
POWER SUPPLY REJECTION
AVDD (+5 V ± 0.25 V) ±0.1 ±0.35 % FSR
ANALOG INPUT
Input Span 2 V p-p
4 V p-p
Input (VINA or VINB) Range 0 V
AVDD V
Input Capacitance 10 pF
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode) 1.0 V
Output Voltage Tolerance (1 V Mode) ±5 ±17 mV
Output Voltage (2.0 V Mode) 2.0 V
Output Voltage Tolerance (2.0 V Mode) ±10 ±35 mV
Output Current (Available for External Loads) 1.0 mA Load Regulation
3
1.0 3.4 mV
REFERENCE INPUT RESISTANCE 8 k
POWER SUPPLIES
Supply Voltages
AVDD 4.75 5 5.25 V (±5% AVDD DRVDD 2.85 5.25 V (±5% DRVDD
Supply Currents
IAVDD 65 72.5 mA IDRVDD 2.0 4.0 mA
POWER CONSUMPTION
External Reference 280 310 mW (VREF = 1 V)
335 373 mW (VREF = 2 V)
Internal Reference 290 mW (VREF = 1 V)
345 mW (VREF = 2 V)
NOTES
1
Includes internal voltage reference error.
2
Excludes internal voltage reference error.
3
Load regulation with 1 mA load current (in addition to that required by the AD9225).
Specifications subject to change without notice.
Operating)
Operating)
–2–
REV. A
Page 3
AD9225
AC SPECIFICATIONS
(AVDD = +5 V, DRVDD = +5 V, f
= 25 MSPS, VREF = 2.0 V, T
SAMPLE
MIN
to T
, Differential Input unless otherwise noted)
MAX
Parameter Min Typ Max Units
SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D)
= 2.5 MHz 67.4 70.7 dB
f
INPUT
f
= 10 MHz 66.7 69.6 dB
INPUT
SIGNAL-TO-NOISE RATIO (SNR)
= 2.5 MHz 69.0 71 dB
f
INPUT
f
= 10 MHz 68.2 70 dB
INPUT
TOTAL HARMONIC DISTORTION (THD)
= 2.5 MHz –82 –72 dB
f
INPUT
f
= 10 MHz –81 –71.5 dB
INPUT
SPURIOUS FREE DYNAMIC RANGE
= 2.5 MHz 73 –85 dB
f
INPUT
f
= 10 MHz 72.5 –83 dB
INPUT
Full Power Bandwidth 105 MHz Small Signal Bandwidth 105 MHz Aperture Delay 1 ns Aperture Jitter 1 ps rms Acquisition to Full-Scale Step 10 ns
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
(AVDD = +5 V, DRVDD = +5 V, unless otherwise noted)
Parameters Symbol Min Typ Max Units
LOGIC INPUTS
High Level Input Voltage V Low Level Input Voltage V High Level Input Current (V Low Level Input Current (V
= DRVDD) I
IN
= 0 V) I
IN
Input Capacitance C
IH
IL
IH
IL
IN
+3.5 V
+1.0 V
–10 +10 µA –10 +10 µA
5pF
LOGIC OUTPUTS
High Level Output Voltage (I High Level Output Voltage (I Low Level Output Voltage (I Low Level Output Voltage (I Output Capacitance C
= 50 µA) V
OH
= 0.5 mA) V
OH
= 1.6 mA) V
OL
= 50 µA) V
OL
OH
OH
OL
OL
OUT
+4.5 V +2.4 V
+0.4 V +0.1 V
5pF
LOGIC OUTPUTS (with DRVDD = 3 V)
High Level Output Voltage (I High Level Output Voltage (I Low Level Output Voltage (I Low Level Output Voltage (I
Specifications subject to change without notice
= 50 µA) V
OH
= 0.5 mA) V
OH
= 1.6 mA) V
OL
= 50 µA) V
OL
.
OH
OH
OL
OL
+2.95 V +2.80 V
+0.4 V +0.05 V
(T
to T
SWITCHING SPECIFICATIONS
MIN
with AVDD = +5 V, DRVDD = +5 V, CL = 20 pF)
MAX
Parameters Symbol Min Typ Max Units
Clock Period CLOCK Pulsewidth High t CLOCK Pulsewidth Low t Output Delay t
1
t
C
CH
CL
OD
40 ns 18 ns 18 ns 13 ns
Pipeline Delay (Latency) 3 Clock Cycles
NOTES
1
The clock period may be extended to 1 ms without degradation in specified performance @ +25 °C.
Specifications subject to change without notice.
–3–REV. A
Page 4
AD9225
WARNING!
ESD SENSITIVE DEVICE
ANALOG
INPUT
INPUT
CLOCK
DATA
OUTPUT
S1
t
CH
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
With
Pin Name Respect to Min Max Units
AVDD AVSS –0.3 +6.5 V DRVDD DRVSS –0.3 +6.5 V AVSS DRVSS –0.3 +0.3 V AVDD DRVDD –6.5 +6.5 V REFCOM AVSS –0.3 +0.3 V CLK AVSS –0.3 AVDD + 0.3 V Digital Outputs DRVSS –0.3 DRVDD + 0.3 V VINA, VINB AVSS –0.3 AVDD + 0.3 V VREF AVSS –0.3 AVDD SENSE AVSS –0.3 AVDD CAPB, CAPT AVSS –0.3 AVDD
Junction Temperature +150 °C Storage Temperature –65 +150 °C Lead Temperature (10 sec) +300 °C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
S2
t
C
t
CL
S3
S4
t
OD
DATA 1
+ 0.3 V + 0.3 V + 0.3 V
PIN CONNECTION
28-Lead SOIC and SSOP
CLK
(LSB) BIT 12
BIT 11 BIT 10
BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2
(MSB) BIT 1
OTR
1 2 3 4 5 6
AD9225
7
TOP VIEW
(Not to Scale)
8
9 10 11 12 13 14
28
DRVDD
27
DRVSS
26
AVDD
25
AVSS
24
VINB
23
VINA
22
CML
21
CAPT
20
CAPB
19
REFCOM (AVSS)
18
VREF
17
SENSE
16
AVSS
15
AVDD
PIN FUNCTION DESCRIPTIONS
Pin Number Name Description
1 CLK Clock Input Pin 2 BIT 12 Least Significant Data Bit (LSB) 3–12 BIT 11–2 Data Output Bit 13 BIT 1 Most Significant Data Bit (MSB) 14 OTR Out of Range 15, 26 AVDD +5 V Analog Supply 16, 25 AVSS Analog Ground 17 SENSE Reference Select 18 VREF Input Span Select (Reference I/O) 19 REFCOM Reference Common
(AVSS) 20 CAPB Noise Reduction Pin 21 CAPT Noise Reduction Pin 22 CML Common-Mode Level (Midsupply) 23 VINA Analog Input Pin (+) 24 VINB Analog Input Pin (–) 27 DRVSS Digital Output Driver Ground 28 DRVDD +3 V to +5 V Digital Output
Driver Supply
ORDERING GUIDE
Model Temperature Range Package Descriptions Package Options
AD9225AR –40°C to +85°C 28-Lead Wide Body Small Outline R-28 AD9225ARS –40°C to +85°C 28-Lead Shrink Small Outline RS-28
AD9225-EB Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9225 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REV. A
Page 5
AD9225
DEFINITIONS OF SPECIFICATION INTEGRAL NONLINEARITY (INL)
INL refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as “negative full scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating ranges.
ZERO ERROR
The major carry transition should occur for an analog value 1/2 LSB below VINA = VINB. Zero error is defined as the deviation of the actual transition from that point.
GAIN ERROR
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.
TEMPERATURE DRIFT
The temperature drift for zero error and gain error specifies the
maximum change from the initial (+25°C) value to the value at
or T
T
MIN
POWER SUPPLY REJECTION
MAX
.
The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit.
APERTURE DELAY
Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD) RATIO
S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the num­ber of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N, the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com­ponents to the rms value of the measured input signal and is expressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D.
–5–REV. A
Page 6
AD9225
Typical Performance Characteristics
1.00
0.75
0.50
0.25
0.00
Title
–0.25
–0.50
–0.75
–1.00
0 4095511
75
70
65
1022 1533 2044 2555 3066 3577
Title
Figure 2. Typical DNL
20.5dB 2V INT REF
26dB 2V INT REF
(AVDD, DRVDD = +5 V, fS = 25 MHz (50% Duty Cycle) unless otherwise noted)
2.00
1.50
1.00
0.50
0
20.50
21.00
21.50
22.00
511
TITLE
1022 1533 2044 2555 3066 3577 40950
Figure 5. Typical INL
70
20.5dB INT 1V
65
60
26dB INT 1V
60
SINAD – dB
55
220dB 2V INT REF
50
1
FREQUENCY – MHz
10
Figure 3. SINAD vs. Input Frequency (Input Span = 4.0 V p-p, V
= 2.5 V Differential Input)
CM
–60
–65
–70
THD – dB
–75
–80
–85
220.0dB 2V INT REF
26.0dB 2V INT REF
20.5dB 2V INT REF
1
FREQUENCY – MHz
10
Figure 4. THD vs. Input Frequency (Input Span = 4.0 V p-p,
= 2.5 V Differential Input)
V
CM
55
SINAD – dB
50
45
220dB INT 1V
1
FREQUENCY – MHz
10
Figure 6. SINAD vs. Input Frequency (Input Span = 2 V p-p Differential Input)
–60
–65
–70
THD – dB
–75
–80
–85
220dB INT 1V
26dB INT 1V
20.5dB INT 1V
1
FREQUENCY – MHz
10
Figure 7. THD vs. Input Frequency (Input Span = 2 V p-p,
= 2.5 V Differential Input)
V
CM
–6–
REV. A
Page 7
AD9225
30
35
40
45
50
55
60
SNR AND SINAD – dBFS
65
70
75
–40 5–35 –30 –25 –20 –15 –10 –5 0
SNR INT 2V REF
SINAD INT 2V REF
AIN – dB
Figure 8. SNR/SINAD vs. AIN (Input Amplitude)
= 12.5 MHz, Input Span = 4.0 V p-p, VCM = 2.5 V
(F
IN
Differential Input)
–65
220.0dB 2V INT REF
–70
–75
–70
–75
–80
THD – dB
INT 1V REF
–85
–90
INT 2V REF
10
FREQUENCY – MHz
Figure 11. THD vs. Sample Rate, (AIN = –0.5 dB, VCM = 2.5 V, Input Span = 4.0 V p-p Differential Input)
75
20.5dB 2V INT REF
70
26.0dB 2V INT REF
65
THD – dB
26.0dB 2V INT REF
–80
–85
–90
1
FREQUENCY – MHz
20.5dB 2V INT REF
10
Figure 9. THD vs. Input Frequency (Input Span =
4.0 V p-p, V
ITS
H
= 2.5 V Single-Ended Input)
CM
246447
3299
N – 1 N
B
IN
4206
N + 1
Figure 10. “Grounded-Input” Histogram (Input Span = 40 V p-p)
SNR – dB
60
55
220.0dB 2V INT REF
50
1
FREQUENCY – MHz
10
Figure 12. SNR vs. Input Frequency (Input Span = 4.0 V p-p, V
= 2.5 V Single-Ended
CM
Input)
–7–REV. A
Page 8
AD9225
INTRODUCTION
The AD9225 is a high performance, complete single-supply 12­bit ADC. The analog input range of the AD9225 is highly flex­ible allowing for both single-ended or differential inputs of varying amplitudes that can be ac or dc coupled.
It utilizes a four-stage pipeline architecture with a wideband input sample-and-hold amplifier (SHA) implemented on a cost­effective CMOS process. Each stage of the pipeline, excluding the last stage, consists of a low resolution flash A/D connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier amplifies the difference be­tween the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash A/D.
The pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. This means that while the converter is capable of capturing a new input sample every clock cycle, it actually takes three clock cycles for the conversion to be fully processed and appear at the output. This latency is not a concern in most applications. The digital output, together with the out-of-range indicator (OTR), is latched into an output buffer to drive the output pins. The output drivers of the AD9225 can be configured to interface with +5 V or +3.3 V logic families.
The AD9225 uses both edges of the clock in its internal timing circuitry (see Figure 1 and specification page for exact timing requirements). The A/D samples the analog input on the rising edge of the clock input. During the clock low time (between the falling edge and rising edge of the clock), the input SHA is in the sample mode; during the clock high time it is in hold. Sys­tem disturbances just prior to the rising edge of the clock and/or excessive clock jitter may cause the input SHA to acquire the wrong value, and should be minimized.
ANALOG INPUT AND REFERENCE OVERVIEW
Figure 13 is a simplified model of the AD9225. It highlights the relationship between the analog inputs, VINA, VINB, and the reference voltage, VREF. Like the voltage applied to the top of the resistor ladder in a flash A/D converter, the value VREF defines the maximum input voltage to the A/D core. The mini­mum input voltage to the A/D core is automatically defined to be –VREF.
VINA
VINB
AD9225
V
CORE
+VREF
A/D
CORE
–VREF
12
difference of the voltages applied at the VINA and VINB input pins. Therefore, the equation,
V
= VINA – VINB (1)
CORE
defines the output of the differential input stage and provides the input to the A/D core.
The voltage, V
VREF V
, must satisfy the condition,
CORE
VREF (2)
CORE
where VREF is the voltage at the VREF pin.
While an infinite combination of VINA and VINB inputs exist that satisfy Equation 2, there is an additional limitation placed on the inputs by the power supply voltages of the AD9225. The power supplies bound the valid operating range for VINA and VINB. The condition,
AVSS – 0.3 V < VINA < AVDD + 0.3 V AVSS – 0.3 V < VINB < AVDD + 0.3 V
(3)
where AVSS is nominally 0 V and AVDD is nominally +5 V, defines this requirement. The range of valid inputs for VINA and VINB is any combination that satisfies both Equations 2 and 3.
For additional information showing the relationship between VINA, VINB, VREF and the digital output of the AD9225, see Table IV.
Refer to Table I and Table II at the end of this section for a summary of both the various analog input and reference configurations.
ANALOG INPUT OPERATION
Figure 14 shows the equivalent analog input of the AD9225 which consists of a differential sample-and-hold amplifier (SHA). The differential input structure of the SHA is highly flexible, allowing the devices to be easily configured for either a differential or single-ended input. The dc offset, or common­mode voltage, of the input(s) can be set to accommodate either single-supply or dual-supply systems. Also, note that the analog inputs, VINA and VINB, are interchangeable with the exception that reversing the inputs to the VINA and VINB pins results in a polarity inversion.
C
H
Q
S2
Q
S2
C
H
VINA
VINB
+
C
PIN
Q
S1
C
PAR
Q
S1
C
PIN
C
PAR
C
S
Q
C
H1
S
Figure 13. Equivalent Functional Input Circuit
The addition of a differential input structure gives the user an additional level of flexibility that is not possible with traditional flash converters. The input stage allows the user to easily config­ure the inputs for either single-ended operation or differential operation. The A/D’s input structure allows the dc offset of the input signal to be varied independently of the input span of the converter. Specifically, the input to the A/D core is the
–8–
Figure 14. Simplified Input Circuit
The AD9225 has a wide input range. The input peaks may be moved to AVDD or AVSS before performance is compromised. This allows for much greater flexibility when selecting single­ended drive schemes. Op amps and ac coupling clamps can be set to available reference levels rather than be dictated to what the ADC “needs.”
REV. A
Page 9
Due to the high degree of symmetry within the SHA topology, a significant improvement in distortion performance for differen­tial input signals with frequencies up to and beyond Nyquist can be realized. This inherent symmetry provides excellent cancella­tion of both common-mode distortion and noise. Also, the required input signal voltage span is reduced by a half which further reduces the degree of R
modulation and its effects on
ON
distortion.
The optimum noise and dc linearity performance for either differential or single-ended inputs is achieved with the largest input signal voltage span (i.e., 4 V input span) and matched input impedance for VINA and VINB. Only a slight degrada­tion in dc linearity performance exists between the 2 V and 4 V input spans.
Referring to Figure 14, the differential SHA is implemented using a switched-capacitor topology. Its input impedance and its switching effects on the input drive source should be consid­ered in order to maximize the converter’s performance. The combination of the pin capacitance, C C
, and the sampling capacitance, CS, is typically less than
PAR
, parasitic capacitance
PIN
5 pF. When the SHA goes into track mode, the input source must charge or discharge the voltage stored on C input voltage. This action of charging and discharging C
to the new
S
, aver-
S
aged over a period of time and for a given sampling frequency,
, makes the input impedance appear to have a benign resistive
F
S
component. However, if this action is analyzed within a sam­pling period (i.e., T = 1/F
), the input impedance is dynamic
S
and hence certain precautions on the input drive source should be observed.
The resistive component to the input impedance can be com­puted by calculating the average charge that gets drawn by C
H
from the input drive source. It can be shown that if CS is allowed to fully charge up to the input voltage before switches
are opened, then the average current into the input is the
Q
S1
same as if there were a resistor of 1/(C
) ohms connected
S FS
between the inputs. This means that the input impedance is inversely proportional to the converter’s sample rate. Since C
is
S
only 5 pF, this resistive component is typically much larger than
that of the drive source (i.e., 8 k at F
= 25 MSPS).
S
The SHA’s input impedance over a sampling period appears as a dynamic input impedance to the input drive source. When the SHA goes into the track mode, the input source should ideally provide the charging current through R
of switch QS1 in an
ON
exponential manner. The requirement of exponential charging means that the most common input source, an op amp, must exhibit a source impedance that is both low and resistive up to and beyond the sampling frequency.
The output impedance of an op amp can be modeled with a series inductor and resistor. When a capacitive load is switched onto the output of the op amp, the output will momentarily drop due to its effective output impedance. As the output recov­ers, ringing may occur. To remedy the situation, a series resistor can be inserted between the op amp and the SHA input as shown in Figure 15. The series resistance helps isolate the op amp from the switched-capacitor load.
AD9225
V
CC
R
S
R
S
V
EE
10mF
0.1mF
Figure 15. Series Resistor Isolates Switched-Capacitor SHA Input from Op Amp. Matching Resistors Improve SNR Performance.
The optimum size of this resistor is dependent on several factors which include the ADC sampling rate, the selected op amp, and
the particular application. In most applications, a 30 to 100
resistor is sufficient. However, some applications may require a larger resistor value to reduce the noise bandwidth or possibly limit the fault current in an overvoltage condition. Other appli­cations may require a larger resistor value as part of an antialias­ing filter. In any case, since the THD performance is dependent on the series resistance and the above mentioned factors, opti­mizing this resistor value for a given application is encouraged.
The source impedance driving VINA and VINB should be matched. Failure to provide that matching will result in degra­dation of the AD9225’s superb SNR, THD and SFDR.
For noise sensitive applications, the very high bandwidth of the AD9225 may be detrimental and the addition of a series resistor and/or shunt capacitor can help limit the wideband noise at the A/D’s input by forming a low-pass filter. Note, however, that the combination of this series resistance with the equivalent input capacitance of the AD9225 should be evaluated for those time domain applications that are sensitive to the input signal’s absolute settling time. In applications where harmonic distortion is not a primary concern, the series resistance may be selected in combination with the SHA’s nominal 10 pF of input capaci­tance to set the filter’s 3 dB cutoff frequency.
A better method of reducing the noise bandwidth, while possi­bly establishing a real pole for an antialiasing filter, is to add some additional shunt capacitance between the input (i.e., VINA and/or VINB) and analog ground. Since this additional shunt capacitance combines with the equivalent input capaci­tance of the AD9225, a lower series resistance can be selected to establish the filter’s cutoff frequency while not degrading the distortion performance of the device. The shunt capacitance also acts like a charge reservoir, sinking or sourcing the addi­tional charge required by the hold capacitor, C ing current transients seen at the op amp’s output.
The effect of this increased capacitive load on the op amp driv­ing the AD9225 should be evaluated. To optimize performance when noise is the primary consideration, increase the shunt capacitance as much as the transient response of the input signal will allow. Increasing the capacitance too much may adversely affect the op amp’s settling time, frequency response, and dis­tortion performance.
AD9225
VINA
VINB
VREF
SENSE REFCOM
, further reduc-
H
–9–REV. A
Page 10
AD9225
REFERENCE OPERATION
The AD9225 contains an onboard bandgap reference that pro­vides a pin strappable option to generate either a 1 V or 2 V output. With the addition of two external resistors, the user can generate reference voltages other than 1 V and 2 V. Another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance. See Table II for a summary of the pin-strapping options for the AD9225 reference configurations.
Figure 16 shows a simplified model of the internal voltage refer­ence of the AD9225. A pin strappable reference amplifier buffers a 1 V fixed reference. The output from the reference amplifier, A1, appears on the VREF pin. The voltage on the VREF pin determines the full-scale input span of the A/D. This input span equals,
Full-Scale Input Span = 2 × VREF
The voltage appearing at the VREF pin as well as the state of the internal reference amplifier, A1, are determined by the volt­age appearing at the SENSE pin. The logic circuitry contains two comparators which monitor the voltage at the SENSE pin. The comparator with the lowest set point (approximately 0.3 V) controls the position of the switch within the feedback path of A1. If the SENSE pin is tied to AVSS (AGND), the switch is connected to the internal resistor network thus providing a VREF of 2.0 V. If the SENSE pin is tied to the VREF pin via a short or resistor, the switch will connect to the SENSE pin. This short will provide a VREF of 1.0 V. An external resistor network will provide an alternative VREF between 1.0 V and 2.0 V. The other comparator controls internal circuitry which will disable the reference amplifier if the SENSE pin is tied AVDD. Dis­abling the reference amplifier allows the VREF pin to be driven by an external voltage reference.
5kV
A2
5kV
A1
LOGIC
AD9225
CAPT
CAPB
LOGIC
VREF
6.25kV
SENSE
6.25kV REFCOM
TO
A/D
5kV
5kV
DISABLE
1V
DISABLE
A2
A1
Figure 16. Equivalent Reference Circuit
The actual reference voltages used by the internal circuitry of the AD9225 appears on the CAPT and CAPB pins. For proper operation when using the internal or an external reference, it is necessary to add a capacitor network to decouple these pins. Figure 17 shows the recommended decoupling network. This capacitive network performs the following three functions: (1) along with the reference amplifier, A2, it provides a low source impedance over a large frequency range to drive the A/D inter­nal circuitry, (2) it provides the necessary compensation for A2, and (3) it bandlimits the noise contribution from the reference. The turn-on time of the reference voltage appearing between CAPT and CAPB is approximately 15 ms and should be evalu­ated in any power-down mode of operation.
0.1mF
CAPT
AD9225
CAPB
0.1mF
10mF
0.1mF
Figure 17. Recommended CAPT/CAPB Decoupling Network
The A/D’s input span may be varied dynamically by changing the differential reference voltage appearing across CAPT and CAPB symmetrically around 2.5 V (i.e., midsupply). To change the reference at speeds beyond the capabilities of A2, it will be necessary to drive CAPT and CAPB with two high speed, low noise amplifiers. In this case, both internal amplifiers (i.e., A1 and A2) must be disabled by connecting SENSE to AVDD, connecting VREF to AVSS and removing the capacitive decou­pling network. The external voltages applied to CAPT and CAPB must be 2.0 V + Input Span/4 and 2.0 V – Input Span/4 respectively in which the input span can be varied between 2 V and 4 V. Note that those samples within the pipeline A/D dur­ing any reference transition will be corrupted and should be discarded.
DRIVING THE ANALOG INPUTS
The AD9225 has a highly flexible input structure allowing it to interface with single ended or differential input interface cir­cuitry. The applications shown in sections “Driving the Analog Inputs” and “Reference Configurations” along with the infor­mation presented in “Input and Reference Overview” of this data sheet, give examples of both single-ended and differential operation. Refer to Tables I and II for a list of the different possible input and reference configurations and their associated figures in the data sheet.
The optimum mode of operation, analog input range, and asso­ciated interface circuitry will be determined by the particular applications performance requirements as well as power supply options. For example, a dc coupled single-ended input would be appropriate for most data acquisition and imaging applications. Also, many communication applications which require a dc coupled input for proper demodulation can take advantage of the excellent single-ended distortion performance of the AD9225. The input span should be configured such that the system’s performance objectives and the headroom requirements of the driving op amp are simultaneously met.
–10–
REV. A
Page 11
Table I. Analog Input Configuration Summary
AD9225
Input Input ␣␣␣␣␣␣Input Range (V) Figure Connection ␣ Coupling Span (V) VINA
Single-Ended ␣ DC 2 0 to 2 1 19, 20 Best for stepped input response applications, requires ±5 V op amp.
2 × VREF 0 to VREF 19, 20 Same as above but with improved noise performance due to
4 0 to 4 2.0 19, 20 Optimum noise performance, excellent THD performance, often
2 × VREF 2.0 – VREF 2.0 30 Optimum THD performance with VREF = 1. Single supply
Single-Ended ␣ AC 2 or 0 to 1 or 1 or VREF 21, 22
2 × VREF 0 to 2 × VREF
4 0.5 to 4.5 2.0 22 Optimum noise performance, excellent THD performance, ability
2 × VREF 2.0 – VREF 2.0 21 Flexible input range, optimum THD performance with VREF = 1.
Differential ␣ AC/DC 2 2 to 3 3 to 2 23, 24 Optimum full-scale THD and SFDR performance well beyond (via Transformer) the A/Ds Nyquist frequency. Preferred mode for undersampling or Amplifier applications.
2 × VREF 2.0 – VREF/2 2.0 + VREF/2 23, 24 Same as above with the exception that full-scale THD and SFDR
4.0 2.0 to 3.0 3.0 to 2.0 23, 24 Optimum noise performance.
NOTE
1
VINA and VINB can be interchanged if signal inversion is required.
1
2 × VREF increase in dynamic range. Headroom/settling time requirements
␣␣␣␣to operation (i.e., +5 V) for many op amps.
2.0 + VREF
␣␣␣␣to Ability to use either +5 V or ±5 V op amp.
2.0 + VREF
␣␣␣␣to ␣␣␣␣to performance can be traded off for better noise performance.
2.0 + VREF/2 2.0 – VREF/2
VINB
1
# Comments
of ±5 op amp should be evaluated.
requires low distortion op amp with VCC > +5 V due to its head­room issues.
to use ±5 V op amp.
Table II. Reference Configuration Summary
Reference Input Span (VINA–VINB) Operating Mode (V p-p) Required VREF (V) Connect To
INTERNAL 2 1 SENSE VREF INTERNAL 4 2 SENSE REFCOM
INTERNAL 2 ≤ SPAN ≤ 4 AND 1 ≤ VREF 2.0 AND R1 VREF AND SENSE
SPAN = 2 × VREF VREF = (1 + R1/R2) R2 SENSE AND REFCOM
EXTERNAL 2 SPAN ≤ 41 ≤ VREF ≤ 2.0 SENSE AVDD
(NONDYNAMIC) VREF EXT. REF.
EXTERNAL 2 SPAN ≤ 4 CAPT and CAPB SENSE AVDD
(DYNAMIC) Externally Driven VREF AVSS
EXT. REF. CAPT EXT. REF. CAPB
–11–REV. A
Page 12
AD9225
Differential modes of operation (ac- or dc-coupled input) pro­vide the best THD and SFDR performance over a wide fre­quency range. Differential operation should be considered for the most demanding spectral-based applications (e.g., direct IF-to­digital conversion). See Figures 23, 24 and section on Differen­tial Mode of Operation. Differential input characterization was performed for this data sheet using the configuration shown in Figure 24.
Single-ended operation requires that VINA be ac or dc coupled to the input signal source while VINB of the AD9225 be biased to the appropriate voltage corresponding to a midscale code transition. Note that signal inversion may be easily accomplished by transposing VINA and VINB. Most of the single-ended specifi­cations for the AD9225 are characterized using Figure 21 cir­cuitry with input spans of 4 V and 2 V as well as VINB = 2.5 V.
Differential operation requires that VINA and VINB be simulta­neously driven with two equal signals that are in and out of phase versions of the input signal. Differential operation of the AD9225 offers the following benefits: (1) Signal swings are smaller and therefore linearity requirements placed on the input signal source may be easier to achieve, (2) Signal swings are smaller and therefore may allow the use of op amps which may otherwise have been constrained by headroom limitations, (3) Differential operation minimizes even-order harmonic products, and (4) Differential operation offers noise immunity based on the device’s common-mode rejection.
As is typical of most IC devices, exceeding the supply limits will turn on internal parasitic diodes resulting in transient currents within the device. Figure 18 shows a simple means of clamping an ac or dc coupled single ended input with the addition of two series resistors and two diodes. An optional capacitor is shown for ac coupled applications. Note that a larger series resistor could be used to limit the fault current through D1 and D2 but should be evaluated since it can cause a degradation in overall performance. A similar clamping circuit could also be used for each input if a differential input signal is being applied. The diodes might cause nonlinearities in the signal. Careful evalua­tion should be performed on the diodes used.
OPTIONAL
V
CC
V
EE
AC COUPLING CAPACITOR
R
30V
AVDD
D2
S1
1N4148
D1 1N4148
R
20V
S2
AD9225
Figure 18. Simple Clamping Circuit
SINGLE-ENDED MODE OF OPERATION
The AD9225 can be configured for single ended operation using dc or ac coupling. In either case, the input of the A/D must be driven from an operational amplifier that will not degrade the A/D’s performance. Because the A/D operates from a single supply, it will be necessary to level shift ground-based bipolar signals to comply with its input requirements. Both dc and ac coupling provide this necessary function, but each method results in different interface issues which may influence the system design and performance.
Single-ended operation is often limited by the availability of driving op amps. Very low distortion op amps that provide great performance out to the Nyquist frequency of the converter are hard to find. Compounding the problem, for dc-coupled, single­ended applications, is the inability of many high performance amplifiers to maintain low distortions as their outputs approach their positive output voltage limit (i.e., 1 dB compression point). For this reason, it is recommended that applications requiring high performance dc coupling use the single-ended to differential circuit shown in Figure 23.
DC COUPLING AND INTERFACE ISSUES
Many applications require the analog input signal to be dc coupled to the AD9225. An operational amplifier can be configured to rescale and level shift the input signal so that it is compatible with the selected input range of the A/D. The input range to the A/D should be selected on the basis of system performance objectives as well as the analog power supply availability since this will place certain constraints on the op amp selection.
Many of the new high performance op amps are specified for
only ±5 V operation and have limited input/output swing capa-
bilities. The selected input range of the AD9225 should be considered with the headroom requirements of the particular op amp to prevent clipping of the signal. Also, since the output of a dual supply amplifier can swing below –0.3 V, clamping its output should be considered in some applications.
In some applications, it may be advantageous to use an op amp specified for single supply +5 V operation since it will inherently limit its output swing to within the power supply rails. Amplifiers like the AD8041, AD8011 and are useful for this purpose but their low bandwidths will limit the AD9225’s performance. High performance amplifiers such as the AD9631, AD9632, AD8056 or AD8055 allow the AD9225 to be configured for larger input spans which will improve the ADC’s noise performance.
Op amp circuits using a noninverting and inverting topology are discussed in the next section. Although not shown, the nonin­verting and inverting topologies can be easily configured as part of an antialiasing filter by using a Sallen-Key or Multiple-Feed­back topology. An additional R-C network can be inserted be­tween the op amp’s output and the AD9225 input to provide a filter pole.
Simple Op Amp Buffer
In the simplest case, the input signal to the AD9225 will already be biased at levels in accordance with the selected input range. It is simply necessary to provide an adequately low source im­pedance for the VINA and VINB analog pins of the A/D. Figure 19 shows the recommended configuration a single-ended drive using an op amp. In this case, the op amp is shown in a nonin­verting unity gain configuration driving the VINA pin. The internal reference drives the VINB pin. Note that the addi-
tion of a small series resistor of 30 to 50 connected to
VINA and VINB will be beneficial in nearly all cases. Refer to section “Analog Input Operation” a discussion on resistor selec­tion. Figure 19 shows the proper connection for a 0 V to 4 V
input range. Alternative single ended ranges of 0 V to 2 × VREF
can also be realized with the proper configuration of VREF (refer to the section “Using the Internal Reference”). Headroom limitations of the op amp must always be considered.
–12–
REV. A
Page 13
AD9225
VINA
VINB
AD9225
1kV
R
S
V
IN
C2
0.1mF
R
S
VCM
1kV
C2
0.1mF
C1
10mF
C1 10mF
C3
0.1mF
4V 0V
+V
R
2.0V
10mF
S
R
0.1mF
U1
–V
AD9225
VINA
S
VINB
VREF
SENSE
maintaining a low impedance over a wide frequency range. The combination of the capacitor and the resistor form a high-pass filter with a high-pass –3 dB frequency determined by the equation,
f
= 1/(2 × π × R × (C1 + C2))
–3 dB
The low impedance VREF voltage source biases both the VINB input and provides the bias voltage for the VINA input. Figure 21 shows the VREF configured for 2.0 V thus the input range of the A/D is 0 V to 4 V. Other input ranges could be selected by
Figure 19. Single-Ended AD9225 Op Amp Drive Circuit
changing VREF.
Op Amp with DC Level Shifting
AD9631
C1
10mF
C2
0.1mF
0.1mF
4.5
2.5
0.5
10mF
+V
+V
R
R
RR
AD9225
R
S
VINA
R
S
VINB
Figure 20 shows a dc-coupled level shifting circuit employing an op amp, A1, to sum the input signal with the desired dc set. Configuring the op amp in the inverting mode with the given resistor values results in an ac signal gain of –1. If the signal inversion is undesirable, interchange the VINA and VINB con­nections to reestablish the original signal polarity. The dc volt­age at VREF sets the common-mode voltage of the AD9225. For example, when VREF = 2.0 V, the input level from the op
+2V
–2V
+5V
0V
V
IN
–5V
amp will also be centered around 2.0 V. The use of ratio matched, thin-film resistor networks will minimize gain and offset errors. Also, an optional pull-up resistor, RP, may be used to reduce the output load on VREF to less than its 1 mA maximum.
Alternative AC Interface
Figure 21. AC-Coupled Input
Figure 22 shows a flexible ac coupled circuit which can be con-
500V*
+V
CC
0.1mF
figured for different input spans. Since the common mode volt­age of VINA and VINB are biased to midsupply independent of VREF, VREF can be pin strapped or reconfigured to achieve input spans between 2 V and 4 V p-p. The AD9225’s CMRR
+VREF –VREF
+V
VREF
0V
RP**
*OPTIONAL RESISTOR NETWORK-OHMTEK ORNA500D **OPTIONAL PULL-UP RESISTOR WHEN USING INTERNAL REFERENCE
DC
500V*
0.1mF
500V*
500V*
Figure 20. Single-Ended Input with DC-Coupled Level Shift
AC COUPLING AND INTERFACE ISSUES
For applications where ac coupling is appropriate, the op amp’s output can be easily level-shifted via a coupling capacitor. This
NC
7
2
3
1
A1
5
4
NC
R
S
6
VINA
AD9225
R
S
VINB
along with the symmetrical coupling R-C networks will reject both power supply variations and noise. The resistors, R, estab­lish the common-mode voltage. They may have a high value
(e.g., 5 k) to minimize power consumption and establish a low
cutoff frequency. The capacitors, C1 and C2, are typically a
0.1 µF ceramic and 10 µF tantalum capacitor in parallel to
achieve a low cutoff frequency while maintaining a low imped­ance over a wide frequency range. R
isolates the buffer ampli-
S
fier from the A/D input. The optimum performance is achieved when VINA and VINB are driven via symmetrical networks. The f
point can be approximated by the equation,
–3 dB
f
=
–3 dB
2 π×6K +(C1+C2)
1
has the advantage of allowing the op amp’s common-mode level to be symmetrically biased to its midsupply level (i.e., (V
)/2). Op amps that operate symmetrically with respect to
V
EE
CC
+
their power supplies typically provide the best ac performance as well as greatest input/output span. Various high speed/perfor­mance amplifiers which are restricted to +5 V/–5 V operation and/or specified for +5 V single-supply operation can be easily configured for the 4 V or 2 V input span of the AD9225. Note that differential transformer coupling, which is another form of ac coupling, should be considered for optimum ac performance.
Simple AC Interface
Figure 21 shows a typical example of an ac-coupled, single­ended configuration. The bias voltage shifts the bipolar, ground­referenced input signal to approximately AVDD/2. The value for C1 and C2 will depend on the size of the resistor, R. The
capacitors, C1 and C2, are a 0.1 µF ceramic and 10 µF tanta-
lum capacitor in parallel to achieve a low cutoff frequency while
–13–REV. A
Figure 22. AC-Coupled Input-Flexible Input Span, V
= 2.5 V
CM
Page 14
AD9225
OP AMP SELECTION GUIDE
Op amp selection for the AD9225 is highly dependent on a particular application. In general, the performance requirements of any given application can be characterized by either time domain or frequency domain parameters. In either case, one should carefully select an op amp which preserves the perfor­mance of the A/D. This task becomes challenging when one considers the AD9225’s high performance capabilities coupled with other extraneous system level requirements such as power consumption and cost.
The ability to select the optimal op amp may be further compli­cated by either limited power supply availability and/or limited acceptable supplies for a desired op amp. Newer, high perfor­mance op amps typically have input and output range limita­tions in accordance with their lower supply voltages. As a result, some op amps will be more appropriate in systems where ac­coupling is allowable. When dc-coupling is required, op amps without headroom constraints such as rail-to-rail op amps or ones where larger supplies can be used should be considered. The following section describes some op amps currently avail­able from Analog Devices. The system designer is always encouraged to contact the factory or local sales office to be updated on Analog Devices latest amplifier product offerings. Highlights of the areas where the op amps excel and where they may limit the performance of the AD9225 is also included.
AD8055: f
= 300 MHz.
–3 dB
Low cost. Best used for driving single-ended ac coupled configuration. Limit: THD is compromised when output is not swinging about 0 V.
AD8056: Dual Version of above amp.
Perfect for single-ended to differential configuration (see Figure 23). Harmonics cancel each other in differential drive, making this amplifier highly recom­mended for a single-ended input signal source. Handles input signals past the 20 MHz Nyquist frequency.
AD9631: f
= 250 MHz.
–3 dB
Moderate cost. Good for single-ended drive applications when signal is anywhere between 0 V and 3 V. Limits: THD is compromised above 8 MHz.
DIFFERENTIAL MODE OF OPERATION
Since not all applications have a signal preconditioned for differ­ential operation, there is often a need to perform a single-ended­to-differential conversion. In systems that do not need to be dc coupled, an RF transformer with a center tap is the best method to generate differential inputs for the AD9225. It provides all the benefits of operating the A/D in the differential mode without contributing additional noise or distortion. An RF transformer also has the added benefit of providing electrical isolation between the signal source and the A/D.
An improvement in THD and SFDR performance can be realized by operating the AD9225 in the differential mode. The perfor­mance enhancement between the differential and single-ended mode is most noteworthy as the input frequency approaches and goes beyond the Nyquist frequency (i.e., f
> FS/2).
IN
500V
VREF
0V
500V
500V
500V
500V
500V
500V
500V
*OPTIONAL
50V
50V
VINA
VINB
10mF
AD9225
REF
+V
R*
0.1mF
Figure 23. Direct Coupled Drive Circuit with AD8056 Dual Op Amp
The circuit shown in Figure 23 is an ideal method of applying a differential dc drive to the AD9225. We have used this configu­ration to drive the AD9225 from 2 V to 4 V spans at frequencies approaching Nyquist with performance numbers matching those shown on pages 2 and 3 of this data sheet (gathered through a transformer). The dc input is shifted to a dc point swinging symmetrically about the reference voltage. The optional resistor will provide additional current if more reference drive is required.
The driver circuit shown in Figure 23 is optimized for dc cou­pling applications requiring optimum distortion performance. This differential op amp driver circuit is configured to convert and level shift a 2 V p-p single-ended, ground referenced signal to a 4 V p-p differential signal centered at the VREF level of the ADC. The circuit is based on two op amps which are configured as matched unity gain difference amplifiers. The single-ended input signal is applied to opposing inputs of the difference am­plifiers, thus providing differential drive. The common-mode offset voltage is applied to the noninverting resistor leg of each difference amplifier providing the required offset voltage. The common-mode offset can be varied over a wide span without any serious degradation in distortion performance as shown in Figures 25a and 25b, thus providing some flexibility in improv-
ing output compression distortion from some ±5 V op amps
with limited positive voltage swing.
To protect the AD9225 from an undervoltage fault condition
from op amps specified for ±5 V operation, two diodes to AGND
can be inserted between each op amp output and the AD9225 inputs. The AD9225 will inherently be protected against any overvoltage condition if the op amps share the same positive power supply (i.e., AVDD) as the AD9225. Note, the gain accuracy and common-mode rejection of each difference ampli­fier in this driver circuit can be enhanced by using a matched thin-film resistor network (i.e., Ohmtek ORNA5000F) for the op amps. Recall, the AD9225’s small signal bandwidth is 105 MHz, hence any noise falling within the baseband band­width of the AD9225 will degrade its overall noise performance.
The noise performance of each unity gain differential driver circuit is limited by its inherent noise gain of two. For unity gain op amps ONLY, the noise gain can be reduced from two to one beyond the input signals passband by adding a shunt capacitor,
, across each op amp’s feedback resistor. This will essentially
C
F
establish a low-pass filter, which reduces the noise gain to one beyond the filter’s f input signal to f
while simultaneously bandlimiting the
–3 dB
. Note, the pole established by this filter can
–3 dB
also be used as the real pole of an antialiasing filter.
–14–
REV. A
Page 15
AD9225
FUND
2ND
3RD
4TH
–119.7
–110.0
–100.0
–90.0
–80.0
–70.0
–60.0
–50.0
–40.0
–30.0
–20.0
–10.0
0.0
2.0E+6 4.0E+6 6.0E+6 8.0E+6 10.0E+6 12.5E+6
FIN = 2.5MHz F
S
= 25MHz
Figure 24 shows the schematic of the suggested transformer circuit. The circuit uses a minicircuits RF transformer, model #T4-1T, which has an impedance ratio of four (turns ratio of
2). The schematic assumes that the signal source has a 50 source impedance. The 1:4 impedance ratio requires the 200
secondary termination for optimum power transfer and VSWR. The center tap of the transformer provides a convenient means of level-shifting the input signal to a desired common-mode voltage.
R
S
49.9V
MINICIRCUITS
T4-1T
200V
33V
R
33V
S
0.1mF
VINA
CML
AD9225
VINB
Figure 24. Transformer Coupled Input
This (Figure 24) configuration was used to gather the differen­tial data on pages 2 and 3.
Transformers with other turns ratios may also be selected to optimize the performance of a given application. For example, a given input signal source or amplifier may realize an improve­ment in distortion performance at reduced output power levels and signal swings. For example, selecting a transformer with a higher impedance ratio (e.g., Minicircuits T16-6T with a 1:16 impedance ratio) effectively “steps up” the signal level thus further reducing the driving requirements of the signal source.
Referring to Figure 24, a series resistors, R
, were inserted between the AD9225 and the secondary
tor, C
S
, and shunt capaci-
S
of the transformer. The value of 33 was selected to specifi-
cally optimize both the THD and SNR performance of the A/D.
and CS help provide a low-pass filter to block high frequency
R
S
noise.
The AD9225 can be easily configured for either a 2 V p-p input span or 4.0 V p-p input span by setting the internal reference (see Table II). Other input spans can be realized with two exter­nal gain setting resistors as shown in Figure 28 of this data sheet. Figures 25a and 25b demonstrate how both spans of the AD9225 achieve the high degree of linearity and SFDR over a wide range of amplitudes required by the most demanding com­munication applications.
Figures 25a and 25b demonstrate the flexibility of common­mode voltage (transformer center tap) with respect to THD.
–76
–78
–80
F
= 10MHz
THD – dB
–82
–84
–86
051
IN
FIN = 2.5MHz
234
COMMON-MODE VOLTAGE – V
Figure 25a. Common-Mode Voltage vs. THD
= 2 V Differential)
(A
IN
–76
–78
–80
THD – dB
–82
–84
–86
0.5 1.0
F
= 10MHz
IN
FIN = 2.5MHz
1.5
2.0 2.5 3.0 3.5 4.0 4.5
COMMON-MODE VOLTAGE – V
Figure 25b. Common-Mode Voltage vs. THD (A
= 4 V Differential)
IN
Figure 25c. Single Tone Frequency Domain Plot Common-Mode Voltage = 2.5 V (A
= 4 V
IN
Differential)
–15–REV. A
Page 16
AD9225
REFERENCE CONFIGURATIONS
The figures associated with this section on internal and external reference operation do not show recommended matching series resistors for VINA and VINB for the purpose of simplicity. Please refer to section “Driving the Analog Inputs, Introduc­tion” for a discussion of this topic. Also, the figures do not show the decoupling network associated with the CAPT and CAPB pins. Please refer to the section “Reference Operation” for a discussion of the internal reference circuitry and the recom­mended decoupling network shown in Figure 17.
USING THE INTERNAL REFERENCE Single-Ended Input with 0 to 2 VREF Range
Figure 26 shows how to connect the AD9225 for a 0 V to 2 V or 0 V to 4 V input range via pin strapping the SENSE pin. An
intermediate input range of 0 to 2 × VREF can be established
using the resistor programmable configuration in Figure 28.
In either case, both the midscale voltage and input span are directly dependent on the value of VREF. More specifically, the midscale voltage is equal to VREF while the input span is equal
to 2 × VREF. Thus, the valid input range extends from 0 to 2 × VREF. When VINA is 0 V, the digital output will be 000 Hex; when VINA is 2 × VREF, the digital output will be FFF Hex.
Shorting the VREF pin directly to the SENSE pin places the internal reference amplifier in unity-gain mode and the resultant VREF output is 1 V. Therefore, the valid input range is 0 V to 2 V. However, shorting the SENSE pin directly to the REFCOM pin configures the internal reference amplifier for a gain of 2.0 and the resultant VREF output is 2.0 V. Thus, the valid input range becomes 0 V to 4 V. The VREF pin should be bypassed
to the REFCOM pin with a 10 µF tantalum capacitor in parallel with a low-inductance 0.1 µF ceramic capacitor.
2 3 VREF
0V
10mF
SHORT FOR 0V TO 2V
SHORT FOR 0V TO 4V
0.1mF
INPUT SPAN
INPUT SPAN
VINA VINB
VREF
AD9225
SENSE
REFCOM
Figure 26. Internal Reference—2 V p-p Input Span,
= 1 V, or 4 V p-p Input Span
V
CM
Figure 27 shows the single-ended configuration that gives good dynamic performance (SINAD, SFDR). To optimize dynamic specifications, center the common mode voltage of the analog input at approximately by 2.5 V by connecting VINB to a low impedance 2.5 V source. As described above, shorting the VREF pin directly to the SENSE pin results in a 1 V reference voltage and a 2 V p-p input span. The valid range for input signals is
1.5 V to 3.5 V. The VREF pin should be bypassed to the REF-
COM pin with a 10 µF tantalum capacitor in parallel with a low-inductance 0.1 µF ceramic capacitor.
This reference configuration could also be used for a differential input in which VINA and VINB are driven via a transformer as shown in Figure 24. In this case, the common-mode voltage, VCM , is set at midsupply by connecting the transformer’s center tap to CML of the AD9225. VREF can be configured for 1.0 V or 2.0 V by connecting SENSE to either VREF or REFCOM respectively. Note that the valid input range for each of the differential inputs is one half of the single-ended input and thus becomes V
3.5V
1.5V
10mF
– VREF/2 to VCM + VREF/2.
CM
VINA VCM
AD9225
VINB
1V
VREF
0.1mF
SENSE REFCOM
Figure 27. Internal Reference—2 V p-p Input Span,
= 2.5 V
V
CM
Resistor Programmable Reference
Figure 28 shows an example of how to generate a reference voltage other than 1.0 V or 2.0 V with the addition of two exter­nal resistors and a bypass capacitor. Use the equation,
VREF = 1 V × (1 + R1/R2)
to determine appropriate values for R1 and R2. These resistors
should be in the 2 k to 100 k range. For the example shown, R1 equals 2.5 k and R2 equals 5 k. From the equation above,
the resultant reference voltage on the VREF pin is 1.5 V. This sets the input span to be 3 V p-p. To assure stability, place a
0.1 µF ceramic capacitor in parallel with R1.
The midscale voltage can be set to VREF by connecting VINB
to VREF to provide an input span of 0 to 2 × VREF. Alterna-
tively, the midscale voltage can be set to 2.5 V by connecting VINB to a low impedance 2.5 V source. For the example shown, the valid input single-ended range for VINA is 1 V to 4 V since VINB is set to an external, low impedance 2.5 V source. The VREF pin should be bypassed to the REFCOM pin with a
10 µF tantalum capacitor in parallel with a low inductance
0.1 µF ceramic capacitor.
4V 1V
10mF
2.5V
0.1mF
R1
2.5kV
R2 5kV
1.5V
C1
0.1mF
VINA
AD9225
VINB
VREF
SENSE
REFCOM
Figure 28. Resistor Programmable Reference +3 V p-p Input Span, V
= 2.5 V
CM
–16–
REV. A
Page 17
AD9225
2 3 REF
0V
+5V
10mF
VINA
VINB
VREF
SENSE
AD9225
+5V
0.1mF
VREF
0.1mF
0.1mF
1111 1111 1111 1111 1111 1111 1111 1111 1110
OTR
–FS
+FS
–FS+1/2 LSB
+FS –1/2 LSB–FS –1/2 LSB
+FS –1 1/2 LSB
0000 0000 0001 0000 0000 0000 0000 0000 0000
1 0 0
0 0 1
OTR DATA OUTPUTS
USING AN EXTERNAL REFERENCE
Using an external reference may enhance the dc performance of the AD9225 by improving drift and accuracy. Figures 29 and 30 show examples of how to use an external reference with the A/D. Table III is a list of suitable voltage references from Ana­log Devices. To use an external reference, the user must disable the internal reference amplifier and drive the VREF pin. Con­necting the SENSE pin to AVDD disables the internal reference amplifier.
Table III. Suitable Voltage References
Initial
Output Drift Accuracy Operating Voltage (ppm/C) % (max) Current
Internal 1.00 26 1.4 1 mA
AD589 1.235 10–100 1.2–2.8 50 µA AD1580 1.225 50–100 0.08–0.8 50 µA REF191 2.048 5–25 0.1–0.5 45 µA
Internal 2.0 26 1.4 1 mA
The AD9225 contains an internal reference buffer, A2 (see Figure 16), that simplifies the drive requirements of an external reference. The external reference must be able to drive about
5 kΩ (±20%) load. Note that the bandwidth of the reference
buffer is deliberately left small to minimize the reference noise contribution. As a result, it is not possible to change the refer­ence voltage rapidly in this mode.
2.5V+VREF
2.5V–VREF
+5V
0.1mF
2.5V
2.5V REF
22mF
R1
0.1mF
VINA
AD9225
VINB
mum of a 10 µF capacitor in parallel with a 0.1 µF low inductance
ceramic capacitor decouple the reference output to ground.
Figure 30. Input Range = 0 V to 2 × VREF
DIGITAL INPUTS AND OUTPUTS Digital Outputs
The AD9225 output data is presented in positive true straight binary for all input ranges. Table IV indicates the output data formats for various input ranges regardless of the selected input range. A twos complement output data format can be created by inverting the MSB.
Table IV. Output Data Format
I
nput (V) Condition (V) Digital Output OTR
VINA–VINB < – VREF 0000 0000 0000 1 VINA–VINB = – VREF 0000 0000 0000 0 VINA–VINB = 0 1000 0000 0000 0 VINA–VINB = + VREF – 1 LSB 1111 1111 1111 0
VINA–VINB + VREF 1111 1111 1111 1
VREF
SENSE
0.1mF
A1
R2
+5V
Figure 29. External Reference
Variable Input Span with VCM = 2.5 V
Figure 29 shows an example of the AD9225 configured for an
input span of 2 × VREF centered at 2.5 V. An external 2.5 V
reference drives the VINB pin thus setting the common-mode voltage at 2.5 V. The input span can be independently set by a voltage divider consisting of R1 and R2 which generates the VREF signal. A1 buffers this resistor network and drives VREF. Choose this op amp based on accuracy requirements. It
is essential that a minimum of a 10 µF capacitor in parallel with a 0.1 µF low inductance ceramic capacitor decouple A1’s output
to ground.
Single-Ended Input with 0 to 2 VREF Range
Figure 30 shows an example of an external reference driving both VINB and VREF. In this case, both the common-mode voltage and input span are directly dependent on the value of VREF. More specifically, the common-mode voltage is equal to
VREF while the input span is equal to 2 × VREF. Thus, the valid input range extends from 0 to 2 × VREF. For example, if
the REF191, a 2.048 V external reference was selected, the valid input range extends from 0 to 4.096 V. In this case, 1 LSB of the AD9225 corresponds to 1 mV. It is essential that a mini-
–17–REV. A
Figure 31. Output Data Format
Out Of Range (OTR)
An out-of-range condition exists when the analog input voltage is beyond the input range of the converter. OTR is a digital out put that is updated along with the data output corresponding to the particular sampled analog input voltage. Hence, OTR has the same pipeline delay (latency) as the digital data. It is LOW when the analog input voltage is within the analog input range. It is HIGH when the analog input voltage exceeds the input range as shown in Figure 32. OTR will remain HIGH until the analog input returns within the input range and another conver­sion is completed. By logical ANDing OTR with the MSB and its complement, overrange high or underrange low conditions can be detected. Table V is a truth table for the over/underrange circuit in Figure 33 which uses NAND gates. Systems requiring programmable gain conditioning of the AD9225 input signal can immediately detect an out-of-range condition, thus elimi­nating gain selection iterations. Also, OTR can be used for digital offset and gain calibration.
Page 18
AD9225
Table V. Out-of-Range Truth Table
OTR MSB Analog Input Is
0 0 In Range 0 1 In Range 1 0 Underrange 1 1 Overrange
MSB
OTR
MSB
OVER = “1”
UNDER = “1”
Figure 32. Overrange or Underrange Logic
Digital Output Driver Considerations (DRVDD)
The AD9225 output drivers can be configured to interface with +5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3 V respectively. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause glitches on the supplies and may affect SINAD performance. Applications requiring the ADC to drive large capacitive loads or large fanout may require additional decoupling capacitors on DRVDD. In extreme cases, external buffers or latches may be required.
Clock Input and Considerations
The AD9225 internal timing uses the two edges of the clock input to generate a variety of internal timing signals. The clock input must meet or exceed the minimum specified pulsewidth high and low (t
and tCL) specifications for the given A/D as
CH
defined in the Switching Specifications at the beginning of the data sheet to meet the rated performance specifications. For example, the clock input to the AD9225 operating at 25 MSPS may have a duty cycle between 45% to 55% to meet this timing requirement since the minimum specified t
and tCL is 18 ns.
CH
For low clock rates, the duty cycle may deviate from this range to the extent that both t
and tCL are satisfied.
CH
All high speed high resolution A/Ds are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (f
) due to only aperture jitter (tA) can be cal-
IN
culated with the following equation:
SNR =20 log
10
2π f
1
INtA
  
In the equation, the rms aperture jitter, tA, represents the root­sum square of all the jitter sources which include the clock in­put, analog input signal, and A/D aperture jitter specification. Undersampling applications are particularly sensitive to jitter.
Clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9225. Power supplies for clock drivers should be separated from the A/D output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other method), it should be retimed by the original clock at the last step.
The clock input is referred to as the analog supply. Its logic threshold is AVDD/2. If the clock is being generated by 3 V logic, it will have to be level shifted into 5 V CMOS logic levels. This can also be accomplished by ac-coupling and level-shifting the clock signal.
–18–
The AD9225 has a clock tolerance of 5% at 25 MHz. One way to obtain a 50% duty cycle clock is to divide down a clock of higher frequency, as shown in Figure 33. This configuration will also decrease the jitter of the source clock.
+5V
R
D
50MHz
+5V
Q
Q
S
25MHz
Figure 33. Divide-by-Two Clock Circuit
In this case a 50 MHz clock is divided by two to produce the 25 MHz clock input for the AD9225. In this configuration, the duty cycle of the 50 MHz clock is irrelevant.
The input circuitry for the CLOCK pin is designed to accom­modate CMOS inputs. The quality of the logic input, particu­larly the rising edge, is critical in realizing the best possible jitter performance of the part: the faster the rising edge, the better the jitter performance.
As a result, careful selection of the logic family for the clock driver, as well as the fanout and capacitive load on the clock line, is important. Jitter-induced errors become more predomi­nant at higher frequency, large amplitude inputs, where the input slew rate is greatest.
Most of the power dissipated by the AD9225 is from the analog power supplies. However, lower clock speeds will reduce digital current. Figure 34 shows the relationship between power and clock rate.
380
360
340
320
300
280
260
POWER – mW
240 220
200
180
0355
2V
INTERNAL
REFERENCE
10 15
SAMPLE RATE
1V
INTERNAL
REFERENCE
3020 25
Figure 34. Power Consumption vs. Clock Rate
Direct IF Down Conversion Using the AD9225
Sampling IF signals above an ADC’s baseband region (i.e., dc to F
/2) is becoming increasingly popular in communication
S
applications. This process is often referred to as Direct IF Down Conversion or Undersampling. There are several potential ben­efits in using the ADC to alias (i.e., or mix) down a narrowband or wideband IF signal. First and foremost is the elimination of a complete mixer stage with its associated baseband amplifiers and filters, reducing cost and power dissipation. Second is the ability to apply various DSP techniques to perform such func­tions as filtering, channel selection, quadrature demodulation, data reduction, detection, etc. A detailed discussion on using
REV. A
Page 19
AD9225
this technique in digital receivers can be found in Analog Devices Application Notes AN-301 and AN-302.
In Direct IF Down Conversion applications, one exploits the inherent sampling process of an ADC in which an IF signal lying outside the baseband region can be aliased back into the baseband region in a similar manner that a mixer will down­convert an IF signal. Similar to the mixer topology, an image rejection filter is required to limit other potential interfering signals from also aliasing back into the ADC’s baseband region. A trade-off exists between the complexity of this image rejection filter and the ADC’s sample rate as well as dynamic range.
The AD9225 is well suited for various IF sampling applications. The AD9225’s low distortion input SHA has a full-power band­width extending beyond 130 MHz thus encompassing many
popular IF frequencies. A DNL of ±0.4 LSB (typ) combined
with low thermal input referred noise allows the AD9225 in the 2 V span to provide 69 dB of SNR for a baseband input sine wave. Also, its low aperture jitter of 0.8 ps rms ensures mini­mum SNR degradation at higher IF frequencies. In fact, the AD9225 is capable of still maintaining 68 dB of SNR at an IF of 71 MHz with a 2 V input span. Note, although the AD9225 can yield a 1 dB to 2 dB improvement in SNR when configured for the larger 4 V span, the 2 V span achieves the optimum full­scale distortion performance at these higher input frequencies. Also, the 2 V span reduces the performance requirements of the input driver circuitry (i.e., IP3) and thus may also be more attractive from a system implementation perspective.
Figure 35 shows a simplified schematic of the AD9225 config­ured in an IF sampling application. To reduce the complexity of the digital demodulator in many quadrature demodulation ap­plications, the IF frequency and/or sample rate are strategically selected such that the bandlimited IF signal aliases back into the center of the ADC’s baseband region (i.e., F
/4). This demodu-
S
lation technique typically reduces the complexity of the post digital demodulator ASIC which follows the ADC.
HIGH
FROM
PREVIOUS
STAGES
MIXER
SAW
FILTER
LINEARITY
AMPLIFIER
RF2317 RF2312
RF
OPTIONAL
BANDPASS
FILTER
MINICIRCUITS
T4-6T
0.1mF
10mF
200V
0.1mF
20V
20V
AD9225
VINA
VINB CML
VREF
SENSE REFCOM
Figure 35. Example of AD9225 IF Sampling Circuit
To maximize its distortion performance, the AD9225 is config­ured in the differential mode with a 2 V span using a transformer. The center-tap of the transformer is biased at midsupply via the CML output of the AD9225. Preceding the AD9225 and trans­former is an optional bandpass filter as well as a gain stage. A low Q passive bandpass filter can be inserted to reduce out­of-band distortion and noise which lies within the AD9225’s 130 MHz bandwidth. A large gain stage(s) is often required to compensate for the high insertion losses of a SAW filter used for channel selection and image rejection. The gain stage will also provide adequate isolation for the SAW filter from the charge
“kick back” currents associated with the AD9225’s switched capacitor input stage.
The distortion and noise performance of an ADC at the given IF frequency is of particular concern when evaluating an ADC for a narrowband IF sampling application. Both single tone and dual tone SFDR vs. amplitude are very useful in assessing an ADC’s dynamic and static nonlinearities. SNR vs. amplitude performance at the given IF is useful in assessing the ADC’s noise performance and noise contribution due to aperture jitter. In any application, one is advised to test several units of the same device under the same conditions to evaluate the given applications sensitivity to that particular device.
Figures 36–39 combine the dual tone SFDR as well as single tone SFDR and SNR performances at IF frequencies of 35 MHz, 45 MHz, 70 MHz, and 85 MHz. Note, the SFDR vs. amplitude data is referenced to dBFS while the single tone SNR data is referenced to dBc. The performance characteristics in these figures are representative of the AD9225 without any preceding gain stage. The AD9225 was operated in the differential mode (via transformer) with a 2 V span and a sample rate between 28 MSPS and 36 MSPS. The analog supply (AVDD) and the digital supply (DRVDD) were set to +5 V and 3.3. V respectively.
100
95
90
85
80
75
70
SNR/SFDR – dBFS
65
60
55
50
–15
SFDR
DUAL-TONE
(dBFS)
SINGLE-TONE
–10 –5
AIN – dBFS
SINGLE-TONE
SNR
(dBc)
SFDR
(dBFS)
0
Figure 36. IF Undersampling at 35 MHz (F1 = 34.63 MHz,
= 35.43 MHz, CLOCK = 20 MHz)
F
2
100
95
90
85
80
75
70
SNR/SFDR – dBFS
65
60
55
50
–15
SFDR
DUAL-TONE
(dBFS)
SINGLE-TONE
–10 –5
AIN – dBFS
SINGLE-TONE
SNR
(dBc)
SFDR
(dBFS)
0
Figure 37. IF Undersampling at 45 MHz (F1 = 44.81 MHz,
= 45.23 MHz, CLOCK = 20 MHz)
F
2
–19–REV. A
Page 20
AD9225
0.1mF
CML
AD9225
100
95 90
85
80
75
70
SNR/SFDR – dBFS
65
60
55
50
–15
SFDR
DUAL-TONE
(dBFS)
SFDR
SINGLE-TONE
(dBFS)
–10 –5
AIN – dBFS
SNR
SINGLE-TONE
(dBc)
0
Figure 38. IF Undersampling at 70 MHz (F1 = 69.50 MHz,
= 70.11 MHz, CLOCK = 25 MHz)
F
2
100
95
90
85
80
75
70
SNR/SFDR – dBFS
65
60
55
50
–15
SFDR
DUAL-TONE
(dBFS)
–10 –5
AIN – dBFS
SFDR
SINGLE-TONE
(dBFS)
SINGLE-TONE
SNR
(dBc)
0
Figure 39. IF Undersampling at 85 MHz (F1 = 84.81 MHz,
= 85.23 MHz, CLOCK = 20 MHz)
F
2
GROUNDING AND DECOUPLING Analog and Digital Grounding
Proper grounding is essential in any high speed, high resolution system. Multilayer printed circuit boards (PCBs) are recom­mended to provide optimal grounding and power schemes. The use of ground and power planes offers distinct advantages:
1. The minimization of the loop area encompassed by a signal and its return path.
2. The minimization of the impedance associated with ground and power paths.
3. The inherent distributed capacitor formed by the power plane, PCB insulation and ground plane.
These characteristics result in both a reduction of electromag­netic interference (EMI) and an overall improvement in performance.
It is important to design a layout that prevents noise from cou­pling onto the input signal. Digital signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. While the AD9225 features separate analog and driver ground pins, it should be treated as an analog com­ponent. The AVSS and DRVSS pins must be joined together
directly under the AD9225. A solid ground plane under the A/D is acceptable if the power and ground return currents are care­fully managed. Alternatively, the ground plane under the A/D may contain serrations to steer currents in predictable directions where cross coupling between analog and digital would other­wise be unavoidable. The AD9225/AD9225EB ground layout, shown in Figure 47, depicts the serrated type of arrangement.
The board is primarily built over a common ground plane. It has a “slit” to route currents near the clock driver. Figure 40 illustrates a general scheme of ground and power implementation, in and around the AD9225.
LOGIC
DV
SUPPLY
D
DIGITAL
LOGIC
ICs
GND
D
V
IN
A
A
D
A A
ADC
IC
= ANALOG = DIGITAL
AVDD
ANALOG CIRCUITS
A
DVDD
C
STRAY
DIGITAL
CIRCUITS
C
STRAY
I
A
B
I
D
DVSSAVSS
AA
Figure 40. Ground and Power Consideration
Analog and Digital Driver Supply Decoupling
The AD9225 features separate analog and driver supply and ground pins, helping to minimize digital corruption of sensitive analog signals. In general, AVDD, the analog supply, should be decoupled to AVSS, the analog common, as close to the chip as physically possible. Figure 41 shows the recommended decou-
pling for the analog supplies; 0.1 µF ceramic chip and 10 µF
tantalum capacitors should provide adequately low impedance over a wide frequency range. Note that the AVDD and AVSS pins are co-located on the AD9225 to simplify the layout of the decoupling capacitors and provide the shortest possible PCB trace lengths. The AD9225/AD9225EB power plane layout, shown in Figure 48 depicts a typical arrangement using a multi­layer PCB.
10mF
0.1mF
AVDD
AD9225
AVSS
Figure 41. Analog Supply Decoupling
The CML is an internal analog bias point used internally by the
AD9225. This pin must be decoupled with at least a 0.1 µF
capacitor as shown in Figure 42. The dc level of CML is ap­proximately AVDD/2. This voltage should be buffered if it is to be used for any external biasing.
Figure 42. CML Decoupling
–20–
REV. A
Page 21
The digital activity on the AD9225 chip falls into two general categories: correction logic, and output drivers. The internal correction logic draws relatively small surges of current, mainly during the clock transitions. The output drivers draw large current impulses while the output bits are changing. The size and duration of these currents are a function of the load on the output bits: large capacitive loads are to be avoided. Note, the internal correction logic of the AD9225 is referenced to AVDD while the output drivers are referenced to DRVDD.
The decoupling shown in Figure 43, 0.1 µF ceramic chip capaci- tors and a 10 µF tantalum are appropriate for a reasonable
capacitive load on the digital outputs (typically 20 pF on each pin). Applications involving greater digital loads should consider increasing the digital decoupling proportionally, and/or using external buffers/latches.
AD9225
10mF
0.1mF
Figure 43. Digital Supply Decoupling
A complete decoupling scheme will also include large tantalum or electrolytic capacitors on the PCB to reduce low frequency ripple to negligible levels. Refer to the AD9225/AD9225EB schematic and layouts in Figures 44–50 for more information regarding the placement of decoupling capacitors.
DRVDD
AD9225
DRVSS
–21–REV. A
Page 22
AD9225
6
VOUT
1
R25
2.49kV
2
JP19
12
1
R26
4.99kV
2
JP20
12
1
R27
4.99kV
2
1
P4
1
P4
3
P4
1
P5
2
P5
J5
J2
U5
REF43
VIN
GND
4
VCCIN
AGND
J1
VEEIN
JP10
12
JP11
12
JP12
12
DRVDDIN
DGND
1
2
1
2
JP13
JP6
2
1
C30
0.1mF
2
1
C29
0.1mF
2
R28 50V
12
2
C26
0.1mF 1
L3
FBEAD
12
1
C48
+
22mF 20V
2
1
2
L4
FBEAD
12
1
C49
+
22mF 20V
2
U9
11
L7404
L5
FBEAD
12
1
C51
+
22mF 20V
2
TP39
1
1
AVDD
C13
0.1mF 1
1
R1 50V
2
U8
21
56
L7404
21
JP7
21
JP8
21
R24 50V
+
1
2
11
1
+
2
10
C8 10mF 10V
2
C2 10mF 10V
VEE
TP37
1
1 2
TP28
1
9
L7404
R35 50V
3
U8
L7404
1
C18
+
10mF 10V
2
C19
10mF
10V
C53
0.1mF
1 2
3
1 2
U9
1
C56
0.1mF
2
2
JP17 AB
2
TP10 1
10
3
IN
AD187
2
IN
2
+
1
VCC
T1
T4-6T
TP36
1
C54
0.1mF
TP6
1
8
5U96
L7404
DRVDD
1
C16
0.1mF
2
1
TP4
1
TP1
1
U8
13 12
L7404
TP38
R34 50V
1
VCC
1
R31 820V
2
7
8
+V
N2
–V
4
VEE
VIN
OUT
N1
1
1
C31
0.1mF
2
4 5 6
TP7
1
U1
REF43
VOUT
GND
R19 4kV
1
U8
3
L7404
TP2
1
U8
1
L7404
TP27
1
4
JP14
2
6
1
0.1mF 12
1
1
C25
0.1mF
2
TP8
D11
+
2
R2
5kV
3
2
CCV
98
L7404
1
2
1
TP3
1
U4
1
+
C28
0.1mF
2
R29 1kV
2
C27
J3
2
1
2
13U912
DVDD
DECOUPLING
1
C9 10mF 10V
1 CW
2
U8
U9
2
L7404
AVDD
DECOUPLING
1
2
TP37
TP30
2
R30 316V
1
R23 200V
L7404
U9
1 2
1
2
3
1
R32 50V
2
JP18
1
P2
P2
1
C15
0.1mF
2
C17
0.1mF
R18 1kV
2
JP9
21
3
34
1
C10
0.1mF
2
U8
JP21
12
10kV
Q1 2N2222
1 2
1
2
JP16
1
A
CLK
2
B
A
JP32
U9
L7404
R3
1
2
C46 15pF
DVDDIN
DGND
JP4
JP1
JP5
B
2
1
C7
+
10mF 10V
2
1
1
+
2
1
2 1
2
21
21
21
3
C3 10mF 10V
TP31
1
R4 10kV
TP29
DUTAVDD
C34
0.1mF
1
1
C45 15pF
2
1
+
2
D10
D9 D8 D7 D6 D5
JP3
1
JP2
1
1 2
1
1
C6 22mF 20V
TP9
1
C57
0.1mF
C21
10mF
10V
12
R21
200V
R22
200V
FBEAD
1
2
2
1
19
OTR
1 2
3 4 5 6 7 8
L1
2 3
4 5 6 7 8 9
D4 D3 D2 D1 D0
2
2
1
2
10mF
G1 G2
A1 A2 A3 A4 A5 A6 A7 A8
CLR
CLK A B C D ENP GND
+
2
C20 10V
1
1
C44 15pF
2
2
74541
1
19
2 3 4 5 6 7 8 9
U2
74LS161
1
1
1
1
+
TP33 1
TP32
1
U6
G1 G2
A1 A2 A3 A4 A5 A6 A7 A8
JP22
JP23
JP24
JP25
1
2
1 2
LOAD
C35
0.1mF
C33
0.1mF
C14
0.1mF
VCC
GND
74541
VCC RCO
QA QB QC QD
ENT
2
2
2
2
2
1
C32
0.1mF
1 2
TP5 1
10V 10mF
2
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
U7
16 15 14 13 12 11 10
9
1
C24
0.1mF
2
C43 15pF
C12
0.1mF
12
C4
+
20 10
18 17 16 15 14 13 12 11
VCC
GND
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
1
C22
+
10mF
10V
2
2 1
1
C42 15pF
2
1
10V 10mF
20
10
18 17
16 15 14 13 12 11
JP28
12
JP30
12
R33 1kV
1
C39
0.001mF
1
C36
0.1mF
2
DUTDRVDD
DVDD
C11
0.1mF 12
C5
21
+
1
JP29
12
JP31
2
1
2
DVDD
1 2
DUTAVDD
JP15
B
A
2
21
J4
AVDD
JP26
12
15
AVDD2
16
AVSS2
17
SENSE
18
VREF
19
REFCOM
20
CAPB
21
CAPT
22
U3
CML
23
VINA
24
VINB
25
AVSS1
26
AVDD1
27
DRVSS
28
DRVDD
AD9225
1
C40
0.001mF
2
1
C41
0.001mF
2
TP40
1
R17 22V 1
R5 22V
1
R6 22V
1
R7 22V
1
R8 22V
1
R9 22V
1 R10 22V
1 R11 22V
1
R12 22V
1
R13 22V
1
R14 22V
1
R15 22V
1
R16 22V
1
3
R20 22V
12
1
C55
0.1mF
2
TP34
L2
FBEAD
1
12
1
C52
0.1mF
2
AVDD
14
OTR
13
D11
12
D10
11
D9
10
D8
9
D7
8
D6
7
D5
6
D4
5
D3
4
D2
3
D1
2
D0
1
CLK
1
C37
0.1mF
2
1
C38
0.1mF
2
L6
FBEAD
1
1
C59
0.1mF
2
TP25
1
2
TP24
1
2
TP23
1
2
TP22
1
2
TP21
1
2
TP20
1
2
TP19
1
2
TP26
1
2
TP18
1
2
TP17
1
2
TP16
1
2
TP15
1
2
TP14
1
2
TP13
1
TP12
1
TP11
1
DVDD
1
C50
+
10mF 10V
2
1
+
2
1
+
2
2
1
C1 10mF 10V
C23 10mF 10V
AVDDIN1
1
C47
+
22mF 20V
2
AGND
JP27
1
C58
+
22mF 20V
2
1P1
3P1
5P1
7P1
9P1
11 P1
13 P1
15
17
19
21
23
25
27
29
31
33
35
37
39
1
2
OTR
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CLK
2
DRVDD
DUTAUDD
DUTAVDDIN
2
AGND
1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P3
P3
P6
P6
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Figure 44. Evaluation Board Schematic
–22–
REV. A
Page 23
AD9225
Figure 45. Evaluation Board Component Side Layout (Not to Scale)
Figure 46. Evaluation Board Ground Plane Layout (Not to Scale)
Figure 48. Evaluation Board Solder Side Layout (Not to Scale)
Figure 49. Evaluation Board Power Plane Layout
Figure 47. Evaluation Board Component Side Silkscreen (Not to Scale)
Figure 50. Evaluation Board Solder Side Silkscreen (Not to Scale)
–23–REV. A
Page 24
AD9225
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Wide Body Small Outline IC
(R-28)
0.7125 (18.10)
0.6969 (17.70)
28 15
0.2992 (7.60)
0.2914 (7.40)
141
0.4193 (10.65)
0.3937 (10.00)
C3241a–1–7/98
0.0118 (0.30)
0.0040 (0.10)
0.311 (7.9)
0.301 (7.64)
0.078 (1.98)
0.068 (1.73)
0.008 (0.203)
0.002 (0.050)
PIN 1
0.0500 (1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
SEATING
PLANE
28-Lead Shrink Small Outline IC
(RS-28)
0.407 (10.34)
0.397 (10.08)
28 15
141
SEATING
PLANE
0.07 (1.79)
0.066 (1.67)
0.009 (0.229)
0.005 (0.127)
PIN 1
0.0256 (0.65)
BSC
0.015 (0.38)
0.010 (0.25)
0.0125 (0.32)
0.0091 (0.23)
0.212 (5.38)
0.205 (5.21)
8° 0°
0.0291 (0.74)
0.0098 (0.25)
0.0500 (1.27)
88 08
0.0157 (0.40)
0.03 (0.762)
0.022 (0.558)
x 458
–24–
PRINTED IN U.S.A.
REV. A
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