Datasheet AD9218BST-80, AD9218BST-65, AD9218BST-40, AD9218BST-105, AD9218-65PCB Datasheet (Analog Devices)

10-Bit, 40/65/80/105 MSPS

a

FEATURES
Dual 10-Bit, 40 MSPS, 65 MSPS, 80 MSPS, and

105 MSPS ADC
Low Power: 275 mW at 105 MSPS per Channel
On-Chip Reference and Track/Holds
300 MHz Analog Bandwidth Each Channel
SNR = 57 dB @ 41 MHz, Encode = 80 MSPS
1 V p-p or 2 V p-p Analog Input Range Each Channel
Single 3.0 V Supply Operation (2.7 V–3.6 V)
Power-Down Mode for Single Channel Operation
Two’s Complement or Offset Binary Output Mode
Output Data Alignment Mode
Pin-Compatible with 8-Bit AD9288
–75 dBc Crosstalk between Channels

APPLICATIONS
Battery-Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
I and Q Communications
Ultrasound Equipment

ENCODE A

A

IN

A

IN

REFINA

REF

OUT

REF

IN

AINB

A

IN

ENCODE B

3 V Dual A/D Converter

FUNCTIONAL BLOCK DIAGRAM

FUNCTIONAL BLOCK DIAGRAM

ADC

10 10

REF

ADC

10 10

D

AD9218

OUTPUT

REGISTER

OUTPUT

REGISTER

GNDV

TIMING

A

A

B

B

T/H

T/H

TIMING

AD9218

D9A–D

USER
SELECT #1

USER
SELECT #2

DATA
FORMAT/
GAIN

D

9B–D0B

V

DD

0A

GENERAL DESCRIPTION

The AD9218 is a dual 10-bit monolithic sampling analog-to­digital converter with on-chip track-and-hold circuits and is
optimized for low cost, low power, small size and ease of use.
The product operates at a 105 MSPS conversion rate with
outstanding dynamic performance over its full operating range.
Each channel can be operated independently.

The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power
supply and an encode clock for full operation. No external
reference or driver components are required for many applica­tions. The digital outputs are TTL/CMOS-compatible and a
separate output power supply pin supports interfacing with

3.3 V or 2.5 V logic.

The clock input is TTL/CMOS-compatible and the 10-bit
digital outputs can be operated from 3.0 V (2.5 V to 3.6 V)
supplies. User-selectable options are available to offer a combi­nation of power-down modes, digital data formats and digital
data timing schemes. In power-down mode, the digital outputs
are driven to a high-impedance state.

Fabricated on an advanced CMOS process, the AD9218 is
available in a 48-lead surface-mount plastic package (7 × 7 mm
LQFP) specified over the industrial temperature range (–40°C
to +85°C).

PRODUCT HIGHLIGHTS

Low Power—Just 275 mW power dissipation per channel at
105 MSPS. Other speed grade proportionally scaled down while
maintaining high ac performance.

Pin Compatibility Upgrade—Allows easy migration from 8-bit
to 10-bit. Pin-compatible with the 8-bit AD9288 dual ADC.

Ease of Use—On-chip reference and user controls provide flex­ibility in system design.

High Performance—Maintain 54 dB SNR at 105 MSPS with a
Nyquist input.

Channel Crosstalk—Very low at –75 dBc.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD9218–SPECIFICATIONS

DC SPECIFICATIONS

(VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.)

Test AD9218BST-40/-65 AD9218BST-80/-105

Parameter Temp Level Min Typ Max Min Typ Max Unit

RESOLUTION 10 10 Bits

ACCURACY

No Missing Codes
Offset Error
Gain Error

1

2

2

Full VI GNT GNT
25°C I –18 2 18 –18 2 18 LSB
25°C I –2 3 8 –2 3.5 8 % FS

Differential Nonlinearity 25°CI –1 ±0.3/±0.6 1/1.3 –1 ± 0.5/± 0.8 1.2/1.7 LSB
(DNL)

Full VI ±0.8 ±0.6/±0.9 LSB

Integral Nonlinearity (INL) 25°C I –1/–1.6 ±0.3/±1 1/1.6 –1.35/–2.7 ±0.75/±2 1.35/2.7 LSB

Full VI ±1 ±1/±2.3 LSB

TEMPERATURE DRIFT

Offset Error Full V 10 4 ppm/°C
Gain Error

2

Full V 80 100 ppm/°C

Reference Full V 40 40 ppm/°C

REFERENCE

Internal Reference Voltage 25°C I 1.18 1.24 1.28 1.18 1.24 1.28 V
(REFOUT)
Input Resistance (REFIN A, B) Full V 9 11 13 9 11 13 kΩ

ANALOG INPUTS

Differential Input Voltage Full V 1 or 2 1 V
Range (AIN, AIN)

3

Common-Mode Voltage Full V VD/3 VD/3 V
Input Resistance Full VI 8 10 14 8 10 14 kΩ
Input Capacitance 25°CV 3 3 pF

POWER SUPPLY

V

D

V

DD

Supply Currents

IV

(VD = 3.0 V)

D

(VDD = 3.0 V)

IV

DD

4

4

Power Dissipation DC
IV

Power-Down Current

D

5

6

Full IV 2.7 3 3.6 2.7 3 3.6 V
Full IV 2.7 3 3.6 2.7 3 3.6 V

Full VI 108/117 113/122 172/183 175/188 mA
25°C V 7/11 13/17 mA
Full VI 325/350 340/365 515/550 525/565 mW
Full VI 20 22 mA

Power Supply Rejection Ratio 25°CI ±1 ±1 mV/V

NOTES

1

No Missing Codes across industrial temperature range guaranteed for -40 MSPS, -65 MSPS, and -80 MSPS grades. No missing codes at room temperature guaran­teed for -105 grade.

2

Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.25 V external reference) -65 Grade in 2 V p-p range, -40, -85, -105 Grades in
1 V p-p range.

3

(AIN – AIN) = ±0.5 V in 1 V range (full scale), (AIN – AIN) = ± 1 V in 2 V range (full scale).

4

AC Power Dissipation measured with rated encode and a 10.3 MHz analog input @ 0.5 dBFS, C

5

DC Power Dissipation measured with rated encode and a dc analog input (Outputs Static, IVDD = 0)

6

In power-down state IVDD = ±10 µA typical (all grades).

Specifications subject to change without notice.

LOAD

= 5 pF.

–2–

REV. 0

AD9218

DIGITAL SPECIFICATIONS

(VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.)

Test AD9218BST-40/-65 AD9218BST-80/-105

Parameter Temp Level Min Typ Max Min Typ Max Unit

DIGITAL INPUTS

Encode Input Common Mode Full V VD/2 VD/2 V
Encode “1” Voltage Full VI 2 2 V
Encode “0” Voltage Full VI 0.8 0.8 V
Encode Input Resistance Full VI 1.8 2.0 2.3 1.8 2.0 2.3 kΩ
Logic “1” Voltage—S1, S2, DFS Full VI 2 2 V
Logic “0” Voltage—S1, S2, DFS Full VI 0.8 0.8 V
Logic “1” Current—S1 Full VI –50 ±10 +50 –50 ±10 +50 µA
Logic “0” Current—S1 Full VI –400 –230 –50 –400 –230 –50 µA
Logic “1” Current—S2 Full VI 50 230 400 50 230 400 µA
Logic “0” Current—S2 Full VI –50 ±10 +50 –50 ±10 +50 µA
Logic “1” Current—DFS Full VI 30 100 200 30 100 200 µA
Logic “0” Current—DFS Full VI –400 –230 –50 –400 –230 –50 µA
Input Capacitance—S1, S2, Encode Inputs 25°CV 2 2 pF
Input Capacitance DFS 25°C V 4.5 4.5 pF

DIGITAL OUTPUTS

Logic “1” Voltage Full VI 2.45 2.45 V
Logic “0” Voltage Full VI 0.05 0.05 V
Output Coding Two’s Comp. or Offset Binary Two’s Comp. or Offset Binary

Specifications subject to change without notice.

AC SPECIFICATIONS

(V

= 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.)

DD

Test AD9218BST-40/-65 AD9218BST-80/-105

Parameter Temp Level Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

1

Signal-to-Noise Ratio (SNR)

(Without Harmonics)
fIN = 10.3 MHz 25°C I 58/55 59/57 57/53 58/55 dB
f

= Nyquist

IN

2

25°C I -/54 59/56 55/52 57/54 dB

Signal-to-Noise Ratio (SINAD)

(With Harmonics)
f

= 10.3 MHz 25°C I 58/54 59/56 56/52 58/53 dB

IN

f

= Nyquist

IN

2

25°C I -/53 59/55 55/51 57/53 dB

Effective Number of Bits

fIN = 10.3 MHz 25°C I 9.4/8.8 9.6/9.1 9.1/8.4 9.4/8.6 Bits
f

= Nyquist

IN

2

25°C I -/8.6 9.6/8.9 9/8.3 9.3/8.6 Bits

Second Harmonic Distortion

fIN = 10.3 MHz 25°C I –72/–66 –89/–77 –69/–60 –77/–68 dBc
f

= Nyquist

IN

2

25°C I -/–63 –89/–72 –65/–57 –76/–66 dBc

Third Harmonic Distortion

fIN = 10.3 MHz 25°C I –68/–62 –79/–68 –62/–57 –71/–63 dBc
f

= Nyquist

IN

2

25°C I -/–60 –78/–64 –63/–57 –73/–69 dBc

Spurious Free Dynamic Range SFDR

fIN = 10.3 MHz 25°C I –68/–62 –79/–67 –62/–57 –69/–62 dBc
f

= Nyquist

IN

2

25°C I -/–60 –78/–64 –63/–57 –70/–63 dBc

Two-Tone Intermod Distortion (IMD)

f

= 10 MHz, f

IN1

= 11 MHz 25°C V –74/–73 dBc

IN2

at –7 dBFS

f

= 30 MHz, f

IN1

= 31 MHz 25°C V –73/–73 –77/–67 dBc

IN2

at –7 dBFS

Analog Bandwidth, Full Power 25°C V 300 300 MHz
Crosstalk 25°C V –75 –75 dBc

NOTES

1

AC specs based on an analog input voltage of –0.5 dBFS at 10.3 MHz unless otherwise noted. AC specs for -40, -80, -105 grades are tested in 1 V p-p range and
driven differentially. AC specs for -65 grade are tested in 2 V p-p range and driven differentially.

2

The -65, -80, and -105 grades are tested close to Nyquist for that grade: 31 MHz, 39 MHz, and 51 MHz for the -65, -80, and -105 grades respectively.

Specifications subject to change without notice.

REV. 0

–3–

AD9218–SPECIFICATIONS

SWITCHING SPECIFICATIONS

(VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.)

Test AD9218BST-40/-65 AD9218BST-80/-105

Parameter Temp Level Min Typ Max Min Typ Max Unit

ENCODE INPUT PARAMETERS

Maximum Encode Rate Full VI 40/65 80/105 MSPS
Minimum Encode Rate Full IV 20/20 20/20 MSPS
Encode Pulsewidth High (t
Encode Pulsewidth Low (t
Aperture Delay (t

)25°CV 2 2 ns

A

) Full IV 7/6 5/3.8 ns

EH

) Full IV 7/6 5/3.8 ns

EL

Aperture Uncertainty (Jitter) 25°C V 3 3 ps rms

DIGITAL OUTPUT PARAMETERS

Output Valid Time (tV)* Full VI 3 3 ns
Output Propagation Delay (t
Output Rise Time (t
Output Fall Time (t

)25°C V 1 1.0 ns

R

)25°C V 1.2 1.2 ns

F

)* Full VI 4.5 7 4.5 6 ns

PD

Out of Range Recovery Time 25°CV 5 5 ns
Transient Response Time 25°CV 5 5 ns
Recovery Time from Power-Down 25°C V 10 10 Cycles
Pipeline Delay Full IV 5 5 Cycles

NOTES
*tV and tPD are measured from the 1.5 level of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to

exceed an ac load of 5 pF or a dc current of ± 40 µA. Rise and fall times measured from 10% to 90%.

Specifications subject to change without notice.

SAMPLE N

SAMPLE

N+1

SAMPLE

N+5

SAMPLE

N+6

ENCODE

A&B

D9A–D

D9B–D

A,

A

IN

B

A

IN

t

A

t

EH

0A

0B

t

EL

DATA N–5

DATA N–5 DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N

1/f

DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N

SAMPLE

N+2

S

SAMPLE

N+3

SAMPLE

N+4

t

PD

Figure 1. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing

t

V

–4–

REV. 0

AD9218

SAMPLE

N+1

t

N+2

SAMPLE

EL

DATA N–9 DATA N–7 DATA N–5 DATA N–3 DATA N–1 DATA N+1

SAMPLE

N+3

1/f

S

N+4

SAMPLE

N+5

SAMPLE

SAMPLE

N+6

N+7

SAMPLE

N+8

t

PD

ENCODE A

ENCODE B

D

D9B–D

A

A,

IN

A

IN

9A–D0A

SAMPLE

B

t

A

t

EH

0B

SAMPLE

N

DATA N–10 DATA N–8 DATA N–6 DATA N–4 DATA N–2 DATA N DATA N+2

Figure 2. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing

SAMPLE

N+1

t

EL

SAMPLE

N+2

SAMPLE

1/f

N+3

S

SAMPLE

N+4

SAMPLE

N+5

SAMPLE

SAMPLE

N+6

N+7

SAMPLE

N+8

ENCODE A

SAMPLE

N

A

A,

IN

A

B

IN

t

A

t

EH

t

V

ENCODE B

D

D9B–D

t

PD

9A–D0A

0B

DATA N–10 DATA N–8 DATA N–6 DATA N–4 DATA N–2 DATA N DATA N+2

DATA N–11 DATA N–9 DATA N–7 DATA N–5 DATA N–3 DATA N–1 DATA N+1

Figure 3. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing

t

V

REV. 0

–5–

AD9218

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V

Analog Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to V

Digital Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to V

REF

Inputs . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V

IN

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C

Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W

θ

JA

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.

2

Measured on a four-layer board with solid ground plane.

1

EXPLANATION OF TEST LEVELS
Test Level

+ 0.5 V

D

+ 0.5 V

DD

I 100% production tested.
II 100% production tested at 25°C and sample tested at speci-

fied temperatures.

III Sample tested only.

IV Parameter is guaranteed by design and characterization testing.

V Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design

and characterization testing for industrial temperature
range; 100% production tested at temperature extremes
for military devices.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9218 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Temperature Package

Model Range Package Description Option

AD9218BST-40, -65, -80, -105 –40°C to +85°C Metric Quad Flat Pack (1.4 mm thick: LQFP) ST-48
AD9218-65PCB 25°C Evaluation Board (Supports -40/-65 Grade)
AD9218-105PCB 25°C Evaluation Board (Supports -80/-105 Grade)

Table I. User Select Modes

S1 S2 User Select Options

0 0 Power-Down Both Channel A and B.
0 1 Power-Down Channel B Only.
1 0 Normal Operation (Data Align Disabled).
1 1 Data Align Enabled (data from both channels

available on rising edge of Clock A. Channel B
data is delayed by a 1/2 clock cycle.)

–6–

REV. 0

AD9218

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1, 12, 16, 27, 29, 32, 34, 45 GND Ground

2A
3 AINA Analog Input for Channel A (Complementary)

4 DFS/GAIN Data Format Select and Analog Input Gain Mode. (Low = offset binary out-

5 REF
6 REF
7 REFINB Reference Voltage Input for Channel B
8 S1 User Select #1 (Refer to Table I)
9 S2 User Select #2 (Refer to Table I)
10 AINB Analog Input for Channel B (Complementary)
11 A
13, 30, 31, 48 V
14 ENC
15, 28, 33, 46 V
17–26 D9
35–44 D0
47 ENC

A Analog Input for Channel A

IN

put available, 1 V p-p supported; high = two’s complement output available,
1 V p-p supported; floating = offset binary output available, 2 V p-p supported;
Set to V

A Reference Voltage Input for Channel A

IN

OUT

B Analog Input for Channel B

IN

D

B

DD

–D0

B

B

–D9

A

A

A

Internal Reference Voltage

Analog Supply (3 V)
Clock Input for Channel B
Digital Supply (2.5 V to 3.6 V)
Digital Output for Channel B (D9B = MSB)
Digital Output for Channel A (D9A = MSB)
Clock Input for Channel A

= two’s complement output available, 2 V p-p supported.)

REF

GND

A

IN

AINA

DFS/GAIN

REF

IN

REF

OUT

REFINB

A

IN

AINB

GND

PIN CONFIGURATION

(MSB)

B

ENC

V

A

D9

AD9218

TOP VIEW

(Not to Scale)

B

DD

GND

(MSB) D9

VDENCAVDDGND

48 47 46 45 44 39 38 3743 42 41 40

1

PIN 1

2

A

IDENTIFIER

3

4

5

A

6

7

8

S1

9

S2

B

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

D

V

AD7AD6AD5AD4AD3AD2A

D8

D8BD7BD6BD5BD4BD3BD2

36

D1

A

35

D0

A

34

GND

33

V

DD

32

GND

31

V

D

30

V

D

29

GND

28

V

DD

27

GND

26

D0

B

25

D1

B

B

REV. 0

–7–

AD9218

TERMINOLOGY
Analog Bandwidth

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.

Aperture Delay

The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Crosstalk

Coupling onto one channel being driven by a low level (–40 dBFS)
signal when the adjacent interfering channel is driven by a
full-scale signal.

Differential Analog Input Resistance, Differential Analog
Input Capacitance and Differential Analog Input Impedance

The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci­tance and differential input impedances are measured with a
network analyzer.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180
degrees out of phase. Peak-to-peak differential is computed by
rotating the inputs phase 180 degrees and again taking the peak
measurement. The difference is then computed between both
peak measurements.

Differential Nonlinearity

The deviation of any code width from an ideal 1 LSB step.

Effective Number of Bits

The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:

SNR dB

ENOB

ENCODE Pulsewidth/Duty Cycle

MEASURED

=

– ..176

602

Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. See timing implications of
changing t

in text. At a given clock rate, these specifica-

ENCH

tions define an acceptable ENCODE duty cycle.

Full-Scale Input Power

Expressed in dBm. Computed using the following equation:

Gain Error

Power

Full Scale

−

2



V

Full Scale rms



Z

10

=

log

INPUT



0 001

.







−








Gain error is the difference between the measured and ideal full
scale input voltage range of the ADC.

Harmonic Distortion, Second

The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.

Harmonic Distortion, Third

The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.

Integral Nonlinearity

The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.

Noise (for Any Range within the ADC)

VZ

=× ×

NOISE

0 001 10

.



−−

FS SNR Signal

dBm dBc dBFS




10






Where Z is the input impedance, FS is the full scale of the
device for the frequency in question, SNR is the value for the
particular input level, and Signal is the signal level within the
ADC reported in dB below full scale. This value includes both
thermal and quantization noise.

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in
power supply voltage.

Signal-to-Noise-and-Distortion (SINAD)

The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics but excluding dc.

Signal-to-Noise Ratio (without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo­nents, excluding the first five harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo­nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered), or dBFS (always
related back to converter full scale).

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.

Two-Tone SFDR

The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).

–8–

REV. 0

AD9218

S2

10k⍀

V

D

S1

10k⍀

V

D

Worst Other Spur

The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.

Transient Response Time

Transient response is defined as the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
negative full scale to 10% below positive full scale.

Out-of-Range Recovery Time

Out of range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.

EQUIVALENT CIRCUITS

V

D

30k⍀ 30k⍀

40⍀ 40⍀

A

IN

15k⍀

15k⍀

A

IN

Figure 4. Analog Input Stage

V

D

REF

10k⍀

Figure 8. Reference Inputs

Figure 9. S2 Input

V

D

2.6k⍀

ENCODE

600⍀

2.6k⍀

Figure 5. Encode Inputs

V

D

OUT

Figure 6. Reference Output Stage

V

DD

Figure 10. S1 Input

V

D

15k⍀

DFS/GAIN

15k⍀

VREF

Figure 11. DFS/Gain Input

40⍀

DX

REV. 0

Figure 7. Digital Output Stage

–9–

AD9218

–Typical Performance Characteristics

0

ENCODE = 105MSPS

–10

–20

–30

–40

–50

dB

–60

–70

–80

–90

–100

= 50.1MHz AT –0.5dBFS

A

IN

SNR = 53.8dB
SINAD = 53.4dB
H2 = –69dB
H3 = –65.8dB

0

52.5

TPC 1. FFT: FS = 105 MSPS, AIN = 50.1 MHz @ –0.5 dBFS,
Differential, 1 V p-p Input Range

0

ENCODE = 80MSPS

–10

= 39MHz AT –0.5dBFS

A

IN

SNR = 56.1dB

–20

SINAD = 55.5dB
H2 = –71.8dB
H3 = –66.2dB

–30

–40

–50

dB

–60

–70

–80

–90

–100

040

0

ENCODE = 40MSPS

–10

= 19.75 MHz AT –0.5dBFS

A

IN

SNR = 58.4dB

–20

SINAD = 58.3dB
H2 = –87dB

–30

H3 = –81dB

–40

–50

dB

–60

–70

–80

–90

–100

020

TPC 4. FFT: FS = 40 MSPS, AIN = 19.7 MHz @ –0.5 dBFS,
Differential, 1 V p-p Input Range

0

ENCODE = 105MSPS

–10

–20

–30

–40

–50

dB

–60

–70

–80

–90

–100

= 70MHz AT –0.5dBFS

A

IN

SNR = 51.9dB
SINAD = 51.8dB
H2 = –70.5dB
H3 = –76.3dB

0

40

TPC 2. FFT: FS = 80 MSPS, AIN = 39 MHz @ –0.5 dBFS,
Differential, 1 V p-p Input Range

0

ENCODE = 65MSPS

–10

AIN = 30.3MHz AT –0.5dBFS

SNR = 56.1dB

–20

SINAD = 55.9dB
SFDR = 72dB

–30

H2 = –83.2dB
H3 = –79dB

–40

–50

dB

–60

–70

–80

–90

–100

0

32.5

TPC 3. FFT: FS = 65 MSPS, AIN = 30.3 MHz @ –0.5 dBFS,
Differential, 2 V p-p Input Range

TPC 5. FFT: FS = 105 MSPS, AIN = 70 MHz @ –0.5 dBFS,
Differential, 1 V p-p Input Range

0

ENCODE = 65MSPS

–10

AIN = 15MHz AT –0.5dBFS
SNR = 56.4dB

–20

SINAD = 55.9dB
H2 = –73.9dB

–30

H3 = –71.7dB

–40

–50

dB

–60

–70

–80

–90

–100

0 32.5

TPC 6. FFT: FS = 65 MSPS, AIN = 15 MHz @ –0.5 dBFS;
with AD8138 Driving ADC Inputs, 1 V p-p Input Range

–10–

REV. 0

AD9218

–100

0

–90

52.5

–80

–70

–60

–50

–40

–30

–20

–10

0

ENCODE = 105MSPS
AIN1 = 30.1MHz AT –7dBFS
AIN2 = 31.1MHz AT –7dBFS
SFDR = –67dBFS

dB

–100

0

–90

40

–80

–70

–60

–50

–40

–30

–20

–10

0

ENCODE = 80MSPS
AIN1 = 29.3MHz AT –7dBFS
AIN2 = 30.3MHz AT –7dBFS
SFDR = –77dBFS

dB

0

ENCODE = 31MSPS

= 8MHz AT –0.5dBFS

A

IN

–10

SNR = 59.23dB
SINAD = 59.1dB

–20

H2 = –87dB
H3 = –81dB

–30

–40

–50

dB

–60

–70

–80

–90

–100

0 15.5

TPC 7. FFT: FS = 31 MSPS, AIN = 8 MHz @ –0.5 dBFS,
Differential, 1 V p-p Input Range

80

75

70

65

60

55

dB

50

45

40

35

30

050

2ND

3RD

SFDR

100 150 200 250

AIN FREQUENCY – MHz

0

ENCODE = 31MSPS

AIN = 8MHz AT –0.5dBFS

–10

SNR = 59dB
SINAD = 58.8dB

–20

H2 = –78.7dB
H3 = –72.9dB

–30

–40

–50

dB

–60

–70

–80

–90

–100

0 15.5

TPC 10. FFT: FS = 31 MSPS, AIN = 8 MHz @ –0.5 dBFS;

with AD8138 Driving ADC Inputs, 1 V p-p Input Range

TPC 8. Harmonic Distortion (Second and Third) and SFDR

Frequency (1 V p-p, FS = 105 MSPS)

vs. A

IN

80

75

2ND

70

65

60

55

dB

50

45

40

35

30

050

SFDR

3RD

100 150 200 250

AIN FREQUENCY – MHz

TPC 9. Harmonic Distortion (Second and Third) and SFDR

Frequency (1 V p-p, FS = 80 MSPS)

vs. A

IN

REV. 0

TPC 11. Two–Tone Intermodulation Distortion (30 MHz
and 31 MHz; 1 V p-p, FS = 105 MSPS)

TPC 12. Two–Tone Intermodulation Distortion (29.3 MHz,

30.3 MHz; 1 V p-p, FS = 80 MSPS)

–11–

AD9218

90

80

H3
1V

70

60

50

dB

40

30

20

10

0 20 40 60 80 100 120 140 160 180

H2 1V

1V DIFFERENTIAL DRIVE

SFDR 1V

H2 2V

H3 2V

SFDR 2V

2V SINGLE-ENDED DRIVE

AIN FREQUENCY – MHz

TPC 13. Harmonic Distortion (Second and Third) and
SFDR vs. A

dB

Frequency (FS = 65 MSPS)

IN

90

85

80

75

70

65

60

55

50

10 20 30 40 50 60 70

SFDR

AIN FREQUENCY – MHz

3rd

2nd

0

ENCODE = 65MSPS

–10

AIN1 = 28.1MHz AT –7dBFS
AIN2 = 29.1MHz AT –7dBFS

–20

SFDR = –72.9dBFS

–30

–40

–50

dB

–60

–70

–80

–90

–100

0

32.5

TPC 16. Two-Tone Intermodulation Distortion
(28 MHz, 29 MHz; 1 V p-p, FS = 65 MSPS)

0

ENCODE = 40MSPS

–10

1 = 10MHz AT –7dBFS

A

IN

A

2 = 11MHz AT –7dBFS

IN

–20

SFDR = 74dBc

–30

–40

–50

dB

–60

–70

–80

–90

–100

0

20

TPC 14. Harmonic Distortion (Second and Third) and
SFDR vs. A

dB

Frequency (1 V p-p, FS = 40 MSPS)

IN

75

70

65

60

55

50

45

020

40 60 80 100

ENCODE RATE – MSPS

SFDR

SINAD

120

TPC 15. SINAD and SFDR vs. Encode Rate

= 10.3 MHz, 105 MSPS Grade) AIN = –0.5 dBFS

(f

IN

Differential, 1 V p-p Analog Input Range

TPC 17. Two–Tone Intermodulation Distortion
(10 MHz, 11 MHz; 1 V p-p, FS = 40 MSPS)

80

75

70

65

dB

60

55

50

45

0 102030 40

ENCODE RATE – MHz

50 60 70 80

SFDR

SNR

SINAD

TPC 18. SINAD and SFDR vs. Encode Rate
(A

= 10.3 MHz, 65 MSPS Grade) AIN = –0.5 dBFS

IN

Differential, 1 V p-p Analog Input Range

–12–

REV. 0

AD9218

75

70

65

60

55

dB

50

45

40

35

30

01

SINAD

2345678

ENCODE POSITIVE PULSEWIDTH – ns

SFDR

TPC 19. SINAD and SFDR vs. Encode Pulsewidth High.

= –0.5 dBFS Single-Ended, 1 V p-p Analog Input

A

IN

Range 105 MSPS

200

180

160

140

mA

120

IVD -65

100

80

020

TPC 20. IVD and I

IVD -105

-65/-105 IV

40 60 80 100 120 140

ENCODE CLOCK RATE – MSPS

vs. Encode Rate (AIN = 10.3 MHz,

VDD

DD

50

45

40

35

30

25

20

15

10

5

0

@ –0.5 dBFS). -65/-105 MSPS Grade Cl = 5 pF

75

70

65

60

dB

55

50

45

40

0 4 6 8 10 12214

SFDR

SINAD

ENCODE POSITIVE PULSEWIDTH – ns

TPC 22. SINAD and SFDR vs. Encode Pulsewidth High.

= –0.5 dBFS Single Ended, 1 V p-p Analog Input

A

IN

Range 65 MSPS

4.5

mA

IV

4.0

3.5

DD

%

3.0

2.5

2.0
–40 –200 20406080

GAIN -105

TEMPERATURE – ⴗC

TPC 23. Gain Error vs. Temperature. AIN = 10.3 MHz,

-65 MSPS Grade, -105 MSPS Grade, 1 V p-p

GAIN -65

REV. 0

1.231

1.229

1.227

1.225

V

1.223

1.221

1.119

–40 –20 0 20406080

TPC 21. V

= 300µA)

(I

LOAD

Output Voltage vs. Temperature

REF

TEMPERATURE – ⴗC

–13–

68

SFDR -65

66

64

62

SNR -65

60

dB

58

56

54

52

–40 –200 20406080

SNR -105

SINAD -105

TEMPERATURE – ⴗC

SFDR -105

SINAD -65

TPC 24. SNR, SINAD, SFDR vs. Temperature.

= 10.3 MHz , -65 MSPS Grade, -105 MSPS Grade,

A

IN

1 V p-p

AD9218

1.50

1.45

1.40

1.35

1.30

V

1.25

1.20

1.15

1.10

1.05

1.00
–1.0 –0.5 0 0.5 1.0 1.5 2.0

TPC 25. V

2.0

1.5

1.0

0.5

0

LSB

–0.5

–1.0

–1.5

–2.0

0

I

LOAD

REF

CODES

– mA

vs. I

LOAD

2.5

1024

TPC 26. Typical INL Plot. 10.3 MHz AIN @ 80 MSPS

90

SFDR – dBFS

80

70

60

50

dB

40

30

20

10

0
–60 –50 –40 –30 –20 –10 0

SFDR – dBc

70 dB REF LINE

SNR – dBc

AIN INPUT LEVEL – dBFS

TPC 27. SFDR vs. AIN Input Level. 10.3 MHz AIN @ 80 MSPS

1.0

0.8

0.6

0.4

0.2

0

LSB

–0.2

–0.4

–0.6

–0.8

–1.0

0

CODES

1024

TPC 28. Typical DNL Plot. 10.3 MHz AIN @ 80 MSPS

–14–

REV. 0

AD9218

THEORY OF OPERATION

The AD9218 ADC architecture is a bit-per-stage pipeline-type
converter utilizing switch capacitor techniques. These stages
determine the 7 MSBs and drive a 3-bit flash. Each stage provides
sufficient overlap and error correction allowing optimization of
comparator accuracy. The input buffers are differential, and both
sets of inputs are internally biased. This allows the most flexible
use of ac-coupled or dc-coupled and differential or single-ended
input modes. The output staging block aligns the data, carries
out the error correction, and feeds the data to output buffers.
The set of output buffers are powered from a separate supply,
allowing adjustment of the output voltage swing. There is no
discernible difference in performance between the two channels.

USING THE AD9218
ENCODE Input

Any high-speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A Track/
Hold circuit is essentially a mixer. Any noise, distortion, or
timing jitter on the clock will be combined with the desired
signal at the A/D output. For that reason, considerable care has
been taken in the design of the ENCODE input of the AD9218,
and the user is advised to give commensurate thought to the clock
source. The ENCODE input is fully TTL/CMOS-compatible.

Digital Outputs

The digital outputs are TTL/CMOS-compatible for lower
power consumption. During power-down, the output buffers
transition to a high impedance state. A data format selection
option supports either two’s complement (set high) or offset
binary output (set low) formats.

Analog Input

The analog input to the AD9218 is a differential buffer. For
best dynamic performance, impedance at AIN and AIN should
match. Special care was taken in the design of the analog input
section of the AD9218 to prevent damage and corruption of
data when the input is overdriven. The nominal input range is

1.024 V p-p. Optimum performance is obtained when the part is
driven differentially where common mode noise is minimized
and even order harmonics are reduced. An example of driving
the AD9218 differentially via a wideband RF transformer for
ac-coupled applications is shown in Figure 12. Applications
that require dc-coupled differential drive can be accommo­dated using the AD8138 differential output op amp, shown
in Figure 13.

A

IN

50⍀

ANALOG

SIGNAL

SOURCE

1:1

25⍀

25⍀

0.1␮F

AD9218

A

IN

50⍀

ANALOG

SIGNAL

SOURCE

10k⍀

5k⍀

AV

500⍀

500⍀

0.1␮F

AD8138

500⍀

525⍀

DD

VOCM

25⍀

15pF

25⍀

AD9218

A

IN

A

IN

Figure 13. Using the AD8138 to Drive the AD9218

Voltage Reference

A stable and accurate 1.25 V voltage reference is built into the
AD9218 (VREF OUT). In normal operation, the internal refer­ence is used by strapping Pin 5 (REF
to Pin 6 (REF

). The input range for each channel can be

OUT

A) and Pin 7 (REFINB)

IN

adjusted independently by varying the reference voltage inputs
applied to the AD9218. No appreciable degradation in per­formance occurs when the reference is adjusted ±5%. The
full-scale range of the ADC tracks reference voltage, which
changes linearly.

Timing

The AD9218 provides latched data outputs, with five pipeline
delays. Data outputs are available one propagation delay (t

PD

)
after the rising edge of the encode command (see Timing Dia­gram). The length of the output data lines and loads placed
on them should be minimized to reduce transients within the
AD9218. These transients can detract from the converter’s
dynamic performance.

The minimum guaranteed conversion rate of the AD9218 is
20 MSPS. At clock rates below 20 MSPS, dynamic performance
will degrade.

User Select Options

Two pins are available for a combination of operational modes.
These options allow the user to power-down both channels,
excluding the reference, or just the B channel. Both modes place
the output buffers in a high impedance state. Recovery from a
power-down state is accomplished in 10 clock cycles following
power-on.

The other option allows the user to skew the B Channel output
data by one-half a clock cycle. In other words, if two clocks are
fed to the AD9218 and are 180 degrees out of phase, enabling
the data align will allow Channel B output data to be available
at the rising edge of Clock A. If the same encode clock is pro­vided to both channels and the data align pin is enabled, output
data from Channel B will be 180 degrees out of phase with
respect to Channel A. If the same encode clock is provided to
both channels and the data align pin is disabled, both outputs are
delivered on the same rising edge of the clock.

Figure 12. Using a Wideband Transformer to Drive the
AD9218

REV. 0

–15–

AD9218

APPLICATIONS

The wide analog bandwidth of the AD9218 makes it attractive
for a variety of high-performance receiver and encoder appli­cations. Figure 14 shows the dual ADC in a typical low cost
I and Q demodulator implementation for cable, satellite, or
wireless LAN modem receivers. The excellent dynamic perfor­mance of the ADC at higher analog input frequencies and
encode rates empowers users to employ direct IF sampling
techniques. IF sampling eliminates or simplifies analog mixer
and filter stages to reduce total system cost and power.

AD9218

Q

ADC

ADC

VCO

I

IF IN

BPF

90

BPF

VCO

Figure 14. Typical I/Q Demodulation Scheme

EVALUATION BOARD

The AD9218 evaluation board offers an easy way to test the
AD9218. It provides a means to drive the analog inputs single­endedly or differentially. Differential drive can be tested through
a wideband RF transformer or a differential output operational
amplifier, the AD8138. The two encode clocks are accessible via
on-board SMB connectors J2, J7. These clocks are buffered
on board to provide the clocks for an on-board DAC and latches.
The digital outputs and output clocks are available at two 40-pin
connectors, P3 and P4. The board has several different modes
of operation, and is shipped in the following configuration:

• Differential Analog Input (RF Transformer Mode)

• Normal Operation Timing Mode

• Internal Voltage Reference

Power Connector

Power is supplied to the board via a detachable 12-pin power strip.

+5 V – Optional Supply for Operational Amplifier
–5 V – Optional Supply for Operational Amplifier
V

A – Optional External Reference Input

REF

B – Optional External Reference Input

V

REF

V

– Supply for Support Logic and DAC

DL

V

– Supply for ADC Outputs

DD

– Supply for ADC Analog

V

D

Analog Inputs

The evaluation board accepts a 1 V analog input signal centered
at ground at each analog input. SMB connectors J4 and J6 are
used for A

and BIN respectively. These signals each drive a

IN

wideband RF transformer T1, T2, allowing the ADC performance
for differential inputs to be measured using a single-ended source.
In this mode resistors R35, R33, R39, and R32 should not be in
place. Each analog input is terminated on the board with 50 Ω to
ground. Each input is ac-coupled on the board through a 0.1 µF
capacitor to an on-chip resistor divider that provides dc bias.
Single-ended performance can be measured by bypassing the
transformers using connectors SMB J5 (Channel A) and J1
(Channel B). In this mode, place a 0 Ω resistor at R35 and R33
(A Channel) and place R39 and R32 (B Channel). Note that the
inverting analog inputs are terminated on the board with 25 Ω
(optimized for differential operation). When driving the board
single-ended these resistors (R1, R3) can be changed to 50 Ω to
provide balanced inputs. The operational amplifier can be
used by connecting to J5 (Channel A) and J1 (Channel B).
The ac-coupling capacitors on the top level should be removed
from the board to use the operational amplifier. The compo­nents to use the op amp should be placed on the bottom of the
board. See PCB Bill of Materials list for values.

Encode

The encode clock for Channel A uses SMB connector J7.
Channel B encode uses SMB connector J2. Each clock input is
terminated on the board with 50 Ω to ground. The input clocks
are fed directly to the ADC and to buffers U5, U6, which drive
the DAC and latches. The clock inputs are TTL-compatible.

Voltage Reference

The AD9218 has an internal 1.25 V voltage reference. An exter­nal reference for each channel may be employed instead. The
evaluation board is configured for the internal reference (use
jumpers E18–E1 and E17–E19). To use external references,
connect to V

A and V

REF

B pins on the power connector P1

REF

and use jumpers E20–E18 and E19–E21.

Normal Operation Mode

In this mode both converters are clocked by the same encode
clock, latency is five clock cycles (see Timing Diagram). Signal
S1 (Pin 8) is held high and signal S2 (Pin 9) is held low. This is
set with the jumpers labeled S1 and S2 (near the analog input).

Data Align Mode

In this mode channel B output is delayed an additional one-half
cycle. Signals S1 (Pin 8) and signal S2 (Pin 9) are both held
high. This is set with the jumpers labeled S1 and S2 (near the
analog input).

Data Format Select

Data Format Select sets the output data format and the gain of
the ADC. Setting DFS (Pin 4) low sets the output format to be
offset binary and gain of 1; setting DFS high sets the output to
be two’s complement and gain of 1. Removing the jumper for
DFS sets the output data format to offset binary and a gain of 2;
setting DFS to the middle selection sets the output data format
to two’s complement and a gain of 2.

–16–

REV. 0

AD9218

PCB Bill of Materials

# Qty REFDES Device Package Value

1 29 C1, C3–C15, C20–C25, C27–C35 Capacitor 0603 0.1 µF
2 2 C2, C36 Capacitor 0603 15 pF
3 7 C16, C17, C18, C19, C26, C37, C38 Capacitor TAJD 10 µF
6 8 J1, J2, J3, J4, J5, J6, J7, J8 Connector SMB
7 3 P1, P4, P11 4-Pin Power Connector TB4 Wieland

25.531.3425.0
Z5.602.5453.0

8 2 P2, P3 HEADER40
10 8 R1–R4, R22–R24, R30 Resistor 0603 25 Ω
11 10 R5–R12, R34, R37 Resistor 0603 50 Ω
12 2 R13, R14 Resistor 0603 2 kΩ
13 6 R15, R17, R18, R26, R29, R31 Resistor 0603 500 Ω
14 2 R16, R25 Resistor 0603 525 Ω
15 2 R19, R27 Resistor 0603 4 kΩ
16 8 R20, R32, R33, R35, R36, R38–R40 Resistor 0603 0 Ω
17 2 R21, R28 Resistor 0603 1 kΩ
18 2 T1, T2 Transformer ADT-1-1WT Minicircuits
19 1 U1 AD9218 LQFP48
20 2 U2, U3 74LCX821 SO24M3
21 1 U4 AD9763 LQFP48
22 2 U5, U6 74LCX86 SO14
23 4 U7, U8, U9, U10 Resistor Array CTS20 22 Ω
24 2 U11, U12 AD8138 SO8NB

NOTE
R22, R23, R24, R30, R32, R33, R35, R36, R38, R39, R40, C2, C36 not placed on board.

Data Outputs

The ADC digital outputs are latched on the board by two
LCX821s, the latch outputs are available at the two 40-pin
connectors at Pins 23–33 on P3 (Channel A) and Pins 23–33 on
P4 (Channel B). The latch output clocks (data ready) are avail­able at Pin 4 on P3 (Channel A) and Pin 4 on P4 (Channel B).
The data ready signal on Channel B can be aligned with Clock
A input by connecting E43–E42 or aligned with Clock B input
by connecting E42–E33.

PIN 37 (CLOCK)

CH1

2.00V CH2 2.00V M 10.0ns CH4 40mV

PIN 31 (DATA)

T

Figure 15. Data Output and Clock at 80-Pin Connector

DAC Outputs

Each channel is reconstructed by an on-board dual channel DAC,
an AD9763. This DAC is intended to assist in debug only. It
should not be used to measure the performance of the ADC.
It is a current output DAC with on-board 50 Ω termination
resistors. Figure 16 is representative of the DAC output with a
full-scale analog input. The scope setting was low bandwidth,
50 Ω termination.

T

1

CH1

500mV⍀ M 50.0ns CH1

380mV

Figure 16. DAC Output

REV. 0

–17–

AD9218

D

DD

V

C17
10␮F

2

VREFA1VREFB

DL

V

C18
10␮F

P11

P1

E10

E32

E31

+5V

C38
10␮F

V

V

C16
10␮F

4

P4

DL

GND3GND

–5V

C37
10␮F

4

3

2 1

D

DD

V

V

GND

V

E9

D

V

DD

V

DD

V

DL

OPTIONAL INPUT PATH FOR OPAMP OR SINGLE-ENDED

GND

GND

J5

A

A

IN

SINGLE-ENDED

R5

50⍀

GND

J4

A

A

IN

DIFFERENTIAL

GND

R6

GND

50⍀

J6

A

B

IN

DIFFERENTIAL

A

B

IN

SINGLE-ENDED

J1

GND

R34
50⍀

R36
0⍀

AMPINA

GND

GND

C15

0.1␮F

GND

AMPINB

R38
0⍀

R37
50⍀

R35

00⍀

C31

0.1␮F

C14

0.1␮F

C30

0.1␮F

GND

GND

1
2

3

1
2

3

R39

0⍀

R33

00⍀

T2

T1

GND

R1
25⍀

C10

GND

0.1␮F

R2

6

25⍀

5

4

6
5

4

R32

0⍀

R4
25⍀

GND

C9

0.1␮F

V

25⍀

D

R3

GND

OPTIONAL INPUT PATH FOR OPAMP OR SINGLE-ENDED

GND

REFINA

H3

GND

C27

0.1␮F

C24

0.1␮F

REFINB

MT HOLE6

H1

MT HOLE6H2MT HOLE6H4MT HOLE6

VREFA

4

3

GND

REF

E23

E28 E26

GND

GND

C19
10␮F

2

+5V

OUT

GND

C11

0.1␮F

–5V

V

V

1

D

E2

D

VREFB

C26
10␮F

GND

E27

GND

C12

0.1␮F

GND

E25

E30

GND

E29 E22

V

AINAB

VREFA
VREFB

E24

A

V

DL

AINA

A

IN

IN

DL

E20

E21

BB

B

E46

E17

E49

GND

GND

E1

GND

GND

E45

GND

E18

E19

E48

GND

E47

10

11

12

E50

DUT CLOCK SELECTABLE TO BE DIRECT OR BUFFERED

ENC

ENCODE A

J7

TIEA

R11

50⍀

GND

E35

V

DL

GND

ENC

E36

E34

GND

V

DD

C8

0.1␮F

ENC

C7

0.1␮F

A

V

D

GND

GND

D9A

4847464544434241403938

D

A

DD

V

V

D9A

GND

A

A

IN

AINAB

IN

OUT

ENC

A

AD9218

1

GND

2

3

4

DFS/GAIN

5

REF

6

REF

7

REFINB

8

S1

9

S2

AINB

AINB

GND

B

D

DD

V

V

ENC

GND

D9B

1314151617181920212223

C5

0.1␮F
V

D

ENC

D9B

GND

GND

C6

B

0.1␮F

V

DD

DUT CLOCK SELECTABLE TO BE DIRECT OR BUFFERED

ENC

ENCODE B

J2

TIEB

V

R7

50⍀

GND

E13

DL

GND

ENC

E16

E14

GND

A

P12 P19

P13

A

CLKLATA

D8A

D7A

D8A

D7A

U1

D8B

D7B

D8B

D7B

B

P20 P21

P23

B

TIEA

P14

GND

D6A

D6A

D6B

D6B

TIEB

P22

DRB

GND

D5A

D5A

D5B

D5B

1

2

3

4

5

6

7

D4A

D4A

D4B

D4B

1

2

3

4

5

6

7

1A

1B

1Y

2A

2B

2Y

GND

D3A

D3A

D3B

D3B

1A

1B

1Y

2A

2B

2Y

GND

74LCX86

D2A

37

D2A

D1A

D0A

GND

V

GND

GND

V

GND

D0B

D1B

D2B

24

D2B

74LCX86

GND

C25

0.1␮F

14

V

CC

13

4B

12

4A

U8

DD

V

V

DD

11

4Y

10

3B

9

3A

8

3Y

36

D1A

35

D0A

34

GND

33

32

GND

31

D

30

D

29

GND

28

27

GND

26

D0B

25

D1B

E40

E3

GND

GND

E39

C4

0.1␮F

C3

0.1␮F

GND

C1

0.1␮F

V

DL

E41

GND

CLKDACA

E38

E37

GND

DRA

V

DL

V

DL

V

DD

V

D

V

DD

GND

C13

0.1␮F

14

V

CC

13

4B

12

4A

U5

11

4Y

10

3B

9

3A

8

3Y

E5

E4

GND

E15

V

DL

E44

CLKLATB

E11

E12

GND

V

DL

V

DL

CLKDACB

Figure 17a. PCB Schematic

–18–

REV. 0

GND

DRA

GND

D9P

D8P

D7P

D6P

D5P

D4P

D3P

D2P

D1P

D0P

GND

GND

GND

GND

GND

GND

GND

E6

E7

GND

DRA

E8

GND

DRB

D9Q

D8Q

D7Q

D6Q

D5Q

D4Q

D3Q

D2Q

D1Q

D0Q

GND

GND

AD9218

GND

GND

GND

GND

GND

393735333129272523211917151311

393735333129272523211917151311

P3

HEADER40

403836343230282624222018161412

403836343230282624222018161412

D9P

D8P

D7P

D6P

D5P

D4P

D3P

D2P

D1P

D0P

201918171615141312

201918171615141312

U9

CT520

VALUE = 22

123456789

123456789

D9X

D8X

D7X

D6X

D5X

D4X

DL

V

D9X

D8X

D7X

D6X

C21

0.1␮F

GND

2423222120191817161514

CC

Y0Y1Y2Y3Y4Y5Y6Y7Y8

V

74LCX821

GNDX0X1X2X3X4X5X6X7X8X9

123456789

D5X

U2

D3X

D4X

D2X

D3X

11

11

10

10

D1X

D0X

D2X

D1X

101112

D0X

13

Y9

CLKLATA

CLK

GND

97531

97531

864

10

864

10

393735333129272523211917151311

393735333129272523211917151311

P2

GND

HEADER40

403836343230282624222018161412

403836343230282624222018161412

D0Q

D1Q

D2Q

D3Q

D4Q

D5Q

D6Q

D7Q

D8Q

D9Q

201918171615141312

201918171615141312

U10

CT520

VALUE = 22

123456789

123456789

D0Y

D1Y

D2Y

D3Y

D4Y

D5Y

DL

V

D0Y

D0Y

D0Y

D0Y

C20

0.1␮F

GND

2423222120191817161514

CC

Y0Y1Y2Y3Y4Y5Y6Y7Y8

V

74LCX821

OEX0X1X2X3X4X5X6X7X8X9

123456789

D0Y

U3

D6Y

D0Y

D7Y

D0Y

11

11

10

10

D8Y

D9Y

D0Y

D0Y

101112

E33

E42

D0Y

13

Y9

CLKLATD

E43

CLK

GND

2

2

97531

10

CLKLATA

97531

864

10

864

2

2

GND

CT520

REV. 0

D9M

D8M

D7M

D7M

D7A

D6M

D6A

D6M

D5M

D5A

GND

D9M

D8M

201918171615141312

201918171615141312

U7

VALUE = 22

123456789

123456789

D9A

D8A

D5M

D4M

D4A

D4M

D3M

D3A

D3M

D2M

D2A

D2M

D1M

D1A

11

10

D1M

D0M

11

10

D0A

D0M

GND

D0N

GND

D0N

D1N

201918171615141312

201918171615141312

U8

CT520

VALUE = 22

123456789

123456789

D0B

D1B

Figure 17b. PCB Schematic

–19–

D1N

D2N

D2B

D2N

D3N

D3B

D3N

D4N

D4B

D4N

D5N

D5B

D5N

D6N

D6B

D6N

D7N

D7B

D7N

D8N

D8B

D8N

D9N

GND

D9N

11

11

10

10

D9B

AD9218

GND

R16

525⍀

NC = NO CONNECT

R18

500⍀

R19

R21

4k⍀

1k⍀

+5V

123

–IN

VOCM

AD8138

DAC OUTPUT ADAC OUTPUT B

GND

GND

C22

0.1␮F

GND

V

DL

1

U11

10

11

12

GND

2

3

4

5

6

7

8

9

DB9
–P1

DB8–P1

DB7–P1

DB6–P1

DB5–P1

DB4–P1

DB3–P1

DB2–P1

DB1–P1

DB0–P1

NC

NC1

GND

R22

25⍀

D9Y

D8Y

D7Y

D6Y

D5Y

D4Y

D3Y

D2Y

D1Y

D0Y

U4

GND5V

C32

0.1␮F

4

V+

+OUT

J3

R10
50⍀

4847464544434241403938

MODE

GND

V

DL

AV

GND

R13, 2k⍀

R12, 50⍀

DD

IA2

IB1

FSADJ1

GND

C23

0.1␮F

REFIO

GND

GND

R14, 2k⍀

REFLO

FSADJ2

J8

GND

R8, 50⍀

IB2IA2

9763

DD

WRT1/IQWRT

CLK1/IQCLK

CLK2/IQRESET

NC2

NC3

GND

DCOM1

DV

1314151617181920212223

GND

GND

GND

C28

0.1␮F

V

C2
15pF

DL

AINA

CLKDACB

CLKDACB

WRT2/IQSEL

CLKDACA

CLKDACA

GND

GND

V

DL

R9

50⍀

GND

ACOM

SLEEP

DCOM2

DB9–P2

C29

0.1␮F

R25

525⍀

GND

GND

37

NC7

NC6

NC5

NC4

DB0–P2

DB1–P2

DB2–P2

DB3–P2

DB4–P2

DB5–P2

DB6–P2

DB7–P2

DB8–

P2

24

GND

00⍀

00⍀

POWER-DOWN OPTION

36

35

34

33

32

31

30

29

28

27

26

25

D8X

D9X

R27

4k⍀

R40

R20

D0X

D1X

D2X

D3X

D4X

D5X

D6X

D7X

R26

500⍀

123

–IN

AD8138

(OPTIONAL)

V

DL

GND

R28

1k⍀

+5V

0.1␮F

4

V+

+OUT

VOCM

GND5V

C35

U12

GND

R30
25⍀

C36
15pF

AINBB

NC = NO CONNECT

AMP

A

IN

R17

500⍀

GND

C33

0.1␮F

+INNCV–

876

–5V

–OUT

5

500⍀

R15

NC = NO CONNECT

R23

25⍀

AMP

AB

AI

IN

R29

500⍀

B

IN

Figure 17c. PCB Schematic

–20–

GND

876

C34

0.1␮F

+INNCV–

–5V

5

–OUT

R31

500⍀

R24
25⍀

B

A

IN

REV. 0

Figure 18. PCB Top Side Silkscreen

AD9218

REV. 0

Figure 19. PCB Top Side Copper

–21–

AD9218

Figure 20. PCB Ground Layer

Figure 21. PCB Split Power Plane

–22–

REV. 0

Figure 22. PCB Bottom Side Copper

AD9218

REV. 0

Figure 23. Bottom Side Silkscreen

–23–

AD9218

(

)

Troubleshooting

If the board does not seem to be working correctly, try the
following:

• Verify power at IC pins.

• Check that all jumpers are in the correct position for the
desired mode of operation.

• Verify V

is at 1.23 V.

REF

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

48-Lead LQFP

(ST-48)

0.063 (1.60)

0.030 (0.75)

0.018 (0.45)

COPLANARITY

0.003 (0.08)

MAX

0.008 (0.2)

0.004 (0.09)

0ⴗ
MIN

7ⴗ
0ⴗ

1

12

13

0.019 (0.5)

0.006 (0.15)

0.002

• Try running encode clock and analog inputs at low speeds
(20 MSPS/1 MHz) and monitor LCX821 outputs, DAC
outputs, and ADC outputs for toggling.

The AD9218 Evaluation Board is provided as a design example
for customers of Analog Devices, Inc. ADI makes no warranties,
express, statutory, or implied, regarding merchantability or
fitness for a particular purpose.

0.354 (9.00) BSC SQ

48

TOP VIEW

(PINS DOWN)

BSC

0.05

0.011 (0.27)

0.006 (0.17)

SEATING
PLANE

37

24

36

25

0.276

(7.00)

BSC

SQ

0.057 (1.45)

0.053 (1.35)

C02001–1.5–7/01(0)

PRINTED IN U.S.A.

–24–

REV. 0