Datasheet AD9216 Datasheet (Analog Devices)

10-Bit, 105 MSPS

FEATURES

Integrated dual 10-bit ADC Single 3 V supply operation (2.85 V to 3.15 V) SNR = 57 dBc (to Nyquist, AD9216-105) SFDR = 75 dBc (to Nyquist, AD9216-105) Low power: 300 mW at 105 MSPS Differential input with 300 MHz 3 dB bandwidth Exceptional crosstalk immunity > 80 dB Offset binary or twos complement data format Clock duty cycle stabilizer

APPLICATIONS

Ultrasound equipment IF sampling in communications receivers

3G, radio point-to-point, LMDS, MMDS Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes

GENERAL DESCRIPTION

The AD9216 is a dual, 3 V, 10-bit, 105 MSPS analog-to-digital converter (ADC). It features dual high performance sample-and hold amplifiers (SHAs) and an integrated voltage reference. The AD9216 uses a multistage differential pipelined architecture with output error correction logic to provide 10-bit accuracy and guarantee no missing codes over the full operating temperature range at up to 105 MSPS data rates. The wide bandwidth, differential SHA allows for a variety of userselectable input ranges and offsets, including single-ended applications. The AD9216 is suitable for various applications, including multiplexed systems that switch full-scale voltage levels in successive channels and for sampling inputs at frequencies well beyond the Nyquist rate.

Dual A/D Converter

AD9216

FUNCTIONAL BLOCK DIAGRAM

AVDD AGND

VIN+_A

VIN–_A

REFT_A

REFB_A

VREF

SENSE

AGND

REFT_B

REFB_B

VIN+_B

VIN–_B

SHA

0.5V

SHA

AD9216

ADC

DRVDD

Figure 1.

10

OUTPUT

BUFFERS

CLOCK

DUTY CYCLE

STABILIZER

CONTROL

10

OUTPUT

BUFFERS

DRGND

Fabricated on an advanced CMOS process, the AD9216 is available in a space saving, Pb-free, 64-lead LFCSP (9 mm × 9 mm) and is specified over the industrial temperature range (−40°C to +85°C).

PRODUCT HIGHLIGHTS

1. Pin compatible with AD9238, dual 12-bit 20 MSPS/40 MSPS/

65 MSPS ADC and AD9248, dual 14-bit 20 MSPS/40 MSPS/ 65 MSPS ADC.

2. 105 MSPS capability allows for demanding high frequency

applications.

MUX/

MODE

MUX/

10

D9_A–D0_A OEB_A

MUX_SELECT CLK_A CLK_B DCS

SHARED_REF PWDN_A PWDN_B DFS

D9_B–D0_B OEB_B

04775-001

Dual single-ended clock inputs are used to control all internal conversion cycles. A duty cycle stabilizer is available on the AD9216 and can compensate for wide variations in the clock duty cycle, allowing the converters to maintain excellent performance. The digital output data is presented in either straight binary or twos complement format.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

3. Low power consumption: AD9216-105: 105 MSPS = 300 mW.

4. The patented SHA input maintains excellent performance for

input frequencies up to 200 MHz and can be configured for single-ended or differential operation.

5. Typical channel crosstalk of > 80 dB @ f

up to 70 MHz.

IN

6. The clock duty cycle stabilizer maintains performance over a

wide range of clock duty cycles.

www.analog.com

AD9216

DC SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 1.

Parameter Temp Test Level Min Typ Max Unit RESOLUTION Full VI 10 Bits ACCURACY

No Missing Codes Full VI Guaranteed

Offset Error Full VI −3.6 ±0.7 +3.6 % FSR

Gain Error

Differential Nonlinearity (DNL)

25°C I −0.65 ±0.5 +1.0 LSB

Integral Nonlinearity (INL)2 Full V −2.8 ±1.0 +2.8 LSB 25°C I −1.8 ±1.0 +1.8 LSB TEMPERATURE DRIFT

Offset Error Full V ±10 µV/°C

Gain Error1 Full V ±75 ppm/°C

Reference Voltage Full V ±15 ppm/°C INTERNAL VOLTAGE REFERENCE

Output Voltage Error Full VI ±2 ±35 mV

Load Regulation @ 1.0 mA 25°C V 1.0 mV INPUT REFERRED NOISE

Input Span = 2.0 V 25°C V 0.5 LSB rms ANALOG INPUT

Input Span, VREF = 1.0 V Full IV 2 V p-p

Input Capacitance REFERENCE INPUT RESISTANCE Full V 7 kΩ POWER SUPPLIES

Supply Voltages

Supply Current

PSRR Full V ±0.1 % FSR POWER CONSUMPTION

P

AVDD

P

DRVDD

Standby Power MATCHING CHARACTERISTICS

Offset Matching Error

Gain Matching Error (Shared Reference Mode) 25°C I −0.6 ±0.1 +0.6 % FSR

Gain Matching Error (Nonshared Reference Mode) 25°C I −1.6 ±0.3 +1.6 % FSR

1

Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).

2

Measured with low frequency ramp at maximum clock rate.

3

Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure for the equivalent analog input structure. 24

4

Measured with low frequency analog input at maximum clock rate with approximately 5 pF loading on each output bit.

5

Standby power is measured with the CLK_A and CLK_B pins inactive (i.e., set to AVDD or AGND).

6

Shared reference mode or nonshared reference mode.

, DCS enabled, unless otherwise noted.

MAX

AD9216BCPZ-105

1

2

3

25°C VI −1.6 ±0.7 +1.6 % FSR Full V −1.0 ±0.5 +1.66 LSB

Full V 2 pF

AVDD Full IV 2.85 3.0 3.15 V DRVDD Full IV 2.85 3.0 3.15 V

4

IAVDD

Full VI 100 110 mA

IDRVDD4 Full VI 24 mA

4

5

6

25°C I 300 330 mW 25°C V 72 mW 25°C V 3.0 mW

25°C I −6.0 ±1.0 +6.0 % FSR

Rev. 0 | Page 3 of 36

AD9216

AC SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 2.

Parameter Temp Test Level Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR)

f

INPUT

25°C I 56.6 57.8 dB f

INPUT

25°C I 56.4 57.6 dB f

INPUT

f

INPUT

SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)

f

INPUT

25°C I 56.5 57.7 dB f

INPUT

25°C I 56.1 57.4 dB f

INPUT

f

INPUT

EFFECTIVE NUMBER OF BITS (ENOB)

f

INPUT

25°C I 9.2 9.4 Bits f

INPUT

25°C I 9.1 9.3 Bits f

INPUT

f

INPUT

WORST HARMONIC (SECOND OR THIRD)

f

INPUT

25°C I −76.0 −68.0 dBc f

INPUT

25°C I −74.0 −65.0 dBc f

INPUT

f

INPUT

WORST OTHER (EXCLUDING SECOND OR THIRD) f

INPUT

25°C I −75.0 −66.0 dBc f

INPUT

25°C I −75.0 −63.0 dBc f

INPUT

f

INPUT

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f

INPUT

25°C I 66.0 75.0 dBc f

INPUT

25°C I 63.0 74.0 dBc f

INPUT

f

INPUT

, DCS enabled, unless otherwise noted.

MAX

AD9216BCPZ-105

= 2.4 MHz Full IV 55.0 57.8 dB

= 50 MHz Full IV 54.8 57.6 dB

= 69 MHz 25°C V 57.4 dB = 100 MHz 25°C V 57.3 dB

= 2.4 MHz Full IV 54.9 57.7 dB

= 50 MHz Full IV 54.3 57.4 dB

= 69 MHz 25°C V 56.8 dB = 100 MHz 25°C V 56.7 dB

= 2.4 MHz Full IV 8.9 9.4 Bits

= 50 MHz Full IV 8.8 9.3 Bits

= 69 MHz 25°C V 9.2 Bits = 100 MHz 25°C V 9.2 Bits

= 2.4 MHz Full IV −76.0 −64.6 dBc

= 50 MHz Full IV −74.0 −58.4 dBc

= 69 MHz 25°C V −74.0 dBc = 100 MHz 25°C V −74.0 dBc

= 2.4 MHz Full IV −75.0 −65.0 dBc

= 50 MHz Full IV −75.0 −62.0 dBc

= 69 MHz 25°C V −77.0 dBc = 100 MHz 25°C V −77.0 dBc

= 2.4 MHz Full IV 64.6 75.0 dBc

= 50 MHz Full IV 58.4 74.0 dBc

= 69 MHz 25°C V 74.0 dBc = 100 MHz 25°C V 74.0 dBc

Rev. 0 | Page 4 of 36

AD9216

AD9216BCPZ-105

Parameter Temp Test Level Min Typ Max Unit

TWO-TONE SFDR (AIN = −7 dBFS)

f

= 69.1 MHz, f

IN1

f

= 100.1 MHz, f

IN1

= 70.1 MHz 25°C V 70 dBc

IN2

= 101.1 MHz 25°C V 69 dBc

IN2

ANALOG BANDWIDTH 25°C V 300 MHz CROSSTALK 25°C V −80.0 dB

Rev. 0 | Page 5 of 36

AD9216

LOGIC SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 3.

Parameter Temp Test Level Min Typ Max Unit LOGIC INPUTS

High Level Input Voltage Full IV 2.0 V Low Level Input Voltage Full IV 0.8 V High Level Input Current Full IV −10 +10 µA Low Level Input Current Full IV −10 +10 µA Input Capacitance Full IV 2 pF

LOGIC OUTPUTS

DRVDD = 3.0 V

1

Output voltage levels measured with 5 pF load on each output.

, DCS enabled, unless otherwise noted.

MAX

AD9216BCPZ-105

1

High Level Output Voltage Full IV 2.95 V Low Level Output Voltage Full IV 0.05 V

Rev. 0 | Page 6 of 36

AD9216

SWITCHING SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 4.

Parameter Temp Test Level Min Typ Max Unit SWITCHING PERFORMANCE

Maximum Conversion Rate Full VI 105 MSPS

Minimum Conversion Rate Full V 10 MSPS

CLK Period Full V 9.5 ns OUTPUT PARAMETERS

Output Propagation Delay2 (tPD) 25°C I 3.75 4.6 ns

Valid Time3 (tV) 25°C I 2.0

Output Rise Time (10% to 90%) 25°C V 1.0 ns

Output Fall Time (10% to 90%) 25°C V 1.0 ns

Output Enable Time

Output Disable Time4 25°C V 1 Cycle

Pipeline Delay (Latency) Full V 6 Cycles APERTURE

Aperture Delay (tA) Full V 1.5 ns

Aperture Uncertainty (tJ) Full V 0.5 ps rms

Wake-Up Time OUT-OF-RANGE RECOVERY TIME Full V 1 Cycle

1

C

LOAD

2

Output delay is measured from clock 50% transition to data 50% transition.

3

Valid time is approximately equal to the minimum output propagation delay.

4

Output enable time is OEB_A, OEB_B falling to respective channel outputs coming out of high impedance. Output disable time is OEB_A, OEB_B rising to respective

channel outputs going into high impedance.

5

Wake-up time is dependent on value of decoupling capacitors; typical values shown for 0.1 µF and 10 µF capacitors on REFT and REFB.

, DCS enabled, unless otherwise noted.

MAX

1

4

5

equals 5 pF maximum for all output switching parameters.

AD9216BCPZ-105

25°C V 1 Cycle

Full V 7 ms

Rev. 0 | Page 7 of 36

AD9216

TIMING DIAGRAM

ANALOG

INPUT

CLK

N–1

N+1

N

t

A

N+2

N+3

N+4

N+5

N+8

N+7

N+6

DATA

OUT

N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1

t

PD

04775-002

Figure 2.

Rev. 0 | Page 8 of 36

AD9216

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating Pin Name With Respect To Min Max Unit

ELECTRICAL

ENVIRONMENTAL

1

2

1

AVDD AGND −0.3 +3.9 V

DRVDD DRGND −0.3 +3.9 V

AGND DRGND −0.3 +0.3 V

AVDD DRVDD −3.9 +3.9 V

Digital Outputs CLK, DCS, MUX_SELECT, SHARED_REF DRGND −0.3 DRVDD + 0.3 V

OEB, DFS AGND −0.3 AVDD + 0.3 V

VINA, VINB AGND −0.3 AVDD + 0.3 V

VREF AGND −0.3 AVDD + 0.3 V

SENSE AGND −0.3 AVDD + 0.3 V

REFB, REFT AGND −0.3 AVDD + 0.3 V

PDWN AGND −0.3 AVDD + 0.3 V

2

Operating Temperature −45 +85 °C

Junction Temperature 150 °C

Lead Temperature (10 sec) 300 °C

Storage Temperature −65 +150 °C

Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is

not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.

Typical thermal impedances (64-lead LFCSP); θ

EIA/JESD51-7.

= 26.4°C/W. These measurements were taken on a 4-layer board (with thermal via array) in still air, in accordance with

JA

EXPLANATION OF TEST LEVELS

Table 6.

Test Level Description

I 100% production tested. II 100% production tested at 25°C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI

100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 9 of 36

AD9216

A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVDD

CLK_A

SHARED_REF

MUX_SELECT

PDWN_A

OEB_A

DNC

D9_A (MSB)

D8_A

D7_A

D6_A

DRGND

DRVDD

D5_A

D4_A

AGND VIN+_A VIN–_A

AGND

AVDD REFT_A REFB_

VREF

SENSE REFB_B REFT_B

AVDD

AGND VIN–_B VIN+_B

AGND

646362616059585756555453525150

PIN 1

1

INDICATOR

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

AD9216

TOP VIEW

(Not to Scale)

D3_A 49

D2_A

48

D1_A

47

D0_A (LSB)

46

DNC

45

DNC

44

DNC

43

DNC

42

DRVDD

41

DRGND

40

DNC

39

D9_B (MSB)

38

D8_B

37

D7_B

36

D6_B

35

D5_B

34

D4_B

33

DNC = DO NOT CONNECT

171819202122232425262728293031

DFS

DCS

DNC

AVDD

CLK_B

PDWN_B

OEB_B

DNC

D0_B (LSB)

DRVDD

DRGND

D1_B

D2_B

32

D3_B

04775-003

Figure 3. Pin Configuration

Rev. 0 | Page 10 of 36

AD9216

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1, 4, 13, 16 AGND Analog Ground. 2 VIN+_A Analog Input Pin (+) for Channel A. 3 VIN−_A Analog Input Pin (−) for Channel A. 5, 12, 17, 64 AVDD Analog Power Supply. 6 REFT_A Differential Reference (+) for Channel A. 7 REFB_A Differential Reference (−) for Channel A. 8 VREF Voltage Reference Input/Output. 9 SENSE Reference Mode Selection. 10 REFB_B Differential Reference (−) for Channel B. 11 REFT_B Differential Reference (+) for Channel B. 14 VIN−_B Analog Input Pin (−) for Channel B. 15 VIN+_B Analog Input Pin (+) for Channel B. 18 CLK_B Clock Input Pin for Channel B. 19 DCS Duty Cycle Stabilizer (DCS) Mode Pin (Active High). 20 DFS Data Output Format Select Pin (Low for Offset Binary, High for Twos Complement). 21 PDWN_B Power-Down Function Selection for Channel B (Active High). 22 OEB_B

23 to 26, 39, 42 to 45, 58

27, 30 to 38

28, 40, 53 DRGND Digital Output Ground. 29, 41, 52 DRVDD

46 to 51, 54 to 57

59 OEB_A

60 PDWN_A Power-Down Function Selection for Channel A (Active High). 61 MUX_SELECT Data Multiplexed Mode. (See Data Format section for how to enable). 62 SHARED_REF Shared Reference Control Bit (Low for Independent Reference Mode, High for Shared Reference Mode). 63 CLK_A Clock Input Pin for Channel A.

DNC Do Not Connect Pins. Should be left floating.

D0_B (LSB) to D9_B (MSB)

D0_A (LSB) to D9_A (MSB)

Output Enable for Channel B (Low Setting Enables Channel B Output Data Bus). Outputs are high impedance when OEB_B is set high.

Channel B Data Output Bits.

Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 µF capacitor. Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF.

Channel A Data Output Bits.

Output Enable for Channel A (Low Setting Enables Channel A Output Data Bus). Outputs are high impedance when OEB_A is set high.

Rev. 0 | Page 11 of 36

AD9216

TERMINOLOGY

Analog Bandwidth

The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.

Aperture Delay

The delay between the 50% point of the rising edge of the encode command and the instant the analog input is sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Clock Pulse Width/Duty Cycle

Pulse-width high is the minimum amount of time that the clock pulse should be left in a Logic 1 state to achieve rated performance; pulse-width low is the minimum time clock pulse should be left in a low state. See timing implications of changing t At a given clock rate, these specifications define an acceptable clock duty cycle.

Crosstalk

Coupling onto one channel being driven by a low level (−40 dBFS) signal when the adjacent interfering channel is driven by a full-scale signal.

Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance

The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180° and by taking the peak measurement again. The difference is then computed between both peak measurements.

Differential Nonlinearity

The deviation of any code width from an ideal 1 LSB step.

Effective Number of Bits (ENOB) The ENOB is calculated from the measured SINAD based on the equation (assuming full-scale input)

in the Clock Input and Considerations section.

EH

ENOB

SINAD

=

MEASURED

6.02

dB1.76−

Full-Scale Input Power

Expressed in dBm and computed using the following equation.

2

⎛

V

FULLSCALE

⎜

Z

⎜

log10

Power

FULLSCALE

=

INPUT

⎜

0.001

⎜

⎜ ⎝

rms

⎞ ⎟

⎟ ⎟ ⎟

⎟ ⎠

Gain Error

The difference between the measured and ideal full-scale input voltage range of the ADC.

Harmonic Distortion, Second

The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc.

Harmonic Distortion, Third

The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc.

Integral Nonlinearity

The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between a 50% crossing of the CLK rising edge and the time when all output data bits are within valid logic levels.

Noise (for Any Range within the ADC)

This value includes both thermal and quantization noise.

noise

ZV

⎛

××=

10.0010

⎜

⎜ ⎝

−−

10

⎞

dBFSdBcdBm

⎟

⎟ ⎠

SignalSNRFS

where:

Z is the input impedance.

FS is the full scale of the device for the frequency in question.

SNR is the value for the particular input level.

is the signal level within the ADC reported in dB below

Signal

full scale.

Rev. 0 | Page 12 of 36

AD9216

Power Supply Rejection Ratio

The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit.

Signal-to-Noise and Distortion (SINAD)

The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc.

Signal-to-Noise Ratio (without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first seven harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. It also may be reported in dBc (that is, degrades as signal level is lowered) or dBFS (that is, always related back to converter full scale).

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product, in dBc.

Two -Ton e SFDR

The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It also may be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (that is, always relates back to converter full scale).

Wors t Oth e r S p u r

The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic), reported in dBc.

Transient Response Time

The time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.

Rev. 0 | Page 13 of 36

AD9216

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD, DRVDD = 3.0 V, T = 25°C, AIN differential drive, full scale = 2 V mode, internal reference, DCS on, unless otherwise noted.

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

Figure 4. FFT: f

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

Figure 5. FFT: f

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

SNR = 57.8dB SINAD = 57.8dB H2 = –92.7dBc H3 = –80.3dBc SFDR = 78.2dBc

20 30010 4050

FREQUENCY (MHz)

= 105 MSPS, AIN = 10.3 MHz @ −0.5 dBFS

S

SNR = 56.9dB SINAD = 56.8dB H2 = –78.5dBc H3 = –80dBc SFDR = 78.3dBc

20 30010 4050

FREQUENCY (MHz)

= 105 MSPS, AIN = 70 MHz @ −0.5 dBFS

S

SNR = 57.5dB SINAD = 57.3dB H2 = –74dBc H3 = –84.3dBc SFDR = 74dBc

04775-018

04775-019

0

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBFS)

–70

–80

–90

–100

27 28 29

Figure 7. FFT: f

70MHz ON CHANNEL A ACTIVE

76MHz CROSSTALK FROM CHANNEL B

30 31 32 33 34 35

(76)

FREQUENCY (MHz)

= 105 MSPS, AIN =70 MHz, 76 MHz

S

(A Port FFT while Both A and B Ports Are Driven @ −0.5 dBFS)

100

H3

90

H2

80

dB

70

60

50

0 20 40 60 80 100 120

SNR

SINAD

CLOCK FREQUENCY (MHz)

SFDR

Figure 8. SNR, SINAD, H2, H3, SFDR vs.

Sample Clock Frequency, A

100

90

80

dB

70

60

= 70 MHz @ −0.5 dBFS

IN

H2

SFDR

H3

SNR

(70)

04775-021

36

04775-022

–120

Figure 6. FFT: f

20 30010 4050

FREQUENCY (MHz)

= 105 MSPS, AIN = 100 MHz @ −0.5 dBFS

S

04775-020

Rev. 0 | Page 14 of 36

50

0 50 100 150 200 250 300

ANALOG INPUT FREQUENCY (MHz)

Figure 9. Analog Inp ut Frequency Sweep, A

=−0.5 dBFS, fS = 105 MSPS

IN

SINAD

04775-023

AD9216

80

70

60

50

dB

40

30

20

–50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0

SFDR dBFS

SFDR dBc

AIN INPUT LEVEL (dBFS)

65dB REF LINE

Figure 10. SFDR vs. Analog Input Level,

= 70 MHz, fS = 105 MSPS

A

IN

0

–10

–20

–30

–40

–50

AMPLITUDE (dBFS)

–60

–70

–80

–90

–100

IMD = –69.9dBc

20 30010 4050

INPUT FREQUENCY (MHz)

Figure 11. Two-Tone IMD Performance,

F1, F2 = 69.1 MHz, 70.1 MHz @ −7 dBFS, 105 MSPS

90

80

70

60

50

dB

40

30

20

10

0

–60 –50 –40 –30 –20 –10 0

TWO-TONE SFDR dBFS

TWO-TONE SFDR dBc

70dB REF LINE

TWO-TONE ANALOG INPUT LEVEL (dBFS)

Figure 12. Two-Tone Intermodulation Distortion vs. Input Drive Level

(69.1 MHz and 70.1 MHz; f

= 105 MSPS; F1, F2 Levels Equal)

S

04775-024

04775-025

04775-026

100

90

80

70

TWO-TONE SFDR dBFS

60

50

dB

40

30

20

10

0

–60 –50 –40 –30 –20 –10 0

TWO-TONE SFDR dBc

70dB REF LINE

TWO-TONE ANALOG INPUT LEVEL (dBFS)

Figure 13. Two-Tone Intermodulation Distortion vs. Input Drive Level

(100.1 MHz and 101.1 MHz; f

100

90

80

70

60

50

40

CURRENT (mA)

30

20

10

0

0 20 40 60 80 100 120

SAMPLE CLOCK RATE (MSPS)

Figure 14. I

C

= 5 pF, AIN = 70 MHz @ −0.5 dBFS

LOAD

80

70

60

SNR DCS ON

50

dB

40

30

20

25 30 35 40 45 50 55 60 65 70 75

SNR DCS OFF

= 105 MSPS; F1, F2 Levels Equal)

S

AVDD CURRENT

DRVDD CURRENT

, I

AVDD

POSITIVE DUTY CYCLE (%)

vs. Clock Frequency,

DRVDD

SFDR DCS ON

SFDR DCS OFF

Figure 15. SNR, SFDR vs. Positive Duty Cycle DCS Enabled, Disabled;

= 70 MHz @ −0.5 dBFS, 105 MSPS

A

IN

04775-027

04775-028

04775-029

Rev. 0 | Page 15 of 36

AD9216

80

75

70

65

60

dB

55

50

45

40

0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.95 1.05 1.15 1.25

SFDR

SNR

VREF (V)

Figure 16. SNR, SFDR vs. External VREF (Full Scale = 2 × VREF)

= 70.3 MHz @ −0.5 dBFS, 105 MSPS

A

IN

1.0

0.8

0.6

0.4

0.2

EXTERNAL REFERENCE MODE

0

–0.2

–0.4

GAIN ERROR (% Full Scale)

–0.6

–0.8

–1.0

–40–20020406080

INTERNAL REFERENCE MODE

TEMPERATURE (°C)

Figure 17. Typical Gain Error Variation vs. Temperature,

= 70 MHz @ 0.5 dBFS, 105 MSPS (Normalized to 25°C)

A

IN

80

04775-030

04775-031

75

70

dB

65

60

55

–40–20020406080

SFDR

SNR

SINAD

TEMPERATURE (°C)

Figure 19. SNR, SINAD, SFDR vs. Temperature,

= 70 MHz @ −0.5 dBFS, 105 MSPS (fS = 2 V, External Reference Mode)

A

IN

80

SNR

SINAD

SFDR

2.92.8 3.0 3.1 3.2 AVDD (V)

= 70 MHz @ −0.5 dBFS, 105 MSPS

IN

75

70

dB

65

60

55

Figure 20. SNR, SINAD, SFDR vs. AVDD, A

2.0

04775-033

04775-034

75

70

dB

65

60

55

–40–20020406080

SFDR

SNR

SINAD

TEMPERATURE (°C)

Figure 18. SNR, SINAD, SFDR vs. Temperature,

= 70 MHz @ −0.5 dBFS, 105 MSPS (fS = 2 V, Internal Reference Mode)

A

IN

04775-032

Rev. 0 | Page 16 of 36

1.5

1.0

0.5

0

LSB

–0.5

–1.0

–1.5

–2.0

0 200 400 600 800 1000

CODE

Figure 21. Typical DNL Plot, A

= 10.3 MHz @ −0.5 dBFS, 105 MSPS

IN

04775-035

AD9216

2.0

1.5

1.0

0.5

0

LSB

–0.5

–1.0

–1.5

–2.0

0 200 400 600 800 1000

Figure 22. Typical INL Plot, A

CODE

= 10.3 MHz @ −0.5 dBFS, 105 MSPS

IN

04775-036

4.9

4.7

4.5

4.3

(ns)

PD

T

4.1

3.9

3.7

3.5 –20 0 20 40 80

–40 60

TEMPERATURE (°C)

Figure 23. Typical Propagation Delay vs. Temperature

04775-037

Rev. 0 | Page 17 of 36

AD9216

EQUIVALENT CIRCUITS

AVDD

VIN+_A, VIN–_A, VIN+_B, VIN–_B

CLK_A, CLK_B

DCS, DFS,

MUX_SELECT,

SHARED_REF

Figure 24. Equivalent Analog Input

AVDD

Figure 25. Equivalent Clock, Digital Inputs Circuit

04775-004

04775-005

PDWN

30kΩ

04775-006

Figure 26. Power-Down Input

DRVDD

04775-007

Figure 27. Digital Outputs

Rev. 0 | Page 18 of 36

AD9216

THEORY OF OPERATION

The AD9216 consists of two high performance ADCs that are based on the AD9215 converter core. The dual ADC paths are independent, except for a shared internal band gap reference source, VREF. Each of the ADC paths consists of a proprietary front end SHA followed by a pipelined switched-capacitor ADC. The pipelined ADC is divided into three sections, consisting of a sample-and-hold amplifier, followed by seven

1.5-bit stages, and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined through the digital correction logic block into a final 10-bit result. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the respective clock.

Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC and a residual multiplier to drive the next stage of the pipeline. The residual multiplier uses the flash ADC output to control a switched capacitor digital-to-analog converter (DAC) of the same resolution. The DAC output is subtracted from the stage’s input signal and the residual is amplified (multiplied) to drive the next pipeline stage. The residual multiplier stage is also called a multiplying DAC (MDAC). One bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC.

The input stage contains a differential SHA that can be configured as ac- or dc-coupled in differential or singleended modes. The output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing.

ANALOG INPUT

The analog input to the AD9216 is a differential switchedcapacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA input accepts inputs over a wide common-mode range. An input common-mode voltage of midsupply is recommended to maintain optimal performance.

input; therefore, the precise values are dependant on the application. In IF under-sampling applications, any shunt capacitors should be removed. In combination with the driving source impedance, they would limit the input bandwidth. For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC.

H

VIN+

VIN

T

C

PAR

T

–

C

PAR

Figure 28. Switched-Capacitor Input

0.5pF

T

H

An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common-mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as:

REFT = 1/2 (AV D D + VREF)

REFB = 1/2 (AV D D − VREF)

Span = 2 × (REFT − REFB) = 2 × VREF

It can be seen from the equations above that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage.

The SHA may be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as

VCM

= VREF/2

MIN

04775-008

The SHA input is a differential switched-capacitor circuit. In Figure 28, the clock signal alternatively switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. Also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC’s

Rev. 0 | Page 19 of 36

VCM

= (AV D D + VREF)/2

MAX

The minimum common-mode input level allows the AD9216 to accommodate ground-referenced inputs. Although optimum performance is achieved with a differential input, a singleended source may be driven into VIN+ or VIN−. In this configuration, one input accepts the signal, while the opposite input should be set to midscale by connecting it to an appropriate reference. For example, a 2 V p-p signal may be applied to VIN+, while a 1 V reference is applied to VIN−.

AD9216

2

The AD9216 then accepts an input signal varying between 2 V and 0 V. In the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies.

85

80

75

70

65

dB

60

55

50

45

40

0.25 0.75 1.25 1.75 2.25 2.75 ANALOG INPUT COMMON-MODE VOLTAGE (V)

Figure 29. Input Common-Mode Voltage Sensitivity

Differential Input Configurations

As previously detailed, optimum performance is achieved while driving the AD9216 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set to AVDD/2, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.

At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the AD9216. This is especially true in IF under-sampling applications where frequencies in the 70 MHz to 200 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration, as shown in Figure 30.

V p-p

49.9Ω

0.1µF

Figure 30. Differential Transformer Coupling

The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion.

2V p-p SFDR

2V p-p SNR

50Ω

10pF

50Ω

10pF

1kΩ

AVDD

VIN_A

AD9216

VIN_B

AGND

04775-009

04775-010

For dc-coupled applications, the AD8138, AD8139, or AD8351 can serve as a convenient ADC driver, depending on requirements. Figure 31 shows an example with the AD8138. The AD9216 PCB has an optional AD8351 on board, as shown in Figure 38 and Figure 39. The AD8351 typically yields better performance for frequencies greater than 30 MHz to 40 MHz.

0.1µF

SCALE/2

49.9Ω

499Ω

1.3kΩ

2kΩ

523Ω

Figure 31. Driving the ADC with the AD8138

SENSE = GROUND

VIN+

FULL

AVDD/2 AVDD/2

VIN–

DIGITAL OUT = ALL ONES DIGITAL OUT = ALL ZEROES

Figure 32. Analog Input Full Scale (Full Scale = 2 V)

499Ω

AD8138

499Ω

33Ω

20pF

33Ω

AVDD

VIN+

AD9216

VIN–

AGND

04775-011

04775-012

Single-Ended Input Configuration

A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, there is a degradation in SFDR and distortion performance due to the large input common-mode swing. However, if the source impedances on each input are matched, there should be little effect on SNR performance.

CLOCK INPUT AND CONSIDERATIONS

Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics.

The AD9216 provides separate clock inputs for each channel. The optimum performance is achieved with the clocks operated at the same frequency and phase. Clocking the channels asynchronously may degrade performance significantly. In some applications, it is desirable to skew the clock timing of adjacent channels. The AD9216’s separate clock inputs allow for clock timing skew (typically ±1 ns) between the channels without significant performance degradation.

Rev. 0 | Page 20 of 36

AD9216

The AD9216 contains two clock duty cycle stabilizers, one for each converter, that retime the nonsampling edge, providing an internal clock with a nominal 50% duty cycle. Faster input clock rates (where it becomes difficult to maintain 50% duty cycles) can benefit from using DCS as a wide range of input clock duty cycles can be accommodated. Maintaining a 50% duty cycle clock is particularly important in high speed applications, when proper track-and-hold times for the converter are required to maintain high performance. The DCS can be enabled by tying the DCS pin high.

The duty cycle stabilizer uses a delay-locked loop to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 2 µs to 3 µs to allow the DLL to acquire and settle to the new rate.

High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (f

) due only to aperture jitter (tJ) can be

INPUT

calculated by

SNR degradation = 2 × log 10[1/2 × p × f

In the equation, the rms aperture jitter,

t

, represents the root-

J

INPUT

× tJ]

sum square of all jitter sources, which includes the clock input, analog input signal, and ADC aperture jitter specification. Under-sampling applications are particularly sensitive to jitter.

For optimal performance, especially in cases where aperture jitter may affect the dynamic range of the AD9216, it is important to minimize input clock jitter. The clock input circuitry should use stable references; for example, use analog power and ground planes to generate the valid high and low digital levels for the AD9216 clock input. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.

POWER DISSIPATION AND STANDBY MODE

The power dissipated by the AD9216 is proportional to its sampling rates. The digital (DRVDD) power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The digital drive current can be calculated by

The analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates that increases with clock frequency.

Either channel of the AD9216 can be placed into standby mode independently by asserting the PWDN_A or PDWN_B pins. Time to go into or come out of standby mode is 5 cycles maximum when only one channel is being powered down. When both channels are powered down, VREF goes to ground, resulting in a wake-up time of ~7 mS dependent on decoupling capacitor values.

It is recommended that the input clock(s) and analog input(s) remain static during either independent or total standby, which results in a typical power consumption of 3 mW for the ADC. If the clock inputs remain active while in total standby mode, typical power dissipation of 10 mW results.

The minimum standby power is achieved when both channels are placed into full power-down mode (PDWN_A = PDWN_B = HI). Under this condition, the internal references are powered down. When either or both of the channel paths are enabled after a power-down, the wake-up time is directly related to the recharging of the REFT and REFB decoupling capacitors and to the duration of the power-down.

A single channel can be powered down for moderate power savings. The powered-down channel shuts down internal circuits, but both the reference buffers and shared reference remain powered on. Because the buffer and voltage reference remain powered on, the wake-up time is reduced to several clock cycles.

DIGITAL OUTPUTS

The AD9216 output drivers can interface directly with 3 V logic families. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches because large drive currents tend to cause current glitches on the supplies that may affect converter performance.

The data format can be selected for either offset binary or twos complement. This is discussed in the Data Format section.

I

= V

DRVDD

where

N is the number of bits changing, and C

DRVDD

× C

LOAD

× f

CLOCK

× N

load on the digital pins that changed.

is the average

LOAD

Rev. 0 | Page 21 of 36

AD9216

OUTPUT CODING

Table 8.

Code (VIN+) − (VIN−) Offset Binary Twos Complement

1023 > +0.998 V 11 1111 1111 01 1111 1111 1023 +0.998 V 11 1111 1111 01 1111 1111 1022 +0.996 V 11 1111 1110 01 1111 1110

• • • •

• • • • 513 +0.002 V 10 0000 0001 00 0000 0001 512 +0.0 V 10 0000 0000 00 0000 0000 511 −0.002 V 01 1111 1111 11 1111 1111

• • • •

• • • • 1 −0.998 V 00 0000 0001 10 0000 0001 0 −1.000 V 00 0000 0000 10 0000 0000 0 < −1.000 V 00 0000 0000 10 0000 0000

TIMING

The AD9216 provides latched data outputs with a pipeline delay of six clock cycles. Data outputs are available one propagation delay (t Figure 2 for a detailed timing diagram.

The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9216. These transients can detract from the converter’s dynamic performance. The lowest conversion rate of the AD9216 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance may degrade.

) after the rising edge of the clock signal. Refer to

PD

DATA FORMAT

The AD9216 data output format can be configured for either twos complement or offset binary. This is controlled by the data format select pin (DFS). Connecting DFS to AGND produces offset binary output data. Conversely, connecting DFS to AVDD formats the output data as twos complement.

The output data from the dual ADCs can be multiplexed onto a single 10-bit output bus. The multiplexing is accomplished by toggling the MUX_SELECT bit, which directs channel data to the same or opposite channel data port. When MUX_SELECT is logic high, the Channel A data is directed to the Channel A output bus, and the Channel B data is directed to the Channel B output bus. When MUX_SELECT is logic low, the channel data is reversed, i.e., the Channel A data is directed to the Channel B output bus, and the Channel B data is directed to the Channel A output bus. By toggling the MUX_SELECT bit, multiplexed data is available on either of the output data ports.

If the ADCs are run with synchronized timing, this same clock can be applied to the MUX_SELECT bit. After the MUX_SELECT rising edge, either data port has the data for its respective channel; after the falling edge, the alternate channel’s data is placed on the bus. Typically, the other unused bus is disabled by setting the appropriate OEB high to reduce power consumption and noise. Figure 33 shows an example of multiplex mode. When multiplexing data, the data rate is two times the sample rate. Note that both channels must remain active in this mode and that each channel’s power-down pin must remain low.

A

–1

B

–1

0

B

0

B

–7

Figure 33. Example of Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT

A

1

B

1

A

B

–6

A

2

B

2

A

B–5A–4B–4A

–5

A

3

B

3

A

4

B

4

B

–3

A

5

B

5

A

B

–2

A–1B

A

6

B

6

A0B0A1B

–1

7

B

7

A

8

B

1

8

ANALOG INPUT ADC A

ANALOG INPUT ADC B

CLK_A = CLK_B = MUX_SELECT

D0_A –D11_A

04775-013

Rev. 0 | Page 22 of 36

AD9216

VOLTAGE REFERENCE

A stable and accurate 0.5 V voltage reference is built into the AD9216. The input range can be adjusted by varying the reference voltage applied to the AD9216, using either the internal reference with different external resistor configurations or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly.

If the ADC is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (common-mode voltage).

Internal Reference Connection

A comparator within the AD9216 detects the potential at the SENSE pin and configures the reference into three possible states, which are summarized in Table 9. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 34), setting VREF to 1 V. If a resistor divider is connected, as shown in Figure 35, the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as

VREF = 0.5 × (1 + R2/R1)

Note that optimum performance is obtained with VREF = 1.0 V; performance degrades as VREF (and full scale) reduces (see Figure 16). In all reference configurations, REFT and REFB drive the ADC core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.

VIN+

10µF

VIN–

ADC

CORE

VREF

0.1µF

SENSE

Figure 34. Internal Reference Configuration

SELECT

LOGIC

0.5V

AD9216

REFT

REFB

0.1µF

10µF

04775-014

Table 9. Reference Configuration Summary

Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p)

External Reference AVDD N/A 2 × External Reference Programmable Reference 0.2 V to VREF 0.5 × (1 + R2/R1) 2 × VREF (See Figure 35) Internal Fixed Reference AGND to 0.2 V 1.0 2.0

Rev. 0 | Page 23 of 36

AD9216

External Reference Operation

The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve the thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may be necessary to reduce gain matching errors to an acceptable level. A high precision external reference may also be selected to provide lower gain and offset temperature drift. Figure 36 shows the typical drift characteristics of the internal reference. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 kΩ load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 V. If the internal reference of the AD9216 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 37 depicts how the internal reference voltage is affected by loading.

0.6

0.5

0.4

0.3 VREF = 1.0V

VREF ERROR (%)

0.2

0.1

0

–40–20 0 20406080

0.05

0

–0.05

TEMPERATURE (°C)

Figure 36. Typical VREF Drift

04775-016

10µF

VIN+ VIN–

CORE

V

REF

10µF

SENSE

R2

R1

SELECT

LOGIC

AD9216

Figure 35. Programmable Reference Configuration

ADC

0.5V

REFT

REFB

0.1µF

10µF

–0.10

VREF ERROR (%)

–0.15

–0.20

–0.25

0 0.5 1.0 1.5 2.0 2.5 3.0

VREF = 1.0V

I

LOAD

(mA)

04775-017

Figure 37. VREF Accuracy vs. Load

Shared Reference Mode

The shared reference mode allows the user to connect the references from the dual ADCs together externally for

04775-015

superior gain and offset matching performance. If the ADCs are to function independently, the reference decoupling can be treated independently and can provide superior isolation between the dual channels. To enable shared reference mode, the SHARED_REF pin must be tied high, and the external differential references must be externally shorted. (REFT_A must be externally shorted to REFT_B, and REFB_A must be shorted to REFB_B.)

Rev. 0 | Page 24 of 36

AD9216

DUAL ADC LFCSP PCB

The PCB requires a low jitter clock source, analog sources, and power supplies. The PCB interfaces directly with ADI’s standard dual-channel data capture board (HSC-ADC-EVAL-DC), which together with ADI’s ADC Analyzer™ software allows for quick ADC evaluation.

POWER CONNECTOR

Power is supplied to the board via three detachable 4-lead power strips.

Table 10. Power Connector

Terminal Comments

VCC1 3.0 V Analog supply for ADC VDD1 3.0 V Output supply for ADC VDL1 3.0 V Supply circuitry VREF Optional external VREF +5 V Optional op amp supply

−5 V Optional op amp supply

1

VCC, VDD, and VDL are the minimum required power connections.

ANALOG INPUTS

The evaluation board accepts a 2 V p-p analog input signal centered at ground at two SMB connectors, Input A and Input B. These signals are terminated at their respective primary side transformer. T1 and T2 are wideband RF transformers that provide the single-ended-to-differential conversion, allowing the ADC to be driven differentially, minimizing even-order harmonics. The analog signals can be low-pass filtered at the secondary transformer to reduce high frequency aliasing.

OPTIONAL OPERATIONAL AMPLIFIER

The PCB has been designed to accommodate an optional AD8139 op amp that can serve as a convenient solution for dc-coupled applications. To use the AD8139 op amp, remove C14, R4, R5, C13, R37, and R36. Place R22, R23, R30, and R24.

CLOCK

The clock inputs are buffered on the board at U5 and U6. These gates provide buffered clocks to the on-board latches U2 and U4, ADC input clocks, and DRA, DRB that are available at the output connector P3, P8. The clocks can be inverted at the timing jumpers labeled with the respective clocks. The clock paths also provide for various termination options. The ADC input clocks can be set to bypass the buffers at P2 to P9 and P10, P12. An optional clock buffer U3, U7 can also be placed. The clock inputs can be bridged at TIEA, TIEB (R20, R40) to allow one to clock both channels from one clock source.

Table 11. Jumpers

Terminal Comments

OEB A Output Enable for A Side PWDN A Power-Down A MUX Mux Input SHARED REF Shared Reference Input DR A Invert DR A LATA Invert A Latch Clock ENC A Invert Encode A OEB B Output Enable for B Side PWDN B Power-Down B DFS Data Format Select SHARED REF Shared Reference Input DR B Invert DR B LATB Invert B Latch Clock ENC B Invert Encode B

VOLTAGE REFERENCE

The ADC SENSE pin is brought out to E41, and the internal reference mode is selected by placing a jumper from E41 to ground (E27). External reference mode is selected by placing a jumper from E41 to E25 and E30 to E2. R56 and R45 allow for programmable reference mode selection.

DATA OUTPUTS

The ADC outputs are latched on the PCB at U2, U4. The ADC outputs have the recommended series resistors in line to limit switching transient effects on ADC performance.

Rev. 0 | Page 25 of 36

AD9216 Preliminary Technical Data

LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM)

Table 12.

No. Quantity Reference Designator Device Package Value

1 2 C1, C3 Capacitors 0201 20 pF

2 7 C2, C5, C7, C9, C10, C22, C36 Capacitors 0805 10 µF 3 44

C4, C6, C8, C11 to C15, C20, C21,

C24 to C27, C29 to C35, C39 to C61 4 6 C16 to C19, C37, C38 Capacitors TAJD 10 µF 5 2 C23, C28 Capacitors 0201 0.1 µF 6 6 J1 to J6 SMBs 7 3 P1, P4, P11 Power Connector Posts Z5.531.3425.0 Wieland 8 3 P1, P4, P11 Detachable Connectors 25.602.5453.0 Wieland 9 2 P31, P8 Connectors 10 4 R1, R2, R32, R34 Resistors 0402 36 Ω 11 10 R3, R6, R7, R8, R11, R14, R33, R42, R51, R61 Resistors 0402 50 Ω 12 4 R4, R5, R36, R37 Resistors 0402 33 Ω 13 9 R9, R10, R12, R13, R20, R35, R38, R40, R43 Resistors 0402 0 Ω 14 6 R15, R16, R18, R26, R29, R31 Resistors 0402 499 Ω 15 2 R17, R25 Resistors 0402 525 Ω 16 27

R19, R21, R27, R28, R39, R41, R44,

R46 to R49, R52, R54, R55, R5 to R60, R62 to R70 17 4 R22 to R24, R30 Resistors 0402 40 Ω 18 2 R45, R56 Resistors 0402 10 kΩ 19 1 R50 Resistor 0402 22 Ω 20 8 RZ1 to RZ6, RZ9, RZ10 Resistor Pack 220 Ω 21 2 T1, T2 Transformers AWT-1WT Mini-Circuits 22 1 U1 AD9216 LFCSP-64 23 2 U2, U425 SN74LVTH162374 TSSOP-48 24 2 U32, U7 SN74LVC1G0 SOT-70 25 2 U5, U6 SN74VCX86 SO-14 26 2 U11, U12 AD8139 SO-8/EP

1

P3, P8 implemented as one 80-pin connector SAMTEC TSW-140-08-L-D-RA.

2

U3, U7 not placed.

Capacitors 0402 0.1 µF

Resistors 0402 1000 Ω

Rev. 0 | Page 26 of 36

Preliminary Technical Data AD9216

LFCSP PCB SCHEMATICS

VD

C58

0.1µF

C36

DUT CLOCK SELECTABLE

TO BE DIRECT OR BUFFERED

VD

E15E14

E13 E12

VD

C25

0.1µF

ENCA

R33

100Ω

VD

0Ω

10µF

4

5

Y

VCC

GND

NC

A

SN74LVC1G04

3

1

2

R42

100Ω

R43

U7

14

4B134A

VCC

74LCX86

1B1Y2A2B2Y

1A

1234567

P12 P10

VD

R39

1kΩ

TIEA

J6

R61

50Ω

C56

0.1µF

MUX

VD

E9

E7

R65

1kΩ

R64

1kΩ

VD

P1

P4

E10

E17

VD

E20

E18

R63

1kΩ

E6

E5

R66

–5V

+5V

EXT_VREF

VDD VDL

VD

EXT_VREFVDLVDD

+5V

–5V

VD

4123 4123 4123

P11

P5

VD

H3

R46

1kΩ

DRA

0Ω

R10

124Y113B103A9

E4VD

C40

0.1µF

J3

ENCODE A

C8

0.1µF

VDD

R62

1kΩ

ENCA

1kΩ

C45

C44

C43

C39

VD

C19

C18

C17

+ + + ++

C16

C38

+

C37

VDL

VDD

P7

P6

H1

R47

1kΩ

MUX

TIEA

TIEB

E34 E16

BUFFERED

0Ω

R38

C26

C4

D0A

42

REFB_A

7

0.1µF

10µF

AMPOUTAB

4

3

0.1µF

C9

8

R58

41

DRVDD1

VREF

PADS TO SHORT

J5

10µF

40

9

SEE

REFERENCES TOGETHER

1kΩ

R20

R14

VDD

U1

SENSE

BELOW

C29

0Ω

R40

50Ω

39

D13_B D13B38D12_B

OTR_B OTRB

DRGND1

REFB_B11REFT_B

10

REFT_B

REFB_B

C54

0.1µF

C7

10µF

0.1µF

C27

REFTA

REFTB

REFBA

P15

P16

VD

E42

E43

R59

R57

1kΩ

TO BE DIRECT OR

DUT CLOCK SELECTABLE

C57

D12B

D11B

35

37

36

D11_B

AGND214VIN_BB15VIN_B16AGND3

AVDD2

13

12

VD

C28

0.1µF

AMPOUTBB

REFBB

P18

P17

CTAPB

R60

1kΩ

C10

10µF

C22

D10_B D10B

6

1

C12

0.1µF

10µF

R37

D9_B D9B34D8_B D8B

5

2

CTAPB

0.1µF

VD

SN74LVC1G04

C3

33Ω

5

1

33

20pF

4

3

AMPINB

AIN B

R6

VCC

NC

ENCB

100Ω

VD

22Ω

4

Y

GND

A

3

2

D7_B

32

D6_B

31

D5_B

30

DRVDD

29

DRGND

28

D4_B

27

D3_B

26

D2_B

25

D1_B

24

D0_B

23

OEB_B

22

PDWN_B

21

DFS

20

DCS

19

CLK_B

18

AVDD3

17

R36

T1

J1

CLKLATB

0Ω

R12

R8

R50

7

100Ω

U3

VD

62B5

2Y

GND

U5

3Y3A3B4Y4A4BVCC

8

9

P9

P13

P2

R52

1kΩ

C42

0.1µF

TIEB

D7B

J2

D6B

0.1µF

D5B

C6

D4B

VDD

D3B D2B D1B D0B

ENCB

VD

C11

0.1µF

1011121314

E36

VD

33Ω

R56

AMPOUTB

C13

0.1µF

VREF AND SENSE CIRCUIT

R7

50Ω

0Ω

8

R9

CLKLATA

R35

3Y

U6

GND

P14

R44

1kΩ

E3

R41

1kΩ

R11

50Ω

D8A

D11A D13A

1µF

.

0 1µF

.

0 1µF

.

0

0.1µF

10µF

H4

H2

TO TIE CLOCKS TOGETHER

D5A

D4A

47

46

D6_A D6A48D5_A

D4_A

D3_A D3A45D2_A D2A44D1_A D1A43D0_A

D7_A D7A

49

D8_A

50

D9_A D9A

51

DRVDD2

52

DRGND2

53

D10_A D10A

54

D11_A

55

D12_A D12A

56

D13_A

57

OTR_A OTRA

58

OEB_A

59

PWDN_A

60 61 62

63 64

65

MUX_SEL

SH_REF CLK_A AVDD5 VD

EPAD

AGND2VIN_A3VIN_AB4AGND1

1

C23

C1

20pF

C24

5

AMPOUTA

R4

33Ω

T2

C14

0.1µF

R3

50Ω

AMPINA

J4

AIN A

AVDD16REFT_A

VD

0.1µF C55

C5

0.1µF

R5

33Ω

CTAPA

6

5

1

2

CTAPA

C31

0.1µF

VD

R48

1kΩ

0Ω

41Y31B21A1

2A

R49

E35

R54

1kΩ

R51

50Ω

ENCODE B

SENSE

10kΩ

E41

E25

VD

E37E38

DRB

1kΩ



R70

C30

R45

E27

VD

R55

1kΩ

R13

74LCX86

C41

0.1µF

VD

E31E33

R69

1kΩ

VD

E26

VD

1kΩ

E29

E21

R68

1kΩ

0.1µF

VD

E40

E22

R67

VREF

C2

VD

1kΩ

E24

10µF

10kΩ

E30

E2

EXT_VREF

MTHOLE6

04775-038

MTHOLE6

Figure 38. PCB Schematic (1 of 3)

Rev. 0 | Page 27 of 36

AD9216 Preliminary Technical Data

D9Q

D8Q

D7Q

D6Q

D5Q

D4Q

D3Q

D2Q

DRA

GND

D13P

D12P

D11P

D10P

GND

D13Q

D12Q

D11Q

D9P

D8P

D7P

D6P

D5P

D4P

D3P

D2P

D1P

D0P

DORP

DRB

D10Q

D1Q

D0Q

DORQ

DORP

D13P

16151413121110

220

RSO16ISO

D = INPUT

Q = OUTPUT

OE2

LE2

24

25

23

2Q8

2D8

26

R3R1R2 312

2Q7

2D7

RZ5

D12P

22

27

GND GND

39

37

39

37

P3

363840

40

D9P

D8P

D11P

R4

D7P

D10P

9

R8

R7

R6

R5

8

7

654

D6P

16151413121110

220

RZ6

RSO16ISO

11131517192123252729313335

D5P

D4P

D3P

D2P

R5

R4

R3R1R2

54312

13579

HEADER40

246

8

10121416182022242628303234

246

8

101214161820222426283032343638

D13Q

D11Q

D10Q

D9Q

D12Q

D1P

D0P

9

R8

R7

R6

8

7

6

DORQ

16151413121110

220

RZ10

RSO16ISO

R3R1R2

312

R6

R5

R4

654

37

39

333537

39

P8

40

D6Q

D3Q

D4Q

D8Q

D7Q

9

R8

R7

8

7

D5Q

16151413121110

220

RZ9

R3R1R2

RSO16ISO

R5

R4

54312

11131517192123252729313335

1113151719212325272931

D0Q

D1Q

D2Q

9

R8

R7

R6

8

7

6

13579

HEADER40

246

8

101214161820222426283032343638

246

8

101214161820222426283032343638



C50

0.1µF

C51

0.1µF

21

28

2Q6

2D6

20

29

2Q5

2D5

12

1Q7

1D7

37

11

GND

38

10

1Q6

GND

1D6

39

9

40

8

1Q5

1D5

41

VDL

5

6

4

7

1Q4

VCC

1D4

42

43

1Q3

1D3

44

GND

45

1Q2

1D2

3

46

1Q1

1D1

2

47

1

OE1

LE1

48

SN74LVCH16373A

24

2Q8

OE2

U2

D = INPUT

Q = OUTPUT

LE2

2D8

25

VDL

13

14

16

17

19

15

18

2Q3

1Q8

2Q1

2Q2

2Q4

VCC

GND

VCC

2D4

30

31

1D8

2D1

2D2

2D3

GND

36

35

33

32

34

23

26

2Q7

2D7

VDL

13

14

16

17

19

20

22

21

2Q6

2D6

GND GND

29

27

28

2Q5

2D5

15

18

2Q1

2Q2

2Q3

2Q4

VCC

2D4

30

31

1Q8

GND

1D8

2D1

2D2

2D3

GND

36

35

33

32

34

12

37

1Q7

1D7

11

38

10

1Q6

GND

1D6

GND

39

9

40

1Q5

1D5

VDL

2

3

5

6

8

4

7

1Q4

VCC

1D4

43

41

42

1Q3

1D3

44

GND

45

1Q2

1D2

46

1Q1

1D1

47

OE1

LE1

1

U4

SN74LVCH16373A

48

C52

0.1µF

C53

0.1µF

C46

0.1µF

C47

0.1µF

C48

0.1µF

C49

0.1µF

CLKLATA

16151413121110

220

RZ3

RSO16ISO

D13A

OTRA

R3R1R2 312

D12A

VDL

9

220

R8

R7

R6

R5

R4

8

7

D11A

D10A

654

D9A

RZ4

D8A

D7A

VDL

16151413121110

R4

R3R1R2

RSO16ISO

D3A

D6A

D4A

D5A

CLKLATA

9

R8

R7

R6

R5

8

7

6

54312

D2A

D0A

D1A

CLKLATB

16151413121110

220

RZ1

RSO16ISO

D13B

OTRB

VDL

9

220

R8

R7

R6

R5

R4

R3R1R2

8

7

654

312

D12B

D11B

D10B

D9B

RZ2

D8B

D7B

VDL

16151413121110

R4

R3R1R2

RSO16ISO

D5B

D6B

D4B

D3B

CLKLATB

9

R8

R7

R6

R5

8

7

6

54312

D0B

D2B

D1B

VDL

04775-039

Figure 39. PCB Schematic (2 of 3)

Rev. 0 | Page 28 of 36

Preliminary Technical Data AD9216

C59

R18

C21

R19

1kΩ

VD

R16

499Ω

AMPINA

OP AMP INPUT OFF PIN ONE OF TRANSFORMER

R17

525Ω

R21

9

C60

499Ω

0.1µF

1kΩ

1

–IN

EPAD

+IN

8

C32

0.1µF

+5V

R22

40Ω

4

36

2

V+

VOCM

U11

+OUT

AMPOUTA

AD8139

–OUT

V–

NC

5

7

C33

0.1µF

–5V

R23

40Ω

AMPOUTAB

AMPINB

C15

R26

499Ω

C20

R28

1kΩ

VD

R25

525Ω

R29

499Ω

R27

9

C34

C61

Figure 40. PCB Schematic (3 of 3)

R15

499Ω

0.1µF

1kΩ

1

–IN

EPAD

+IN

8

0.1µF

R31

499Ω

C35

0.1µF

+5V

R30

40Ω

4

36

2

V+

VOCM

U12

+OUT

AD8139

V–

–OUT

NC

5

7

–5V

R24

40Ω

AMPOUTB AMPOUTBB

04775-040

Rev. 0 | Page 29 of 36

AD9216 Preliminary Technical Data

LFCSP PCB LAYERS

Figure 41. PCB Top-Side Silkscreen

04775-041

Rev. 0 | Page 30 of 36

Preliminary Technical Data AD9216

Figure 42. PCB Top-Side Copper Routing

04775-042

Rev. 0 | Page 31 of 36

AD9216 Preliminary Technical Data

Figure 43. PCB Ground Layer

04775-043

Rev. 0 | Page 32 of 36

Preliminary Technical Data AD9216

Figure 44. PCB Split Power Plane

04775-044

Rev. 0 | Page 33 of 36

AD9216 Preliminary Technical Data

Figure 45. PCB Bottom-Side Copper Routing

04775-045

Rev. 0 | Page 34 of 36

Preliminary Technical Data AD9216

Figure 46. PCB Bottom-Side Silkscreen

THERMAL CONSIDERATIONS

The AD9216 LFCSP package has an integrated heat slug that improves the thermal and electrical properties of the package when locally attached to a ground plane at the PCB. A thermal (filled) via array to a ground plane beneath the part provides a path for heat to escape the package, lowering junction temperature. Improved electrical performance also results from the reduction in package parasitics due to proximity of the ground plane. Recommended array is 0.3 mm vias on 1.2 mm pitch. θ Soldering the slug to the PCB is a requirement for this package.

= 26.4°C/W with this recommended configuration.

JA

04775-046

04775-047

Figure 47. Thermal Via Array

Rev. 0 | Page 35 of 36

AD9216 Preliminary Technical Data

OUTLINE DIMENSIONS

0.30

0.25

0.18

64

1

PIN 1 INDICATOR

BSC SQ

PIN 1 INDICATOR

9.00

0.60 MAX

49

48

0.60 MAX

4.85 *

4.70 SQ

4.55

16

1.00

0.85

0.80

12° MAX

SEATING PLANE

TOP

VIEW

0.80 MAX

0.65 TYP

0.50 BSC

*

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD

EXCEPT FOR EXPOSED PAD DIMENSION

8.75

BSC SQ

0.20 REF

0.45

0.40

0.35

0.05 MAX

0.02 NOM

33

32

EXPOSED PAD

(BOTTOM VIEW)

7.50 REF

17

Figure 48. 64-Lead Lead Frame Chip Scale Package [LFCSP]

9 mm × 9 mm Body (CP-64-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9216BCPZ-105 AD9216BCPZRL7-1051 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP) CP-64-1 AD9216-105PCB Evaluation Board with AD9216BCPZ-105

1

Z = Pb-free part.

1

−40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP) CP-64-1

D04775–0–10/04(0)

Rev. 0 | Page 36 of 36

Datasheet AD9216 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

DC SPECIFICATIONS

AC SPECIFICATIONS

LOGIC SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING DIAGRAM

ABSOLUTE MAXIMUM RATINGS

EXPLANATION OF TEST LEVELS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS

EQUIVALENT CIRCUITS

THEORY OF OPERATION

ANALOG INPUT

Differential Input Configurations

Single-Ended Input Configuration

CLOCK INPUT AND CONSIDERATIONS

POWER DISSIPATION AND STANDBY MODE

DIGITAL OUTPUTS

OUTPUT CODING

TIMING

DATA FORMAT

VOLTAGE REFERENCE

Internal Reference Connection

External Reference Operation

Shared Reference Mode

DUAL ADC LFCSP PCB

POWER CONNECTOR

ANALOG INPUTS

OPTIONAL OPERATIONAL AMPLIFIER

CLOCK

VOLTAGE REFERENCE

DATA OUTPUTS

LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM)

LFCSP PCB SCHEMATICS

LFCSP PCB LAYERS

THERMAL CONSIDERATIONS

OUTLINE DIMENSIONS

ORDERING GUIDE