Datasheet AD9204 Datasheet (ANALOG DEVICES)

10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,

A

V

FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply
SNR

61.3 dBFS at 9.7 MHz input

61.0 dBFS at 200 MHz input

SFDR

75 dBc at 9.7 MHz input
73 dBc at 200 MHz input

Low power

30 mW per channel at 20 MSPS

63 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
DNL = ±0.11 LSB
Serial port control options

Scalable analog input: 1 V p-p to 2 V p-p differential

Offset binary, gray code, or twos complement data format

Optional clock duty cycle stabilizer

Integer 1-to-8 input clock divider

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock out with programmable clock and data

alignment

APPLICATIONS

Communications
Diversity radio systems
Multimode digital receivers

GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Ultrasound
Radar/LIDAR
PET/SPECT imaging

1.8 V Dual Analog-to-Digital Converter

AD9204

FUNCTIONAL BLOCK DIAGRAM

DCS

SPI

CSB

MUX OPTION

CONTROLS

PDWN DFSCLK+ CLK–

MODE

CMOS

CMOS

OEB

ORA

D9A

D0A

OUTPUT BUFF ER

DCOA

DRVDD

ORB

D9B

D0B

OUTPUT BUFFER

DCOB

SDIOGND

PROGRAMMING DATA

AD9204

DUTY CYCLE

STABILIZER

Figure 1.

VIN+A

VIN–A

VREF

SENSE

VCM

RBIAS

VIN–B

VIN+B

DD SCLK

ADC

REF

SELECT

ADC

DIVIDE

1TO 8

SYNC

PRODUCT HIGHLIGHTS

1. The AD9204 operates from a single 1.8 V analog power

supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.

2. The patented sample-and-hold circuit maintains excellent

performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.

3. A standard serial port interface supports various product

features and functions, such as data output formatting,
internal clock divider, power-down, DCO/DATA timing
and offset adjustments, and voltage reference modes.

4. The AD9204 is packaged in a 64-lead RoHS compliant

LFCSP that is pin compatible with the AD9268 16-bit
ADC, the AD9251 and AD9258 14-bit ADCs, and the

AD9231 12-bit ADC, enabling a simple migration path

between 10-bit and 16-bit converters sampling from
20 MSPS to 125 MSPS.

08122-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

AD9204

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications ..................................................................................... 4

DC Specifications ......................................................................... 4

AC Specifications .......................................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 7

Timing Specifications .................................................................. 8

Absolute Maximum Ratings ............................................................ 9

Thermal Characteristics .............................................................. 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 12

AD9204-80 .................................................................................. 12

AD9204-65 .................................................................................. 14

AD9204-40 .................................................................................. 15

AD9204-20 .................................................................................. 16

Equivalent Circuits ......................................................................... 17

Theory of Operation ...................................................................... 19

ADC Architecture ...................................................................... 19

Analog Input Considerations .................................................... 19

Voltage Reference ....................................................................... 22

Clock Input Considerations ...................................................... 23

Power Dissipation and Standby Mode .................................... 25

Digital Outputs ........................................................................... 26

Timing ......................................................................................... 26

Built-In Self-Test (BIST) and Output Test .................................. 27

Built-In Self-Test (BIST) ............................................................ 27

Output Test Modes ..................................................................... 27

Channel/Chip Synchronization .................................................... 28

Serial Port Interface (SPI) .............................................................. 29

Configuration Using the SPI ..................................................... 29

Hardware Interface ..................................................................... 30

Configuration Without the SPI ................................................ 30

SPI Accessible Features .............................................................. 30

Memory Map .................................................................................. 31

Reading the Memory Map Register Table ............................... 31

Open Locations .......................................................................... 31

Default Values ............................................................................. 31

Memory Map Register Table ..................................................... 32

Memory Map Register Descriptions ........................................ 34

Applications Information .............................................................. 35

Design Guidelines ...................................................................... 35

Outline Dimensions ....................................................................... 36

Ordering Guide .......................................................................... 36

REVISION HISTORY

7/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 36

AD9204

GENERAL DESCRIPTION

The AD9204 is a monolithic, dual-channel, 1.8 V supply, 10-bit,
20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter
(ADC). It features a high performance sample-and-hold circuit
and on-chip voltage reference.

The product uses multistage differential pipeline architecture
with output error correction logic to provide 10-bit accuracy at
80 MSPS data rates and to guarantee no missing codes over the
full operating temperature range.

The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom
user-defined test patterns entered via the serial port interface (SPI).

A differential clock input controls all internal conversion cycles.
An optional duty cycle stabilizer (DCS) compensates for wide
variations in the clock duty cycle while maintaining excellent
overall ADC performance.

The digital output data is presented in offset binary, gray code, or
twos complement format. A data output clock (DCO) is provided
for each ADC channel to ensure proper latch timing with receiving
logic. Both 1.8 V and 3.3 V CMOS levels are supported and output
data can be multiplexed onto a single output bus.

The AD9204 is available in a 64-lead RoHS compliant LFCSP
and is specified over the industrial temperature range (−40°C
to +85°C).

Rev. 0 | Page 3 of 36

AD9204

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.

Table 1.

AD9204-20/AD9204-40 AD9204-65 AD9204-80

Parameter Temp

RESOLUTION Full 10 10 10 Bits
ACCURACY

No Missing Codes Full Guaranteed Guaranteed Guaranteed
Offset Error Full ±0.1 ±0.70 ±0.1 ±0.50 ±0.1 ±0.70 % FSR
Gain Error1 Full +1.8 +1.8 +1.8 % FSR
Differential Nonlinearity (DNL)2 Full ±0.30 ±0.30 ±0.30 LSB
25°C ±0.075 ±0.15 ±0.11 LSB
Integral Nonlinearity (INL)2 Full ±0.60 ±0.60 ±0.60 LSB
25°C ±0.15 ±0.25 ±0.25 LSB

MATCHING CHARACTERISTICS

Offset Error 25°C ±0.0 ±0.75 ±0.0 ±0.75 ±0.0 ±0.75 % FSR
Gain Error1 25°C ±0.3 ±0.3 ±0.3 % FSR

TEMPERATURE DRIFT

Offset Error Full ±2 ±2 ±2 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode) Full 0.981 0.993 1.005 0.981 0.993 1.005 0.981 0.993 1.005 V
Load Regulation Error at 1.0 mA Full 2 2 2 mV

INPUT REFERRED NOISE

VREF = 1.0 V 25°C 0.06 0.08 0.08 LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V Full 2 2 2 V p-p
Input Capacitance3 Full 6 6 6 pF
Input Common-Mode Voltage Full 0.9 0.9 0.9 V

Input Common-Mode Range Full 0.5 1.3 0.5 1.3 0.5 1.3 V
REFERENCE INPUT RESISTANCE Full 7.5 7.5 7.5 kΩ
POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
DRVDD Full 1.7 3.6 1.7 3.6 1.7 3.6 V

Supply Current

IAVDD2 Full 33.5/46.4 35.8/49.6 61.1 64.8 70.3 75.2 mA
IDRVDD2 (1.8 V) Full 2.6/4.4 6.5 8.0 mA
IDRVDD2 (3.3 V) Full 5.0/8.3 12.4 15.3 mA

POWER CONSUMPTION

DC Input Full 59.5/82.1 108 125 mW

Sine Wave Input2 (DRVDD = 1.8 V) Full 64.9/91.4 69.5/97.7 121.7 128.5 141 150 mW

Sine Wave Input2 (DRVDD = 3.3 V) Full 76.7/111 150.8 177 mW

Standby Power4 Full 37/37 37 37 mW

Power-Down Power Full 2.2 2.2 2.2 mW

1

Measured with a 1.0 V external reference.

2

Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.

3

Input capacitance refers to the effective capacitance between one differential input pin and AGND.

4

Standby power is measured with a dc input, the CLK active.

Unit Min Typ Max Min Typ Max Min Typ Max

Rev. 0 | Page 4 of 36

AD9204

AC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.

Table 2.

AD9204-20/AD9204-40 AD9204-65 AD9204-80

Parameter1 Temp

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 9.7 MHz 25°C 61.7 61.5 61.3 dBFS
fIN = 30.5 MHz 25°C 61.6 61.4 61.3 dBFS
Full 61.0 60.5 dBFS
fIN = 70 MHz 25°C 61.6 61.4 61.3 dBFS
Full 60.4 dBFS
fIN = 200 MHz 25°C 61.0 61.0 dBFS

SIGNAL-TO-NOISE-AND DISTORTION (SINAD)

fIN = 9.7 MHz 25°C 61.5 61.2 61.1 dBFS
fIN = 30.5 MHz 25°C 61.5 61.2 61.1 dBFS
Full 60.1 59.7 dBFS
fIN = 70 MHz 25°C 61.5 61.2 61.1 dBFS
Full 59.5 dBFS
fIN = 200 MHz 25°C 60 60 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 9.7 MHz 25°C 9.9 9.8 9.8 Bits
fIN = 30.5 MHz 25°C 9.9 9.8 9.8 Bits
fIN = 70 MHz 25°C 9.9 9.8 9.8 Bits
fIN = 200 MHz 25°C 9.6 9.6 Bits

WORST SECOND OR THIRD HARMONIC

fIN = 9.7 MHz 25°C −81 −78 −78 dBc
fIN = 30.5 MHz 25°C −81 −78 −78 dBc
Full −65 −64 dBc
fIN = 70 MHz 25°C −82 −78 −78 dBc
Full −64 dBc
fIN = 200 MHz 25°C −73 −73 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 9.7 MHz 25°C 78 75 75 dBc
fIN = 30.5 MHz 25°C 78 75 75 dBc
Full 65 64 dBc
fIN = 70 MHz 25°C 78 75 75 dBc
Full 64 dBc
fIN = 200 MHz 25°C 73 73 dBc

WORST OTHER (HARMONIC OR SPUR)

fIN = 9.7 MHz 25°C −82 −80 −80 dBc
fIN = 30.5 MHz 25°C −82 −80 −80 dBc
Full −71 −70 dBc
fIN = 70 MHz 25°C −82 −80 −80 dBc
Full −70 dBc
fIN = 200 MHz 25°C −80 −80 dBc

TWO-TONE SFDR

fIN = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) 25°C 78 78 dBc
CROSSTALK2 Full −100 −100 −100 dBc
ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.

Rev. 0 | Page 5 of 36

Unit Min Typ Max Min Typ Max Min Typ Max

AD9204

DIGITAL SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.

Table 3.

AD9204-20/AD9204-40/AD9204-65/AD9204-80

Parameter Temp

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 0.9 V
Differential Input Voltage Full 0.2 3.6

Input Voltage Range Full GND − 0.3 AVDD + 0.2 V
High Level Input Current Full −10 +10 μA
Low Level Input Current Full −10 +10 μA
Input Resistance Full 8 10 12 kΩ
Input Capacitance Full 4 pF

LOGIC INPUTS (SCLK/DFS, SYNC, PDWN)1

High Level Input Voltage Full 1.2 DRVDD + 0.3 V
Low Level Input Voltage Full 0 0.8 V
High Level Input Current Full −50 −75 μA
Low Level Input Current Full −10 +10 μA
Input Resistance Full 30 kΩ
Input Capacitance Full 2 pF

LOGIC INPUTS (CSB)2

High Level Input Voltage Full 1.2 DRVDD + 0.3 V
Low Level Input Voltage Full 0 0.8 V
High Level Input Current Full −10 +10 μA
Low Level Input Current Full +40 +135 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF

LOGIC INPUTS (SDIO/DCS)2

High Level Input Voltage Full 1.2 DRVDD + 0.3 V
Low Level Input Voltage Full 0 0.8 V
High Level Input Current Full −10 +10 μA
Low Level Input Current Full +40 +130 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF

DIGITAL OUTPUTS

DRVDD = 3.3 V

High Level Output Voltage, IOH = 50 μA Full 3.29 V
High Level Output Voltage, IOH = 0.5 mA Full 3.25 V
Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V
Low Level Output Voltage, IOL = 50 μA Full 0.05 V

DRVDD = 1.8 V

High Level Output Voltage, IOH = 50 μA Full 1.79 V
High Level Output Voltage, IOH = 0.5 mA Full 1.75 V
Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V
Low Level Output Voltage, IOL = 50 μA Full 0.05 V

1

Internal 30 kΩ pull-down.

2

Internal 30 kΩ pull-up.

Unit Min Typ Max

V p­p

Rev. 0 | Page 6 of 36

AD9204

SWITCHING SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.

Table 4.

AD9204-20/AD9204-40 AD9204-65 AD9204-80

Parameter Temp

CLOCK INPUT PARAMETERS

Input Clock Rate Full 625 625 625 MHz

Conversion Rate1 Full 3 20/40 3 65 3 80 MSPS

CLK Period—Divide-by-1 Mode (t

) Full

CLK

50/25

15.38 12.5 ns
CLK Pulse Width High (tCH) 25.0/12.5 7.69 6.25 ns
Aperture Delay (tA) Full 1.0 1.0 1.0 ns
Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD) Full
DCO Propagation Delay (t
DCO to Data Skew (t

SKEW

) Full 3

DCO

) Full 0.1

3

3
3

0.1

3 ns
3 ns

0.1 ns
Pipeline Delay (Latency) Full 9 9 9 Cycles
Wake-Up Time2 Full 350 350 350 μs
Standby Full 600/400 300 260 ns

OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles

1

Conversion rate is the clock rate after the CLK divider.

2

Wake-up time is dependent on the value of the decoupling capacitors.

Unit Min Typ Max Min Typ Max Min Typ Max

VIN

CLK+

CLK–

DCOA/DCOB

CH A/CH B DATA

N – 1

t

A

N

N + 1

t

CH

t

CLK

t

DCO

t

SKEW

N – 9

t

PD

N + 2

N – 8N – 7N – 6N – 5

N + 3

N + 4

N + 5

08122-002

Figure 2. CMOS Output Data Timing

VIN

CLK+

CLK–

DCOA/DCOB

CH A/CH B DATA

N – 1

t

A

N

N + 1

t

CH

t

CLK

t

DCO

t

SKEW

CH A

CH B

N – 9

N – 9

t

PD

Figure 3. CMOS Interleaved Output Timing

Rev. 0 | Page 7 of 36

CH A
N – 8

N + 2

CH B
N – 8

CH A
N – 7

N + 3

CH B
N – 7

CH A
N – 6

N + 4

CH B
N – 6

CH A
N – 5

N + 5

08122-003

AD9204

TIMING SPECIFICATIONS

Table 5.

Parameter Conditions Min Typ Max Unit

SYNC TIMING REQUIREMENTS

t

SYNC to rising edge of CLK setup time 0.24 ns

SSYNC

t

SYNC to rising edge of CLK hold time 0.40 ns

HSYNC

SPI TIMING REQUIREMENTS

tDS Setup time between the data and the rising edge of SCLK 2 ns
tDH Hold time between the data and the rising edge of SCLK 2 ns
t

Period of the SCLK 40 ns

CLK

tS Setup time between CSB and SCLK 2 ns
tH Hold time between CSB and SCLK 2 ns
t

SCLK pulse width high 10 ns

HIGH

t

SCLK pulse width low 10 ns

LOW

t

EN_SDIO

t

DIS_SDIO

Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge

Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge

CLK+

10 ns

10 ns

t

SSYNC

SYNC

Figure 4. SYNC Input Timing Requirements

t

HSYNC

08122-004

Rev. 0 | Page 8 of 36

AD9204

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

AVDD to AGND −0.3 V to +2.0 V
DRVDD to AGND −0.3 V to +3.9 V
VIN+A, VIN+B, VIN−A, VIN−B to AGND −0.3 V to AVDD + 0.2 V
CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V
SYNC to AGND −0.3 V to DRVDD + 0.3 V
VREF to AGND −0.3 V to AVDD + 0.2 V
SENSE to AGND −0.3 V to AVDD + 0.2 V
VCM to AGND −0.3 V to AVDD + 0.2 V
RBIAS to AGND −0.3 V to AVDD + 0.2 V
CSB to AGND −0.3 V to DRVDD + 0.3 V
SCLK/DFS to AGND −0.3 V to DRVDD + 0.3 V
SDIO/DCS to AGND −0.3 V to DRVDD + 0.3 V
OEB to AGND −0.3 V to DRVDD + 0.3 V
PDWN to AGND −0.3 V to DRVDD + 0.3 V
D0A/D0B Th rough D13A/D13B to AGND −0.3 V to DRVDD + 0.3 V
DCOA/DCOB to AGND
Operating Temperature Range (Ambient) −40°C to +85°C
Maximum Junction Temperature

Under Bias

Storage Temperature Range (Ambient) −65°C to +150°C

−0.3 V to DRVDD + 0.3 V

150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS

The exposed paddle is the only ground connection for the chip.
The exposed paddle must be soldered to the AGND plane of the
user’s circuit board. Soldering the exposed paddle to the user’s
board also increases the reliability of the solder joints and
maximizes the thermal capability of the package.

Table 7. Thermal Resistance

Airflow
Veloc ity

Packa ge Type

64-Lead LFCSP

9 mm × 9 mm
(CP-64-4)

1

Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3

Per MIL-Std 883, Method 1012.1.

4

Per JEDEC JESD51-8 (still air).

(m/sec)

0 23 2.0 °C/W

1.0 20 12 °C/W

2.5 18 °C/W

1, 2

θ

JA

1, 3

θ

JC

1, 4

θ

Unit

JB

Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown in Ta b l e 7 , airflow improves heat dissipation,
which reduces θ

. In addition, metal in direct contact with the

JA

package leads from metal traces, through holes, ground, and
power planes reduces the θ

.

JA

ESD CAUTION

Rev. 0 | Page 9 of 36

AD9204

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVD D

AVD D

VIN+B

VIN–B

AVD D

AVD D

RBIAS

VCM

SENSE

VREF

AVD D

AVD D

VIN–A

VIN+A

AVD D

646362616059585756555453525150

AVD D

49

CLK+
CLK–

SYNC

NC
NC
NC
NC
NC
NC

DRVDD

D1B
D2B
D3B
D4B
D5B

10
11
12
13
14
15
16

D0B (LSB)

NOTES

1. NC = NO CONNECT

2. THE EXPOSED PADDLE MUST BE SOLDERED TO T HE PCB GROUND
TO ENSURE PRO PER HEAT DISSIPATIO N, NOISE, AND MECHANICAL
STRENGTH BENE FITS.

PIN 1

1

INDICATOR

2
3
4
5
6
7
8
9

171819202122232425262728293031

D6B

D7B

D8B

DRVDD

AD9204

TOP VIEW

(Not to Scale)

ORB

DCOA

DCOB

D9B (MSB)

NCNCNC

NCNCNC

DRVDD

48

PDWN

47

OEB

46

CSB

45

SCLK/DFS

44

SDIO/DCS

43

ORA

42

D9A (MSB)

41

D8A

40

D7A

39

D6A

38

D5A

37

DRVDD

36

D4A

35

D3A

34

D2A

33

D1A

32

D0A (LSB)

08122-005

Figure 5. Pin Configuration

Table 8. Pin Function Description

Pin No. Mnemonic Description

0 GND Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND.
1, 2 CLK+, CLK− Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
3 SYNC Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.
4, 5, 6, 7, 8, 9, 25, 26, 27,

NC Do Not Connect.

29, 30, 31
10, 19, 28, 37 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V).
11 to 18, 20, 21 D0B to D9B Channel B Digital Outputs. D9B = MSB.
22 ORB Channel B Out-of-Range Digital Output.
23 DCOB Channel B Data Clock Digital Output.
24 DCOA Channel A Data Clock Digital Output.
32 to 36, 38 to 42 D0A to D9A Channel A Digital Outputs. D9A = MSB.
43 ORA Channel A Out-of-Range Digital Output.
44 SDIO/DCS

SPI Data Input/Output (SDIO). Bidirectional SPI Data I/O in SPI mode. 30 kΩ internal pull­down in SPI mode.

Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode.
30 kΩ internal pull-up in non-SPI (DCS) mode.

45 SCLK/DFS SPI Clock (SCLK) Input in SPI mode. 30 kΩ internal pull-down.

Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal
pull-down.
DFS high = twos complement output.

DFS low = offset binary output.
46 CSB SPI Chip Select. Active low enable; 30 kΩ internal pull-up.
47 OEB

Digital Input. Enable Channel A and Channel B digital outputs if low, three-state outputs if

high. 30 kΩ internal pull-down.
48 PDWN Digital Input. 30 kΩ internal pull-down.

PDWN high = power-down device.

PDWN low = run device, normal operation.

Rev. 0 | Page 10 of 36

AD9204

Pin No. Mnemonic Description

49, 50, 53, 54, 59, 60, 63, 64 AVDD 1.8 V Analog Supply Pins.
51, 52 VIN+A, VIN−A Channel A Analog Inputs.
55 VREF Voltage Reference Input/Output.
56 SENSE Reference Mode Selection.
57 VCM Analog output voltage at midsupply to set common mode of the analog inputs.
58 RBIAS Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
61, 62 VIN−B, VIN+B Channel B Analog Inputs.

Rev. 0 | Page 11 of 36

AD9204

TYPICAL PERFORMANCE CHARACTERISTICS

AD9204-80

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS
disabled, unless otherwise noted.

0

80MSPS

30.5MHz @ –1dBF S
SNR = 60.5dB (61. 5dBFS)

–20

SFDR = 83.5d Bc

–20

0

80MSPS

9.7MHz @ –1dBF S
SNR = 60.5dB (6 1.5dBFS)
SFDR = 80.3d Bc

–40

–60

AMPLITUDE ( dB)

–80

–100

–120

50 10152025303540

FREQUENCY (MHz)

Figure 6. AD9204-80 Single-Tone FFT with fIN = 9.7 MHz

AMPLITUDE (dBFS)

0

–20

–40

–60

–80

–100

80MSPS

70.3MHz @ –1dBF S
SNR = 60.4dB (6 1.4dBFS)
SFDR = 82.2d Bc

–40

–60

AMPLI TUDE (d B)

–80

–100

–120

08122-033

50 10152025303540

FREQUENCY (MHz)

08122-034

Figure 9. AD9204-80 Single-Tone FFT with fIN = 30.5 MHz

0

80MSPS
200MHz @ –1dBFS
SNR = 60.1dB (60. 1dBFS)

–20

SFDR = 74.176d Bc

–40

–60

2

AMPLITUDE (dBFS)

–80

–100

6

4

+

3

5

–120

50 10152025303540

FREQUENCY (MHz)

Figure 7. AD9204-80 Single-Tone FFT with fIN = 70.3 MHz

0

80MSPS

30.5MHz @ –7dBF S

–15

32.5MHz @ –7dBF S
SFDR = 78dBc

–30

–45

–60

–75

AMPLI TUDE (d B)

F2 – F1

–90

–105

–120

40 8 12 16 20 24 28 32 36 40

Figure 8. AD9204-80 Two-Tone FFT with f

F1 + F2

2F1 – F2

2F2 + F1

FREQUENCY (MHz )

= 30.5 MHz and f

IN1

2F1 – F2

= 32.5 MHz

IN2

08122-062

08122-036

Figure 11. AD9204-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with

Rev. 0 | Page 12 of 36

–120

50 10152025303540

FREQUENCY (MHz)

Figure 10. AD9204-80 Single-Tone FFT with fIN =200 MHz

–10

–30

IMD3 (dBc)

–50

–70

SFDR/IMD3 (dBFS/dBc)

–90

–110

–60 –54 –48 –42 –36 –30 –24 –18 –12 –6

f

= 30.5 MHz and f

IN1

SFDR (dBc)

SFDR (dBFS)

IMD3 (dBFS)

INPUT AMPLITUDE (dBFS)

= 32.5 MHz

IN2

08122-134

08122-054

AD9204

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS
disabled, unless otherwise noted.

85

80

75

70

65

60

SNR/SFDR (dBF S/dBc)

55

50

0 50 100 150 200

SFDR (dBc)

SNR (dBFS)

AIN FREQUENCY (MHz)

Figure 12. AD9204-80 SNR/SFDR vs. Input Frequency (AIN) with

2 V p-p Full Scale

85

08122-057

90

80

70

60

50

40

30

SNR/SFDR (dBc/dBFS)

20

10

0

–60 –50 –30 –10 0

SFDRFS

SNRFS

SFDR

SNR

–40 –20

INPUT AMPLITUDE (dBc)

08122-061

Figure 15. AD9204-80 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7MHz

120,000

80

75

70

SNR/SFDR (dBFS/dBc)

65

60

0 1020304050607080

SFDR (dBc)

SNR (dBFS)

SAMPLE RATE ( MHz)

Figure 13. AD9204-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz

0.20

0.16

0.12

0.08

0.04

0

–0.04

DNL ERROR (LSB)

–0.08

–0.12

–0.16

–0.20

24 224 424 624 824 1024

OUTPUT CODE

Figure 14. AD9204-80 DNL with fIN = 9.7 MHz

100,000

80,000

60,000

40,000

NUMBER OF HIT S

20,000

0

N – 3N – 2N – 1 N N + 1 N + 2N + 3

08122-055

OUTPUT CODE

08122-048

Figure 16. AD9204-80 Grounded Input Histogram

1.0

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

24 224 424 624 824 1024

08122-038

OUTPUT CODE

08122-037

Figure 17. AD9204-80 INL with fIN = 9.7 MHz

Rev. 0 | Page 13 of 36

AD9204

AD9204-65

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS
disabled, unless otherwise noted.

0

0

–20

–40

–60

65MSPS

9.7MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
SFDR = 83.1dBc

–10

–30

–50

SFDR (dBc)

IMD3 (dBc)

AMPLITUDE (dB)

–80

–100

–120

50 1015202530

FREQUENCY (MHz )

Figure 18. AD9204-65 Single-Tone FFT with fIN = 9.7 MHz

AMPLITUDE (dB)

–20

–40

–60

–80

–100

–120

0

50 1015202530

FREQUENCY (MHz )

65MSPS

70.3MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
SFDR = 83.4dBc

Figure 19. AD9204-65 Single-Tone FFT with fIN = 70.3 MHz

0

–20

–40

65MSPS

30.5MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
SFDR = 83.9dBc

–70

SFDR/IMD3 (dBFS/dBc)

–90

–110

–60 –54 –48 –42 –36 –30 –24 –18 –12 –6

08122-030

Figure 21. AD9204-65 SNR/SFDR vs. Input Amplitude (AIN) with f

SFDR (dBFS )

IMD3 (dBFS)

INPUT AMPLITUDE (dBF S )

= 9.7 MHz

IN

08122-060

85

80

75

70

65

60

SNR/SFDR (dBFS/dBc)

55

50

0 50 100 150 200

08122-032

SFDR (dBc)

SNR (dBFS)

AIN FREQUENCY ( M Hz)

08122-056

Figure 22. AD9204-65 SNR/SFDR vs. Input Frequency (AIN) with

2 V p-p Full Scale

–60

AMPLITUDE ( dB)

–80

–100

–120

50 1015202530

FREQUENCY (MHz )

Figure 20. AD9204-65 Single-Tone FFT with fIN = 30.5 MHz

08122-031

Rev. 0 | Page 14 of 36

AD9204

AD9204-40

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS
disabled, unless otherwise noted.

0

40MSPS

9.7MHz @ –1dBFS
SNR = 60.6dB (61. 6dBFS)

–20

SFDR = 82.0dBc

–40

–60

AMPLI TUDE (d B)

–80

–100

–120

0 5 10 15 20

FREQUENCY (MHz )

Figure 23. AD9204-40 Single-Tone FFT with fIN = 9.7 MHz

0

–20

40MSPS

30.5MHz @ –1dBF S
SNR = 60.6dB (6 1.6dBFS)
SFDR = 83.8d Bc

08122-028

90

80

70

60

50

40

30

SNR/SFDR (dBc/dBFS)

20

10

0
–60 –50 –30 –10 0

SFDRFS

SNRFS

SFDR

SNR

–40 –20
INPUT AMPLITUDE (dBc)

08122-059

Figure 25. AD9204-40 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz

–40

–60

AMPLI TUDE (d B)

–80

–100

–120

24680 101214161820

FREQUENCY (MHz)

Figure 24. AD9204-40 Single-Tone FFT with fIN = 30.5 MHz

08122-029

Rev. 0 | Page 15 of 36

AD9204

AD9204-20

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS
disabled, unless otherwise noted.

0

20MSPS

9.7MHz @ –1dBFS

–20

SNR = 60.6dBFS (61.6dBFS)
SFDR = 81.3dBc

–40

–60

AMPLI TUDE (d B)

–80

–100

–120

20468

FREQUENCY (MHz)

Figure 26. AD9204-20 Single-Tone FFT with fIN = 9.7 MHz

0

20MSPS

30.5MHz @ –1dBF S

–20

SNR = 60.6dBFS (61.6dBFS)
SFDR = 84.0dBc

–40

10

08122-024

90

80

70

60

50

40

30

SNR/SFDR (dBc/dBFS)

20

10

0

–60 –50 –40 –30 –20

SFDR (dBFS)

SNR (dBFS)

SFDR (dBc)

INPUT AMPLITUDE (dBc)

SNR (dBc)

–10

0

08122-058

Figure 28. AD9204-20 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7MHz

–60

AMPLI TUDE (d B)

–80

–100

–120

2046810

FREQUENCY (MHz)

08122-026

Figure 27. AD9204-20 Single-Tone FFT with fIN = 30.5 MHz

Rev. 0 | Page 16 of 36

AD9204

A

V

S

A

V

V

A

A

V

EQUIVALENT CIRCUITS

DRVDD

DD

VIN±x

08122-039

Figure 29. Equivalent Analog Input Circuit

Figure 32. Equivalent Digital Output Circuit

08122-042

CLK+

CLK–

5Ω

15kΩ

15kΩ

5Ω

Figure 30. Equivalent Clock Input Circuit

DD

DRVDD

30kΩ

DIO/DCS

350Ω

30kΩ

0.9V

DR

DD

SCLK/DFS, SYNC,

OEB, AND PDWN

08122-040

Figure 33. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit

RBIAS

ND VCM

350Ω

30kΩ

08122-043

DD

375Ω

08122-044

Figure 31. Equivalent SDIO/DCS Input Circuit

08122-041

Figure 34. Equivalent RBIAS, VCM Circuit

Rev. 0 | Page 17 of 36

AD9204

V

S

A

V

A

V

DR

CSB

350Ω

DD

AVD D

30kΩ

VREF

DD

375Ω

7.5kΩ

Figure 35. Equivalent CSB Input Circuit

DD

ENSE

375Ω

08122-045

Figure 37. Equivalent VREF Circuit

08122-046

08122-047

Figure 36. Equivalent SENSE Circuit

Rev. 0 | Page 18 of 36

AD9204

V

THEORY OF OPERATION

The AD9204 dual ADC design can be used for diversity
reception of signals, where the ADCs are operating identically
on the same carrier but from two separate antennae. The ADCs
can also be operated with independent analog inputs. The user
can sample any f

/2 frequency segment from dc to 200 MHz,

S

using appropriate low-pass or band-pass filtering at the ADC
inputs with little loss in ADC performance. Operation to
300 MHz analog input is permitted but occurs at the
expense of increased ADC noise and distortion.

In nondiversity applications, the AD9204 can be used as a base­band or direct downconversion receiver, where one ADC is
used for I input data and the other is used for Q input data.

Synchronization capability is provided to allow synchronized
timing among multiple channels or multiple devices.

Programming and control of the AD9204 are accomplished
using a 3-bit SPI-compatible serial interface.

ADC ARCHITECTURE

The AD9204 architecture consists of a multistage, pipelined ADC.
Each stage provides sufficient overlap to correct for flash errors
in the preceding stage. The quantized outputs from each stage are
combined into a final 10-bit result in the digital correction logic.
The pipelined architecture permits the first stage to operate with
a new input sample, while the remaining stages operate with
preceding samples. Sampling occurs on the rising edge of
the clock.

Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.

The output staging block aligns the data, corrects errors, and
passes the data to the CMOS output buffers. The output buffers
are powered from a separate (DRVDD) supply, allowing adjust­ment of the output voltage swing. During power-down, the
output buffers go into a high impedance state.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9204 is a differential switched­capacitor circuit designed for processing differential input
signals. This circuit can support a wide common-mode range
while maintaining excellent performance. By using an input
common-mode voltage of midsupply, users can minimize
signal-dependent errors and achieve optimum performance.

H

C

PAR

IN+x

VIN–x

C

PAR

Figure 38. Switched-Capacitor Input Circuit

C

SAMPLE

SS

SS

C

SAMPLE

H

The clock signal alternately switches the input circuit between
sample-and-hold mode (see Figure 38). When the input circuit
is switched to sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current injected from the output
stage of the driving source. In addition, low Q inductors or ferrite
beads can be placed on each leg of the input to reduce high
differential capacitance at the analog inputs and, therefore,
achieve the maximum bandwidth of the ADC. Such use of low
Q inductors or ferrite beads is required when driving the converter
front end at high IF frequencies. Either a shunt capacitor or two
single-ended capacitors can be placed on the inputs to provide a
matching passive network. This ultimately creates a low-pass
filter at the input to limit unwanted broadband noise. See the
AN-742 Application Note, the AN-827 Application Note, and the
Analog Dialogue article “Transformer-Coupled Front-End for

Wideband A/D Converters” (Volume 39, April 2005) for more

information. In general, the precise values depend on the
application.

H

H

08122-006

Rev. 0 | Page 19 of 36

AD9204

Input Common Mode

The analog inputs of the AD9204 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide a
dc bias externally. Setting the device so that VCM = AVDD/2 is
recommended for optimum performance, but the device can
function over a wider range with reasonable performance, as
shown in Figure 39 and Figure 40.

An on-board, common-mode voltage reference is included in
the design and is available from the VCM pin. The VCM pin
must be decoupled to ground by a 0.1 µF capacitor, as described
in the Applications Information section.

100

90

80

70

SNR/SFDR (d BFS/dBc)

60

50

0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3

SFDR (dBc)

SNR (dBFS)

INPUT COMMON-MODE VOLTAGE (V)

08122-139

Figure 39. SNR/SFDR vs. Input Common-Mode Voltage,

= 32.1 MHz, fS = 80 MSPS

f

IN

100

90

80

70

SNR/SFDR (d BFS/dBc)

60

50

0.5 0 .6 0.7 0.8 0.9 1.0 1. 1 1. 2 1. 3

SFDR (dBc)

SNR (dBFS)

INPUT COMMON-MODE VOLTAGE (V)

08122-140

Figure 40. SNR/SFDR vs. Input Common-Mode Voltage,

= 10.3 MHz, fS = 20 MSPS

f

IN

Differential Input Configurations

Optimum performance is achieved while driving the AD9204 in a
differential input configuration. For baseband applications, the

AD8138, ADA4937-2, and ADA4938-2 differential drivers provide

excellent performance and a flexible interface to the ADC.

The output common-mode voltage of the ADA4938-2 is easily
set with the VCM pin of the AD9204 (see Figure 41), and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.

200Ω

VIN

0.1µF

76.8Ω
90Ω

120Ω

ADA4938-2

200Ω

33Ω

10pF

33Ω

VIN–x

VIN+x

AVDD

ADC

VCM

Figure 41. Differential Input Configuration Using the ADA4938-2

For baseband applications below ~10 MHz where SNR is a key
parameter, differential transformer-coupling is the recommended
input configuration. An example is shown in Figure 42. To bias
the analog input, the VCM voltage can be connected to the
center tap of the secondary winding of the transformer.

R

2V p-p

49.9Ω

C

R

0.1µF

Figure 42. Differential Transformer-Coupled Configuration

VIN–x

VIN+x

ADC

VCM

The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz (MHz). Excessive signal power can
also cause core saturation, which leads to distortion.

At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9204. For applications above
~10 MHz where SNR is a key parameter, differential double balun
coupling is the recommended input configuration (see Figure 44).

An alternative to using a transformer-coupled input at frequencies
in the second Nyquist zone is to use the AD8352 differential driver.
An example is shown in Figure 45. See the AD8352 data sheet
for more information.

In any configuration, the value of Shunt Capacitor C is dependent
on the input frequency and source impedance and may need to
be reduced or removed. Tab l e 9 displays the suggested values to
set the RC network. However, these values are dependent on
the input signal and should be used only as a starting guide.

Table 9. Example RC Network

R Series

Frequency Range (MHz)

(Ω Each) C Differential (pF)

0 to 70 33 22
70 to 200 125 Open

08122-007

08122-008

Rev. 0 | Page 20 of 36

AD9204

A

V

F

2

p

V

Single-Ended Input Configuration

A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input common­mode swing. If the source impedances on each input are matched,
there should be little effect on SNR performance. Figure 43
shows a typical single-ended input configuration.

0.1µF

V p-

SP

A

P

S

0.1µF

Figure 44. Differential Double Balun Input Configuration

CC

0.1µF

0Ω

ANALOG INPUT

ANALOG INPUT

16

1

2

R

C

D

0.1µF

R

D

G

3

4

5

0Ω

Figure 45. Differential Input Configuration Using the AD8352

8, 13

AD8352

10

14

0.1µF

1V p-p

49.9Ω

10µF

10µF

0.1µF

0.1µF

AVD D

1kΩ

1kΩ

1kΩ

1kΩ

DD

R

C

R

VIN+x

VIN–x

ADC

08122-009

Figure 43. Single-Ended Input Configuration

R0.1µ

25Ω

0.1µF

25Ω

0.1µF

11

200Ω

200Ω

0.1µF

C

R

0.1µF
R

C

R

0.1µF

VIN+x

VIN–x

ADC

VIN+x

VIN–x

VCM

ADC

VCM

08122-010

08122-011

Rev. 0 | Page 21 of 36

AD9204

VOLTAGE REFERENCE

A stable and accurate 1.0 V voltage reference is built into the
AD9204. The VREF can be configured using either the internal

1.0 V reference or an externally applied 1.0 V reference voltage.
The various reference modes are summarized in the sections that
follow. The Reference Decoupling section describes the best
practices PCB layout of the reference.

Internal Reference Connection

A comparator within the AD9204 detects the potential at the
SENSE pin and configures the reference into two possible
modes, which are summarized in Tabl e 10. If SENSE is grounded,
the reference amplifier switch is connected to the internal resistor
divider (see Figure 46), setting VREF to 1.0 V.

VIN+A/ VIN+B

VIN–A/VIN–B

In either internal or external reference mode, the maximum
input range of the ADC can be varied by configuring SPI
Address 0x18 as shown in Tab le 1 1 , resulting in a selectable
differential span from 1 V p-p to 2 V p-p.

If the internal reference of the AD9204 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 47 shows
how the internal reference voltage is affected by loading.

0

–0.5

–1.0

INTERNAL V

–1.5

–2.0

REF

= 0.993V

ADC

CORE

VREF

0.1µF1.0µF

SENSE

Figure 46. Internal Reference Configuration

SELECT

LOGIC

0.5V

ADC

08122-012

–2.5

REFERENCE VOL TAGE ERROR ( %)

–3.0

02

0.2 0.4 0.6 0.8 1.0 1.4 1.6 1.81.2

LOAD CURRENT (mA)

Figure 47. VREF Accuracy vs. Load Current

.0

Table 10. Reference Configuration Summary

Selected Mode SENSE Voltage (V) Resulting VREF (V) Resulting Differential Span (V p-p)

Fixed Internal Reference AGND to 0.2 1.0 internal 2.0
Fixed External Reference AVDD 1.0 applied to external VREF pin 2.0

Table 11. Scaled Differential Span Summary

Selected Mode Resulting VREF (V) SPI Register 0x18 (Hex) Resulting Differential Span (V p-p)

Fixed Internal or External Reference 1.0 (internal or external) 0xC0 1.0
Fixed Internal or External Reference 1.0 (internal or external) 0xC8 1.14
Fixed Internal or External Reference 1.0 (internal or external) 0xD0 1.33
Fixed Internal or External Reference 1.0 (internal or external) 0xD8 1.6
Fixed Internal or External Reference 1.0 (internal or external) 0xE0 2.0

08122-014

Rev. 0 | Page 22 of 36

AD9204

External Reference Operation

The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac­teristics. Figure 48 shows the typical drift characteristics of the
internal reference in 1.0 V mode.

4

3

2

1

0

–1

ERROR (mV)

–2

REF

V

–3

–4

–5

–6

–40 –20 0 20 40 60 80

V

ERROR (mV)

REF

TEMPERATURE ( °C)

08122-052

Figure 48. Typical VREF Drift

When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent

7.5 kΩ load (see Figure 37). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the AD9204 sample clock
inputs, CLK+ and CLK−, with a differential signal. The signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased internally
(see Figure 49) and require no external bias.

AVDD

0.9V

CLK–CLK+

Clock Input Options

The AD9204 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter
is of the most concern, as described in the Jitter Considerations
section.

Figure 50 and Figure 51 show two preferred methods for clocking
the AD9204 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF transformer or an RF balun.

The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is recom­mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary limit clock excursions into the AD9204 to approx­imately 0.8 V p-p differential.

This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9204 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance.

XFMR

0.1µF

®

0.1µF0.1µF

0.1µF

0.1µF1nF

0.1µF

SCHOTTKY

DIODES:

HSMS2822

SCHOTTKY

DIODES:

HSMS2822

CLK+

CLK–

CLK+

CLK–

ADC

ADC

08122-018

Mini-Circuits

ADT1-1WT, 1:1 Z

CLOCK

INPUT

50Ω

100Ω

Figure 50. Transformer-Coupled Differential Clock (Up to 200 MHz)

CLOCK

INPUT

50Ω

1nF

Figure 51. Balun-Coupled Differential Clock (Up to 625 MHz)

08122-017

2pF 2pF

Figure 49. Equivalent Clock Input Circuit

08122-016

Rev. 0 | Page 23 of 36

AD9204

C

If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 52. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer

excellent jitter performance.

CLOCK

INPUT

CLOCK

INPUT

50kΩ 50kΩ

0.1µF

0.1µF

AD951x

PECL DRIVER

Figure 52. Differential PECL Sample Clock (Up to 625 MHz)

0.1µF
CLK+

100Ω

0.1µF

240Ω240Ω

ADC

CLK–

A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 53. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517
clock drivers offer excellent jitter performance.

CLOCK

INPUT

CLOCK

INPUT

50kΩ 50kΩ

0.1µF

0.1µF

AD951x

LVDS DRIVER

Figure 53. Differential LVDS Sample Clock (Up to 625 MHz)

0.1µF

100Ω

0.1µF

CLK+

ADC

CLK–

In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK− pin to ground with a 0.1 F capacitor (see
Figure 54).

V

CC

0.1µF

1kΩ

1kΩ

AD951x

CMOS DRI VER

LOCK
INPUT

1

50Ω

1

50Ω RESISTOR I S OPTIO NAL.

Figure 54. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

OPTIONAL

100Ω

0.1µF

0.1µF
CLK+

ADC

CLK–

08122-019

08122-020

08122-021

Input Clock Divider

The AD9204 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.
Optimum performance can be obtained by enabling the
internal duty cycle stabilizer (DCS) when using divide ratios
other than 1, 2, or 4.

The AD9204 clock divider can be synchronized using the
external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow
the clock divider to be resynchronized on every SYNC signal
or only on the first SYNC signal after the register is written. A
valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows multiple parts to have their
clock dividers aligned to guarantee simultaneous input
sampling.

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.

The AD9204 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9204. Noise and distortion perform­ance are nearly flat for a wide range of duty cycles with the DCS
on, as shown in Figure 55.

Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 µs to 5 µs
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.

80

75

70

65

DCS ON

60

SNR (dBFS)

55

50

45

40

10 20 30 40 50 60 70 80

DCS OFF

POSITI VE DUTY CYCLE (%)

08122-053

Figure 55. SNR vs. DCS On/Off

Rev. 0 | Page 24 of 36

AD9204

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low fre­quency SNR (SNR
jitter (t

) can be calculated by

JRMS

SNR

= −10 log[(2π × f

HF

) at a given input frequency (f

LF

× t

INPUT

)2 + 10 ]

JRMS

INPUT

) due to

)10/(LFSNR−

In the previous equation, the rms aperture jitter represents
the clock input jitter specification. Input frequency (IF)
undersampling applications are particularly sensitive to jitter,
as illustrated in Figure 56.

80

75

70

65

60

SNR (dBFS)

55

50

45

1 10 100 1k

FREQUENCY (MHz)

3.0ps

0.05ps

0.2ps

0.5ps

1.0ps

1.5ps

2.0ps

2.5ps

08122-022

Figure 56. SNR vs. Input Frequency and Jitter

The clock input should be treated as an analog signal in cases in
which aperture jitter may affect the dynamic range of the AD9204.
To avoid modulating the clock signal with digital noise, keep
power supplies for clock drivers separate from the ADC output
driver supplies. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.

See the AN-501 Application Note and the AN-756 Application
Note available on www.analog.com for more information.

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 57, the analog core power dissipated by
the AD9204 is proportional to its sample rate. The digital
power dissipation of the CMOS outputs is determined primarily
by the strength of the digital drivers and the load
on each output bit.

The maximum DRVDD current (IDRVDD) can be calculated as

IDRVDD = V

where N is the number of output bits (30, in the case of the
AD9204).

This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of f

CLK

lished by the average number of output bits switching, which
is determined by the sample rate and the characteristics of the
analog input signal.

Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 57 was
taken using the same operating conditions as those used in the
Typical Performance Characteristics, with a 5 pF load on each
output driver.

140

130

120

110

100

90

80

70

ANALOG CORE P OWER (mW)

60

50

0 10 20 30 40 50 60 70 80

Figure 57. AD9204 Analog Core Power vs. Clock Rate

DRVDD

× C

LOAD

× f

CLK

× N

/2. In practice, the DRVDD current is estab-

AD9204-80

AD9204-65

AD9204-40

AD9204-20

CLOCK RATE (MS PS)

08122-051

Rev. 0 | Page 25 of 36

AD9204

The AD9204 is placed in power-down mode either by the SPI
port or by asserting the PDWN pin high. In this state, the ADC
typically dissipates 2.2 mW. During power-down, the output
drivers are placed in a high impedance state. Asserting the
PDWN pin low returns the AD9204 to its normal operating
mode. Note that PDWN is referenced to the digital output
driver supply (DRVDD) and should not exceed that supply
voltage.

Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power­down mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.

When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map section
for more details.

DIGITAL OUTPUTS

The AD9204 output drivers can be configured to interface with

1.8 V to 3.3 V CMOS logic families. Output data can also be
multiplexed onto a single output bus to reduce the total number of
traces required.

The CMOS output drivers are sized to provide sufficient output
current to drive a wide variety of logic families. However, large
drive currents tend to cause current glitches on the supplies that
may affect converter performance.

Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.

The output data format can be selected to be either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Tab l e 12).

As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.

Table 12. SCLK/DFS Mode Selection (External Pin Mode)

Voltage at Pin SCLK/DFS SDIO/DCS

AGND Offset binary (default) DCS disabled
DRVDD Twos complement DCS enabled (default)

Digital Output Enable Function (OEB)

The AD9204 has a flexible three-state ability for the digital
output pins. The three-state mode is enabled using the OEB
pin or through the SPI interface. If the OEB pin is low, the
output data drivers and DCOs are enabled. If the OEB pin is
high, the output data drivers and DCOs are placed in a high
impedance state. This OEB function is not intended for rapid
access to the data bus. Note that OEB is referenced to the digital
output driver supply (DRVDD) and should not exceed that
supply voltage.

When using the SPI interface, the data outputs and DCO of
each channel can be independently three-stated by using the
output disable (OEB) bit (Bit 4) in Register 0x14.

TIMING

The AD9204 provides latched data with a pipeline delay of
nine clock cycles. Data outputs are available one propagation
delay (t

Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9204. These
transients can degrade converter dynamic performance.

The lowest typical conversion rate of the AD9204 is 3 MSPS. At
clock rates below 3 MSPS, dynamic performance can degrade.

Data Clock Output (DCO)

The AD9204 provides two data clock output (DCO) signals
intended for capturing the data in an external register. The CMOS
data outputs are valid on the rising edge of DCO, unless the DCO
clock polarity has been changed via the SPI. See Figure 2 and
Figure 3 for a graphical timing description.

) after the rising edge of the clock signal.

PD

Table 13. Output Data Format

Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode OR

VIN+ − VIN− < −VREF − 0.5 LSB 00 0000 0000 0000 10 0000 0000 0000 1
VIN+ − VIN− = −VREF 00 0000 0000 0000 10 0000 0000 0000 0
VIN+ − VIN− = 0 10 0000 0000 0000 00 0000 0000 0000 0
VIN+ − VIN− = +VREF − 1.0 LSB 11 1111 1111 1111 01 1111 1111 1111 0
VIN+ − VIN− > +VREF − 0.5 LSB 11 1111 1111 1111 01 1111 1111 1111 1

Rev. 0 | Page 26 of 36

AD9204

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

The AD9204 includes a built-in test feature designed to enable
verification of the integrity of each channel, as well as facilitate
board level debugging. A built-in self-test (BIST) feature that
verifies the integrity of the digital datapath of the AD9204 is
included. Various output test options are also provided to place
predictable values on the outputs of the AD9204.

BUILT-IN SELF-TEST (BIST)

The BIST is a thorough test of the digital portion of the selected
AD9204 signal path. Perform the BIST test after a reset to ensure
that the part is in a known state. During BIST, data from an internal
pseudorandom noise (PN) source is driven through the digital
datapath of both channels, starting at the ADC block output.
At the datapath output, CRC logic calculates a signature from
the data. The BIST sequence runs for 512 cycles and then stops.
Once completed, the BIST compares the signature results with a
predetermined value. If the signatures match, the BIST sets Bit 0
of Register 0x24, signifying that the test passed. If the BIST test
failed, Bit 0 of Register 0x24 is cleared. The outputs are connected
during this test so that the PN sequence can be observed as it
runs. Writing 0x05 to Register 0x0E runs the BIST. This enables the
Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence

generator, Bit 2 (BIST INIT) of Register 0x0E. At the completion
of the BIST, Bit 0 of Register 0x24 is automatically cleared. The PN
sequence can be continued from its last value by writing a 0 in
Bit 2 of Register 0x0E. However, if the PN sequence is not reset,
the signature calculation will not equal the predetermined value
at the end of the test. At that point, the user must rely on
verifying the output data.

OUTPUT TEST MODES

The output test options are described in Tab l e 1 7 at Address
0x0D. When an output test mode is enabled, the analog section
of the ADC is disconnected from the digital back-end blocks,
and the test pattern is run through the output formatting block.
Some of the test patterns are subject to output formatting, and
some are not. The PN generators from the PN sequence tests
can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These
tests can be performed with or without an analog signal (if
present, the analog signal is ignored), but they do require an
encode clock. For more information, see the AN-877 Appli­cation Note, Interfacing to High Speed ADCs via SPI.

Rev. 0 | Page 27 of 36

AD9204

CHANNEL/CHIP SYNCHRONIZATION

The AD9204 has a SYNC input that offers the user flexible
synchronization options for synchronizing sample clocks
across multiple ADCs. The input clock divider can be enabled
to synchronize on a single occurrence of the SYNC signal or on
every occurrence. The SYNC input is internally synchronized

to the sample clock; however, to ensure that there is no timing
uncertainty between multiple parts, the SYNC input signal should
be externally synchronized to the input clock signal, meeting the
setup and hold times shown in Tabl e 5. Drive the SYNC input
using a single-ended CMOS-type signal.

Rev. 0 | Page 28 of 36

AD9204

SERIAL PORT INTERFACE (SPI)

The AD9204 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. The SPI
gives the user added flexibility and customization, depending
on the application. Addresses are accessed via the serial port
and can be written to or read from via the port. Memory is
organized into bytes that can be further divided into fields,
which are documented in the Memory Map section. For
detailed operational information, see the AN-877 Applica­tion Note, Interfacing to High Speed ADCs via SPI.

CONFIGURATION USING THE SPI

Three pins define the SPI of this ADC: the SCLK, the SDIO,
and the CSB (see Table 14). The SCLK (a serial clock) is used
to synchronize the read and write data presented from and to
the ADC. The SDIO (serial data input/output) is a dual-purpose
pin that allows data to be sent and read from the internal ADC
memory map registers. The CSB (chip select bar) is an active­low control that enables or disables the read and write cycles.

Table 14. Serial Port Interface Pins

Pin Function

SCLK

Serial Clock. The serial shift clock input is used to
synchronize serial interface reads and writes.

SDIO

Serial Data Input/Output. A dual-purpose pin that
typically serves as an input or an output, depending
on the instruction being sent and the relative position
in the timing frame.

CSB

Chip Select Bar. An active-low control that gates the read
and write cycles.

The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Figure 58 and
Tabl e 5.

Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high, SPI
functions are placed in high impedance mode. This mode turns
on any SPI pin secondary functions.

During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits, as shown in Figure 58.

All data is composed of 8-bit words. The first bit of the first byte
in a multibyte serial data transfer frame indicates whether a read
command or a write command is issued. This allows the serial
data input/output (SDIO) pin to change direction from an input
to an output at the appropriate point in the serial frame.

In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.

Data can be sent in MSB-first mode or in LSB-first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this
and other features, see the AN-877 Application Note, Inter facing
to High Speed ADCs via SPI.

CSB

SCLK

SDIO

DON’T CARE

t

t

DS

t

S

R/W W1 W0 A12 A11 A10 A9 A8 A7

t

DH

HIGH

t

LOW

Figure 58. Serial Port Interface Timing Diagram

t

CLK

Rev. 0 | Page 29 of 36

D5 D4 D3 D2 D1 D0

t

H

DON’T CARE

DON’T CAREDON’T CARE

08122-023

AD9204

HARDWARE INTERFACE

The pins described in Ta b l e 14 constitute the physical interface
between the programming device of the user and the serial port
of the AD9204. The SCLK and CSB pins function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.

The SPI interface is flexible enough to be controlled by
either FPGAs or microcontrollers. One method for SPI
configuration is described in detail in the AN-812 Appli­cation Note, Microcontroller-Based Serial Port Interface
(SPI) Boot Circuit.

The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used
for other devices, it may be necessary to provide buffers between
this bus and the AD9204 to prevent these signals from transi­tioning at the converter inputs during critical sampling periods.

SDIO/DCS and SCLK/DFS serve a dual function when the
SPI interface is not being used. When the pins are strapped to
AVDD or ground during device power-on, they are associated
with a specific function. The Digital Outputs section describes
the strappable functions supported on the AD9204.

CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the
PDWN pin serve as standalone CMOS-compatible control
pins. When the device is powered up, it is assumed that the
user intends to use the pins as static control lines for the duty
cycle stabilizer, output data format, output enable, and power­down feature control. In this mode, connect the CSB chip
select to AVDD, which disables the serial port interface.

Table 15. Mode Selection

External

Pin

SDIO/DCS AVDD (default) Duty cycle stabilizer enabled

SCLK/DFS AVDD Twos complement enabled

OEB AVDD Outputs in high impedance

PDWN AVDD Chip in power-down or standby

Voltage Configuration

AGND Duty cycle stabilizer disabled

AGND (default) Offset binary enabled

AGND (default) Outputs enabled

AGND (default) Normal operation

SPI ACCESSIBLE FEATURES

Tabl e 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD9204 part-specific features are described in
detail in Tabl e 17.

Table 16. Features Accessible Using the SPI

Feature Description

Mode

Clock Allows the user to access the DCS via the SPI
Offset

Tes t I /O

Output Mode Allows the user to set up outputs
Output Phase Allows the user to set the output clock polarity
Output Delay Allows the user to vary the DCO delay
VREF Allows the user to set the reference voltage

Allows the user to set either power-down mode
or standby mode

Allows the user to digitally adjust the
converter offset

Allows the user to set test modes to have known
data on output bits

Rev. 0 | Page 30 of 36

AD9204

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table (see Table 17) has
eight bit locations. The memory map is roughly divided into
four sections: the chip configuration registers (Address 0x00
to Address 0x02); the device index and transfer registers
(Address 0x05 and Address 0xFF); the program registers
(Address 0x08 to Address 0x2E); and the digital feature control
registers (Address 0x100 and Address 0x101).

Table 17 documents the default hexadecimal value for each
hexadecimal address shown. The column with the heading Bit 7
(MSB) is the start of the default hexadecimal value given. For
example, Address 0x18, the VREF register, has a hexadecimal
default value of 0xE0. This means that Bits[7:5] = 1, and the
remaining Bits[4:0] = 0. This setting is the default reference
selection setting. The default value uses a 2.0 V p-p reference.
For more information on this function and others, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI. This
document details the functions controlled by Register 0x00 to
register 0xFF. The remaining registers, Register 0x100 and
Register 0x101, are documented in the Memory Map Register
Descriptions section following Table 17.

OPEN LOCATIONS

All address and bit locations that are not included in the SPI
map are not currently supported for this device. Unused bits of
a valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open, it is omitted from the SPI map (for example, Address 0x13)
and should not be written.

DEFAULT VALUES

After the AD9204 is reset, critical registers are loaded with
default values. The default values for the registers are given
in the memory map register table (see Table 17).

Logic Levels

An explanation of logic level terminology follows:

• “Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

• “Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Transfer Register Map

Address 0x08 to Address 0x18 are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer bit.
This allows these registers to be updated internally and simulta­neously when the transfer bit is set. The internal update takes
place when the transfer bit is set, and then the bit autoclears.

Channel-Specific Registers

Some channel setup functions can be programmed differently
for each channel. In these cases, channel address locations are
internally duplicated for each channel. These registers and bits
are designated in the memory map register table as local. These
local registers and bits can be accessed by setting the appropriate
Channel A (Bit 0) or Channel B (Bit 1) bits in Register 0x05.

If both bits are set, the subsequent write affects the registers of
both channels. In a read cycle, set only Channel A or Channel B
to read one of the two registers. If both bits are set during an
SPI read cycle, the part returns the value for Channel A.
Registers and bits designated as global in the memory map
register table affect the entire part or the channel features for
which independent settings are not allowed between channels.
The settings in Register 0x05 do not affect the global registers
and bits.

Rev. 0 | Page 31 of 36

AD9204

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Tab l e 17 are not currently supported for this device.

Table 17.

Default
Addr
(Hex)

Chip Configuration Registers

0x00 SPI port

0x01 Chip ID (global) 8-bit chip ID bits [7:0]

0x02 Chip grade

Device Index and Transfer Registers

0x05 Channel index Open Open Open Open Open Open ADC B

0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronously

Program Registers (May or May Not Be Indexed by Device Index)

0x08 Modes External

0x09 Clock (global) Open Open Open Open Open Duty

0x0B Clock divide

Register
Name

configuration
(global)

(global)

(global)

Bit 7
(MSB)

0 LSB

AD9204 = 0x25

Open Speed grade ID 6:4

power­down
enable
(local)

Open Clock divider [2:0]

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Soft reset 1 1 Soft

first

20 MSPS = 000
40 MSPS = 001
65 MSPS = 010
80 MSPS = 011

External pin function
0x00 full power-down
0x01 standby
(local)

Open Open 00 = chip run

reset

Open Unique speed

Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4

100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8

LSB first 0 0x18 The nibbles are

default

01 = full power­down
10 = standby
11 = chip wide
digital reset
(local)

Bit 0
(LSB)

ADC A
default

cycle
stabilize

Value

(Hex)

Unique chip ID

0xFF Bits are set to

0x80 Determines

0x00

0x00 The divide ratio is

Comments

mirrored so that
LSB- or MSB-first
mode registers
correctly, regard­less of shift mode

used to diffe­rentiate devices;
read only

grade ID used to
differentiate
devices; read only

determine which
device on-chip
receives the next
write command;
the default is all
devices on-chip

transfers data
from the master
shift register to
the slave

various generic
modes of chip
operation

the value plus 1

Rev. 0 | Page 32 of 36

AD9204

Default
Addr
(Hex)

0x0D Test mode (local) User test mode

0x0E BIST enable Open Open BIST INIT Open BIST

0x10 Offset adjust

0x14 Output mode 00 = 3.3 V CMOS

0x15 OUTPUT_ADJUST 3.3 V DCO

0x16 OUTPUT_PHASE DCO

0x17 OUTPUT_DELAY Enable

0x18 VREF Reserved =11 Internal VREF adjustment [2:0]

0x19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined

0x1A USER_PATT1_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined

0x1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined

Register
Name

(local)

Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Reset PN
(local)
00 = single
01 = alternate
10 = single once
11 = alternate
once

8-bit device offset adjustment [7:0] (local)
Offset adjust in LSBs from +127 to −128 (twos complement format)

10 = 1.8 V CMOS

drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes

output
polarity
0 =
normal
1 =
inverted
(local)

DCO
delay

long gen

Output mux

enable

(interleaved)

1.8 V DCO

drive strength

00 = 1 stripe

01 = 2 stripes

10 = 3 stripes (default)

11 = 4 stripes

Input clock phase adjust [2:0]

Enable

data

delay

000 = 1.0 V p-p

001 = 1.14 V p-p

010 = 1.33 V p-p

011 = 1.60 V p-p

100 = 2.0 V p-p

Reset PN
short gen

Output
disable
(local)

Output test mode [3:0] (local)
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one/zero word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency

Open Output

invert
(local)

3.3 V data
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes

(Value is number of input clock
cycles of phase delay)
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles

DCO/Data delay[2:0]
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns

0xE0 Selects and/or

00 = offset binary
01 = twos
complement
10 = gray code
11 = offset binary
(local)

1.8 V data
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes
(default)
11 = 4 stripes

Bit 0
(LSB)

enable

Value
(Hex) Comments

0x00 When set, the test

data is placed on
the output pins in
place of normal
data

0x00 When Bit 0 is set,

the BIST function
is initiated

0x00 Device offset trim

0x00 Configures the

outputs and the
format of the data

0x22 Determines

CMOS output
drive strength
properties

0x00 On devices that

utilize global
clock divide,
determines which
phase of the
divider output is
used to supply
the output clock;
internal latching
is unaffected

0x00 This sets the fine

output delay of
the output clock
but does not
change internal
timing

adjusts the VREF

pattern, 1 LSB

pattern, 1 MSB

pattern, 2 LSB

Rev. 0 | Page 33 of 36

AD9204

Default
Addr
(Hex)

0x1C USER_PATT2_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined

0x24 MISR_LSB Open Open Open Open Open Open Open B0 0x00 Least significant

0x2A Features Open Open Open Open Open Open Open OR

0x2E Output assign Open Open Open Open Open Open Open

Digital Feature Control

0x100 Sync control

0x101 USR2 Enable

Register
Name

(global)

Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Open Open Open Open Open Clock

OEB

Open Open Open Enable

Pin 47
(local)

GCLK
detect

divider
next sync
only

Run
GCLK

Clock
divider
sync
enable

Open Disable

Bit 0
(LSB)

output
enable

(local)

0 = ADC A
1 = ADC B
(local)

Master
sync
enable

SDIO
pull­down

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.

Sync Control (Register 0x100)

Bits[7:3]—Reserved

Bit 2—Clock Divider Next Sync Only

If the master sync enable bit (Address 0x100, Bit 0) and the
clock divider sync enable bit (Address 0x100, Bit 1) are high,
Bit 2 allows the clock divider to sync to the first sync pulse it
receives and to ignore the rest. The clock divider sync enable
bit (Address 0x100, Bit 1) resets after it syncs.

Bit 1—Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal
is enabled when Bit 1 and Bit 0 are high and the device is
operating in continuous sync mode as long as Bit 2 of the
sync control is low.

USR2 (Register 0x101)

Bit 7—Enable OEB Pin 47

Normally set high, this bit allows Pin 47 to function as the
output enable. If it is set low, it disables Pin 47.

Bit 3—Enable GCLK Detect

Normally set high, this bit enables a circuit that detects encode
rates below about 5 MSPS. When a low encode rate is detected,
an internal oscillator, GCLK, is enabled, ensuring the proper
operation of several circuits. If set low, the detector is disabled.

Bit 2—Run GCLK

This bit enables the GCLK oscillator. For some applications
with encode rates below 10 MSPS, it may be preferable to set
this bit high to supersede the GCLK detector.

Bit 0—Disable SDIO Pull-Down

This bit can be set high to disable the internal 30 kΩ pull-down
on the SDIO pin, which can be used to limit the loading when
many devices are connected to the SPI bus.

Bit 0—Master Sync Enable

Bit 0 must be high to enable any of the sync functions.

Value

(Hex) Comments

pattern, 2 MSB

byte of MISR; read
only

0x01 Disables the OR

Ch A =

0x00

Ch B =

0x01

0x01

0x88 Enables internal

pin for the
indexed channel

Assign an ADC to
an output
channel

oscillator for clock
rates < 5 MHz

Rev. 0 | Page 34 of 36

AD9204

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting design and layout of the AD9204 as a system,
it is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD9204, it is strongly
recommended that two separate supplies be used. Use one 1.8 V
supply for analog (AVDD); use a separate 1.8 V to 3.3 V supply for
the digital output supply (DRVDD). If a common 1.8 V AVDD
and DRVDD supply must be used, the AVDD and DRVDD
domains must be isolated with a ferrite bead or filter choke
and separate decoupling capacitors. Several different decoupling
capacitors can be used to cover both high and low frequencies.
Locate these capacitors close to the point of entry at the PCB
level and close to the pins of the part, with minimal trace length.

A single PCB ground plane should be sufficient when using the
AD9204. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.

Exposed Paddle Thermal Heat Sink Recommendations

The exposed paddle (Pin 0) is the only ground connection
for the AD9204 and, therefore, it must be connected to analog
ground (AGND) on the customer’s PCB. To achieve the best
electrical and thermal performance, mate an exposed (no
solder mask) continuous copper plane on the PCB to the
AD9204 exposed paddle, Pin 0.

The copper plane should have several vias to achieve the
lowest possible resistive thermal path for heat dissipation to
flow through the bottom of the PCB. Fill or plug these vias
with nonconductive epoxy.

To maximize the coverage and adhesion between the ADC and
the PCB, a silkscreen should be overlaid to partition the continuous
plane on the PCB into several uniform sections. This provides
several tie points between the ADC and the PCB during the reflow
process. Using one continuous plane with no partitions guarantees
only one tie point between the ADC and the PCB. For detailed
information about packaging and PCB layout of chip scale
packages, see the AN-772 Application Note, A Design and

Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP), at www.analog.com.

VCM

The VCM pin should be decoupled to ground with a 0.1 F
capacitor, as shown in Figure 42.

RBIAS

The AD9204 requires that a 10 kΩ resistor be placed between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and should have at least a 1% tolerance.

Reference Decoupling

Externally decouple the VREF pin to ground with a low ESR,

1.0 F capacitor in parallel with a low ESR, 0.1 F ceramic
capacitor.

SPI Port

The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9204 to keep these signals from transitioning at the converter
inputs during critical sampling periods.

Rev. 0 | Page 35 of 36

AD9204

OUTLINE DIMENSIONS

49

48

0.60 MAX

EXPOSED PAD

(BOTTOM VIEW)

PIN 1

64

INDICATOR

1

6.35

6.20 SQ

6.05

PIN 1

INDICATOR

9.00

BSC SQ

TOP VIE W

8.75

BSC SQ

0.60

MAX

0.50

BSC

1.00

0.85

0.80

SEATING

PLANE

12° MAX

0.50

0.40

0.30

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

0.05 MAX

0.02 NOM

0.20 REF

33

32

7.50
REF

16

17

FOR PROPER CO NNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DESCRI PTIONS
SECTION O F THIS DAT A SHEET.

0.25 MIN

091707-C

Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad (CP-64-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9204BCPZ-80
AD9204BCPZRL7-80
AD9204BCPZ-65
AD9204BCPZRL7-65
AD9204BCPZ-40
AD9204BCPZRL7-40
AD9204BCPZ-20
AD9204BCPZRL7-20
AD9204-80EBZ1 Evaluation Board
AD9204-65EBZ1 Evaluation Board
AD9204-40EBZ1 Evaluation Board
AD9204-20EBZ1 Evaluation Board

1

Z = RoHS Compliant Part.

2

The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND.

1, 2

–40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4

1, 2

–40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4

1, 2

–40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4

1, 2

–40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4

1, 2

–40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4

1, 2

–40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4

1, 2

–40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4

1, 2

–40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4

©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08122-0-7/09(0)

Rev. 0 | Page 36 of 36