Datasheet AD9059BRS, AD9059-PCB Datasheet (Analog Devices)

a

14

13

12

11

10

17
16
15

19
18

20

28
27
26
25
24
23
22
21

9

8

1
2
3
4

7

6

5

TOP VIEW

(Not to Scale)

AD9059

AINA

V

D

ENCODE

GND

AINB

VREF

PWRDN

V

D

D7B (MSB)

V

DD

GND

GND

V

DD

D7A (MSB)

D6A
D5A
D4A

D4B

D5B

D6B

D3A
D2A
D1A

D0A (LSB)

D3B

D0B (LSB)

D1B

D2B

Dual 8-Bit, 60 MSPS A/D Converter

AD9059

FEATURES
Dual 8-Bit ADCs on a Single Chip
Low Power: 400 mW Typical
On-Chip +2.5 V Reference and T/Hs
1 V p-p Analog Input Range
Single +5 V Supply Operation
+5 V or +3 V Logic Interface
120 MHz Analog Bandwidth
Power-Down Mode: < 12 mW

APPLICATIONS
Digital Communications (QAM Demodulators)
RGB & YC/Composite Video Processing
Digital Data Storage Read Channels
Medical Imaging
Digital Instrumentation

PRODUCT DESCRIPTION

The AD9059 is a dual 8-bit monolithic analog-to-digital con­verter optimized for low cost, low power, small size, and ease of
use. With a 60 MSPS encode rate capability and full-power
analog bandwidth of 120 MHz typical, the component is ideal
for applications requiring multiple ADCs with excellent dy­namic performance.

To minimize system cost and power dissipation, the AD9059
includes an internal +2.5 V reference and dual track-and-hold
circuits. The ADC requires only a +5 V power supply and an
encode clock. No external reference or driver components are
required for many applications.

The AD9059’s single encode input is TTL/CMOS compatible
and simultaneously controls both internal ADC channels. The
parallel 8-bit digital outputs can be operated from +5 V or +3 V
supplies. A power-down function may be exercised to bring to­tal consumption to < 12 mW when ADC data is not required
for lengthy periods of time. In power-down mode the digital
outputs are driven to a high impedance state.

Fabricated on an advanced BiCMOS process, the AD9059
is available in a space saving 28-lead surface mount plastic
package (28 SSOP) and is specified over the industrial
(–40°C to +85°C) temperature range.

Customers desiring single channel digitization may consider the
AD9057, a single 8-bit, 60 MSPS monolithic based on the
AD9059 ADC core. The AD9057 is available in a 20-lead sur­face mount plastic package (20 SSOP) and is specified over the
industrial temperature range.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

AINA

VREF

AINB

V

D

T/H

T/H

PWRDN

AD9059

+2.5V

GND

ADC

ADC

V

DD

8

ENCODE

8

D7A–D0A

D7B–D0B

A

B

PIN CONFIGURATION

© Analog Devices, Inc., 1996

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

AD9059–SPECIFICA TIONS

ELECTRICAL CHARACTERISTICS

(VD = +5 V, VDD = +3 V; external reference; ENCODE = 60 MSPS unless otherwise noted)

AD9059BRS

Parameter Temp Test Level Min Typ Max Units

RESOLUTION 8 Bits
DC ACCURACY

Differential Nonlinearity +25°C I 0.75 2.0 LSB

Full VI 2.5 LSB

Integral Nonlinearity +25°C I 0.75 2.0 LSB

Full VI 2.5 LSB
No Missing Codes Full VI GUARANTEED
Gain Error

Gain Tempco

1

1

+25°C I –6 –2.5 +6 % FS

Full VI –8 +8 % FS

Full V ±70 ppm/°C

ANALOG INPUT

Input Voltage Range (Centered at +2.5 V) +25°C V 1.0 V p-p
Input Offset Voltage +25°C I –15 0 +15 mV

Full VI –25 +25 mV
Input Resistance +25°C V 150 kΩ
Input Capacitance +25°CV 2 pF
Input Bias Current +25°CI 616µA
Analog Bandwidth +25°C V 120 MHz

CHANNEL MATCHING (A to B)

Gain Delta +25°CV ±1% FS
Input Offset Voltage Delta +25°CV ±4mV

BANDGAP REFERENCE

Output Voltage Full VI 2.4 2.5 2.6 V
Temperature Coefficient Full V ±10 ppm/°C

SWITCHING PERFORMANCE

Maximum Conversion Rate Full VI 60 MSPS
Minimum Conversion Rate Full IV 5 MSPS
Aperture Delay (t
Aperture Uncertainty (Jitter) +25°C V 5 ps, rms
Output Valid Time (t
Output Propagation Delay (tPD)

DYNAMIC PERFORMANCE

) +25°C V 2.7 ns

A

2

)

V

2

3

Full IV 4.0 6.6 ns

Full IV 9.5 14.2 ns

Transient Response +25°CV 9 ns
Overvoltage Recovery Time +25°CV 9 ns
Signal-to-Noise Ratio (SINAD) (with Harmonics)

f

= 10.3 MHz +25°C I 40 44.5 dB

IN

f

= 76 MHz +25°C V 43.5 dB

IN

Effective Number of Bits

f

= 10.3 MHz +25°C I 6.35 7.1 Bits

IN

f

= 76 MHz +25°C V 6.9 Bits

IN

Signal-to-Noise Ratio (SNR) (Without Harmonics)

f

= 10.3 MHz +25°C I 42 46 dB

IN

f

= 76 MHz +25°CV 45 dB

IN

2nd Harmonic Distortion

f

= 10.3 MHz +25°C I –50 –62 dBc

IN

f

= 76 MHz +25°C V –54 dBc

IN

3rd Harmonic Distortion

f

= 10.3 MHz +25°C I –46 –60 dBc

IN

f

= 76 MHz +25°C V –54 dBc

IN

Two-Tone Intermodulation Distortion (IMD) +25°C V –52 dBc
Channel Crosstalk Rejection +25°C V –50 dBc
Differential Phase +25°C V 0.8 Degrees
Differential Gain +25°C V 1.0 %

–2–

REV. 0

AD9059

WARNING!

ESD SENSITIVE DEVICE

AD9059BRS

Parameter Temp Test Level Min Typ Max Units

DIGITAL INPUTS

Logic “1” Voltage Full VI 2.0 V
Logic “0” Voltage Full VI 0.8 V
Logic “1” Current Full VI ±1 µA
Logic “0” Current Full VI ±1 µA
Input Capacitance +25°C V 4.5 pF
Encode Pulse Width High (t
Encode Pulse Width Low (tEL) +25°C IV 6.7 166 ns

DIGITAL OUTPUTS

Logic “1” Voltage (V
Logic “1” Voltage (V
Logic “0” Voltage (V

DD
DD
DD

Output Coding Offset Binary Code

POWER SUPPLY

V

Supply Current (VD = +5 V) Full VI 72 92 mA

D

V

Supply Current (VDD = +3 V)

DD

Power Dissipation

5, 6

Power-Down Dissipation Full VI 6 12 mW
Power Supply Rejection Ratio (PSRR) +25°C I 15 mV/V

NOTES

1

Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference).

2

tV and tPD are measured from the 1.5 V level of the ENCODE to the 10%/90% levels of the digital output swing. The digital output load during test is not to exceed
an ac load of 10 pF or a dc current of ±40 µA.

3

SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 1.0 V full-scale input range.

4

Digital supply current based on VDD = +3 V output drive with <10 pF loading under dynamic test conditions.

5

Power dissipation is based on 60 MSPS encode and 10.3 MHz analog input dynamic test conditions (VD = +5 V ± 5%, VDD = +3 V ± 5%).

6

Typical thermal impedance for the RS style (SSOP) 28-pin package: θJC = 39°C/W, θCA = 70°C/W, θJA = 109°C/W.

Specifications subject to change without notice.

) +25°C IV 6.7 166 ns

EH

= +3 V) Full VI 2.95 V
= +5 V) Full IV 4.95 V
= +3 V or +5 V) Full VI 0.05 V

4

Full VI 13 15 mA

Full VI 400 505 mW

EXPLANATION OF TEST LEVELS

Test Level

I – 100% production tested.
II – 100% production tested at +25°C and sample tested at

specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characteriza-

tion testing.
V – Parameter is a typical value only.

VI – 100% production tested at +25°C; guaranteed by

design and characterization testing for industrial tem-

perature range.

ABSOLUTE MAXIMUM RATINGS*

VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V

Analog Inputs . . . . . . . . . . . . . . . . . . . . . –0.5 V to V

Digital Inputs . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V

V

Input . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V

REF

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Operating Temperature . . . . . . . . . . . . . . . . .–55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods may affect device reliability.

ORDERING GUIDE

Model Temperature Range Package Option

AD9059BRS –40°C to +85°C RS-28
AD9059/PCB +25°C Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9059 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

+ 0.5 V

D

+ 0.5 V

D

REV. 0

–3–

AD9059

AIN

ENCODE

DIGITAL

OUTPUTS

N N + 3 N + 5

N + 1

t

A

tEHt

EL

t

V

N – 3 N – 2 N – 1 N N + 1 N + 2

t

PD

t

APERTURE DELAY

A

t

PULSE WIDTH HIGH

EH

t

PULSE WIDTH LOW

EL

t

OUTPUT VALID TIME

V

t

OUTPUT PROP DELAY

PD

N + 2

N + 4

MIN TYP

2.7ns

6.7ns

6.7ns

4.0ns

6.6ns

9.5ns

MAX

166ns
166ns

14.2ns

Figure 1. Timing Diagram

PIN CONFIGURATION

AINA

VREF

PWRDN

GND

V

D7A (MSB)

D6A
D5A
D4A
D3A
D2A
D1A

D0A (LSB)

V

D

DD

1
2
3
4
5

AD9059

6

TOP VIEW

(Not to Scale)

7
8

9
10
11
12
13
14

28

AINB

27

GND

26

ENCODE

25

V

24

GND

23

V

22

D7B (MSB)

21

D6B
D5B

20
19

D4B

18

D3B

17

D2B

16

D1B

15

D0B (LSB)

D

DD

PIN DESCRIPTIONS

Pin No. Name Function

1, 28 AINA, AINB Analog Inputs for ADC A and B.
2 VREF Internal Voltage Reference (+2.5 V

Typical); Bypass with 0.1 µF to
Ground or Overdrive with External
Voltage Reference.

3 PWRDN Power-Down Function Select;

Logic HIGH for Power-Down
Mode (Digital Outputs Go to High­Impedance State).

4, 25 V

D

Analog +5 V Power Supply.
5, 24, 27 GND Ground.
6, 23 V

DD

Digital Output Power Supply.

Nominally +3 V to +5 V.
7–14 D7A–D0A Digital Outputs of ADCA.
22–15 D7B–D0B Digital Outputs of ADCB.
26 ENCODE Encode Clock for ADCs A and B

(ADCs Sample Simultaneously On

the Rising Edge of ENCODE).

Table I. Digital Coding (VREF = +2.5 V)

Analog Input Voltage Level Digital Output

3.0 V Positive Full Scale 1111 1111

2.502 V Midscale + 1/2 LSB 1000 0000

2.498 V Midscale – 1/2 LSB 0111 1111

2.0 V Negative Full Scale 0000 0000

–4–

REV. 0

0

ANALOG INPUT FREQUENCY – MHz

dB

–30

–70

0 16020 40 60 80 100 120 140

–35

–50

–55

–60

–65

–40

–45

2ND HARMONIC

3RD HARMONIC

ENCODE = 60MSPS
AIN = –0.5dBFS

FREQUENCY – MHz

dB

0

–10

–90

03010 20

–50

–60

–70

–80

–30

–40

–20

ENCODE = 60MSPS
F1 IN = 9.5MHz @ –7.0dBFS
F2 IN = 9.9MHz @ –7.0dBFS
2F1 - F2 = –52.0dBc
2F2 - F1 = –53.0dBc

ENCODE RATE – MSPS

dB

54

24

6

5 102030405060708090

48

30

18

12

42

36

AIN = 10.3MHz, –0.5dBFS

SNR

SINAD

–10

–20

–30

–40

dB

–50

–60

–70

–80

–90

030

ENCODE = 60MSPS
ANALOG IN = 10.3MHz, –0.5dBFS
SINAD = 43.9dB
ENOB = 7.0 BITS
SNR = 45.1dB

FREQUENCY – MHz

AD9059

Figure 2. FFT Spectral Plot 60 MSPS, 10.3 MHz

0

ENCODE = 60MSPS

–10

ANALOG IN = 76MHz, –0.5dBFS
SINAD = 43.0dB

–20

ENOB = 6.85 BITS
SNR = 44.1dB

–30

–40

dB

–50

–60

–70

–80

–90

030

FREQUENCY – MHz

Figure 5. Harmonic Distortion vs. AIN Frequency

Figure 3. Spectral Plot 60 MSPS, 76 MHz

46

44

42

40

SINAD

SNR

Figure 6. Two-Tone IMD

38

ENCODE = 60MSPS

dB

AIN = –0.5dBFS

36

34

32

REV. 0

30

0 16020 40 60 80 100 120 140

Figure 4. SINAD/SNR vs. AIN Frequency

ANALOG INPUT FREQUENCY – MHz

Figure 7. SINAD/SNR vs. Encode Rate

–5–

AD9059

TEMPERATURE – °C

10

t

PD

– ns

9.5

–45 9002570

8.0

6.5

6.0

9.0

8.5

7.0

7.5

VDD = +5V

VDD = +3V

11

12

dB

ENCODE HIGH PULSE WIDTH – ns

46

45.5

40.5

5.8 10.9

44.5
44

43.5
43

45

41

41.5

42

42.5

6.7 7.5 8.35 9.2 10

SNR

ENCODE = 60MSPS
AIN = 10.3MHz, –0.5dBFS

SINAD

600

550

500

AIN = 10.3MHz, –0.5dBFS

450

400

POWER – mW

350

300

250

5 102030405060708090

VDD = +5V

VDD = +3V

ENCODE RATE – MSPS

Figure 8. Power Dissipation vs. Encode Rate

45.5

45.0

44.5

44.0

43.5

dB

43.0
ENCODE = 60MSPS

42.5

AIN = 10.3MHz, –0.5dBFS

42.0

41.5

–45 9002570

TEMPERATURE – °C

SNR

SINAD

Figure 11. tPD vs. Temperature/Supply (+3 V/+5 V)

Figure 9. SINAD/SNR vs. Temperature

0

–0.2

–0.4

–0.6

–0.8

–1.0

GAIN ERROR – %

–1.2

–1.4

–1.6

–1.8

–45 9002570

TEMPERATURE – °C

Figure 10. ADC Gain vs. Temperature (With External
+2.5 V Reference)

–6–

Figure 12. SINAD/SNR vs. Encode Pulse Width

0

–1

–2
–3

–4
–5

–6

ADC GAIN – dB

ENCODE = 60MSPS

–7

AIN = –0..5dBFS

–8
–9

–10

1

25

ANALOG FREQUENCY – MHz

20 50

100

200

50010

Figure 13. ADC Frequency Response

REV. 0

AD9059

THEORY OF OPERATION

The AD9059 combines Analog Devices’ proprietary MagAmp
gray code conversion circuitry with flash converter technology
to provide dual high performance 8-bit ADCs in a single low
cost monolithic device. The design architecture ensures low
power, high speed, and 8-bit accuracy.

The AD9059 provides two linked ADC channels that are
clocked from a single ENCODE input (refer to block diagram).
The two ADC channels simultaneously sample the analog in­puts (AINA and AINB) and provide non-interleaved parallel
digital outputs (D0A–D7A and D0B–D7B). The voltage refer­ence (VREF) is internally connected to both ADCs so channel
gains and offsets will track if external reference control is
desired.

The analog input signal is buffered at the input of each ADC
channel and applied to a high speed track-and-hold. The T/H
circuit holds the analog input value during the conversion pro­cess (beginning with the rising edge of the ENCODE com­mand). The T/H’s output signal passes through the gray code
and flash conversion stages to generate coarse and fine digital
representations of the held analog input level. Decode logic
combines the multistage data and aligns the 8-bit word for
strobed outputs on the rising edge of the ENCODE command.
The MagAmp/Flash architecture of the AD9059 results in three
pipeline delays for the output data.

USING THE AD9059
Analog Inputs

The AD9059 provides independent single-ended high imped­ance (150 kΩ) analog inputs for the dual ADCs. Each input
requires a dc bias current of 6 µA (typical) centered near +2.5 V
(±10%). The dc bias may be provided by the user or may be
derived from the ADC’s internal voltage reference. Figure 14
shows a low cost dc bias implementation allowing the user to
capacitively couple ac signals directly into the ADC without ad­ditional active circuitry. For best dynamic performance the
VREF pin should be decoupled to ground with a 0.1 µF capaci-
tor (to minimize modulation of the reference voltage), and the
bias resistor should approximately 1 kΩ.

Figure 15 shows typical connections for high performance dc bi­asing using the ADC’s internal voltage reference. All compo­nents may be powered from a single +5 V supply (example
analog input signals are referenced to ground).

Voltage Reference

A stable and accurate +2.5 V voltage reference is built into the
AD9059 (VREF). The reference output is used to set the ADC
gain/offset and can provide dc bias for the analog input signals.
The internal reference is tied to the ADC circuitry through a
800 Ω internal impedance and is capable of providing 300 µA
external drive current (for dc biasing the analog input or other
user circuitry).

Some applications may require greater accuracy, improved tem­perature performance, or gain adjustments which cannot be ob­tained using the internal reference. An external voltage may be

applied to the VREF pin to overdrive the internal voltage refer­ence for gain adjustment of up to ±10% (the VREF pin is inter­nally tied directly to the ADC circuitry). ADC gain and offset
will vary simultaneously with external reference adjustment with
a 1:1 ratio (a 2% or 50 mV adjustment to the +2.5 V reference
varies ADC gain by 2% and ADC offset by 50 mV).

Theoretical input voltage range versus reference input voltage
may be calculated from the following equations:

V

(p-p) = VREF/2.5

RANGE

V

MIDSCALE

V

TOP-OF-RANGE

V

BOTTOM-OF-RANGE

= VREF

= VREF + V

= VREF – V

RANGE

/2

RANGE

/2

The external reference should have a 1 mA minimum sink/
source current capability to ensure complete overdrive of the
internal voltage reference.

Digital Logic (+5 V/+3 V Systems)

The digital inputs and outputs of the AD9059 can easily be
configured to interface directly with +3 V or +5 V logic systems.
The encode and power-down (PWRDN) inputs are CMOS
stages with TTL thresholds of 1.5 V, making the inputs compat­ible with TTL, +5 V CMOS, and +3 V CMOS logic families.
As with all high speed data converters, the encode signal should
be clean and jitter free to prevent degradation of ADC dynamic
performance.

The AD9059’s digital outputs will also interface directly with
+5 V or +3 V CMOS logic systems. The voltage supply pins
(V

) for these CMOS stages are isolated from the analog V

DD

D

voltage supply. By varying the voltage on these supply pins the
digital output HIGH levels will change for +5 V or +3 V sys­tems. The V
die. Care should be taken to isolate the V

pins are internally connected on the AD9059

DD

supply voltages

DD

from the +5 V analog supply to minimize noise coupling into
the ADCs.

The AD9059 provides high impedance digital output operation
when the ADC is driven into power-down mode (PWRDN,
logic HIGH). A 200 ns (minimum) power-down time should
be provided before a high impedance characteristic is required.
A 200 ns power-up period should be provided to ensure accu­rate ADC output data after reactivation (valid output data is
available three clock cycles after the 200 ns delay).

Timing

The AD9059 is guaranteed to operate with conversion rates
from 5 MSPS to 60 MSPS. At 60 MSPS the ADC is designed
to operate with an encode duty cycle of 50%, but performance
is insensitive to moderate variations. Pulse width variations of
up to ±10% (allowing the encode signal to meet the minimum/
maximum HIGH/LOW specifications) will cause no degrada­tion in ADC performance (refer to Figure 1 Timing Diagram).

Due to the linked ENCODE architecture of the ADCs, the
AD9059 cannot be operated in a two-channel ping-pong mode.

REV. 0

–7–

AD9059

Power Dissipation

The power dissipation of the AD9059 is specified to reflect a
typical application setup under the following conditions: en­code is 60 MSPS, analog input is –0.5 dBFS at 10.3 MHz, V

D

is +5 V, VDD is +3 V, and digital outputs are loaded with 7 pF
typical (10 pF maximum). The actual dissipation will vary as
these conditions are modified in user applications. Figure 8
shows typical power consumption for the AD9059 versus ADC
encode frequency and V

VIN

A

(1V p-p)

EXTERNAL V

REF

(OPTIONAL)

VIN

(1V p-p)

B

supply voltage.

DD

0.1µF

0.1µF

0.1µF

1kΩ

1kΩ

+5V

1

AINA

AD9059

3

V

REF

28

AINB

Figure 14. Capacitively Coupled AD9059

A power-down function allows users to reduce power dissipa­tion when ADC data is not required. A TTL/CMOS HIGH
signal (PWRDN) shuts down portions of the dual ADC and
brings total power dissipation to less than 10 mW. The internal
bandgap voltage reference remains active during power-down
mode to minimize ADC reactivation time. If the power-down
function is not desired, Pin 3 should be tied to ground. Both
ADC channels are controlled simultaneously by the PWRDN
pin; they cannot be shut down or turned on independently.

Applications

The wide analog bandwidth of the AD9059 makes it attractive
for a variety of high performance receiver and encoder applica­tions. Figure 16 shows the dual ADC in a typical low cost I & Q
demodulator implementation for cable, satellite, or wireless
LAN modem receivers. The excellent dynamic performance of
the ADC at higher analog input frequencies and encode rates
empowers users to employ direct IF sampling techniques (refer
to Figure 3, Spectral Plot). IF sampling eliminates or simplifies
analog mixer and filter stages to reduce total system cost and
power.

VIN

VIN

(–0.5V TO +0.5V)

1kΩ

10kΩ

+5V

AD8041

10kΩ

0.1µF

+5V

AD8041

1kΩ

1kΩ

A

1kΩ

B

1

3

28

AINA

V

REF

AD9059

AINB

+5V

Figure 15. DC Coupled AD9059 (VIN Inverted)

AD9059

ADC

ADC

VCO

IF IN

90

VCO

BPF

°

BPF

Figure 16. I and Q Digital Receiver

The high sampling rate and analog bandwidth of the AD9059
are ideal for computer RGB video digitizer applications. With a
full-power analog bandwidth of 2× the maximum sampling rate,
the ADC provides sufficient pixel-to-pixel transient settling
time to ensure accurate 60 MSPS video digitization. Figure 17
shows a typical RGB video digitizer implementation for the
AD9059.

AD9059

RED

GREEN

H-SYNC

BLUE

ADC

ADC

PLL

ADC

ADC

AD9059

8

8

PIXEL CLOCK

8

–8–

Figure 17. RGB Video Encoder

REV. 0

AD9059

+V

+V

D

+V

D

DD

+3V TO +5V

+V

D

3kΩ

800Ω

+2.5V

Voltage Reference

V

2.5kΩ

REF

ENCODE

PWRDN

Digital Inputs

Figure 18. Equivalent Circuits

Evaluation Board

The AD9059/PCB evaluation board provides an easy-to-use
analog/digital interface for the dual 8-bit, 60 MSPS ADC. The
board includes typical hardware configurations for a variety of
high speed digitization evaluations. On-board components in­clude the AD9059 (in the 28-pin SSOP package), optional ana­log input buffer amplifiers, digital output latches, board timing
drivers, and configurable jumpers for ac coupling, dc coupling,
and power-down function testing. The board is configured at
shipment for dc coupling using the AD9059’s internal reference.

For dc coupled analog input applications, amplifiers U3 and U4
are configured to operate as unity gain inverters with adjustable
offset for the analog input signals. For full-scale ADC drive
each analog input signal should be 1 V p-p into 50 Ω referenced
to ground. Each amplifier offsets its analog signal by +VREF
(+2.5 V typical) to center the voltage for proper ADC input
drive. For dc coupled operation, connect E7 to E9 (analog in­put A to R11), E14 to E13 (amplifier output to analog input A
of AD9059), E4 to E5 (analog input B to R10), and E11 to E10
(amplifier output to analog input B of AD9059) using the board
jumper connectors.

For ac coupled analog input applications, amplifiers U3 and U4
are removed from the analog signal paths. The analog signals
are coupled through capacitors C11 and C12, each terminated
to the VREF voltage through separate 1 kΩ resistors (providing
bias current for the AD9059 analog inputs, AINA and AINB).

D0–D7

Digital Outputs

AIN

500Ω

Analog Inputs

V

REF

Analog input signals to the board should be 1 V p-p into 50 Ω
for full-scale ADC drive. For ac coupled operation, connect E7
to E8 (analog input A to C12 feedthrough capacitor), E13 to
E15 (C12 to R15 termination resistor for channel A), E4 to E6
(analog input B to C11 feedthrough capacitor), and E10 to E12
(C11 to R14 termination resistor for channel B) using the board
jumper connectors.

The on-board reference voltage may be used to drive the ADC
or an external reference may be applied. The standard configu­ration employs the internal voltage reference without any exter­nal connection requirements. An external voltage reference may
be applied at board connector input REF to overdrive the lim­ited current output of the AD9059’s internal voltage reference.
The external voltage reference should be +2.5 V typical.

The power-down function of the AD9059 can be exercised
through a board jumper connection. Connect E2 to E1 (+5 V
to PWRDN) for power-down mode operation. For normal op­eration, connect E3 to E1 (ground to PWRDN).

The encode signal source should be TTL/CMOS compatible
and capable of driving a 50 Ω termination. The digital outputs
of the AD9059 are buffered through latches on the evaluation
board (U5 and U6) and are available for the user at connector
Pins 30–37 and Pins 22–29. Latch timing is derived from the
ADC ENCODE clock and a digital clocking signal is provided
for the board user at connector Pins 2 and 21.

REV. 0

–9–

AD9059

ANALOG IN–A

BNC

J5

E7

R13
50Ω

ANALOG IN–B

BNC

J4

E4

R12
50Ω

+5V

DECOUPLING CAPS

J12, GND

J9, V

U1

AD9059RS

AINA
REF
PWRDN
V

D

GND
V

DD

D7A
D6A
D5A
D4A
D3A
D2A
D1A
D0A

R15
50Ω

DD

AINB

GND
ENC

GND

V
D7B
D6B
D5B
D4B
D3B
D2B
D1B
D0B

V

DD

0.1µF

D

C9

28
27
26
25

+5V

24
23
22
21
20
19
18
17
16
15

74AC00

1
2

74AC00

4

5

74AC00

12
13

D7B
D6B
D5B
D4B
D3B
D2B
D1B
D0B

U7

U7

U7

P2

C37DRPF

1
2

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7

3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

21
22
23
24
25
26
27
28
29

30
31
32
33
34
35
36
37

U5

74ACQ574

9

D0B

8

D1B

7

D2B

6

D3B

5

D4B

4

D5B

3

D6B

2

D7B

74ACQ574

9

D7A

8

D6A

7

D5A

6

D4A

5

D3A

4

D2A

3

D1A

2

D0A

3

6

11

12

8D
7D
6D
5D
4D
3D
2D
1D

CK

DB0

8Q

13

DB1

7Q

14

DB2

6Q

15

DB3

5Q

16

DB4

4Q

17

3Q

DB5

18

2Q

DB6

19

1Q

DB7

OE

111

U6

12

8D
7D
6D
5D
4D
3D
2D
1D

CK

DA7

8Q

13

DA6

7Q

14

DA5

6Q

15

DA4

5Q

16

DA3

4Q

17

3Q

DA2

18

2Q

DA1

19

1Q

DA0

OE

111

U4

D

AD8041Q

1

NC

2
3
4

–V

1kΩ

R9
10kΩ

1
2
3
4

C4

0.1µF

DIS

+V

S

NC

S

R7

R8

10kΩ

R8

1kΩ

U3

AD8041Q

NC

DIS

+V

–V

S

C6

0.1µF

NC

C5

0.1µF

S

8
7
6
5

R14

1kΩ

+5V

8
7
6
5

+5V

C7

0.1µF

E8

E9

R11
1kΩ

R10
1kΩ

E5

E6

J11, V

C3

0.1µF

R15
1kΩ

R5

10Ω

C17
10µF

+5V

C13

0.1µF

C12

0.1µF

J1, REF

E2

E3

R4

10Ω

C14

0.1µF

E14

E15

C10

0.1µF

E12

E11

C15
10µF

E13

E1

PWRDN

C11

0.1µF

0.1µF

E10

C8

+5V

D7A
D6A
D5A
D4A
D3A
D2A
D1A
D0A

ENCODE

C16
10µF

10
11
12
13
14

1
2
3
4
5
6
7
8
9

BNC

J10

Figure 19. AD9059 Dual Evaluation Board Schematic

–10–

REV. 0

AD9059

Figure 20. Evaluation Board Layout (Top)

REV. 0

Figure 21. Evaluation Board Layout (Bottom)

–11–

AD9059

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead SSOP

(RS-28)

0.407 (10.34)

0.397 (10.08)

0.311 (7.9)

0.301 (7.64)

0.078 (1.98)

0.068 (1.73)

0.008 (0.203)

0.002 (0.050)

28 15

PIN 1

0.015 (0.38)

0.0256
(0.65)

BSC

0.010 (0.25)

SEATING

PLANE

0.212 (5.38)

141

0.07 (1.79)

0.066 (1.67)

0.009 (0.229)

0.005 (0.127)

0.205 (5.21)

8°
0°

C2160–10–7/96

0.03 (0.762)

0.022 (0.558)

–12–

PRINTED IN U.S.A.

REV. 0