Datasheet AD9058ATJ-883, AD9058ATD-883, AD9058AKJ, AD9058AKD, AD9058AJJ Datasheet (Analog Devices)

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

a

AD9058

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

Dual 8-Bit 50 MSPS

A/D Converter

FUNCTIONAL BLOCK DIAGRAM

8

B

–V

REF

A

IN

ENCODE

+V

REF

8-BIT

ANALOG-

TO-DIGITAL

CONVERTER

8-BIT

ANALOG-

TO-DIGITAL

CONVERTER

+V

REF

ENCODE

A

IN

–V

REF

8

A

AD9058

2V

REF

QUADRATURE RECEIVER

8

Q

LO

8

I

AD9058

G

G

90ⴗ

RF

GENERAL DESCRIPTION

The AD9058 combines two independent high-performance
8-bit analog-to-digital converters (ADCs) on a single monolithic
IC. Combined with an optional on-board voltage reference,
the AD9058 provides a cost effective alternative for systems
requiring two or more ADCs.

Dynamic performance (SNR, ENOB) is optimized to provide
up to 50 MSPS conversion rates. The unique architecture
results in low input capacitance while maintaining high per­formance and low power (<0.5 watt/channel). Digital inputs
and outputs are TTL compatible.

Performance has been optimized for an analog input of 2 V p-p
(± 1 V; 0 V to 2 V). Using the onboard 2 V voltage reference,
the AD9058 can be set up for unipolar positive operation
(0 V to 2 V). This internal voltage reference can drive
both ADCs.

Commercial (0°C to 70°C) and military (–55°C to +125°C)
temperature range parts are available. Parts are supplied in
hermetic 48-lead DIP and 44-lead “J” lead packages.

FEATURES
Two Matched ADCs on Single Chip
50 MSPS Conversion Speed
On-Board Voltage Reference
Low Power (<1W)
Low Input Capacitance (10 pF)
65 V Power Supplies
Flexible Input Range

APPLICATIONS
Quadrature Demodulation for Communications
Digital Oscilloscopes
Electronic Warfare
Radar

REV. C

–2–

AD9058–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

[ⴞVS = ⴞ5 V; V

REF

= 2 V (internal); ENCODE = 40 MSPS; AIN = 0 V to +2 V; –V

REF

=

GROUND, unless otherwise noted.]2 All specifications apply to either of the two ADCs.

Test AD9058AJD/AJJ AD9058AKD/AKJ

Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Unit

RESOLUTION 8 8 Bits

DC ACCURACY

Differential Nonlinearity 25°C I 0.25 0.65 0.25 0.5 LSB

Full VI 0.8 0.7 LSB

Integral Nonlinearity 25°C I 0.5 1.3 0.5 1.0 LSB

Full VI 1.4 1.25 LSB

No Missing Codes Full VI Guaranteed Guaranteed

ANALOG INPUT

Input Bias Current 25°C I 75 170 75 170 µA

Full VI 340 340 µA
Input Resistance 25°C I 12 28 12 28 kΩ
Input Capacitance 25°CIV 1015 1015 pF
Analog Bandwidth 25°C V 175 175 MHz

REFERENCE INPUT

Reference Ladder Resistance 25°C I 120 170 220 120 170 220 Ω

Full VI 80 270 80 270 Ω
Ladder Tempco Full V 0.45 0.45 Ω/°C
Reference Ladder Offset 25°CI 8 16 8 16 mV

(Top) Full VI 24 24 mV

Reference Ladder Offset 25°CI 8 23 8 23 mV

(Bottom) Full VI 33 33 mV

Offset Drift Coefficient Full V 50 50 µV/°C

INTERNAL VOLTAGE REFERENCE

Reference Voltage 25°C I 1.95 2.0 2.20 1.95 2.0 2.20 V

Full VI 1.90 2.25 1.90 2.25 V
Temperature Coefficient Full V 150 150 µV/°C
Power Supply Rejection

Ratio (PSRR) 25°C I 10 25 10 25 mV/V

SWITCHING PERFORMANCE

Maximum Conversion Rate

4

25°C I 50 50 60 MSPS
Aperture Delay (t

A

)25°C IV 0.1 0.8 1.5 0.1 0.8 1.5 ns
Aperture Delay Matching 25°C IV 0.2 0 5 0.2 0.5 ns
Aperture Uncertainty (Jitter) 25°C V 10 10 ps, rms
Output Delay (Valid) (t

V

)

4

25°CI 8 5 8 ns

Output Delay (t

V

) Tempco Full V 16 16 ps/°C

Propagation Delay (t

PD

)

4

25°C I 12 12 19 ns

Propagation Delay (t

PD

) Tempco Full V –16 –16 ps/°C

Output Time Skew 25°CV 1 1 ns

ENCODE INPUT

Logic “1” Voltage Full VI 2 2 V
Logic “0” Voltage Full VI 0.8 0.8 V
Logic “1” Current Full VI 600 600 µA
Logic “0” Current Full VI 1000 1000 µA
Input Capacitance 25°CV 5 5 pF
Pulsewidth (High) 25°CI 8 8 ns
Pulsewidth (Low) 25°CI 8 8 ns

REV. C

–3–

AD9058

Test AD9058AJD/AJJ AD9058AKD/AKJ

Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

Transient Response 25°CV 2 2 ns
Overvoltage Recovery Time 25°CV 2 2 ns
Effective Number of Bits (ENOB)

5

Analog Input @ 2.3 MHz 25°C I 7.7 7.2 7.7 Bits

@ 10.3 MHz 25°C I 7.4 7.1 7.4 Bits

Signal-to-Noise Ratio

5

Analog Input @ 2.3 MHz 25°C I 48 45 48 dB

@ 10.3 MHz 25°C I 46 44 46 dB

Signal-to-Noise Ratio

5

(Without Harmonics)

Analog Input @ 2.3 MHz 25°C I 48 46 48 dB

@ 10.3 MHz 25°C I 47 45 47 dB

2nd Harmonic Distortion

Analog Input @ 2.3 MHz 25°C I 58 48 58 dBc

@ 10.3 MHz 25°C I 58 48 58 dBc

3rd Harmonic Distortion

Analog Input @ 2.3 MHz 25°C I 58 50 58 dBc

@ 10.3 MHz 25°C I 58 50 58 dBc

Crosstalk Rejection

6

25°C IV 60 48 60 dBc

DIGITAL OUTPUTS

Logic “1” Voltage (I

OH

= 2 mA) Full VI 2.4 2.4 V

Logic “0” Voltage (IOL = 2 mA) Full VI 0.4 0.4 V

POWER SUPPLY

7

+VS Supply Current Full VI 127 154 127 154 mA
–V

S

Supply Current Full VI 27 38 27 38 mA

Power Dissipation Full VI 770 960 770 960 mW

NOTES

1

Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is
not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.

2

For applications in which +VS may be applied before –VS, or +VS current is not limited to 500 mA, a reverse biased clamping diode should be inserted between
ground and –VS to prevent destructive latch up. See section entitled “Using the AD9058.”

3

Typical thermal impedances: 44-lead hermetic J-Leaded ceramic package: θJA = 86.4°C/W; θJC = 24.9°C/W; 48-lead hermetic DIP θJA = 40°C/W; θ

JC

= 12°C/W.

4

To achieve guaranteed conversion rate, connect each data output to ground through a 2 k Ω pull-down resistor.

5

SNR performance limits for the 48-lead DIP “D” package are 1 dB less than shown. ENOB limits are degraded by 0.3 dB. SNR and ENOB measured with
analog input signal 1 dB below full scale at specified frequency.

6

Crosstalk rejection measured with full-scale signals of different frequencies (2.3 MHz and 3.5 MHz) applied to each channel. With both signals synchronously
encoded at 40 MSPS, isolation of the undesired frequency is measured with an FFT.

7

Applies to both A/Ss and includes internal ladder dissipation.

Specifications subject to change without notice.

REV. C

AD9058

–4–

EXPLANATION OF TEST LEVELS

Test Level

I – 100% production tested.
II – 100% production tested at 25°C, and sample tested at

specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization

testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at 25°C. 100%

production tested at temperature extremes for extended

temperature devices; sample tested at temperature

extremes for commercial/industrial devices.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9058 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

DIGITAL BITS

+V

S

AD9058 Equivalent Digital Outputs

5V

ENCODE

13k⍀

AD9058 Equivalent Encode Circuit

AD9058

ENCODE**

A

IN

**

–V

REF

+V

S

–V

S

–5.2V

+5V

GROUND

COMP

+V

REF

+V

INT

D0–D7*+V

S

** INDICATES EACH PIN IS CONNECTED THROUGH 100⍀

* INDICATES EACH PIN IS CONNECTED THROUGH 2k⍀

0.1␮F

AD9058 Burn-In Connections

ABSOLUTE MAXIMUM RATINGS

1

Analog Input . . . . . . . . . . . . . . . . . . . . . . . . –1.5 V to +2.5 V

+V

S

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V

–V

S

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.8 V to –6 V

2

Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +V

S

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Voltage Reference Current . . . . . . . . . . . . . . . . . . . . . . 53 mA

+V

REF

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 V

–V

REF

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.5 V

Operating Temperature Range

AD9058AJD/AJJ/AKD/AKJ . . . . . . . . . . . . . . . 0°C to 70°C

Maximum Junction Temperature

3

AD9058AJD/AJJ/AKD/AKJ . . . . . . . . . . . . . . . . . . . 150°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

ORDERING GUIDE

Temperature Package

Model Range Description Option

1

AD9058AJJ 0°C to 70°C 44-Lead J-Leaded J-44

Ceramic

2

AD9058AKJ 0°C to 70°C 44-Lead J-Leaded J-44

Ceramic, AC Tested

AD9058ATJ/883

3

–55°C to +125°C 44-Lead J-Leaded J-44

Ceramic, AC Tested
AD9058AJD 0°C to 70°C 48-Lead Ceramic DIP D-48
AD9058AKD 0°C to 70°C 48-Lead Ceramic D-48

DIP, AC Tested
AD9058ATD/883

3

–55°C to +125°C 48-Lead Ceramic D-48

DIP, AC Tested

NOTES

1

D = Hermetic Ceramic DIP Package; J = Leaded Ceramic Package.

2

Hermetically sealed ceramic package; footprint equivalent to PLCC.

3

For specifications, refer to Analog Devices Military Products Databook.

REV. C

AD9058

–5–

7

17

18

28

39

29

GROUND

GROUND

6

+V

REF

COMP

NC

ENCODE

GROUND

GROUND

GROUND

NC

GROUND

ENCODE

D

7

(MSB)

40

TOP VIEW

(Not to Scale)

AD9058

NC = NO CONNECT

GROUND

+V

INT

+V

REF

+V

S

A

IN

A

IN

+V

S

+V

S

+V

S

–V

REF

–V

S

–V

REF

–V

S

+V

S

–V

S

–V

S

+V

S

D7(MSB)

D

0

(LSB)

D

0

(LSB)

D

6

D

5

D

3

D

4

D

2

D

1

D

1

D

2

D

3

D

4

D

5

D

6

AD9058AJJ/AKJ Pinouts

TOP VIEW

(Not to Scale)

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

AD9058

NC = NO CONNECT

GROUND D

7

(MSB)

ENCODE D

6

+V

S

D

5

GROUND D

4

–V

REF

D

3

–V

S

D

2

NC D

1

A

IN

D0(LSB)

+V

S

GROUND

GROUND –V

S

+V

REF

GROUND

COMP +V

S

+V

INT

+V

S

+V

REF

GROUND

GROUND –V

S

+V

S

GROUND

A

IN

D0(LSB)

NC D

1

D

2

–V

REF

D

3

GROUND D

4

+V

S

D

5

ENCODE D

6

GROUND D7(MSB)

–V

S

AD9058AJD/AKD Pinouts

PIN FUNCTION DESCRIPTIONS

J-Lead Ceramic DIP

Pin Number Pin Number

ADC-A ADC-B Mnemonic Function ADC-A ADC-B

343 +V

REF

Top of Internal Voltage Reference Ladder 14 11
4 42 GROUND Analog Ground Return 15 10
541 +V

S

Positive 5 V Analog Supply Voltage 16 9
6 40 AIN Analog Input Voltage 17 8
739 –V

S

Negative 5 V Supply Voltage 19 6
838 –V

REF

Bottom of Internal Voltage Reference Ladder 20 5
937 +V

S

Positive 5 V Digital Supply Voltage 22 3
10 36 ENCODE TTL-Compatible Convert Command 23 2
11 35 D7 (MSB) Most Significant Bit of TTL Digital Output 25 48
12–17 34–29 D6–D1 TTL-Compatible Digital Output Bits 26–31 47–42
18 28 D0 (LSB) Least Significant Bit of TTL Digital Output 32 41
19 27 GROUND Digital Ground Return 21, 24, 33 1, 4, 40
20 26 –V

S

Negative 5 V Supply Voltage 34 39
21 25 GROUND Analog Ground Return 35 38
22 24 +V

S

Positive 5 V Analog Supply Voltage 36 37
COMMON PINS COMMON PINS
1 COMP Connection for External (0.1 µF) 12

Compensation Capacitor
2+V

INT

Internal 2 V Reference; Can Drive 13

+V

REF

for Both ADCs.

REV. C

AD9058

–6–

THEORY OF OPERATION

The AD9058 contains two separate 8-bit analog-to-digital con­verters (ADCs) on a single silicon die. The two devices can be
operated independently with separate analog inputs, voltage
references and clocks.

In a traditional flash converter, 256 input comparators are required
to make the parallel conversion for 8-bit resolution. This is in
marked contrast to the scheme used in the AD9058, as shown
in Figure 1.

Unlike traditional “flash,” or parallel, converters, each of the two
ADCs in the AD9058 utilizes a patented interpolating archi­tecture to reduce circuit complexity, die size and input capacitance.
These advantages accrue because, compared to a conventional
flash design, only half the normal number of input comparator
cells is required to accomplish the conversion.

In this unit, each of the two independent ADCs uses only 128 (2

7

)
comparators to make the conversion. The conversion for the
seven most significant bits (MSBs) is performed by the 128
comparators. The value of the least significant bit (LSB) is
determined by interpolation between adjacent comparators in
the decoding register. A proprietary decoding scheme processes
the comparator outputs and provides an 8-bit code to the output
register of each ADC; the scheme also minimizes error codes.

8

256

ANALOG IN

–V

REF

+V

REF

INTERPOLATING LATCHES

DECODE LOGIC

LATCHES

8

128

127

2

1

Figure 1. AD9058 Comparator Block Diagram

Analog input range is established by the voltages applied at the
voltage reference inputs (+V

REF

and –V

REF

). The AD9058 can
operate from 0 V to +2 V using the internal voltage reference,
or anywhere between –1 V and +2 V using external references.
Input range is limited to 2 V p-p when using external references.
The internal resistor ladder divides the applied voltage reference
into 128 steps, with each step representing two 8-bit quanti­zation levels.

COMP

ENCODE

A

ENCODE

+V

INT

A

IN A

+V

S

D0A(LSB)

–V

S

D0B(LSB)

D

7A

(MSB)

A

IN B

D7B(MSB)

AD9058

(J-LEAD)

–V

REF A

–V

REF B

ENCODE

B

+V

REF A

+V

REF B

CLOCK

ANALOG

IN A ⴞ0.5V

ANALOG

IN B ⴞ0.5V

0.1␮F

0.1␮F

+5V

–5V

0.1␮F

–2V

+2V

AD9617

400⍀

400⍀

20k⍀

200⍀

200⍀

800⍀

800⍀

20k⍀

5⍀

5⍀

0.1␮F

10pF

1k⍀

50⍀

(SEE TEXT)

CLOCK

8

8

1N4001

4, 19, 21,
25, 27, 42

74HCT 273

74HCT 273

40

1

43

3

2

6

38

8

7, 20,
26, 39

28
29
30
31
32
33
34
35

18
17
16
15
14
13
12
11

5, 9, 22,
24, 37, 41

10 36

AD9617

AD707

74HCT04

Figure 2. AD9058 Using Internal 2 V Voltage Reference

REV. C

AD9058

–7–

AD9618

COMP

ENCODE

A

ENCODE

A

IN A

+V

S

D0A(LSB)

–V

S

D0B(LSB)

D

7A

(MSB)

A

IN B

D7B(MSB)

AD9058

(J-LEAD)

+V

REF A

+V

REF B

ENCODE

B

–V

REF A

–V

REF B

CLOCK

ANALOG

IN A

ⴞ0.125V

ANALOG

IN B

ⴞ0.125V

0.1␮F

+5V

–5V

0.1␮F

+5V

400⍀

400⍀

50⍀

50⍀

10k⍀

5⍀

5k⍀

0.1␮F

10pF

1k⍀

50k⍀

(SEE TEXT)

CLOCK

8

8

1N4001

4, 19, 21,
25, 27, 42

74ACT 273

74ACT 273

40

1

8

38

2

6

43

3

7, 20,
26, 39

28
29
30
31
32
33
34
35

18
17
16
15
14
13
12
11

5, 9, 22,
24, 37, 41

10 36

AD9618

74ACT04

0.1␮F

RZ1

RZ2

–1V

ⴞ1V

150⍀

2N3906

–5V

1/2

AD708

20k⍀

ⴞ1V

2N3904

10⍀

+5V

150⍀

1/2

AD708

20k⍀

AD580

1

3

0.1␮F

0.1␮F

10k⍀ 10k⍀

Figure 3. AD9058 Using External Voltage References

The onboard voltage reference, +V

INT

, is a bandgap reference
which has sufficient drive capability for both reference ladders.
It provides a 2 V reference that can drive both ADCs in the
AD9058 for unipolar positive operation (0 V to 2 V).

USING THE AD9058

Refer to Figure 2. Using the internal voltage reference con­nected to both ADCs as shown reduces the number of external
components required to create a complete data acquisition sys­tem. The input ranges of the ADCs are positive unipolar in this
configuration, ranging from 0 V to 2 V. Bipolar input signals
are buffered, amplified and offset into the proper input range
of the ADC using a good low distortion amplifier such as the
AD9617 or AD9618.

The AD9058 offers considerable flexibility in selecting the ana­log input ranges of the ADCs; the two independent ADCs can
even have different input ranges if required. In Figure 3 above,
the AD9058 is shown configured for ±1 V operation

The Reference Ladder Offset shown in the specifications table refers
to the error between the voltage applied to the +V

REF

(top) or

–V

REF

(bottom) of the reference ladder and the voltage required
at the analog input to achieve a 1111 1111 or 0000 0000 transi­tion. This indicates the amount of adjustment range which must
be designed into the reference circuit for the AD9058.

The diode shown between ground and –V

S

is normally reverse
biased and is used to prevent latch-up. Its use is recommended
for applications in which power supply sequencing might allow
+V

S

to be applied before –VS; or the +VS supply is not current

limited. If the negative supply is allowed to float (the +5 V supply
is powered up before the –5 V supply), substantial +5 V supply
current will attempt to flow through the substrate (V

S

supply con­tact) to ground. If this current is not limited to <500 mA, the part
may be destroyed. The diode prevents this potentially destructive
condition from occurring.

Timing

Refer to the AD9058 Timing Diagram. The AD9058 provides
latched data outputs with no pipeline delay. To conserve power,
the data outputs have relatively slow rise and fall times. When
designing system timing, it is important to observe (1) setup and
hold times; and (2) the intervals when data is changing.

Figure 3 shows 2 kΩ pull-down resistors on each of the D

0–D7

output data bits. When operating at conversion rates higher than
40 MSPS, these resistors help equalize rise and fall times and
ease latching the output data into external latches. The 74ACT
logic family devices have short setup and hold times and are the
recommended choices for speeds of 40 MSPS or more.

Layout

To Ensure optimum performance, a single low-impedance ground
plane is recommended. Analog and digital grounds should be
connected together and to the ground plane at the AD9058
device. Analog and digital power supplies should be bypassed to
ground through 0.1 µF ceramic capacitors as close to the unit
as possible.

For prototyping or evaluation, surface mount sockets are available
from Methode (part #213-0320602) for evaluating AD9058

REV. C

AD9058

–8–

surface mount packages. To evaluate the AD9058 in through­hole PCB designs, use the AD9058AJD/AKD with individual pin
sockets (AMP part #6-330808-0). Alternatively, surface mount
AD9058 units can be mounted in a through-hole socket (Circuit
Assembly Corporation, Irvine California part #CA-44SPC-T).

AD9058 APPLICATIONS

Combining two ADCs in a single package is an attractive alter­native in a variety of systems when cost, reliability and space are
important considerations. Different systems emphasize particu­lar specifications, depending on how the part is used.

In high density digital radio communications, a pair of high
speed ADCs are used to digitize the in-phase (I) and quadrature
(Q) components of a modulated signal. The signal presented to
each ADC in this type of system consists of message-dependent
amplitudes varying at the symbol rate, which is equal to the
sample rates of the converters.

t

A

= APERTURE TIME

t

V

= DATA DELAY OF PRECEDING ENCODE

t

PD

= OUTPUT PROPAGATION DELAY

ANALOG

INPUT

ENCODE

D

0–D7

VALID DATA

FOR N–1

VALID DATA

FOR N

VALID DATA

FOR N+1

DATA

CHANGING

t

V

t

A

N

N+1

N+2

t

PD

Figure 4. AD9058 Timing Diagram

Figure 5 shows what the analog input to the AD9058 would
look like when observed relative to the sample clock. Signal-to­noise ratio (SNR), transient response, and sample rate are all
critical specifications in digitizing this “eye pattern.”

ANALOG

INPUT

SAMPLE

CLOCK

Figure 5. AD9058 I and Q Input Signals

Receiver sensitivity is limited by the SNR of the system. For the
ADC, SNR is measured in the frequency domain and calculated
with a Fast Fourier Transform (FFT). The signal-to-noise ratio
equals the ratio of the fundamental component of the signal
(rms amplitude) to the rms level of the noise. Noise is the sum
of all other spectral components, including harmonic distortion,
but excluding dc.

Although the signal being sampled does not have a significant
slew rate at the instant it is encoded, dynamic performance of
the ADC and the system is still critical. Transient response is the

time required for the AD9058 to achieve full accuracy when a
step function input is applied. Overvoltage recovery time is the
interval required for the AD9058 to recover to full accuracy after
an overdriven analog input signal is reduced to its input range.

Time domain performance of the ADC is also extremely impor­tant in digital oscilloscopes. When a track (sample)-and-hold is
used ahead of the ADC, its operation becomes similar to that
described above for receivers.

The dynamic response to high-frequency inputs can be described
by the effective number of bits (ENOB). The effective number of

bits is calculated with a sine wave curve fit and is expressed as:

ENOB = N – LOG

2

[Error (measured)/Error (ideal)]

where N is the resolution (number of bits) and measured error is
actual rms error calculated from the converter’s outputs with
a pure sine wave applied as the input.

Maximum conversion rate is defined as the encode (sample) rate
at which SNR of the lowest frequency analog test signal drops
no more than 3 dB below the guaranteed limit.

HARMONIC DISTORTION – dB

60

55

50

45

40

35

INPUT FREQUENCY – MHz

0.1 1 10 100

30

+25 C

–55 C

+125 C

Figure 6. Harmonic Distortion vs. Analog Input Frequency

SIGNAL-TO-NOISE RATIO (SNR) – dB

55

50

45

40

35

INPUT FREQUENCY – MHz

0.1 1 10 100

30

+25 C AND +125 C

–55 C

EFFECTIVE NUMBER OF BITS (ENOB)

8.0

7.2

6.4

5.5

Figure 7. AD9058 Dynamic Performance vs. Analog Input
Frequency

REV. C

AD9058

–9–

Die Dimensions . . . . . . . . . . . . . . . . 106 × 108 × 15 (± 2) mils

Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils

Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold

Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None

Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V

S

Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride

Die Attach . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic)

Bond Wire . . . . . . . . . . . . 1–1.3 mil, Gold; Gold Ball Bonding

ENCODE

D

7

(MSB)

–V

REF

–V

S

+V

S

D

1

D

2

D

3

D

4

D

5

D

6

GROUND

GROUND

GROUND

GROUND

+V

S

–V

S

–V

S

+V

S

D0(LSB)

D

0

(LSB)

GROUND

GROUND

+V

REF

COMP

+V

INT

+V

REF

+V

S

A

IN

A

IN

+V

S

ENCODE

+V

S

–V

REF

–V

S

D

7

(MSB)

D

6D5

D3D

4

D2D

1

MECHANICAL INFORMATION

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

44-Lead J-Leaded Ceramic (J-44) Package

7

40

39

29

2818

6

PIN 1

TOP VIEW

17

0.650 ⴞ0.008 SQ
(16.51 ⴞ0.203)

0.690 ⴞ0.012 SQ

(17.5 ⴞ0.305)

0.500ⴞ0.008

(12.70 ⴞ0.203)

0.012
(0.30)

MIN

0.630 ⴞ0.020

(16.0 ⴞ0.058)

0.050
TYP
(1.27)

0.017

(0.432)

TYP

0.037 ⴞ0.012

(0.940 ⴞ0.305)

0.135 (3.42)
MAX

0.020
TYP
(0.508)

48-Lead Hermetic Ceramic DIP (D-48) Package

40

1 24

25

0.62 (15.75)

0.59 (14.99)

PIN 1

0.023 (0.58)

0.014 (0.36)

0.060 (1.52)

0.015 (0.38)

0.070 MAX
(1.77 MAX)

0.150
(3.81)
MIN

0.110 (2.79)

0.090 (2.29)

0.225 MAX

(5.72 MAX)

2.400 ⴞ0.024

(60.96 ⴞ0.609)

0.62 (15.75)

0.59 (12.95)

0.015 (0.38)

0.008 (0.20)

0.63 (16.00)

0.52 (13.21)

REV. C

AD9058

–10–

AD9058–Revision History

Location Page

Data Sheet changed from REV. B to REV. C.

Edits to ELECTRICAL CHARACTERISTICS headings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edits to Pinout captions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edits to Layout section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

–11–

–12–

C00562

–0–6/01(C)

PRINTED IN U.S.A.