Page 1
10-Bit, 60 MSPS
a
FEATURES
60 MSPS Sampling Rate
9.3 Effective Number of Bits at fIN = 10.3 MHz
250 mW Total Power at 60 MSPS
Selectable Input Bandwidth of 50 MHz or 130 MHz
On-Chip T/H and Voltage Reference
Single +5 V Supply Voltage
+5 V or +3 V Logic I/O Compatible
Input Range and Output Coding Options Available
APPLICATIONS
Medical Imaging
Digital Communications
Professional Video
Instrumentation
Set-Top Box
GENERAL DESCRIPTION
The AD9051 is a complete 10-bit monolithic sampling analogto-digital converter (ADC) with an onboard track-and-hold and
reference. The unit is designed for low cost, high performance
applications and requires only +5 V and an encode clock to
achieve 60 MSPS sample rates with 10-bit resolution.
The encode clock is TTL compatible and the digital outputs are
CMOS; both can operate with +5 V/+3 V logic. The two-step
architecture used in the AD9051 is optimized to provide the
best dynamic performance available while maintaining low
power consumption.
A/D Converter
AD9051
FUNCTIONAL BLOCK DIAGRAM
BWSEL
+5V
AINB
AIN
ENCODE
TIMING
A +2.5 V reference is included onboard, or the user can provide
an external reference voltage for gain control or matching of
multiple devices. Fabricated on a state-of-the-art BiCMOS
process, the AD9051 is packaged in a space saving surface
mount package (SSOP) and is specified over the industrial tem-
perature range (–40°C to +85°C).
+5V GND
AD9051
T/H
SUM
AMP
IN OUT
REFERENCE
CIRCUITS
ADC
DAC
ADC
DECODE
LOGIC
10
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
Page 2
(VD = +5 V, VDD = +3 V; external reference = 2.50 V; ENCODE = 60 MSPS
AD9051–SPECIFICATIONS
Parameter Temp Level Min Typ Max Min Typ Max Units
RESOLUTION 10 10 Bits
DC ACCURACY
Differential Nonlinearity +25°C I 0.75 1.50 0.75 1.50 LSB
Integral Nonlinearity +25°C I 0.75 1.50 0.75 1.50 LSB
No Missing Codes +25°C I ␣␣␣␣␣GUARANTEED ␣␣␣␣␣GUARANTEED ␣ ␣ ␣
Gain Error
Gain Tempco
ANALOG INPUT
Input Voltage Range
Input Offset Voltage +25°C I –14 5.0 26 –14 5.0 26 LSB
Input Resistance +25°C I 4.0 6.0 4.0 6.0 kΩ
Input Capacitance +25°CV 5 5 pF
Analog Bandwidth (BW SEL +VD/NC)
BANDGAP REFERENCE
Output Voltage (I
Temperature Coefficient Full V ±33 ±33 ppm/°C
Power Supply Sensitivity Full V 6.2 6.2 mV/V
Reference Input Current (V
SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 60 60 MSPS
Minimum Conversion Rate
Aperture Delay (t
Aperture Uncertainty (Jitter) +25°C V 5 5 ps, rms
Output Valid Time (tV)
Output Propagation Delay (tPD)
DYNAMIC PERFORMANCE
Transient Response +25°C V 10 10 ns
Overvoltage Recovery Time +25°C V 10 10 ns
ENOBS
f
f
f
Signal-to-Noise Ratio (SINAD)
f
f
f
Signal-to-Noise Ratio (Without Harmonics)
f
f
f
2nd Harmonic Distortion
f
f
f
3rd Harmonic Distortion
f
f
f
Two-Tone Intermodulation
Distortion (IMD) +25°C V –65 –65 dBc
Differential Phase +25°C V 0.1 0.1 Degrees
Differential Gain +25°CV 0.5 0.5 %
1
1
2
3
@ 200 µA) Full VI 2.4 2.5 2.6 2.4 2.5 2.6 V
O
= 2.50 V) Full VI 2.0 25 2.0 25 µA
IN
4
) +25°CV 2.5 2.5 ns
A
5
5
6
= 1.20 MHz +25°C V 9.6 9.6 ENOB
IN
= 10.3 MHz +25°C I 8.93 9.3 8.93 9.3 ENOB
IN
= 29.0 MHz +25°C V 9.1 9.1 ENOB
IN
= 1.20 MHz +25°C V 58.5 57.5 dB
IN
= 10.3 MHz +25°C I 55 57 54 56 dB
IN
= 29.0 MHz +25°C V 55 54 dB
IN
= 1.20 MHz +25°C V 59 59 dB
IN
= 10.3 MHz +25°C I 56 58 56 58 dB
IN
= 29.0 MHz +25°C V 56.5 56.5 dB
IN
= 1.20 MHz +25°C V –74 –68 dBc
IN
= 10.3 MHz +25°C I –73 –60 –64 –58 dBc
IN
= 29.0 MHz +25°C V –67 –60 dBc
IN
= 1.20 MHz +25°C V –74 –69 dBc
IN
= 10.3 MHz +25°C I –70 –60 –65 –60 dBc
IN
= 29.0 MHz +25°C V –65 –60 dBc
IN
unless otherwise noted)
Test AD9051BRS AD9051BRS-2V
Full V 0.90 0.90 LSB
Full V 0.90 0.90 LSB
+25°CI ±0.3 ±2.5 ±0.3 ±3.0 % FS
Full VI ±5.0 ±5.5 % FS
Full V ±10 ±10 ppm/°C
+25°C V 1.25 2.0 V p-p
+25°C V 50/130 50/130 MHz
Full IV 2.0 5.0 2.0 5.0 MSPS
Full VI 4.0 4.0 ns
Full VI 5.5 10 5.5 10 ns
–2–
REV. A
Page 3
AD9051
Test AD9051BRS AD9051BRS-2V
Parameter Temp Level Min Typ Max Min Typ Max Units
ENCODE INPUT
Logic “1” Voltage Full VI 2.0 2.0 V
Logic “0” Voltage Full VI 0.8 0.8 V
Logic “1” Current Full VI 1 1 µA
Logic “0” Current Full VI 1 1 µA
Input Capacitance +25°CV 7.5 7.5 pF
Encode Pulsewidth High (t
Encode Pulsewidth Low (t
DIGITAL OUTPUTS
Logic “1” Voltage (5.0 VDD) Full VI 4.95 4.95 V
Logic “0” Voltage (5.0 V
Logic “1” Voltage (3.0 V
Logic “0” Voltage (3.0 V
Output Coding
7
POWER SUPPLY
, VDD Supply Current Full VI 50 63 50 63 mA
V
D
Power Dissipation
Power Supply Rejection Ratio
(PSRR)
NOTES
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference).
2
Contact factory or authorized sales agent for information concerning the availability of expanded input voltage range devices.
33
dB bandwidth with full-power input signal.
4
Minimum conversion rate at which all data sheet specifications remain stable.
5
tV and tPD are measured from the threshold crossing of the ENCODE input to valid TTL levels 0.5 V and 2.4 V of the digital outputs with VDD = 3.0 V. The output
ac load during test is 5 pF.
6
SNR/harmonics tested with an analog input voltage of –0.5 dBfs. All tests performed at 60 MSPS.
7
Contact factory or authorized sales agent for information concerning the availability of alternative output coding and input range devices.
8
Power dissipation is measured under the following conditions: analog input = –FS at 60 MSPS ENCODE.
9
A change in input offset voltage with respect to a change in VD.
Specifications subject to change without notice.
8
9
) +25°CIV 7.5 7.5 ns
EH
) +25°CIV 7.5 7.5 ns
EL
) Full VI 0.05 0.05 V
DD
) Full VI 2.95 2.95 V
DD
) Full VI 0.05 0.05 V
DD
Offset Binary Offset Binary
Full VI 250 315 250 315 mW
+25°CI ±2 ±10 ±7 ±15 mV/V
–3–REV. A
Page 4
AD9051
ABSOLUTE MAXIMUM RATINGS*
VD, VDD␣ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
D
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . .+175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . .+150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
ORDERING GUIDE
EXPLANATION OF TEST LEVELS
Test Level
I. 100% production tested.
D
II. 100% production tested at +25°C and sample tested at
D
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at +25°C; guaranteed by design
and characterization testing for industrial temperature range.
Model Temperature Range Package Description Package Options
AD9051BRS –40°C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28
AD9051BRS-2V –40°C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28
AD9051/PCB +25°C Evaluation Board
AD9051-2V/PCB +25°C Evaluation Board
Table I. Digital Coding (Single-Ended Input with AIN, AINB Bypassed to GND)
OR Digital Output
Analog Input Voltage Level (Out of Range) MSB␣ .␣ .␣ .␣ ␣ LSB
3.126 (3.50)* Positive Full Scale + 1 LSB 1 1111111111
2.5 Midscale 0 0111111111
1.874 (1.50)* Negative Full Scale – 1 LSB 1 0000000000
*(BRS-2V Version)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9051 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
Page 5
AD9051
PIN FUNCTION DESCRIPTIONS
Pin No. Name Function
1, 6, 7, 12, 21, 23 GND Ground.
2, 8, 11 V
D
3 VREFOUT Internal bandgap voltage reference (nominally +2.5 V).
4 VREFIN Input to reference amplifier. Voltage reference for ADC is connected here.
5 BWSEL Bandwidth Select. NC = 130 MHz nominal. +V
9 AINB Complementary analog input pin (Analog input bar).
10 AIN Analog input pin.
13 ENCODE Encode clock input to ADC. Internal T/H is placed in hold mode (ADC is encoding)
14 OR Out of range signal. Logic “0” when analog input is in nominal range. Logic “1” when
15 D9 (MSB) Most significant bit of ADC output.
16–19 D8–D5 Digital output bits of ADC.
20, 22 V
DD
24–27 D4–D1 Digital output bits of ADC.
28 D0 (LSB) Least significant bit of ADC output.
Analog +5 V power supply.
= 50 MHz nominal.
D
on rising edge of encode signal.
analog input is out of nominal range.
Digital output power supply (only used by digital outputs).
PIN CONFIGURATION
GND
VREFOUT
VREFIN
BWSEL
GND
GND
AINB
AIN
GND
ENCODE
OR
V
D
V
D
V
D
1
2
3
4
5
6
AD9051
7
TOP VIEW
8
(Not to Scale)
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D0 (LSB)
D1
D2
D3
D4
GND
V
DD
GND
V
DD
D5
D6
D7
D8
D9 (MSB)
N N + 1 N + 2 N + 3 N + 4 N + 5
AIN
t
A
ENCODE
DIGITAL
OUTPUTS
tEHt
EL
t
PD
N – 5 N – 4 N – 3 N – 2 N – 1 N
Figure 1. Timing Diagram
V
D
12kV
12kV
INPUT
AINB (PIN 9)
AIN (PIN 10)
12kV
BUFFER
12kV
Analog Input Encode
VDD (PINS 20, 22)
+3V TO +5V
ENCODE
(PIN 13)
V
D
V
D
D0–D9, OR
VREF
(PIN 3)
OUT
Output Stage VREF
Figure 2. Equivalent Circuits
–5–REV. A
Page 6
AD9051
–Typical Performance Characteristics
255
250
245
240
235
230
225
DISSIPATION – mW
220
215
210
15
20 25 30 35 40 45 50 55 60
15
CLOCK RATE – MSPS
Figure 3. Power Dissipation vs. Clock Rate
60
59
58
57
56
55
54
SNR/SINAD – dB
53
52
51
50
0
SINAD @ 60MSPS
SNR @ 60MSPS
20 30 40 50 60 70 80
FREQUENCY – MHz
SNR @ 40MSPS
SINAD @ 40MSPS
Figure 4. SNR/SINAD vs. AIN Frequency
0
–1
BWSEL DISABLED
–2
–3
BWSEL ENABLED
ADC GAIN – dB
–4
–5
–6
1
40 52 80 118 141
ANALOG INPUT FREQUENCY – MHz
201
Figure 6. ADC Gain vs. AIN Frequency
59
58.5
58
57.5
57
SNR – dB
56.5
56
55.5
55
9010
–40
ENCODE = 60MSPS
ENCODE = 40MSPS
TEMPERATURE – 8C
AIN = 10.3MHz
45250–20
65
85
Figure 7. SNR vs. Temperature
–50
–55
–60
–65
–70
–75
dB
–80
–85
–90
–95
–100
3RD @ 40MSPS
0
2ND @ 60MSPS
2ND @ 40MSPS
3RD @ 60MSPS
20 30 40 50 60 70 80
FREQUENCY – MHz
Figure 5. Harmonics vs. AIN Frequency
60
59
58
57
56
55
SNR – dB
54
53
52
51
9010
50
5
40302010
ENCODE – MSPS
AIN = 10.3MHz
50 60
70
Figure 8. SNR vs. Clock Rate
–6–
REV. A
Page 7
AD9051
FREQUENCY – MHz
0
–10
–40
–100
–30
–90
–20
–50
–80
–70
–60
dB
AIN = 21.7MHz
ENCODE = 60 MSPS
SNR = 57.76dB
SINAD = 56.27dB
0 3.8 7.5 11.3 15.0 18.8 22.5 26.3 30
FREQUENCY – MHz
0
–10
–40
–100
–30
–90
–20
–50
–80
–70
–60
dB
AIN1 = 9.5MHz, –7dBFS
AIN2 = 9.9MHz, –7dBFS
IMD = –65dBc
ENCODE = 60 MSPS
0 3.8 7.5 11.3 15.0 18.8 22.5 26.3 30
0
–10
AIN = 10.3MHz
ENCODE = 40 MSPS
SNR = 58.6dB
–20
SINAD = 57.69dB
–30
–40
–50
dB
–60
–70
–80
–90
–100
0 2.5 5.0 7.5 10 12.5 15 17.5 20
FREQUENCY – MHz
Figure 9. FFT Plot 40 MSPS, 10.3 MHz
0
–10
AIN = 15.2MHz
ENCODE = 40 MSPS
SNR = 58.47dB
–20
SINAD = 57.04dB
–30
–40
–50
dB
–60
–70
–80
–90
–100
0 2.5 5.0 7.5 10 12.5 15 17.5 20
FREQUENCY – MHz
Figure 10. FFT Plot 40 MSPS, 15.2 MHz
0
AIN = 15.2MHz
–10
ENCODE = 60 MSPS
SNR = 58.29dB
–20
SINAD = 57.23dB
–30
–40
–50
dB
–60
–70
–80
–90
–100
0 3.8 7.5 11.3 15.0 18.8 22.5 26.3 30
FREQUENCY – MHz
Figure 12. FFT Plot 60 MSPS, 15.2 MHz
Figure 13. FFT Plot 60 MSPS, 21.7 MHz
0
–10
–20
–30
–40
–50
dB
–60
–70
–80
–90
–100
0 3.8 7.5 11.3 15.0 18.8 22.5 26.3 30
Figure 11. FFT Plot 60 MSPS, 10.3 MHz
FREQUENCY – MHz
AIN = 10.3MHz
ENCODE = 60 MSPS
SNR = 58.15dB
SINAD = 57.25dB
Figure 14. Two-Tone IMD
–7–REV. A
Page 8
AD9051
1.2
1.0
0.8
0.6
% GAIN ERROR
0.4
0.2
0
0
Figure 15. Gain vs. Clock Rate
16
14
12
10
8
6
OFFSET – mV
4
2
0
0
Figure 16. Offset vs. Clock Rate
20 30 40 50
ENCODE – MSPS
20 30 40 50
ENCODE – MSPS
6.5
5V RISING
3V RISING
45250–20
85
65
6
5.5
5V FALLING
– ns
PD
t
5
3V FALLING
4.5
6010
4
–40
TEMPERATURE – 8C
Figure 18. tPD vs. Temperature +3 V/+5 V
2.51
2.50
2.49
2.48
2.47
2.46
REF VOLTAGE
2.45
2.44
2.43
6010
2.42
0.1
0.55 0.7 0.85 1 1.15 1.3 1.45 1.6 1.75 1.9 2.0
0.25 0.4
SOURCE CURRENT – mA
V
OUT
Figure 19. Reference Load Regulation
60
58
56
54
52
50
SNR – dB
48
46
44
42
40
25 5530
SNR @ 40MSPS
SNR @ 60MSPS
35 40 45 50
DUTY CYCLE – %
60 65 70 75
Figure 17. SNR vs. Duty Cycle
–8–
80
70
60
50
40
30
% OCCURANCE
20
10
0
512 513 514 515 516 517 518
CODE
Figure 20. Midscale Histogram (Inputs Tied)
REV. A
Page 9
AD9051
THEORY OF OPERATION
Refer to the block diagram on the front page.
The AD9051 employs a subranging architecture with digital
error correction. This combination of design techniques ensures
true 10-bit accuracy at the digital outputs of the converter.
At the input, the analog signal is buffered by a high speed differential buffer and applied to a track-and-hold (T/H) that holds
the analog value present when the unit is strobed with an
ENCODE command. The conversion process begins on the
rising edge of this pulse. The two stage architecture completes a
coarse and then a fine conversion of the T/H output signal.
Error correction and decode logic correct and align data from
the two conversions and present the result as a 10-bit parallel
digital word. Output data are strobed on the rising edge of the
ENCODE command. The subranging architecture results in five
pipeline delays for the output data. Refer to the AD9051 Timing
Diagram.
USING THE AD9051
3 V System
The digital input and outputs of the AD9051 can be easily
configured to directly interface to 3 V logic systems. The encode
input (Pin 13) is TTL compatible with a logic threshold of
1.5 V. This input is actually a CMOS stage (refer to Equivalent
Encode Input Stage) with a TTL threshold, allowing operation
with TTL, CMOS and 3 V CMOS logic families. Using 3 V
CMOS logic allows the user to drive the encode directly without
the need to translate to +5 V. This saves the user power and
board space. As with all high speed data converters, the clock
signal must be clean and jitter free to prevent the degradation of
dynamic performance.
The AD9051 outputs can also directly interface to 3 V logic
systems. The digital outputs are standard CMOS stages (refer to
AD9051 Output Stage) with isolated supply pins (Pins 20, 22
). By varying the voltage on the VDD pins, the digital output
V
DD
levels vary respectively. By connecting Pins 20 and 22 to the
3 V logic supply, the AD9051 will supply 3 V output levels.
Care should be taken to filter and isolate the output supply of
the AD9051 as noise could be coupled into the ADC, limiting
performance.
Analog Input
The analog input of the AD9051 is a differential input buffer
(refer to AD9051 Equivalent Analog Input). The differential
inputs are internally biased at +2.5 V, obviating the need for
external biasing. Excellent performance is achieved whether the
analog inputs are driven single-endedly or differentially (for best
dynamic performance, impedances at AIN and AINB should
match).
Figure 21 shows typical connections for the analog inputs when
using the AD9051 in a dc coupled system with single-ended
signals. All components are powered from a single +5 V supply.
The AD820 is used to offset the ground referenced input signal
to the level required by the AD9051.
AC coupling of the analog inputs of the AD9051 is easily accomplished. Figure 22 shows capacitive coupling of a single-ended
signal while Figure 23 shows transformer coupling differentially
into the AD9051.
␣␣
140V
V
IN
–0.625V
TO
+0.625V
140V
0.1mF
1kV
1kV
+5V
AD9631
+5V
AD820
+5V
10
AD9051
9
0.1mF
Figure 21. Single Supply, Single-Ended, DC-Coupled ␣ ␣
AD9051
140V
V
IN
–0.625V
TO
+0.625V
140V
+5V
–5V
0.1mF
AD9631
0.1mF
+5V
10
AD9051
9
Figure 22. Single-Ended, Capacitively-Coupled AD9051
140V
V
IN
–0.625V
TO
+0.625V
140V
+5V
–5V
AD9631
0.1mF
T1-1T
50V
+5V
10
AD9051
9
Figure 23. Differentially Driven AD9051 Using Transformer Coupling
The AD830 provides a unique method of providing dc level
shift for the analog input. Using the AD830 allows a great deal
of flexibility for adjusting offset and gain. Figure 24 shows the
AD830 configured to drive the AD9051. The offset is provided
by the internal biasing of the AD9051 differential input (Pin 9).
For more information regarding the AD830, see the AD830
data sheet.
V
IN
–0.625V
TO
+0.625V
1
2
3
4
+15V
AD830
–5V
7
10
9
0.1mF
+5V
AD9051
Figure 24. Level-Shifting with the AD830
–9–REV. A
Page 10
AD9051
Overdrive of the Analog Input
Special care was taken in the design of the analog input section
of the AD9051 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is +1.875 V
to 3.125 V (1.25 V p-p centered at 2.5 V). Out-of-range comparators detect when the analog input signal is out of this range
and the input buffer is clamped. The digital outputs are locked
at their maximum or minimum value (i.e., all “0” or all “1”).
This precludes the digital outputs changing to an invalid value
when the analog input is out of range.
The input is protected to one volt outside the power supply
rails. For nominal power (+5 V and ground), the analog input
will not be damaged with signals from +5.5 V to –0.5 V.
Timing
The performance of the AD9051 is very insensitive to the duty
cycle of the clock. Pulsewidth variations of as much as ±15%
for encode rates of 40 MSPS and ±10% for encode rates of
60 MSPS will cause no degradation in performance. (See Figure 17, SNR vs. Duty Cycle.)
The AD9051 provides latched data outputs, with five pipeline
delays. Data outputs are available one propagation delay (t
PD
)
after the rising edge of the encode command (refer to Figure 1, Timing Diagram). The length of the output data lines
and loads placed on them should be minimized to reduce transients within the AD9051; these transients can detract from the
converter’s dynamic performance.
Power Dissipation
The power dissipation specification in the parameter table is
measured under the following conditions: encode is 60 MSPS,
analog input is –FS.
As shown in Figure 3, the actual power dissipation varies based
on these conditions. For instance, reducing the clock rate will
reduce power as expected for CMOS-type devices. The loading
determines the power dissipated in the output stages.
The analog input frequency and amplitude in conjunction with
the clock rate determine the switching rate of the output data
bits. Power dissipation increases as more data bits switch at
faster rates. For instance, if the input is a dc signal that is out of
range, no output bits will switch. This minimizes power in the
output stages, but is not realistic from a usage standpoint.
The dissipation in the output stages can be minimized by interfacing the outputs to 3 V logic (refer to Using the AD9051, 3 V
System). The lower output swings minimize power consumption as follows: (1/2 C
Voltage Reference
LOAD
2
× V
× Update Rate).
DD
A stable and accurate +2.5 V voltage reference is built into the
AD9051 (Pin 3, VREFOUT). In normal operation the internal
reference is used by strapping together Pins 3 and 4 of the
AD9051. The internal reference has 500 µA of extra drive cur-
rent that can be used for other circuits.
Some applications may require greater accuracy, improved
temperature performance, or adjustment of the gain of the
AD9051, which cannot be obtained by using the internal reference. For these applications, an external +2.5 V reference can
be used to connect to Pin 4 of the AD9051. The VREFIN
requires 2 µA of drive current.
The input range can be adjusted by varying the reference voltage applied to the AD9051. No appreciable degradation in
performance occurs when the reference is adjusted ±5%. The
full-scale range of the ADC tracks reference voltage changes
linearly.
EVALUATION BOARD
The AD9051 evaluation board is a convenient and easy way to
evaluate the performance of the AD9051.
Analog Input
The evaluation board requires a 1.25 V p-p input. The signal is
buffered by an AD9631 op amp in the unity gain configuration.
The signal is then ac coupled before entering the AD9051
where a dc offset is internally generated. Leave E3 unconnected
to E4 for usage with the AD9631. To evaluate performance
without this buffer, remove the AD9631 and connect E3 to E4.
Keep E1 connected to E2 for use in the low bandwidth mode
(50 MHz). Removing this connector will enable high bandwidth mode (130 MHz). Low bandwidth is the recommended
mode of operation in order to minimize any high frequency
noise coupling into the input of the AD9051.
Encode
The evaluation board is driven with a TTL or CMOS clock
into a clock buffer of ac type CMOS logic. This buffer will
drive the encode to the AD9051, the data latches, and a “data
ready.”
Data Out
The digital data is captured by a pair 74ACQ574 latches. Any
unused connector pins should be grounded to the device that is
capturing data from the evaluation board. This minimizes any
grounding loops that may degrade performance. A separate
power plane is provided for supplying the latches, clock buffer,
and digital outputs of the AD9051. This supply can be 3 V or
5V.
Layout
The AD9051 is not layout sensitive if some important guidelines are met. The evaluation board layout provides an example where these guidelines have been followed to optimize
performance.
• Provide a solid ground plane connecting both analog and
digital sections. Cuts in this plane near the AD9051 should
be kept to a minimum.
• Excellent bypassing is essential. All capacitors should be
placed as close as possible to the AD9051. No vias should
be used to connect capacitors to the AD9051 as this may
create a parasitic inductance that can reduce bypassing
effectiveness.
The AD9051 evaluation board is provided as a design example
for customers of Analog Devices. ADI makes no warranties
express, statutory, or implied regarding merchantability of
fitness for a particular purpose.
–10–
REV. A
Page 11
AD9051
Figure 25. Evaluation Board Top Layer
Figure 26. Evaluation Board Ground Layer
Figure 27. Evaluation Board Bottom Layer
Figure 28. Silkscreen
–11–REV. A
Page 12
AD9051
74ACQ574
1
OUT_EN
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
GND
74ACQ574
1
OUT_EN
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
GND
GND
V
DD
U4
CLOCK
GND
V
DD
U5
CLOCK
VCC
VCC
C17
0.1mF
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
C16
0.1mF
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
GND
GND
GND
P1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
C3321a–0–11/98
+5VA –5V
C12
C10
1mF
0.1mF
+5VA
GND
–5V
GND
V
DD
E3 E4
R3
140V
R4
140V
J1
R5
50V
2
U2
3
AD9631
J1
C11
C14
0.1mF
1mF
GND
P6
1
1
2
2
3
3
4
4
5
5
R1
25V
R2
25V
6
C5
0.1mF
C6
0.1mF
1
2
+5VA
+5VA
GND
GND
+5VA
+5VA
GND
U3
74AC00
R6
50V
4
5
U3
V
DD
C13
C15
0.1mF
1mF
AD9051
GND5
V
DD1
GND6
V
DD2
D1
D2
D3
D4
D5
D6
D7
D8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
GND1
+5VA1
VREFOUT
VREFIN
BWSEL
U1
GND2
GND3
+5A2
AINB
AIN
+5A3
GND4
ENCODE
OR
(LSB) D0
(MSB) D9
C1
0.1mF
0.1mF
0.1mF
0.1mF
3
6
C2
E2 E1
C3
C7
2
3
4
5
6
7
8
9
10
11
12
13
14
C8
0.1mF
C9
0.1mF
GND
GND
V
DD
GND
V
DD
GND
10
10
74AC00
9
V
DD
10
12
13
U3
74AC00
U3
8
11
74AC00
Figure 29. Evaluation Board Schematic
0.311 (7.9)
0.301 (7.64)
0.078 (1.98)
0.068 (1.73)
0.008 (0.203)
0.002 (0.050)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead SSOP
(RS-28)
0.407 (10.34)
0.397 (10.08)
28 15
PIN 1
0.0256
(0.65)
BSC
0.015 (0.38)
0.010 (0.25)
SEATING
PLANE
–12–
0.212 (5.38)
141
0.07 (1.79)
0.066 (1.67)
0.009 (0.229)
0.005 (0.127)
0.205 (5.21)
8°
0°
PRINTED IN U.S.A.
0.03 (0.762)
0.022 (0.558)
REV. A
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