Datasheet AD9050 Datasheet (Analog Devices)

+5V

10 BITS

0.1µF

0.1µF

0.1µF

ENCODE

(2)

74AC574

3

4

10

5

6

9

1, 7, 12,

21, 23

13

2, 8, 11,

20, 22

AD9050

AIN

(+3.3V ± 0.512V)

+5V

10-Bit, 40 MSPS/60 MSPS

a

FEATURES
Low Power: 315 mW @ 40 MSPS, 345 mW @ 60 MSPS
On-Chip T/H, Reference
Single +5 V Power Supply Operation
Selectable 5 V or 3 V Logic I/O
SNR: 53 dB Minimum at 10 MHz w/40 MSPS

APPLICATIONS
Medical Imaging
Instrumentation
Digital Communications
Professional Video

PRODUCT DESCRIPTION

The AD9050 is a complete 10-bit monolithic sampling analog­to-digital converter (ADC) with an onboard track-and-hold and
reference. The unit is designed for low cost, high performance
applications and requires only +5 V and an encode clock to
achieve 40 MSPS or 60 MSPS sample rates with 10-bit resolution.

The encode clock is TTL compatible and the digital outputs
are CMOS; both can operate with 5 V/3 V logic, selected by the
user. The two-step architecture used in the AD9050 is opti­mized to provide the best dynamic performance available while
maintaining low power consumption.

A 2.5 V reference is included onboard, or the user can provide
an external reference voltage for gain control or matching of
multiple devices. Fabricated on an advanced BiCMOS pro­cess, the AD9050 is packaged in space saving surface mount
packages (SOIC, SSOP) and is specified over the industrial
(–40°C to +85°C) temperature range. The 60 MSPS version
(AD9050BRS-60) is only available in the SSOP package.

AINB

AIN

ENCODE

A/D Converter

AD9050

FUNCTIONAL BLOCK DIAGRAM

GND

+5V

+5V

AD9050

T/H

TIMING

Figure 1. Typical Connections

SUM
AMP

REFERENCE CKTS

ADC

DAC

ADC

DECODE

LOGIC

10

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

AD9050–SPECIFICA TIONS

(VD, VDD = +5 V; internal reference; ENCODE = 40 MSPS for BR/BRS, 60 MSPS for BRS-60

ELECTRICAL CHARACTERISTICS

Parameter Temp Level Min Typ Max Min Typ Max Units

RESOLUTION 10 10 Bits
DC ACCURACY

Differential Nonlinearity +25°C I 0.75 1.75 0.85 1.85 LSB

Full V 1.0 1.1 LSB

Integral Nonlinearity +25°C I 1.0 1.75 1.25 2.0 LSB

Full V 1.25 1.50 LSB
No Missing Codes Full IV GUARANTEED GUARANTEED
Gain Error +25°CI ±1.0 7.5 ±1.0 8.5 % FS
Gain Tempco

ANALOG INPUT

Input Voltage Range +25°C V 1.024 1.024 V p-p
Input Offset Voltage +25°C I –10 +7 +25 –10 +7 +25 mV

Input Resistance +25°C I 3.5 5.0 6.5 3.5 5.0 6.5 kΩ
Input Capacitance +25°CV 5 5 pF
Analog Bandwidth +25°C V 100 100 MHz

BANDGAP REFERENCE

Output Voltage +25°C I 2.4 2.5 2.6 2.4 2.5 2.6 V
Temperature Coefficient

1

Full V ±100 ±100 ppm/°C

Full IV –32 +51 –32 +51 mV

1

Full V ± 50 ± 50 ppm/°C

unless otherwise noted)

Test AD9050BR/BRS AD9050BRS-60

SWITCHING PERFORMANCE

Maximum Conversion Rate +25°C I 40 60 MSPS
Minimum Conversion Rate +25°C IV 1.5 3 1.5 3 MSPS
Aperture Delay (t
Aperture Uncertainty (Jitter) +25°C V 5 5 ps, rms
Output Propagation Delay (tPD)

) +25°C V 2.7 2.7 ns

A

2

Full IV 5 15 5 15 ns

DYNAMIC PERFORMANCE

Transient Response +25°C V 10 10 ns
Overvoltage Recovery Time +25°C V 10 10 ns
ENOBS

f

= 2.3 MHz +25°C V 8.93 8.93 ENOBs

IN

f

= 10.3 MHz +25°C I 8.51 8.85 8.15 8.51 ENOBs

IN

Signal-to-Noise Ratio (SINAD)

3

fIN = 2.3 MHz +25°C V 55.5 55.5 dB
f

= 10.3 MHz +25°C I 53 55 51 53 dB

IN

Signal-to-Noise Ratio

(Without Harmonics)

f

= 2.3 MHz +25°C V 56 56 dB

IN

f

= 10.3 MHz +25°C I 53.5 55.5 51.5 54.0 dB

IN

2nd Harmonic Distortion

f

= 2.3 MHz +25°C V –69 –69 dBc

IN

f

= 10.3 MHz +25°C I –67 –60 –64 –58.5 dBc

IN

3rd Harmonic Distortion

f

= 2.3 MHz +25°C V –75 –75 dBc

IN

f

= 10.3 MHz +25°C I –70 –58 –62 –57.5 dBc

IN

Two-Tone Intermodulation

Distortion (IMD)

4

+25°C V 65 65 dBc
Differential Phase +25°C V 0.15 0.15 Degrees
Differential Gain +25°C V 0.25 0.25 %

–2–

REV. B

AD9050

Test AD9050BR/BRS AD9050BRS-60

Parameter Temp Level Min Typ Max Min Typ Max Units

ENCODE INPUT

Logic “1” Voltage Full IV 2.0 2.0 V
Logic “0” Voltage Full IV 0.8 0.8 V
Logic “1” Current Full IV 1 1 µA
Logic “0” Current Full IV 1 1 µA
Input Capacitance +25°C V 10 10 pF
Encode Pulse Width High (t
Encode Pulse Width Low (tEL) +25°C IV 10 166 6.7 166 ns

DIGITAL OUTPUTS

Logic “1” Voltage Full IV 4.95 4.95 V
Logic “0” Voltage Full IV 0.05 0.05 V
Logic “1” Voltage (3.0 V
Logic “0” Voltage (3.0 V
Output Coding Offset Binary Code Offset Binary Code

) +25°C IV 10 166 6.7 166 ns

EH

) Full IV 2.95 2.95 V

DD

) Full IV 0.05 0.05 V

DD

POWER SUPPLY

V

, VDD Supply Current

D

Power Dissipation
Power Supply Rejection Ratio

(PSRR)

NOTES

1

“Gain Tempco” is for converter only; “Temperature Coefficient” is for bandgap reference only.

2

Output propagation delay (tPD) is measured from the 50% point of the rising edge of the encode command to the midpoint of the digital outputs with 10 pF maximum
loads.

3

RMS signal to rms noise with analog input signal 0.5 dB below full scale at specified frequency for BR/BRS, 1.0 dB below full scale for BRS-60.

4

Intermodulation measured relative to either tone with analog input frequencies of 9.5 MHz and 9.9 MHz at 7 dB below full scale.

5

Power dissipation is measured at full update rate with AIN of 10.3 MHz and digital outputs loaded with 10 pF maximum. See Figure 4 for power dissipation at other
conditions.

6

Measured as the ratio of the change in offset voltage for 5% change in +VD.

Specifications subject to change without notice.

6

EXPLANATION OF TEST LEVELS

Test Level

I – 100% Production Tested.
IV – Parameter is guaranteed by design and characteriza-

tion testing.

V – Parameter is a typical value only.

5

5

Full IV 40 63 80 40 69 87.2 mA
Full IV 315 400 345 486 mW

+25°CI ±10 ±10 mV/V

ABSOLUTE MAXIMUM RATINGS*

VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V

ANALOG IN . . . . . . . . . . . . . . . . . . . . . . –1.0 V to V

Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V

V

Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V

REF

+ 1.0 V

D

D
D

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Operating Temperature

AD9050BR/BRS/BRS-60 . . . . . . . . . . . . . . .–40°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.

REV. B

ORDERING GUIDE

Model Temperature Range Package Option*

AD9050BR –40°C to +85°C R-28
AD9050BRS –40°C to +85°C RS-28
AD9050BRS-60 – 40°C to +85°C RS-28

*R = Small Outline (SO); RS = Shrink Small Outline (SSOP).

–3–

AD9050

WARNING!

ESD SENSITIVE DEVICE

Table I. AD9050 Digital Coding (Single Ended Input AIN, AINB Bypassed to GND)

OR Digital Output

Analog Input Voltage Level (Out of Range) MSB . . . LSB

3.813 Positive Full Scale + 1 LSB 1 1111111111

3.300 Midscale 0 0111111111

2.787 Negative Full Scale – 1 LSB 1 0000000000

PIN FUNCTION DESCRIPTIONS

Pin No Name Function

1, 7, 12, 21, 23 GND Ground.
2, 8, 11 V
3VREF
4 VREF

D

OUT
IN

5 COMP Internal compensation pin, 0.1 µF bypass connected here to V
6 REF

BP

9 AINB Complementary analog input pin (Analog input bar).
10 AIN Analog input pin.
13 ENCODE Encode clock input to ADC. Internal T/H is placed in hold mode (ADC is encoding)

14 OR Out of range signal. Logic “0” when analog input is in nominal range. Logic “1” when
15 D9 (MSB) Most significant bit of ADC output.

16–19 D8–D5 Digital output bits of ADC.
20, 22 V

DD

24–27 D4–D1 Digital output bits of ADC.
28 D0 (LSB) Least significant bit of ADC output.

Analog +5 V ± 5% power supply.
Internal bandgap voltage reference (nominally +2.5 V).
Input to reference amplifier. Voltage reference for ADC is connected here.

(+5 V).

D

External connection for (0.1 µF) reference bypass capacitor.

on rising edge of encode signal.
analog input is out of nominal range.

Digital output power supply (only used by digital outputs).

PIN CONFIGURATION

GND

1

V

2

D

VREF

3

OUT

VREF

4

IN

5
6

REF

BP

GND

AINB

GND

ENCODE

AD9050

7

TOP VIEW

8

V

(Not to Scale)

D

9

AIN D5

10
11

V

D

12
13

OR

14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

D0 (LSB)
D1
D2
D3
D4COMP
GND
V

DD

GND
V

DD

D6
D7
D8
D9 (MSB)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9050 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. B

N N + 1 N + 2 N + 3 N + 4 N + 5

AD9050

AIN

ENCODE

DIGITAL

OUTPUTS

tEHt

AINB (Pin 9)

AIN (Pin 10)

t

A

EL

t

PD

N – 5 N – 4 N – 3 N – 2 N – 1 N

Figure 2. Timing Diagram

V

D

INPUT

8k

8k

16k

BUFFER

16k

VDD (Pins 20, 22)

Output Stage

V

D

VREF

OUT

(Pin 3)

VREF

(Pin 4)

+3V to +5V

IN

MIN TYP MAX

t

APERTURE DELAY 2.7ns

A

t

PULSE WIDTH HIGH 10ns* 166ns

EH

t

PULSE WIDTH LOW 10ns* 166ns

EL

t

OUTPUT PROP DELAY 5.0ns 8.2ns 15.0ns

PD

*FOR BR/BRS, SEE SPECIFICATION TABLE

D0–D9, OR

ENCODE

(Pin 13)

Encode InputAnalog Input

V

D

A

V

VREF

BF

(Pin 6)

V

D

V

REF

Output

Reference Circuit

Figure 3. Equivalent Circuits

REV. B

–5–

AD9050–Typical Performance Curves

350

340

330

320

310

300

290

DISSIPATION – mW

280

270

260

250

10

0

20 30 40 50 60

CLOCK RATE – MSPS

5V

3V

Figure 4. Power Dissipation vs. Clock Rate

80

74

68

62

dB

56

50

44

38

1 10 100

HD 40

HD 60

SNR 40

SNR 60

ANALOG INPUT FREQUENCY – MHz

60
59

58

57

56

55

(SINAD)

54

53

SIGNAL-TO-NOISE RATIO – dB

52

51

50

– 20

–40

0

ENCODE = 40 MSPS
A

= 10.3 MHz

IN

20 40 60 80

TEMPERATURE – °C

Figure 7. SNR vs. Temperature

0

–10
–20
–30
–40
–50
–60

dB

–70
–80

–90
–100
–110
–120

0202.5 5 7.5 10 12.5 15 17.5
FREQUENCY – MHz

ENCODE = 40 MSPS
f1 IN = 9.5 MHz @ –7 dBFS
f2 IN = 9.9 MHz @ –7 dBFS
2f1–f2 = –65.4 dBc
2f2–f1 = –65.0 dBc

Figure 5. SNR/Distortion vs. Frequency

58

56

54

52

SNR – dB

50

48

46

0

10

20 30

CLOCK RATE – MSPS

SNR

40 60

Figure 6. SNR vs. Clock Rate

Figure 8. Two-Tone IMD

0.50

0.25

0.00

–0.25

DIFF GAIN – %

–0.50

–0.25

DIFF PHASE – Degrees

50

–0.50

123456

0.50

0.25

0.00

123456

Figure 9. Differential Gain/Differential Phase

–6–

REV. B

AD9050

TEMPERATURE – °C

15.0

10.0

–40 – 20

t

PD

–

ns

020406080

14.0

11.0

9.0

8.0

13.0

12.0

[1] - 5V DATA RISING EDGE
[2] - 5V DATA FALLING EDGE
[3] - 3V DATA RISING EDGE
[4] - 3V DATA FALLING EDGE

7.0

6.0

5.0
100

[3]
[1]

[4]

[2]

0

–10
–20
–30
–40
–50
–60

dB

–70
–80

–90
–100
–110
–120

0202.5 5 7.5 10 12.5 15 17.5

ENCODE = 40 MSPS
ANALOG IN = 2.3 MHz
SNR = 55.1 dB
SNR (W/O HAR) = 55.5 dB
2ND HARMONIC = 69.3 dB
3RD HARMONIC = 72.9 dB

FREQUENCY – MHz

Figure 10. FFT Plot 40 MSPS, 2.3 MHz

0
–10
–20

–30
–40

–50

dB

–60

–70
–80

–90

–100

02051015

FREQUENCY – MHz

ENCODE = 60 MSPS
ANALOG IN = 10.3 MHz
SNR = 55.8 dB
SNR (W/O HAR) = 56.2 dB
2ND HARMONIC = 67.2 dB
3RD HARMONIC = 73.2 dB

25 30

60

54

48

(SINAD)

42

SIGNAL-TO-NOISE – dB

36

30

25 4540 50 55

SINAD_40

SINAD_60

DUTY CYCLE – %

Figure 13. SNR vs. Clock Pulse Width

1.0

0.5

0.0

–0.5
–1.0
–1.5
–2.0

ADC GAIN – dB

–2.5
–3.0
–3.5
–4.0
–4.5

1

10

ANALOG INPUT FREQUENCY – MHz

100

AIN = 10.3 MHz

60 65

1000

REV. B

Figure 11. FFT Plot 60 MSPS, 10.3 MHz

0
–10

ENCODE = 40 MSPS
ANALOG IN = 10.3 MHz

–20

SNR = 54.6 dB
SNR (W/O HAR) = 55.2 dB

–30

2ND HARMONIC = 66.4 dB

–40

3RD HARMONIC = 70.5 dB

–50
–60

dB

–70
–80
–90

–100
–110
–120

0202.5 5 7.5 10 12.5 15 17.5
FREQUENCY – MHz

Figure 12. FFT Plot 40 MSPS, 10.3 MHz

Figure 14. ADC Gain vs. AIN Frequency

Figure 15. tPD vs. Temperature 3 V/5 V

–7–

AD9050

THEORY OF OPERATION

Refer to the block diagram on the front page.
The AD9050 employs a subranging architecture with digital

error correction. This combination of design techniques en­sures true 10-bit accuracy at the digital outputs of the converter.

At the input, the analog signal is buffered by a high speed differ­ential buffer and applied to a track-and-hold (T/H) that holds
the analog value present when the unit is strobed with an
ENCODE command. The conversion process begins on the
rising edge of this pulse. The two stage architecture completes a
coarse and then a fine conversion of the T/H output signal.

Error correction and decode logic correct and align data from
the two conversions and present the result as a 10-bit parallel
digital word. Output data are strobed on the rising edge of the
ENCODE command. The subranging architecture results in
five pipeline delays for the output data. Refer to the AD9050
Timing Diagram.

USING THE AD9050
3 V System

The digital input and outputs of the AD9050 can be easily
configured to directly interface to 3 V logic systems. The en­code input (Pin 13) is TTL compatible with a logic threshold of

1.5 V. This input is actually a CMOS stage (refer to Equivalent
Encode Input Stage) with a TTL threshold, allowing operation
with TTL, CMOS and 3 V CMOS logic families. Using 3 V
CMOS logic allows the user to drive the encode directly without
the need to translate to +5 V. This saves the user power and
board space. As with all high speed data converters, the clock
signal must be clean and jitter free to prevent the degradation of
dynamic performance.

The AD9050 outputs can also directly interface to 3 V logic
systems. The digital outputs are standard CMOS stages (refer
to AD9050 Output Stage) with isolated supply pins (Pins 20, 22
V

). By varying the voltage on the VDD pins, the digital output

DD

levels vary respectively. By connecting Pins 20 and 22 to the
3 V logic supply, the AD9050 will supply 3 V output levels.
Care should be taken to filter and isolate the output supply of
the AD9050 as noise could be coupled into the ADC, limiting
performance.

Analog Input

The analog input of the AD9050 is a differential input buffer
(refer to AD9050 Equivalent Analog Input). The differential
inputs are internally biased at +3.3 V, obviating the need for
external biasing. Excellent performance is achieved whether the
analog inputs are driven single-ended or differential (for best
dynamic performance, impedances at AIN and AINB should
match).

Figure 16 shows typical connections for the analog inputs when
using the AD9050 in a dc coupled system with single ended
signals. All components are powered from a single +5 V supply.
The AD820 is used to offset the ground referenced input signal
to the level required by the AD9050.

AC coupling of the analog inputs of the AD9050 is easily ac­complished. Figure 17 shows capacitive coupling of a single
ended signal while Figure 18 shows transformer coupling differ­entially into the AD9050.

1kΩ

V

IN

–0.5V to +0.5V

1kΩ

0.1µF

1kΩ

1kΩ

+5V

AD8041

+5V

AD820

+5V

10

AD9050

9

0.1µF

Figure 16. Single Supply, Single Ended, DC Coupled
AD9050

1kΩ

V

IN

–0.5V to +0.5V

1kΩ

+5V

–5V

0.1µF

AD8011

0.1µF

+5V

10

AD9050

9

Figure 17. Single Ended, Capacitively Coupled AD9050

1kΩ

V

IN

–0.5V to +0.5V

1kΩ

+5V

–5V

AD8011

0.1µF

50Ω

T1-1T

+5V

10

AD9050

9

Figure 18. Differentially Driven AD9050 Using Trans­former Coupling

The AD830 provides a unique method of providing dc level shift
for the analog input. Using the AD830 allows a great deal of
flexibility for adjusting offset and gain. Figure 19 shows the
AD830 configured to drive the AD9050. The offset is provided
by the internal biasing of the AD9050 differential input (Pin 9).
For more information regarding the AD830, see the AD830
data sheet.

V

IN

–0.5V to +0.5V

1
2
3
4

+15V

AD830

–5V

710

9

0.1µF

+5V

AD9050

Figure 19. Level Shifting with the AD830

–8–

REV. B

AD9050

Overdrive of the Analog Input

Special care was taken in the design of the analog input section
of the AD9050 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is +2.788 V to

3.812 V (1.024 V p-p centered at 3.3 V). Out-of-range com­parators detect when the analog input signal is out of this range
and shut the T/H off. The digital outputs are locked at their
maximum or minimum value (i.e., all “0” or all “1”). This pre­cludes the digital outputs from changing to an invalid value
when the analog input is out of range.

When the analog input signal returns to the nominal range, the
out-of-range comparators switch the T/H back to the active
mode and the device recovers in approximately 10 ns.

The input is protected to one volt outside the power supply
rails. For nominal power (+5 V and ground), the analog input
will not be damaged with signals from +6.0 V to –1.0 V.

Timing

The performance of the AD9050 is very insensitive to the duty
cycle of the clock. Pulse width variations of as much as ± 10%
will cause no degradation in performance. (see Figure 13, SNR
vs. Clock Pulse Width).

The AD9050 provides latched data outputs, with five pipeline
delays. Data outputs are available one propagation delay (t

PD

)
after the rising edge of the encode command (refer to the
AD9050 Timing Diagram). The length of the output data lines
and loads placed on them should be minimized to reduce tran­sients within the AD9050; these transients can detract from the
converter’s dynamic performance.

The minimum guaranteed conversion rate of the AD9050 is
3 MSPS. Below a nominal of 1.5 MSPS the internal T/H
switches to a track function only. This precludes the T/H from
drooping to the rail during the conversion process and mini­mizes saturation issues. At clock rates below 3 MSPS dynamic
performance degrades. The AD9050 will operate in burst mode
operation, but the user must flush the internal pipeline each
time the clock stops. This requires five clock pulses each time
the clock is restarted for the first valid data output (refer to Fig­ure 2 Timing Diagram).

Power Dissipation

The power dissipation specification in the parameter table is
measured under the following conditions: encode is 40 MSPS
or 60 MSPS, analog input is –0.5 dBFS at 10.3 MHz, the digi­tal outputs are loaded with approximately 7 pF (10 pF maxi­mum) and V

is 5 V. These conditions intend to reflect actual

DD

usage of the device.
As shown in Figure 4, the actual power dissipation varies based

on these conditions. For instance, reducing the clock rate will
reduce power as expected for CMOS-type devices. Also the
loading determines the power dissipated in the output stages.
From an ac standpoint, the capacitive loading will be the key
(refer to Equivalent Output Stage).

The analog input frequency and amplitude in conjunction with
the clock rate determine the switching rate of the output data
bits. Power dissipation increases as more data bits switch at
faster rates. For instance, if the input is a dc signal that is out of
range, no output bits will switch. This minimizes power in the
output stages, but is not realistic from a usage standpoint.

The dissipation in the output stages can be minimized by inter­facing the outputs to 3 V logic (refer to USING THE AD9050,
3 V System). The lower output swings minimize consumption.
Refer to Figure 4 for performance characteristics.

Voltage Reference

A stable and accurate +2.5 V voltage reference is built into the
AD9050 (Pin 3, V

Output). In normal operation the internal

REF

reference is used by strapping Pins 3 and 4 of the AD9050 to­gether. The internal reference has 500 µA of extra drive current
that can be used for other circuits.

Some applications may require greater accuracy, improved tem­perature performance, or adjustment of the gain of the AD9050,
which cannot be obtained by using the internal reference. For
these applications, an external +2.5 V reference can be used to
connect to Pin 4 of the AD9050. The VREF

requires 5 µA of

IN

drive current.
The input range can be adjusted by varying the reference volt-

age applied to the AD9050. No appreciable degradation in per­formance occurs when the reference is adjusted ± 5%. The
full-scale range of the ADC tracks reference voltage changes
linearly.

REV. B

–9–

AD9050

Figure 20. Evaluation Board Top Layer

Figure 21. Evaluation Board Ground Layer

Figure 22. Evaluation Board Bottom Layer

Figure 23. Silkscreen

–10–

REV. B

AD9050

U3

74AC574R

9

C14

0.1µF

8D

8

7D

7

6D

6

5D

5

4D

4

3D

3

2D

2

1D

74AC574R

9

8D

8

7D

7

6D

6

5D

5

4D

4

3D

3

2D

2

1D

CK

11

CK

11

C15

0.1µF

U1

R5
1k

3

OUT

Y1

SW41

+5V

C9

0.1µF

6

GND

C7

0.1µF

TP3

TP1

C1

0.1µF

C2

0.1µF

C3

0.1µF

2

R2
2k

+5V

+5V

2

IN
IN

3

R1
50

+5V

12
13

U6:D
74AC00R

J1

10µF

U2
AD9631Q

6

OUT

U6:B
74AC00R

4
5

4

VCC

11

J6

+

C5

R4

J2

1k

R3
50

J7

AD9050R

15

D9/MSB

+5V
+5V

E1

C12

0.1µF

16

D8

17

D7

18

D6

19

D5

24

D4

25

D3

26

D2

27

D1

28

D0

20
22

TP2

+5V

3

8

C13

0.1µF

3

VREF

OUT

4

VREF

IN

5

COMP

6

REF

BP

9

AINB

10

AIN

13

ENC

14

OR

+5V

U6:A
74AC00R

1
2

9

10

U6:C
74AC00R

C10

0.1µF

U4

12

8Q

13

7Q

14

6Q

15

5Q

16

4Q

17

3Q

18

2Q

19

1Q

OE

1

12

8Q

13

7Q

14

6Q

15

5Q

16

4Q

17

3Q

18

2Q

19

1Q

OE

1

C16

C17

C22

0.1µF

0.1µF

0.1µF

C23

0.1µF

+5V

HDR20

20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

C24

0.1µF

J3

J5

C6

10µF

+

C8

0.1µF

–5.2V

–5.2V

C20

0.1µF

Figure 24. Evaluation Board Schematic

REV. B

–11–

AD9050

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead SOIC

(R-28)

0.7125 (18.10)

0.6969 (17.70)

28 15

141

0.2992 (7.60)

0.2914 (7.40)

0.4193 (10.65)

C2048b–2–3/97

0.3937 (10.00)

PIN 1

0.0118 (0.30)

0.0040 (0.10)

0.311 (7.9)

0.078 (1.98)

0.068 (1.73)

0.008 (0.203)

0.002 (0.050)

0.0500
(1.27)

BSC

28 15

0.301 (7.64)

PIN 1

0.0256
(0.65)

BSC

0.0192 (0.49)

0.0138 (0.35)

28-Lead SSOP

0.407 (10.34)

0.397 (10.08)

0.015 (0.38)

0.010 (0.25)

0.1043 (2.65)

0.0926 (2.35)

SEATING

PLANE

(RS-28)

141

0.07 (1.79)

0.066 (1.67)

SEATING

PLANE

0.0125 (0.32)

0.0091 (0.23)

0.212 (5.38)

0.205 (5.21)

0.009 (0.229)

0.005 (0.127)

0.0291 (0.74)

0.0098 (0.25)

8°
0°

8°
0°

x 45°

0.0500 (1.27)

0.0157 (0.40)

0.03 (0.762)

0.022 (0.558)

–12–

PRINTED IN U.S.A.

REV. B