Datasheet AD9040A Datasheet (Analog Devices)

10-Bit 40 MSPS

A/D Converter

AD9040A

FEATURES
Low Power: 940 mW
53 dB SNR @ 10 MHz A

IN

On-Chip Track-and-Hold, Reference
CMOS Compatible
2 V p-p Analog Input
Fully Characterized Dynamic Performance

APPLICATIONS
Ultrasound Medical Imaging
Digital Oscilloscopes
Professional Video
Digital Communications
Advanced Television (MUSE Decoders)
Instrumentation

GENERAL DESCRIPTION

The AD9040A is a complete 10-bit monolithic sampling analog­to-digital converter (ADC) with on-board track-and-hold (T/H)
and reference. The unit is designed for low cost, high perfor­mance applications and requires only an encode signal to achieve
40 MSPS sample rates with 10-bit resolution.

Digital inputs and outputs are CMOS compatible; the analog
input requires a signal of 2 V p-p amplitude. The two-step
architecture used in the AD9040A is optimized to provide the
best dynamic performance available while maintaining low
power requirements of only 940 mW typically; maximum dissi­pation is 1.1 W at 40 MSPS.

The signal-to-noise ratio (SNR), including harmonics, is 53 dB,
or 8.5 ENOB, when sampling an analog input of 10.3 MHz at
40 MSPS. Competitive devices perform at less than 7.5 ENOB
and require external references and larger input signals.

The AD9040A A/D converter is available in either a 28-lead
PDIP or a 28-lead SOIC package. The two models operate over
a commercial temperature range of 0°C to 70°C. Contact the
factory regarding availability of ceramic military temperature
range devices.

FUNCTIONAL BLOCK DIAGRAM

ENCODE

AMP

ARRAY

ERROR

CORRECTION

6-BIT

ADC

DECODE

LOGIC

10

GND

BP

A

IN

V

OUT

V

REF

REF

T/H T/H T/H

BAND GAP

REFERENCE

REF
AMP

AD9040A

5-BIT

ADC

DECODE

LOGIC

PRODUCT HIGHLIGHTS

1. CMOS compatible logic for direct interface to ASICs.

2. On-board track-and-hold provides excellent high frequency
performance on analog inputs, critical for communications
and medical imaging applications.

3. High input impedance and 2 V p-p input range reduce need
for external amplifiers.

4. Easy to use; no cumbersome external voltage references
required, allowing denser packing of ADCs for multichannel
applications.

5. Available in 28-lead PDIP and SOIC packages.

6. Evaluation board includes AD9040AJR, reconstruction DAC,
and latches. Space is available near the analog input and digital
outputs of the converter for additional circuits. Order as part
number AD9040A/PCB (schematic shown in data sheet).

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

(+VS = VD = +5 V; –VS = –5 V; internal reference: Encode = 40.5 MSPS, unless

AD9040A–SPECIFICATIONS

otherwise noted.)

Test AD9040AJN/AD9040AJR

Parameter (Conditions) Temp Level Min Typ Max Unit

RESOLUTION 10 Bits

DC ACCURACY

Differential Nonlinearity 25°CI 1.0 2.0 LSB

Full VI 2.5 LSB

Integral Nonlinearity 25°CI 1.0 2.25 LSB

Full VI 2.5 LSB
No Missing Codes Full VI Guaranteed
Gain Error 25°CI ± 0.5 ± 1.5 % FS

Gain Temperature Coefficient

1

Full VI ± 2% FS

Full V ± 70 ppm/°C

ANALOG INPUT

Input Voltage Range 25°CV 2 V p-p
Input Offset Voltage 25°CI ± 2 ± 25 mV

Full VI ± 30 mV
Input Bias Current 25°CI 7 15 µA

Full VI 25 µA
Input Resistance 25°CI 200 350 kΩ
Input Capacitance 25°CV 5 pF
Analog Bandwidth 25°CV 48 MHz

BAND GAP REFERENCE

Output Voltage Full VI 2.4 2.6 V
Temperature Coefficient

1

Full V ± 40 ppm/°C

SWITCHING PERFORMANCE

Maximum Conversion Rate 25°CI 40 MSPS
Minimum Conversion Rate 25°CIV210 MSPS
Aperture Delay (t
Aperture Uncertainty (Jitter) 25°CV 7 ps, rms
Output Propagation Delay (t

)25°CV 1.9 ns

A

2

PD

)

25°CI 7.5 10 12 ns

Full IV 6 14 ns

DYNAMIC PERFORMANCE

3

Transient Response 25°CV 25 ns
Overvoltage Recovery Time 25°CV 40 ns
Signal-to-Noise Ratio

4

fIN = 2.3 MHz 25°CI 4854 dB

= 10.3 MHz 25°CI 4753 dB

f

IN

Signal-to-Noise Ratio

4

(Without Harmonics)

= 2.3 MHz 25°CI 4955 dB

f

IN

f

= 10.3 MHz 25°CI 4854 dB

IN

Signal-to-Noise Ratio

4, 5

fIN = 2.3 MHz 25°CI 56 dB
f

= 10.3 MHz 25°CI 55 dB

IN

Signal-to-Noise Ratio

4, 5

(Without Harmonics)

f

= 2.3 MHz 25°CI 57 dB

IN

= 10.3 MHz 25°CI 56 dB

f

IN

Second Harmonic Distortion

= 2.3 MHz 25°CI 5667 dBc

f

IN

= 10.3 MHz 25°CI 5665 dBc

f

IN

Third Harmonic Distortion

= 2.3 MHz 25°CI 5773 dBc

f

IN

= 10.3 MHz 25°CI 5770 dBc

f

IN

Two-Tone Intermodulation

6

25°CV 62 dBc

Distortion Rejections
Differential Phase 25°C III 0.15 0.5 Degrees
Differential Gain 25°C III 0.25 1.0 %

REV. D–2–

AD9040A

Test AD9040AJN/AD9040AJR

Parameter (Conditions) Temp Level Min Typ Max Unit

ENCODE INPUT

Logic 1 Voltage Full VI 4.0 V
Logic 0 Voltage Full VI 1.0 V
Logic 1 Current Full VI ± 1 µA
Logic 0 Current Full VI ± 1 µA
Input Capacitance 25°CV 14 pF
Encode Pulsewidth (High) (t
Encode Pulsewidth (Low) (tEL)

DIGITAL OUTPUTS

Logic 1 Voltage Full VI 4.95 V
Logic 0 Voltage Full VI 0.05 V
Output Coding Offset Binary

POWER SUPPLY

Supply Current Full VI 13 20 mA

V

D

+VS Supply Current Full VI 89 110 mA
–V

Supply Current Full VI 87 105 mA

S

Power Dissipation Full VI 0.94 1.2 W
Power Supply Rejection Ratio (PSRR)825°CI ± 15 mV/V

NOTES

1

Gain temperature coefficient is for a converter using internal reference; temperature coefficient is for band gap reference only.

2

Output propagation delay (tPD) is measured from the 50% point of the falling edge of the encode command to the min/max voltage levels of the digital outputs with
10 pF maximum loads.

3

Minimum values apply to AD9040AJR only.

4

RMS signal to rms noise with analog input signal 1 dB below full scale at specified frequency.

5

Encode = 32 MSPS.

6

Third order intermodulation measured with analog input frequencies of 2.3 MHz and 2.4 MHz at 7 dB below full scale.

7

For rated performance at 40 MSPS, duty cycle of encode command should be 50% ±10%.

8

Measured as the ratio of the change in offset voltage for a 5% change in +VS or –VS.

Specifications subject to change without notice.

EH

7

)

7

25°CIV 10 100 ns
25°CIV 10 100 ns

EXPLANATION OF TEST LEVELS

Test Level

I 100% production tested.

II 100% production tested at 25°C and sample tested at speci-

fied temperatures. AC testing done on sample basis.
III Sample tested only.
IV Parameter is guaranteed by design and characterization

testing.
VParameter is a typical value only.
VI All devices are 100% production tested at 25°C. 100%

production tested at temperature extremes for military tem-

perature devices; guaranteed by design and characterization

testing for industrial devices.

REV. D

–3–

AD9040A

ABSOLUTE MAXIMUM RATINGS

± VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

V

D

Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V

Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +V

V

Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +V

REF

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Operating Temperature

AD9040AJN/AD9040AJR . . . . . . . . . . . . . . . . . 0°C to 70°C

1

Maximum Junction Temperature2 (JN/JR Suffixes) . . . . 150°C

Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . . . . . 300°C

NOTES

to +V

S

1

Absolute maximum ratings are limiting values to be applied individually and

S

beyond which the serviceability of the circuit may be impaired. Functional

S

operability is not necessarily implied. Exposure to absolute maximum rating

S

conditions for an extended period of time may affect device reliability.

2

Typical thermal impedances (parts soldered to board):

N Package (PDIP): ␪JA = 42°C/W; ␪JC = 10°C/W.
R Package (SOIC): ␪JA = 47°C/W; ␪JC = 10°C/W.

Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9040AJN 0°C to 70°C 28-Lead PDIP N-28
AD9040AJR 0°C to 70°C 28-Lead SOIC Package R-28
AD9040AJR-REEL 0°C to 70°C 28-Lead SOIC Package R-28

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9040A features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

A

ENCODE

DIGITAL

OUTPUTS

N

tEHt

t

A

t

N + 1

NO. 2 NO. 3

EL

PD

DESCRIPTIONSYMBOL

APERTURE DELAY

t

A

t

PULSEWIDTH HIGH

EH

t

PULSEWIDTH LOW

EL

OUTPUT PROP DELAY

t

PD

N – 1N – 2N – 3

MIN TYP MAX

1.9ns

10ns

10ns 100ns

7.5ns

10ns

100ns

12ns

IN

Figure 1. Timing Diagram

REV. D–4–

PIN CONFIGURATION

)

PDIP and SOIC

–V

GND

+V

GND

V

OUT

V

REF

BP

REF

NC

ENCODE

+V

GND

–V

A

GND

1

S

2

3

S

4

5

6

AD9040A

7

TOP VIEW

(Not to Scale)

8

9

10

S

11

12

S

13

IN

14

NC = NO CONNECT

28

27

26

25

24

23

22

21

20

19

18

17

16

15

D0 (LSB)

D1

D2

D3

D4

V

GND

–V

D5

D6

D7

D8

D9 (MSB

OR

AD9040A

S

IN

GND

D8

D7

D6

D5

–V

D

S

DGND

+V

S

D

D4
D3

D2

D1

OR

D9 (MSB)

S

–V

D0 (LSB)

GND

DIE LAYOUT AND MECHANICAL INFORMATION

Die Dimensions . . . . . . . . . 204 mils × 185 mils × 21 (± 1) mils

Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 4 mils × 4 mils

Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum

Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None

Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V

Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5,070

Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride

Die Attach (JN/JR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Epoxy

Bond Wire (JN/JR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold

–V

A

GND

S

+V

NC = NO CONNECT

+V

S

ENCODE

NC

BP

REF

V

REF

V

OUT

GND

S

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1, 12, 21 –V

S

5 V Power Supply.

2, 4, 11, 14, 22 GND Ground.

3, 10 +V

5V

6V

7BP

S

OUT

REF

REF

Analog 5 V Power Supply.

Internal Band Gap Voltage Reference (Nominally 2.5 V).

Noninverting Input to Reference Amplifier. Voltage reference for ADC is connected here.

External Connection for (0.1 µF) Reference Bypass Capacitor.

8NCNo Connection Internally.

9 ENCODE Encode Clock Input to ADC. Internal track-and-hold placed in hold mode (ADC is encoding)

on rising edge.

13 A

IN

Noninverting Input to Track-and-Hold Amplifier.

15 OR Out-of-Range Condition Output. Active high when analog input exceeds input range of ADC by

1 LSB (< F

– 1 LSB or > +FS + 1 LSB).

S

16 D9 (MSB) Most Significant Bit of ADC Output; TTL/CMOS Compatible.

17–20 D8–D5 Digital Output Bits of ADC; TTL/CMOS Compatible.

23 V

D

Digital +5 V Power Supply.

24–27 D4–D1 Digital Output Bits of ADC; TTL/CMOS Compatible.

28 D0 (LSB) Least Significant Bit of ADC Output; TTL/CMOS Compatible.

REV. D

–5–

AD9040A

DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by FFT analysis) is
reduced by 3 dB.

Aperture Delay

The delay between the rising edge of the encode command and
the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Differential Gain

The percentage of amplitude change of a small high frequency
sine wave (3.58 MHz) superimposed on a low frequency signal
(15.734 kHz).

Differential Nonlinearity

The deviation of any code from an ideal 1 LSB step.

Differential Phase

The phase change of a small high frequency sine wave (3.58 MHz)
superimposed on a low frequency signal (15.734 kHz).

Harmonic Distortion

The rms value of the fundamental divided by the rms value of
the harmonic.

Integral Nonlinearity

The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal
frequency tested drops by no more than 3 dB below the guar­anteed limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between the 50% point of the falling edge of the encode
command and the 1 V/4 V points of output data.

Overvoltage Recovery Time

The amount of time required for the converter to recover to
10-bit accuracy after an analog input signal 150% of full scale is
reduced to the full-scale range of the converter.

Power Supply Rejection Ratio (PSRR)

The ratio of a change in input offset voltage to a change in power
supply voltage.

Signal-to-Noise Ratio (SNR)

The ratio of the rms signal amplitude to the rms value of noise,
which is defined as the sum of all other spectral components,
including harmonics but excluding dc, with an analog input
signal 1 dB below full scale.

Signal-to-Noise Ratio (Without Harmonics)

The ratio of the rms signal amplitude to the rms value of noise,
which is defined as the sum of all other spectral components,
excluding the first eight harmonics and dc, with an analog input
signal 1 dB below full scale.

Transient Response

The time required for the converter to achieve 10-bit accuracy
when a step function is applied to the analog input.

Two-Tone Intermodulation Distortion (IMD) Rejection

The ratio of the power of either of the two input signals to the
power of the strongest third order IMD signal.

1k⍀ 1k⍀

A

IN

ANALOG INPUT

V

2k⍀

V

V

CC

CC

1mA1mA

SS

1k⍀ 1k⍀

V

REF

GND

REFERENCE CIRCUIT

6.8k⍀

V

CC

R

L

2.5k⍀

BP

REF

V

SS

BAND GAP OUTPUT

GND

V

OUT

R

L

V

CC

GND

CMOS OUTPUT

D0-D9

Figure 2. Equivalent Circuits

REV. D–6–

Typical Performance Characteristics–AD9040A

)

)

5

)

1.2

1.0

0.8

0.6

DISSIPATION (W)

0.4

1

24610204060

CLOCK RATE (MSPS

TPC 1. Power Dissipation
vs. Clock Rate

1.0

0.5

LEAST SIGNIFICANT BITS (LSB)

0

0

10 20 30 40

CLOCK RATE (MSPS

TPC 4. Differential Nonlinearity
vs. Clock Rate

–73

–68

HARMONIC

DISTORTION

–63

SNR

–58

–53

HARMONIC DISTORTION (dBc)

–48

1

24610204060

ENCODE = 40.5MSPS

FREQUENCY (MHz)

TPC 2. Harmonic Distortion
and SNR vs. Analog Input

1024

896

768

640

512

384

256

DIGITAL OUTPUT CODE

128

0

051015 20 25 30 35 40 45 50

TIME (ns)

TPC 5. Transient Response

66

60

54

48

SIGNAL-TO-NOISE RATIO (dB)

42

100

SIGNAL-TO-NOISE RATIO (dB)

1024

992

960

928

DIGITAL OUTPUT CODE

66

60

A

= 10.3MHz

54

48

42

4

IN

12 20 28 36

CLOCK RATE (MSPS

TPC 3. SNR vs. Clock Rate

96

64

32

0

051015 20 25 30 35 40 45 50

TIME (ns)

TPC 6. Transient Response
(Expanded View)

60

ENCODE = 32.2MSPS

55

50

45

SIGNAL-TO-NOISE RATIO (dB)

40

ENCODE = 40.5MSPS

–15 25 85–55 65 105

–35 5 45 12

TEMPERATURE (ⴗC)

TPC 7. SNR vs. Temperature

REV. D

AIN = 10.3MHz

0

–65

dBc

0

FREQUENCY (MHz)

TPC 8. FFT Response

ENCODE = 32.2MSPS
ANALOG IN = 2.3MHz
SNR = 56.79dB
SNR (w/o har.) = 57.58dB
SECOND HARMONIC = –68.5dB
THIRD HARMONIC = 80.7dB

8.0 16.1

–7–

0

ENCODE = 32.2MSPS
ANALOG IN = 10.3MHz
SNR = 55.37dB
SNR (w/o har.) = 56.77dB
SECOND HARMONIC = –63.3dB
THIRD HARMONIC = –75.4dB

–65

dBc

0

FREQUENCY (MHz)

TPC 9. FFT Response

8.0 16.1

AD9040A

)

–65

dBc

0

ENCODE = 40.5MSPS
ANALOG IN = 2.3MHz
SNR = 55.20dB
SNR (w/o har.) = 55.90dB
SECOND HARMONIC = –75.1dB
THIRD HARMONIC = –73.2dB

0

FREQUENCY (MHz)

TPC 11. FFT Response

0

–65

dBc

0

FREQUENCY (MHz

TPC 10. FFT Response

ENCODE = 40.5MSPS
f1 IN = 2.25MHz @ –7dBFS
f2 IN = 2.35MHz @ –7dBFS
2f1 – f2 = –69.4dBFS
2f2 – f1 = –69.2dBFS

2.5 5.0

THEORY OF OPERATION

The AD9040A employs subranging architecture and digital error
correction. This combination of design techniques ensures true
10-bit accuracy at the digital outputs of the converter.

At the input, the analog signal is applied to a track-and-hold
(T/H) that holds the analog value that is present when the
unit is strobed with an encode command. The conversion
process begins on the rising edge of this pulse, which should
have a 50% (± 10%) duty cycle. The minimum encode rate of
the AD9040A is 10 MSPS because of the use of three inter­nal track-and-hold devices.

The held analog value of the first track-and-hold is applied to a
5-bit flash converter and a pair of internal track-and-hold devices
(shown in the Functional Block Diagram as a single unit). The
track-and-hold devices pipeline the analog signal to the ampli­fier array through a residue ladder and switching circuit while the
5-bit flash converter resolves the most significant bits (MSB) of
the held analog voltage.

When the 5-bit flash converter has completed its cycle, its out­put activates 1 of 32 ladder switches; these in turn cause the
correct residue signal to be applied to the error amplifier array.

The output of the error amplifier is applied to a 6-bit flash con­verter whose output supplies the five least significant bits (LSB)
of the digital output along with one bit of error correction for
the 5-bit main range converter.

Decode logic aligns the data from the two converters and pre­sents the result as a 10-bit parallel digital word. The output
stage of the AD9040A is CMOS. Output data are strobed on
the trailing edge of the encode command.

The full-scale range of the AD9040A is determined by the refer­ence voltage applied to the V

(Pin 6) input. This voltage sets

REF

the internal flash and residue ladder voltage drops; these estab­lish the value of the LSB. Because of headroom restraints, the
full-scale range cannot be increased by applying a higher than
specified reference voltage. Conversely, a lower reference volt­age will reduce the full-scale range of the converter but will also
decrease its performance. An internal band gap reference volt­age of 2.5 V is provided to assure optimum performance over
the operating temperature range.

0

ENCODE = 40.5MSPS
ANALOG IN = 10.3MHz
SNR = 53.38dB
SNR (w/o har.) = 54.31dB
SECOND HARMONIC =
–64.7dB
THIRD HARMONIC =
–73.7dB

–65

dBc

10.0 20.2

0

10.0 20.2

FREQUENCY (MHz)

TPC 12. FFT Response

USING THE AD9040A
Timing

The duty cycle of the encode clock for the AD9040A is critical
for obtaining the rated performance of the ADC. Internal
pulsewidths within the track-and-hold are established by the
encode command pulsewidth; to ensure rated performance, the
duty cycle should be held at 50%. Duty cycle variations of less
than ± 10% will cause no degradation in performance.

Operation at encode rates less than 10 MSPS is not recom­mended. The internal track-and-hold saturates, causing erroneous
conversions. This track-and-hold saturation precludes clocking
the AD9040A in burst mode. The 50% duty cycle must be
maintained even for sample rates down to 10 MSPS.

The AD9040A provides latched data outputs, with 2 1/2 pipe­line delays. Data outputs are available one propagation delay
(t

) after the falling edge of the encode command (see Figure 1).

PD

The length of the output data lines and the loads placed on them
should be minimized to reduce transients within the AD9040A;
these transients can detract from the converter’s dynamic per­formance.

Voltage Reference

A stable voltage reference is required to establish the 2 V p-p
range of the AD9040A. There are two options for creating this
reference. The easiest and least expensive way to implement it is
to use the (2.5 V) band gap voltage reference which is internal
to the ADC. Figure 3 illustrates the connections for using the
internal reference. The internal reference has 500 µA of extra
drive current that can be used for other circuits.

AD9040A

–V

0.1␮F

S

BP

V

OUT

V

REF

REF

2.5V

REF

AMP

BAND GAP

REFERENCE

REFERENCE

Figure 3. Using Internal Reference

REV. D–8–

AD9040A

Some applications may require greater accuracy, improved
temperature performance, or adjustment of the gain (input
range) of the AD9040A, which cannot be obtained by using the
internal reference. For these applications, an external 2.5 V
reference can be used, as shown in Figure 4. The V

REF

input

requires 5 µA of drive current.

AD9040A

BAND GAP

REFERENCE

REF

AMP

REFERENCE

REFERENCE

–V

0.1␮F

S

V

OUT

V

0.1␮F

BP

REF

REF

Figure 4. Using External Reference

In applications using multiple AD9040As, slaving the reference
inputs to a single reference output will improve gain tracking
among the ADCs, as shown in Figure 5.

AD9040A

V

OUT

V

REF

BP

–V

AD9040A

V

BP

REF

–V

AD9040A

REF

0.1␮F

S

REF

0.1␮F

S

0.1␮F

0.1␮F

The input range can be varied by adjusting the reference voltage
applied to the AD9040A. By decreasing the reference voltage,
the gain can be reduced approximately 10% with no degrada­tion in performance. Increasing the reference voltage increases
the gain, but for proper operation, the reference voltage should
not exceed 2.6 V.

Time-Gain Control ADC

Ultrasound and sonar systems require an increase in gain versus
time. This allows the system to correct for attenuation of return
pulses. Figure 6 shows the AD600/AD602 amplifier and the
AD9040A ADC configured as a time-gain control analog-to­digital converter. The control voltage ramps from –625 mV to
+625 mV, permitting 40 dB of gain-control range. The voltage
used for gain control can be either a linear ramp or the output
of a voltage-output DAC, such as the AD7242.

GAIN CONTROL

VOLTAGE

–625mV

A1H1

AD600/AD602

+625mV

AD9040A

Figure 6. Ultrasound/Sonar Time-Gain Control
ADC using X-AMP™

Transient Response

Figure 7 illustrates the method for evaluating ADC transient
performance. Two synthesizers are locked in synchronization
but tuned to frequencies that are slightly offset from a 2 to 1
submultiple.

One synthesizer clocks a flat pulse network at a frequency of

19.9609375 MHz to provide the analog input signal; the other
synthesizer output is shaped to provide a CMOS 40 MHz sam­pling clock. At the output of the AD9040A, output data reflects
an interleaved alias of the input pulse. The repetitive sampling
allows the measurement of ADC transient response as shown in
the TPCs in this data sheet.

V

BP

REF

0.1␮F

REF

0.1␮F

–V

S

Figure 5. Slaving Multiple AD9040As to a Single
Internal Reference

In the Specifications table, the gain temperature coefficient
parameter under dc accuracy applies to the ADC when the inter­nal reference is being used. If an external reference is used, its
temperature coefficient must be taken into account to deter­mine overall temperature performance.

REV. D

–9–

MARCONI 2030

SYNTHESIZER

REF

19.9609375MHz

MARCONI 2030

SYNTHESIZER

REF

40MHz

Figure 7. Transient Response Test

FLAT PULSE

NETWORK

SINE

TO

CMOS

ANALOG

IN

AD9040A

ENCODE

OUTPUT

AD9040A

Layout Information

Preserving the accuracy and dynamic performance of the
AD9040A requires that designers pay special attention to the
layout of the printed circuit board.

Analog paths should be kept as short as possible and be properly
terminated to avoid reflections. The analog input and reference
voltage connections should be kept away from digital signal
paths; this reduces the amount of digital switching noise that is
capacitively coupled into the analog section. Digital signal paths
should also be kept short and run lengths should be matched to
avoid propagation delay mismatch. The AD9040A digital out­puts should be buffered or latched close to the device (<2 cm).
This prevents load transients, which may feed back into the device.

In high speed circuits, layout of the ground is critical. A single,
low impedance ground plane on the component side of the
board is recommended. Power supplies should be capacitively
coupled to the ground plane with high quality chip capacitors to
reduce noise in the circuit. Multilayer boards allow designers to
lay out signal traces without interrupting the ground plane and
provide low impedance ground planes. In systems with dedi­cated analog and digital grounds, all grounds of the AD9040A
should be connected to the analog ground plane.

The power supplies of the AD9040A should be isolated from
the supplies used for external devices; this reduces the amount
of noise coupled into the ADC. The digital 5 V connection of
the device (V
be connected to the same supply as +V
necting V

, Pin 23) powers the digital outputs and should

D

to a system digital supply may couple noise into the

D

(Pins 3 and 10). Con-

S

device. Sockets limit dynamic performance and are not recom­mended for use with the AD9040A.

EVALUATION BOARD

The evaluation board for the AD9040A (AD9040A/PCB) pro­vides an easy and flexible method for evaluating the ADC’s

performance without (or prior to) developing a user-specific
printed circuit board. The two-sided board includes a recon­struction DAC and digital output interface and uses the layout
and applications suggestions outlined above. It is available from
Analog Devices at nominal cost.

Generous space is provided near the analog input and digital
outputs to support any additional signal processing components
the user may wish to add. This prototyping area includes through­holes with 100-mil centers to support a variety of component
additions.

Input/Output/Supply Information

Power supply, analog input, clock connections, and reconstructed
output (RC OUTPUT) are identified by labels on the evalua­tion board. Operation of the evaluation board should conform
to the following characteristics.

Table I. Evaluation Board Characteristics

Parameter Typical Unit

Supply Current

+5 V 250 mA
–5.2 V 300 mA

A

IN

Impedance 51 Ω
Voltage Range ± 1.0 V

CLOCK

Impedance 51 Ω
Frequency 40 MSPS

RC OUTPUT

Impedance 51 Ω
Voltage Range 0 V to –1 V V

Analog Input

Analog input signals can be fed directly into the device under
test input (A

). The AIN input is terminated at the device with

IN

a 51 Ω resistor.

REV. D–10–

AD9040A

Figure 8. PCB Top View

DAC Reconstruction

The AD9040A evaluation board provides an onboard AD9721
reconstruction DAC for observing the digitized analog input
signal. The AD9721 is terminated into 51 Ω to provide a 1 V p-p
signal at the output (RC OUTPUT).

Figure 9. PCB Bottom View

Output Data

The output data bits are latched with a CMOS 74AC574 that
drives a 40-pin connector (AMP p/n 102153-9). The data
and clock signals are available on the connector per the pin
assignments shown on the schematic of the evaluation board
(see Figure 10). Output data are available on the falling edge
of the clock.

REV. D

–11–

AD9040A

Analog Input Voltage Level Out-of-Range Digital Output

+1.002 V

Table II. Digital Coding

Positive Full Scale LSB+ 1

MSB . . . LSB

1

1111111111

+1 V

+1/2 V

0 V

–1/2 V

–1 V

–1.002 V

Positive Full Scale

Full Scale LSB– 1

Positive Scale

12 1

/–

Bipolar Zero

12 1

Negative Scale

Full Scale LSB

Negative Full Scale

Negative Full Scale LSB– 1

12

/

Scale LSB

Scale LSB

+

12//

+ 1

0
0

0
0

1111111111

1111111110

1100000000

1011111111

0 10000000000
0 01111111111

0
0

0
0

1

0100000000
0011111111

0000000001
0000000000

0000000000

REV. D–12–

AIN

BNC

J1

BNC

J2

CLK

J7

J8

J9

R1
51⍀

9

10

1

+5V

2

4

5

12
13

C2

0.1␮F

C4

0.1␮F

C7

0.1␮FC80.1␮FC90.1␮F

+5V

R2
51⍀

U1

74HC86

U1

74HC86

U1

74HC86

U1

74HC86

C3
10␮F

C5
10␮F

–5V

11

8

3

6

+5V

CLK

–5V

GND

–5V

C14

0.1␮F

–5V

–5V

–5V

+5V

+5V

+5V

GND

GND

GND

GND

GND

C1

0.1␮F

AD9040AJR

A

IN

V

REF

V

OUT

ENC

–V

S

–V

S

–V

S

+V

S

+V

S

V

D

GND

GND

GND

GND

GND

BP

C15

0.1␮F

C10

0.1␮F

REF

U2

OR

(MSB)

D9

D8

D7

D6

D5

D4

D3

D2

D0

(LSB)

NC

C16

0.1␮F

C11

0.1␮F

AD9040A

U4

74AC574

2

3

4

5

6

7

8

9

9

8

7

6

5

4

C17

0.1␮F

C12

0.1␮F

3

2

D1

1D

1Q

2D

2Q

3D

3Q

4D

4Q

5D

5Q

6D

6Q

7D

7Q

8D

8Q

CK

OE

11

U3

74AC574

8D

7D

6D

5D

4D

3D

2D

1D

CK

OE

11

C13

0.1␮F

C18

0.1␮F

8Q

7Q

6Q

5Q

4Q

3Q

2Q

1Q

19

18

17

E1

16

15

14

13

12

1

12

13

14

15

16

17

18

19

1

CLK

D9
D8
D7
D6

D5
D4
D3

D2

D1

D0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

H40DMC

1

2
3
4
5
6
7
8

9
10

11

12
13
14
15
16
17
18
19
20

R18 100⍀

R17 100⍀

R16 100⍀

R15 100⍀

R14 100⍀

R13 100⍀

R12 100⍀

R11 100⍀

R10 100⍀

R9 100⍀

J3

40
39
38
37
36
35
34
33
32

31
30
29

28
27
26
25
24
23
22
21

GND
GND
GND
GND
GND
GND
GND

GND
GND
GND

GND
GND
GND

GND
GND
GND
GND
GND
GND
GND

AD9721BR

D1 (MSB)

D2

D3

D4

D5

D6

D7

D8

D9

D10 (LSB)

CLOCK

INVERT

H3#4H4

U5

GND

–5V

–5V

GND

CAMP IN

REF OUT

CAMP OUT

REF IN

IOUT

IOUT

ANA RET

RSET

–5V

GND

+5V

H5#4H6

#4

GND

–5V

–5V

GND

C21
10␮F

–5V

–5V

C6

0.1␮F

R6

51⍀

R5
51⍀

–5V

GND

+5V

#4

H1 H2

R7
2k⍀

RC

OUTPUT

BNC
J5

REV. D

Figure 10. PCB Schematic

–13–

AD9040A

OUTLINE DIMENSIONS

28-Lead Plastic Dual In-Line Package [PDIP]

(N-28)

Dimensions shown in millimeters and (inches)

1.565 (39.7)

1.380 (35.1)

28

1

15

0.580 (14.73)

0.485 (12.32)

14

0.250 (6.35)
MAX

0.200 (5.05)

0.115 (2.93)

0.100 (2.54)
BSC

0.022 (0.558)

0.014 (0.356)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-011AB

0.015 (0.39)
MIN

0.70 (1.77)

0.30 (0.77)

SEATING
PLANE

0.625 (15.87)

0.600 (15.24)

0.015 (0.381)

0.008 (0.204)

28-Lead Standard Small Outline Package [SOIC]

Wide Body

(R-28)

Dimensions shown in inches and (millimeters)

18.10 (0.7126)

17.70 (0.6969)

28 15

1

7.60 (0.2992)

7.40 (0.2913)

14

10.65 (0.4193)

10.00 (0.3937)

0.195 (4.95)

0.125 (3.18)

2.65 (0.1043)

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

1.27 (0.0500)

COMPLIANT TO JEDEC STANDARDS MS-013AE

BSC

0.51 (0.0201)

0.33 (0.0130)

2.35 (0.0925)

SEATING
PLANE

0.32 (0.0126)

0.23 (0.0091)

0.75 (0.0295)

0.25 (0.0098)

8ⴗ
0ⴗ

ⴛ 45ⴗ

1.27 (0.0500)

0.40 (0.0157)

REV. D–14–

AD9040A

Revision History

Location Page

5/03—Data Sheet changed from REV. C to REV. D.

Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2/02—Data Sheet changed from REV. B to REV. C.

Edits to Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

REV. D

–15–

C00553–0–5/03(D)

–16–