Datasheet AD9020TZ-883, AD9020TE-883, AD9020SZ-883, AD9020SE-883, AD9020KZ Datasheet (Analog Devices)
...Page 1
10-Bit 60 MSPS
a
FEATURES
Monolithic 10-Bit/60 MSPS Converter
TTL Outputs
Bipolar (ⴞ1.75 V) Analog Input
56 dB SNR @ 2.3 MHz Input
Low (45 pF) Input Capacitance
MIL-STD-883-Compliant Versions Available
APPLICATIONS
Digital Oscilloscopes
Medical Imaging
Professional Video
Radar Warning/Guidance Systems
Infrared Systems
GENERAL DESCRIPTION
The AD9020 A/D converter is a 10-bit monolithic converter
capable of word rates of 60 MSPS and above. Innovative architecture using 512 input comparators instead of the traditional
1024 required by other flash converters reduces input capacitance and improves linearity.
Encode and outputs are TTL-compatible, making the AD9020
an ideal candidate for use in low power systems. An overflow bit is provided to indicate analog input signals greater
than +V
Voltage sense lines are provided to insure accurate driving of the
± V
REF
resistor ladder help optimize the integral linearity of the unit.
Either 68-pin ceramic leaded (gull wing) packages or ceramic
LCCs are available and are specifically designed for low thermal
impedances. Two performance grades for temperatures of both
0°C to 70°C and –55°C to +125°C ranges are offered to allow
the user to select the linearity best suited for each application.
Dynamic performance is fully characterized and production
tested at 25°C. MIL-STD-883 units are available.
The AD9020 A/D Converter is available in versions compliant
with MIL-STD-883. Refer to the Analog Devices Military Products Databook or current AD9020/883B data sheet for detailed
specifications.
.
SENSE
voltages applied to the units. Quarter-point taps on the
ANALOG IN
+V
REF
+V
SENSE
3/4
REF
1/2
REF
1/4
REF
–V
SENSE
–V
REF
ENCODE
A/D Converter
AD9020
FUNCTIONAL BLOCK DIAGRAM
MSB
C
O
M
P
A
R
A
T
O
R
L
A
T
C
H
E
S
INVERT
AD9020
OVERFLOW
1024
–V
S
LSBS
INVERT
D
E
C
O
D
E
L
O
G
I
C
+V
S
10
GROUND
L
A
T
C
H
R/2
R/2
R/2
R/2
R/2
R/2
R/2
OVERFLOW
512
R
385
384
R
R
257
256
R
R
129
128
R
R
2
R
1
R/2
OVERFLOW
D
(MSB)
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D0 (LSB)
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
Page 2
AD9020–SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V
–V
S
ANALOG IN . . . . . . . . . . . . . . . . . . . . . . . . . . . –2 V to +2 V
+V
, –V
, 3/4
+V
REF
REF
REF
to –V
, 1/2
REF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
REF
REF
, 1/4
DIGITAL INPUTS . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +V
ELECTRICAL CHARACTERISTICS
1
. . . . . . . . . . –2 V to +2 V
REF
(ⴞVS = ⴞ5 V; ⴞV
3/4
, 1/2
, 1/4
REF
REF
Current . . . . . . . . . . . . . . . . . . . ± 10 mA
REF
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature
AD9020JE/KE/JZ/KZ . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature
Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . . . . . 300°C
S
= ⴞ1.75 V; ENCODE = 40 MSPS unless otherwise noted)
SENSE
2
. . . . . . . . . . . . . . . . . 150°C
Test AD9020JE/JZ AD9020KE/KZ
Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Unit
RESOLUTION 10 10 Bits
DC ACCURACY
3
Differential Nonlinearity 25°C I 1.0 1.25 0.75 1.0 LSB
Full VI 1.5 1.25 LSB
Integral Nonlinearity 25°C I 1.25 2.75 1.0 2.25 LSB
Full VI 3.0 2.50 LSB
No Missing Codes Full VI Guaranteed
ANALOG INPUT
Input Bias Current
4
25°C I 0.4 1.0 0.4 1.0 mA
Full VI 2.0 2.0 mA
Input Resistance 25°C I 2.0 7.0 2.0 7.0 kΩ
Input Capacitance
4
25°C V 45 45 pF
Analog Bandwidth 25°C V 175 175 MHz
REFERENCE INPUT
Reference Ladder Resistance 25°C I 22 37 56 22 37 56 Ω
Full VI 14 66 14 66 Ω
Ladder Tempco Full V 0.1 0.1 Ω/°C
Reference Ladder Offset
Top of Ladder 25°C I 45 90 45 90 mV
Full VI 90 90 mV
Bottom of Ladder 25°C I 45 90 45 90 mV
Full VI 90 90 mV
Offset Drift Coefficient Full V 50 50 µV/°C
SWITCHING PERFORMANCE
Conversion Rate 25°C I 60 60 MSPS
Aperture Delay (t
Aperture Uncertainty (Jitter) 25° C V 5 5 ps, rms
Output Delay (t
Output Time Skew
)25°CV 1 1 ns
A
5
OD
)
5
25°C I 6 10 13 6 10 13 ns
25°CI 35 35 ns
DYNAMIC PERFORMANCE
Transient Response 25°C V 10 10 ns
Overvoltage Recovery Time 25°C V 10 10 ns
Effective Number of Bits (ENOB)
= 2.3 MHz 25°C I 7.9 9.0 7.9 9.0 Bits
f
IN
= 10.3 MHz 25°C IV 7.6 8.4 7.6 8.4 Bits
f
IN
f
= 15.3 MHz 25°C IV 7.2 8.0 7.2 8.0 Bits
IN
Signal-to-Noise Ratio
6
fIN = 2.3 MHz 25°C I 49.5 56 49.5 56 dB
f
= 10.3 MHz 25°C I 47.5 53 47.5 53 dB
IN
f
= 15.3 MHz 25°C I 45.5 50 45.5 50 dB
IN
Signal-to-Noise Ratio
6
(Without Harmonics)
f
= 2.3 MHz 25°C I 49.5 56 49.5 56 dB
IN
= 10.3 MHz 25°C I 49.5 54 49.5 54 dB
f
IN
fIN = 15.3 MHz 25°C I 48 52 48 52 dB
–2–
REV. C
Page 3
AD9020
Test AD9020JE/JZ AD9020KE/KZ
Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE (continued)
Harmonic Distortion
f
= 2.3 MHz 25°C I 54.5 67 54.5 67 dBc
IN
f
= 10.3 MHz 25°C I 48.5 59 48.5 59 dBc
IN
= 15.3 MHz 25°C I 46.5 53 46.5 53 dBc
f
IN
Two-Tone Intermodulation
Distortion Rejection
Differential Phase 25°C V 0.5 0.5 Degree
Differential Gain 25°CV 1 1 %
ENCODE INPUT
Logic “1” Voltage Full VI 2.0 2.0 V
Logic “0” Voltage Full VI 0.8 0.8 V
Logic “1” Current Full VI 500 500 µA
Logic “0” Current Full VI 800 800 µA
Input Capacitance 25°CV 5 5 pF
Pulsewidth (High) 25°CI66ns
Pulsewidth (Low) 25°CI66ns
DIGITAL OUTPUTS
Logic “1” Voltage (I
Logic “0” Voltage (IOL = 6 mA) Full VI 0.4 V
POWER SUPPLY
Supply Current 25°C I 440 530 440 530 mA
+V
S
Supply Current 25°C I 140 170 140 170 mA
–V
S
Power Dissipation 25°C I 2.8 3.3 2.8 3.3 W
Power Supply Rejection
Ratio (PSRR)
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and beyond which the service ability of the circuit may be impaired. Functional operability is
not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances (part soldered onto board): 68-pin leaded ceramic chip carrier: θJC = 1°C/W; θJA = 17°C/W (no air flow); θJA = 15°C/W
(air flow = 500 LFM). 68-pin ceramic LCC: θJC = 2.6°C/W; θJA = 15°C/W (no air flow); θJA = 13°C/W (air flow = 500 LFM).
3
3/4
, 1/2
REF
tested and not included in linearity specifications.
4
Measured with ANALOG IN = +V
5
Output delay measured as worst-case time from 50% point of the rising edge of ENCODE to 50% point of the slowest rising or falling edge of D0–D9. Output skew
measured as worst-case difference in output delay among D0–D9.
6
RMS signal to rms noise with analog input signal 1 dB below full scale at specified frequency.
7
Intermodulation measured with analog input frequencies of 2.3 MHz and 3.0 MHz at 7 dB below full scale.
8
Measured as the ratio of the worst-case change in transition voltage of a single comparator for a 5% change in +V
Specifications subject to change without notice.
, and 1/4
REF
7
= 2 mA) Full VI 2.4 2.4 V
OH
25°C V 70 70 dBc
Full VI 542 542 mA
Full VI 177 177 mA
Full VI 3.4 3.4 W
8
reference ladder taps are driven from dc sources at +0.875 V, 0 V, and –0.875 V, respectively. Accuracy of the overflow comparator is not
REF
SENSE
Full VI 6 10 6 10 mV/V
.
or –VS.
S
REV. C
–3–
Page 4
AD9020
EXPLANATION OF TEST LEVELS
Test Level
I – 100% production tested.
II – 100% production tested at 25°C, and sample tested at
specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at 25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature extremes
for commercial/industrial devices.
DIE LAYOUT AND MECHANICAL INFORMATION
Die Dimensions . . . . . . . . . . . . . . . 206 ⫻ 140 ⫻ 15 (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 ⫻ 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V
S
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
S
GROUND
–V
REF
1/2
S
+V
S
+V
GROUND
GROUND
+V
S
+V
GROUND
GROUND
S
S
–VS–V
GROUND
+V
S
D
5
D
6
D
7
D
8
D
(MSB)
9
OVERFLOW
+V
S
GROUND
–V
S
+V
S
–V
REF
–V
SENSE
1/4
REF
NC
LSBs INVERT
MSB INVERT
S
–V
+V
D0 (LSB)
+V
GROUND
–V
+V
ENCODE
GROUND
+V
REF
+V
SENSE
D
D
D
D
S
4
3
2
1
S
S
S
S
S
–V
GROUND
–V
REF
+V
3/4
ANALOG IN
ANALOG IN
S
GROUND
+V
S
GROUND
S+VS
GROUND
+V
S
S
–V
+V
GROUND
ORDERING GUIDE
Device Range Description Option*
AD9020JZ 0°C to 70°C 68-Lead Leaded Ceramic Z-68
AD9020JE 0°C to 70°C 68-Terminal Ceramic LCC E-68A
AD9020KZ 0°C to 70°C 68-Lead Leaded Ceramic Z-68
AD9020KE 0°C to 70°C 68-Terminal Ceramic LCC E-68A
AD9020SZ/883 –55°C to +125°C 68-Lead Leaded Ceramic Z-68
AD9020SE/883 –55°C to +125°C 68-Terminal Ceramic LCC E-68A
AD9020TZ/883 –55°C to +125°C 68-Lead Leaded Ceramic Z-68
AD9020TE/883 –55°C to +125°C 68-Terminal Ceramic LCC E-68A
AD9020/PCB 0°C to 70°C Evaluation Board
*E = Ceramic Leadless Chip Carrier; Z = Ceramic Leaded Chip Carrier.
AD1
AD2
+2V
–2V
Temperature Package
5.0V
0.1F
3,6,15,18,25,30,33,34,
REF
REF
37,40,45,52,55,65,68
+V
S
AD9020
–V
S
2,16,28,29,35,
41,42,54,64
–5.2V
GROUND
0.1F
– D
D
0
D
– D
5
19
4
23
46
9
51
4,5,13,17,
27,31,32,
36,38,39,
43,53,66,67
100⍀
8
ANALOG IN
9
510⍀
14
ENCODE
+V
12
56
–V
59
LSBs INVERT
MSB INVERT
61
STATIC: AD1 = –2V; AD2 = +2.4V
DYNAMIC: AD1 = ⴞ2V TRIANGLE WAVE
AD2 = TTL PULSE TRAIN
510⍀
510⍀
Figure 1. Burn-In Circuit
–4–
REV. C
Page 5
PIN CONFIGURATION
AD9020
NC
+V
SENSE
+V
REF
GND
ENCODE
+V
–V
GND
+V
(LSB) D
NC
+V
NC
REF
S
ANALOG IN
3/4
+V
ANALOG IN
9
10
S
S
S
0
D
1
D
2
D
3
D
4
S
26
27 43
S
S
S
–V
–V
+V
GND
S
REF
S
–V
GND
GND
+V
1/2
AD9020
TOP VIEW
(NOT TO SCALE)
S
S
S
–V
+V
+V
GND
GND
GND
+VS+V
+VS+V
GND
GND
GND
S
GND
S
–V
S
REF
1/4
–VS–V
NC
61
S
MSB INVERT
NC
60
LSBs INVERT
NC
–V
–V
+V
–V
GND
+V
OVERFLOW
D
D
D
D
D
+V
NC
44
NC = NO CONNECT
GND
SENSE
REF
S
S
S
(MSB)
9
8
7
6
5
S
PIN FUNCTION DESCRIPTIONS
Pin No. Name Function
1 1/2
2, 16, 28, 29, 35, 41, 42, –V
REF
S
Midpoint of internal reference ladder.
Negative supply voltage; nominally –5.0 V ± 5%.
54, 64
3, 6, 15, 18, 25, 30, 33, 34, +V
S
Positive supply voltage; nominally 5 V ± 5%.
37, 40, 45, 52, 55, 65, 68
4, 5, 13, 17, 27, 31, 32, GROUND All ground pins should be connected together and to low impedance ground
36, 38, 39, 43, 53, 66, 67 plane.
7 3/4
REF
Three-quarter point of internal reference ladder.
8, 9 ANALOG IN Analog input; nominally between ± 1.75 V.
11 +V
SENSE
Voltage sense line to most positive point on internal resistor ladder.
Normally 1.75 V.
12 +V
REF
Voltage force connection for top of internal reference ladder. Normally driven
to provide 1.75 V at +V
SENSE
.
14 ENCODE TTL-compatible convert command used to begin digitizing process.
19–23, 46–50 D
51 OVERFLOW TTL-compatible output indicating ANALOG IN > +V
56 –V
57 –V
0–D4
REF
SENSE
, D5–D
TTL-compatible digital output data.
9
.
SENSE
Voltage force connection for bottom of internal reference ladder. Normally
driven to provide –1.75 V at –V
SENSE
.
Voltage sense line to most negative point on internal resistor ladder.
Normally –1.75 V.
59 LSBs INVERT Normally grounded. When connected to +V
, lower order bits (D0–D8) are
S
inverted.
61 MSB INVERT Normally grounded. When connected to +V
, most significant bit (MSB; D9)
S
is inverted.
63 1/4
REF
One-quarter point of internal reference ladder.
REV. C
–5–
Page 6
AD9020
THEORY OF OPERATION
Refer to the AD9020 block diagram. As shown, the AD9020
uses a modified “flash,” or parallel, A/D architecture. The
analog input range is determined by an external voltage reference (+V
and –V
REF
), nominally ± 1.75 V. An internal
REF
resistor ladder divides this reference into 512 steps, each representing two quantization levels. Taps along the resistor ladder
(1/4
REF
, 1/2
and 3/4
REF
) are provided to optimize linearity.
REF
Rated performance is achieved by driving these points at 1/4,
1/2, and 3/4, respectively, of the voltage reference range.
The A/D conversion for the nine most significant bits (MSBs)
is performed by 512 comparators. The value of the least significant bit (LSB) is determined by a unique interpolation
scheme between adjacent comparators. The decoding logic
processes the comparator outputs and provides a 10-bit code
to the output stage of the converter.
Flash architecture has an advantage over other A/D architectures because conversion occurs in one step. This means the
performance of the converter is primarily limited by the speed
and matching of the individual comparators. In the AD9020,
an innovative interpolation scheme takes advantage of flash
architecture but minimizes the input capacitance, power and
device count usually associated with that method of conversion.
These advantages occur by using only half the normal number of input comparator cells to accomplish the conversion.
In addition, a proprietary decoding scheme minimizes error
codes. Input control pins allow the user to select from among
Binary, Inverted Binary, Two’s Complement and Inverted
Two’s Complement coding (see Table I).
APPLICATIONS
Many of the specifications used to describe analog/digital
converters have evolved from system performance requirements in these applications. Different systems emphasize
particular specifications, depending on how the part is used.
The following applications highlight some of the specifications
and features that make the AD9020 attractive in these systems.
Wideband Receivers
Radar and communication receivers (baseband and direct IF
digitization), ultrasound medical imaging, signal intelligence
and spectral analysis all place stringent ac performance requirements on analog-to-digital converters (ADCs).
Frequency domain characterization of the AD9020 provides signal-to-noise ratio (SNR) and harmonic distortion data to
simplify selection of the ADC.
Receiver sensitivity is limited by the Signal-to-Noise Ratio of
the system. The SNR for an ADC is measured in the frequency domain and calculated with a Fast Fourier Transform
(FFT). The SNR equals the ratio of the fundamental component of the signal (rms amplitude) to the rms value of the
noise. The noise is the sum of all other spectral components,
including harmonic distortion, but excluding dc.
Good receiver design minimizes the level of spurious signals
in the system. Spurious signals developed in the ADC are the
result of imperfections (nonlinearities, delay mismatch, varying input impedance, etc.) in the device transfer function.
In the ADC, these spurious signals appear as Harmonic Distortion. Harmonic Distortion is also measured with an FFT
and is specified as the ratio of the fundamental component of
the signal (rms amplitude) to the rms value of the worst-case
harmonic (usually the 2nd or 3rd).
Two-Tone Intermodulation Distortion (IMD) is a frequently
cited specification in receiver design. In narrow-band receivers, third-order IMD products result in spurious signals in
the passband of the receiver. Like mixers and amplifiers, the
ADC is characterized with two, equal-amplitude, pure input
frequencies. The IMD equals the ratio of the power of either
of the two input signals to the power of the strongest thirdorder IMD signal. Unlike mixers and amplifiers, the IMD
does not always behave as it does in linear devices (reduced
input levels do not result in predictable reductions in IMD).
Performance graphs provide typical harmonic and SNR data
for the AD9020 for increasing analog input frequencies. In
choosing an A/D converter, always look at the dynamic range
for the analog input frequency of interest. The AD9020
specifications provide guaranteed minimum limits at three
analog test frequencies.
Aperture Delay is the delay between the rising edge of the
ENCODE command and the instant at which the analog input is
sampled. Many systems require simultaneous sampling of
more than one analog input signal with multiple ADCs. In
these situations, timing is critical and the absolute value of
the
aperture delay is not as critical as the matching between devices.
Aperture Uncertainty, or jitter, is the sample-to-sample variation in
aperture delay. This is especially important when sampling high
slew rate signals in wide bandwidth systems. Aperture uncertainty
is one of the factors that degrade dynamic performance as the analog input frequency is increased.
Digitizing Oscilloscopes
Oscilloscopes provide amplitude information about an observed
waveform with respect to time. Digitizing oscilloscopes must
accurately sample this signal, without distorting the information
to be displayed.
One figure of merit for the ADC in these applications is Effective
Number of Bits (ENOBs). ENOB is calculated with a sine wave
curve fit and equals:
ENOB = N – LOG
[Error (measured)/Error (ideal)]
2
N is the resolution (number of bits) of the ADC. The measured
error is the actual rms error calculated from the converter outputs with a pure sine wave input.
The Analog Bandwidth of the converter is the analog input fre-
quency at which the spectral power of the fundamental signal is
reduced 3 dB from its low frequency value. The analog bandwidth is a good indicator of a converter’s stewing capabilities.
–6–
REV. C
Page 7
AD9020
The Maximum Conversion Rate is defined as the encode rate at
which the SNR for the lowest analog signal test frequency tested
drops by no more than 3 dB below the guaranteed limit.
Imaging
Both visible and infrared imaging systems require similar characteristics from ADCs. The signal input (from a CCD camera,
or multiplexer) is a time division multiplexed signal consisting of
a series of pulses whose amplitude varies in direct proportion to
the intensity of the radiation detected at the sensor. These varying levels are then digitized by applying encode commands at
the correct times, as shown in Figure 2.
+FS
–FS
ENCODE
A
IN
AD9020
Figure 2. Imaging Application Using AD9020
The actual resolution of the converter is limited by the thermal
and quantization noise of the ADC. The low frequency test for
SNR or ENOB is a good measure of the noise of the AD9020.
At this frequency, the static errors in the ADC determine the
useful dynamic range of the ADC.
Although the signal being sampled does not have a significant
slew rate, this does not imply dynamic performance is not important. The Transient Response and Overvoltage Recovery Time
specifications ensure that the ADC can track full-scale changes
in the analog input sufficiently fast to capture a valid sample.
Transient Response is the time required for the AD9020 to achieve
full accuracy when a step function is applied. Overvoltage
Recovery Time is the time required for the AD9020 to recover to
full accuracy after an analog input signal 150% of full scale is
reduced to the full-scale range of the converter.
Professional Video
Digital Signal Processing (DSP) is now common in television
production. Modern studios rely on digitized video to create
state-of-the-art special effects. Video instrumentation also
requires high resolution ADCs for studio quality measurement
and frame storage.
The AD9020 provides sufficient resolution for these demanding
applications. Conversion speed, dynamic performance and analog bandwidth are suitable for digitizing both composite and
RGB video sources.
USING THE AD9020
Voltage References
The AD9020 requires that the user provide two voltage
references: +V
and –V
REF
. These two voltages are applied
REF
across an internal resistor ladder (nominally 37 Ω) and set the
analog input voltage range of the converter. The voltage references
should be driven from a stable, low impedance source. In addition
to these two references, three evenly spaced taps on the resistor
ladder (1/4
REF
, 1/2
REF
, 3/4
) are available. Providing a reference
REF
to these quarter points on the resistor ladder wil improve the
integral linearity of the converter and improve ac performance. (ac
and dc specifications are tested while driving the quarter points
at the indicated levels.) Figure 3 is not intended to show the
transfer function of the ADC, but illustrates how the linearity of
the device is affected by reference voltages applied to the ladder.
1111111111
1100000000
1000000000
OUTPUT CODE
0100000000
0000000000
–V
SENSE
(NOT TO SCALE)
1/4
REF
TAPS
FLOATING
IDEAL
LINEARITY
1/2
TAPS
DRIVEN
REF
V
IN
3/4
REF
+V
SENSE
Figure 3. Effect of Reference Taps on Linearity
Resistance between the reference connections and the taps of the
first and last comparators causes offset errors. These errors, called
“top and bottom of the ladder offsets,” can be nulled by using the
voltage sense lines, +V
SENSE
and –V
, to adjust the reference
SENSE
voltages. Current through the sense lines should be limited to less
than 100 µA. Excessive current drawn through the voltage sense
lines will affect the accuracy of the sense line voltage.
REV. C
–7–
Page 8
AD9020
Figure 5 shows a reference circuit that nulls out the offset errors
using two op amps, and provides appropriate voltage references
to the quarter-point taps. Feedback from the sense lines causes
the op amps to compensate for the offset errors. The two transistors limit the amount of current drawn directly from the op
amps; resistors at the base connections stabilize their operation.
The 10 kΩ resistors (R1–R4) between the voltage sense lines
form an external resistor ladder; the quarter point voltages are
taken off this external ladder and buffered by an op amp. The
actual values of resistors R1–R4 are not critical, but they should
match well and be large enough (≥10 kΩ) to limit the amount
of current drawn from the voltage sense lines.
The select resistors (RS) shown in the schematic (each pair can be
a potentiometer) are chosen to adjust the quarter-point voltage
references, but are not necessary if R1–R4 match within 0.05%.
An alternative approach for defining the quarter-point references
of the resistor ladder is to evaluate the integral linearity error of
an individual device, and adjust the voltage at the quarter-points
to minimize this error. This may improve the low frequency ac
performance of the converter.
Performance of the AD9020 has been optimized with an analog
input voltage of ± 1.75 V (as measured at ± V
). If the analog
SENSE
input range is reduced below these values, relatively larger differential nonlinearity errors may result because of comparator
mismatches. As shown in Figure 4, performance of the converter
is a function of ± V
SENSE
.
10.0
9.0
8.0
7.0
6.0
EFFECTIVE NUMBER OF BITS (ENOB)
5.0
SIGNAL-TO-NOISE (SNR) – dB
62
56
50
44
38
32
0.4
0.6
1.0 1.2 1.4 1.8 2.01.6
0.8
ⴞV
SENSE
– Volts
Figure 4. SNR and ENOB vs. Reference Voltage
Applying a voltage greater than 4 V across the internal resistor
ladder will cause current densities to exceed rated values, and
may cause permanent damage to the AD9020. The design
of the reference circuit should limit the voltage available to
the references.
Analog Input Signal
The signal applied to ANALOG IN drives the inputs of 512
parallel comparator cells (see Figure 6). This connection typically has an input resistance of 7 kΩ, and input capacitance of
45 pF. The input capacitance is nearly constant over the analog input voltage range, as shown in the graph that illustrates
that characteristic.
The analog input signal should be driven from a low-distortion,
low-noise amplifier. A good choice is the AD9617, a wide
bandwidth, monolithic operational amplifier with excellent ac
and dc performance. The input capacitance should be isolated
by a small series resistor (24 Ω for the AD9617) to improve the
ac performance of the amplifier (see Figure 14).
–8–
REV. C
Page 9
AD9020
DIGITAL BITS
AND OVERFLOW
+V
S
356⍀
1.75V
150⍀
+2.5V
10k⍀
10k⍀
AD580
10k⍀
10k⍀
1/2
AD708
R1
R2
R3
R4
+1.75V
R
S
R
S
R
S
R
S
150⍀
1/2
AD708
1/2
AD708
1/2
AD708
+5V
+0.875V
0V
–0.875V
0.1F
0.1F
0.1F
0.1F
+V
+V
REF
SENSE
3/4
REF
1/2
REF
1/4
REF
AD9020
ⴱ
R/2
R
R/2
R/2
R
R
R/2
R/2
R
R
R/2
R/2
R
TO COMPARATORS
ANALOG
INPUT
Figure 6. Equivalent Analog Input
+V
3/4
1/2
1/4
–V
SENSE
REF
REF
REF
SENSE
20k⍀
20k⍀
–1.75V
150⍀
1/2
AD708
–5V
Figure 5. Reference Circuit
0.1F
–V
SENSE
–V
REF
RESISTANCE = < 5⍀
ⴱ
ⴱ
R
R
R/2
= WIRING
Figure 7. Equivalent Digital Outputs
5.0V
13k⍀
ENCODE
Figure 8. Equivalent Encode Circuit
REV. C
–9–
Page 10
AD9020
ANALOG
INPUT
ENCODE
DATA
OUTPUT
N
t
a
N
N
t
OD
DATA FOR N DATA FOR N + 1
Figure 9. Timing Diagram
Timing
In the AD9020, the rising edge of the ENCODE signal triggers
the A/D conversion by latching the comparators. (See Figure 9.)
The ENCODE is TTL/CMOS-compatible and should be driven
from a low jitter (phase noise) source. Jitter on the ENCODE
signal will raise the noise floor of the converter. Fast, clean edges
will reduce the jitter in the signal and allow optimum ac performance. Locking the system clock to a crystal oscillator also
helps reduce jitter. The AD9020 is designed to operate with a
50% duty cycle; small (10%) variations in duty cycle should not
degrade performance.
Data Format
The format of the output data (D0–D9) is controlled by the MSB
INVERT and LSBs INVERT pins. These inputs are dc control
inputs, and should be connected to GROUND or +V
. Table I
S
gives information to choose from among Binary, Inverted Binary,
Two’s Complement and Inverted Two’s Complement coding.
The OVERFLOW output is an indication that the analog input
signal has exceeded the voltage at +V
. The accuracy of the
SENSE
overflow transition voltage and output delay are not tested or
included in the data sheet limits. Performance of the overflow
indicator is dependent on circuit layout and slew rate of the
encode signal. The operation of this function does not affect the
other data bits (D
). It is not recommended for applications
0–D9
requiring a critical measure of the analog input voltage.
N + 1
N + 1
t
– APERTURE DELAY
a
t
– OUTPUT DELAY
OD
Layout and Power Supplies
Proper layout of high speed circuits is always critical but particularly important when both analog and digital signals
are involved.
Analog signal paths should be kept as short as possible and be
properly terminated to avoid reflections. The analog input voltage and the voltage references should be kept away from digital
signal paths; this reduces the amount of digital switching noise
that is capacitively coupled into the analog section of the circuit.
Digital signal paths should also be kept short, and run lengths
should be matched to avoid propagation delay mismatch.
In high-speed circuits, layout of the ground circuit is a critical factor. A single, low impedance ground plane, on the component
side of the board, will reduce noise on the circuit ground. Power
supplies should be capacitively coupled to the ground plane to
reduce noise in the circuit. Multilayer boards allow designers to
lay out signal traces without interrupting the ground plane and
provide low impedance power planes.
It is especially important to maintain the continuity of the ground
plane under and around the AD9020. In systems with dedicated
digital and analog grounds, all grounds of the AD9020 should be
connected to the analog ground plane.
The power supplies (+VS and –VS) of the AD9020 should be isolated from the supplies used for external devices; this further reduces
the amount of noise coupled into the A/D converter. Sockets limit
the dynamic performance and should be used only for prototypes or
evaluation—PCK Elastomerics Part # CCS-68-55 is recommended
for the LCC package.
An evaluation board is available to aid designers and provide a
suggested layout.
–10–
REV. C
Page 11
AD9020
43
44
45
46
47
48
49
50
–1.8
INPUT CAPACITANCE – pF
INPUT RESISTANCE – k⍀
ANALOG INPUT (AIN) – Volts
–1.2 –0.6 0
0.6
1.2 1.8
0
10
20
30
40
50
60
70
RESISTANCE
CAPACITANCE
62
ENCODE RATE = 40MSPS
25ⴗC
55ⴗC & 125ⴗC
10 100
200
SIGNAL-TO-NOISE (SNR) – dB
56
50
44
38
32
26
20
1
INPUT FREQUENCY – MHz
Figure 10. SNR and ENOB vs. Input Frequency
30
35
40
45
125ⴗC
10.0
9.0
8.0
7.0
6.0
5.0
4.0
EFFECTIVE NUMBER OF BITS (ENOB)
SIGNAL-TO-NOISE (SNR) – dB
62
56
50
44
38
32
26
20
1
Figure 12. SNR and ENOB vs. Conversion Rate
ANALOG INPUT = 2.3MHz
10 100
CONVERSION RATE – MSPS
10.0
9.0
8.0
7.0
6.0
5.0
4.0
EFFECTIVE NUMBER OF BITS (ENOB)
50
55
HARMONICS – dBc
60
65
70
1
INPUT FREQUENCY – MHz
Figure 11. Harmonics vs. Input Frequency
–55ⴗC
10 100
25ⴗC
Figure 13. Input Capacitance/Resistance vs. Input Voltage
Table I. Truth Table
Offset Binary Two’s Complement
Range True Inverted True Inverted
0 = –1.75 V MSB INV = “0” MSB INV = “1” MSB INV = “1” MSB INV = “0”
Step FS = +1.75 V LSBs INV = “0” LSBs INV = “1” LSBs INV = “0” LSBs INV = “1”
1024 > +1.7500 (1)1111111111 (1)0000000000 (1)0111111111 (1)1000000000
1023 +1.7466 1111111111 0000000000 0111111111 1000000000
1022 +1.7432 1111111110 0000000001 0111111110 1000000001
•• • • • •
•• • • • •
•• • • • •
512 +0.0034 1000000000 0111111111 0000000000 1111111111
511 0.000 0111111111 1000000000 1111111111 0000000000
510 –0.0034 0111111110 1000000001 1111111110 0000000001
•• • • • •
•• • • • •
•• • • • •
02 –1.7432 0000000010 1111111101 1000000010 0111111101
01 –1.7466 0000000001 1111111110 1000000001 0111111110
00 <–1.7466 0000000000 1111111111 1000000000 0111111111
The overflow bit is always 0 except where noted in parentheses ( ). MSB INVERT and LSBs INVERT are considered dc controls.
REV. C
–11–
Page 12
AD9020
(
)
(
)
AD9020/PCB EVALUATION BOARD
The AD9020/PCB Evaluation Board is available from the factory
and is shown here in block diagram form. The board includes a
reference circuit that allows the user to adjust both references
and the quarter-point voltages. The AD9617 is included as the
drive amplifier, and the user can configure the gain from –1 to –15.
+5V
–5V
BUFFERED
ANALOG
INPUT
TO ERROR
WAVEFORM
CIRCUIT
200⍀
50⍀
400⍀
U5
AD9617
ANALOG
J2
24⍀
REFERENCE
CIRCUIT
DUT
INPUT
+V
–V
S
ANALOG
INPUT
+V
REF
+V
SENSE
3/4
REF
1/2
REF
1/4
REF
–V
SENSE
–V
REF
GND
S
AD9020
DUT
On-board reconstruction of the digital data is provided through
the AD9713, a 12-bit monolithic DAC. The analog and reconstructed waveforms can be summed on the board to allow the
user to observe the linearity of the AD9020 and the effects of
the quarterpoint voltages. The digital data and an adjustable
Data Ready signal are available through a 37-pin edge connector.
DAC
OUT
MSB
INVERT
LSBs
INVERT
D0 (LSB)
D9 (MSB)
OVERFLOW
ENCODE
AD9713
+5V
D
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
D
D
D
D
LATCHES
D
D
D
D
D
TTL CLK
Q
TTL
CLK
DAC
D
I
TIMING
CIRCUIT
OUT
50⍀
OUTPUT
DATA
COLLECTOR
DATA
READY
TO ERROR
WAVEFORM
CIRCUIT
C00548b–0–7/01(C)
0.040
(1.016)
MIN
1.210 ⴞ 0.010
(30.73 ⴞ 0.254)
0.025 (0.625)
MIN
Figure 14. AD9020/PCB Evaluation Board Block Diagram
68-Leaded Ceramic Chip Carrier
(Z-68)
0.130 (3.301)
TYP
0.105 ⴞ 0.013
(2.667 ⴞ 0.330)
0.025
(0.625)
MIN
0.050
(1.27)
TYP
0.018 ⴞ 0.002
(0.457 ⴞ 0.05)
10
26
9
27
0.950 ⴞ 0.010 SQ
0.700 ⴞ 0.005 SQ
(17.78 ⴞ 0.127)
(24.13 ⴞ 0.254)
PIN 1
TOP VIEW
0.850 ⴞ 0.009
21.59 ⴞ 0.229
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.105 ⴞ 0.013
(2.667 ⴞ 0.330)
61
60
0.030
(0.762)
44
43
0.075 ⴞ 0.008
(1.905 ⴞ 0.203)
TYP
68-Terminal
Leadless Chip Carrier (LCC)
(E-68A)
0.950 ⴞ 0.010 SQ
(24.13 ⴞ 0.254)
9
10
PIN 1
TOP VIEW
26
27
0.700 ⴞ 0.005 SQ
(17.78 ⴞ 0.127)
0.850 ⴞ 0.009
21.59 ⴞ 0.229
61
43
60
0.050
(1.27)
TYP
0.036 ⴞ 0.003
(0.965 ⴞ 0.076)
44
0.050 ⴞ 0.008
(1.27 ⴞ 0.076)
PRINTED IN U.S.A.
AD9020–Revision History
Location Page
Data Sheet changed from REV. B to REV. C.
Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
–12–
REV. C
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