Page 1
10-Bit 60 MSPS
a
FEATURES
Monolithic 10-Bit/60 MSPS Converter
TTL Outputs
Bipolar (61.75 V) Analog Input
56 dB SNR @ 2.3 MHz Input
Low (45 pF) Input Capacitance
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Digital Oscilloscopes
Medical Imaging
Professional Video
Radar Warning/Guidance Systems
Infrared Systems
GENERAL DESCRIPTION
The AD9020 A/D converter is a 10-bit monolithic converter
capable of word rates of 60 MSPS and above. Innovative architecture using 512 input comparators instead of the traditional
1024 required by other flash converters reduces input capacitance and improves linearity.
Encode and outputs are TTL-compatible, making the AD9020
an ideal candidate for use in low power systems. An overflow
bit is provided to indicate analog input signals greater than
+V
Voltage sense lines are provided to insure accurate driving of the
±V
resistor ladder help optimize the integral linearity of the unit.
Either 68-pin ceramic leaded (gull wing) packages or ceramic
LCCs are available and are specifically designed for low thermal
impedances. Two performance grades for temperatures of both
0°C to +70°C and –55°C to +125°C ranges are offered to allow
the user to select the linearity best suited for each application.
Dynamic performance is fully characterized and production
tested at +25°C. MIL-STD-883 units are available.
The AD9020 A/D Converter is available in versions compliant
with MIL-STD-883. Refer to the Analog Devices Military Products Databook or current AD9020/883B data sheet for detailed
specifications.
.
SENSE
voltages applied to the units. Quarter-point taps on the
REF
ANALOG IN
+V
+V
SENSE
3/4
1/2
1/4
–V
SENSE
–V
ENCODE
A/D Converter
FUNCTIONAL BLOCK DIAGRAM
8
9
12
REF
11
R/2
R
R/2
7
REF
R/2
R
R
R/2
1
REF
R/2
R
R
R/2
63
REF
R/2
R
R
R
R/2
57
56
REF
14
512
385
384
257
256
129
128
2
1
OVERFLOW
C
O
M
P
A
R
A
OVERFLOW OVERFLOW
T
O
1024 10
R
L
A
T
C
H
E
S
–V
AD9020
INVERT
D
E
C
O
D
E
L
O
G
I
C
+V
S
S
MSB
GROUND
LSBS
INVERT
5961
L
A
T
C
H
OVERFLOW
51
D
50
D
49
48
D
D
47
46
D
23
D
22
D
21
D
20
D
19
D
(MSB)
9
8
7
6
5
4
3
2
1
(LSB)
0
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A
.Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1997
Page 2
AD9020–SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
–V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–6 V
S
ANALOG IN . . . . . . . . . . . . . . . . . . . . . . . . . . . –2 V to +2 V
+V
, –V
, 3/4
+V
REF
REF
REF
to –V
, 1/2
REF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
REF
REF
, 1/4
DIGITAL INPUTS . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +V
ELECTRICAL CHARACTERISTICS
1
. . . . . . . . . . –2 V to +2 V
REF
(6VS = 65 V; 6V
3/4
, 1/2
, 1/4
REF
REF
Current . . . . . . . . . . . . . . . . . . . ±10 mA
REF
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature
AD9020JE/KE/JZ/KZ . . . . . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Maximum Junction Temperature
Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . . . . +300°C
S
= 61.75 V; ENCODE = 40 MSPS unless otherwise noted)
SENSE
2
. . . . . . . . . . . . . . . . +175°C
Test AD9020JE/JZ AD9020KE/KZ
Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Units
RESOLUTION 10 10 Bits
DC ACCURACY
3
Differential Nonlinearity +25°C I 1.0 1.25 0.75 1.0 LSB
Full VI 1.5 1.25 LSB
Integral Nonlinearity +25°C I 1.25 2.0 1.0 1.5 LSB
Full VI 2.5 2.0 LSB
No Missing Codes Full VI Guaranteed
ANALOG INPUT
Input Bias Current
4
+25°C I 0.4 1.0 0.4 1.0 mA
Full VI 2.0 2.0 mA
Input Resistance +25°C I 2.0 7.0 2.0 7.0 kΩ
Input Capacitance
4
+25°C V 45 45 pF
Analog Bandwidth +25°C V 175 175 MHz
REFERENCE INPUT
Reference Ladder Resistance +25°C I 22 37 56 22 37 56 Ω
Full VI 14 66 14 66 Ω
Ladder Tempco Full V 0.1 0.1 Ω/°C
Reference Ladder Offset
Top of Ladder +25°C I 45 90 45 90 mV
Full VI 90 90 mV
Bottom of Ladder +25°C I 45 90 45 90 mV
Full VI 90 90 mV
Offset Drift Coefficient Full V 50 50 µV/°C
SWITCHING PERFORMANCE
Conversion Rate +25°C I 60 60 MSPS
Aperture Delay (t
Aperture Uncertainty (Jitter) +25°C V 5 5 ps, rms
Output Delay (t
Output Time Skew
) +25°CV 1 1 ns
A
5
OD
)
5
+25°C I 6 10 13 6 10 13 ns
+25°CI 35 35 ns
DYNAMIC PERFORMANCE
Transient Response +25°C V 10 10 ns
Overvoltage Recovery Time +25°C V 10 10 ns
Effective Number of Bits (ENOB)
f
= 2.3 MHz +25°C I 8.6 9.0 8.6 9.0 Bits
IN
f
= 10.3 MHz +25°C IV 8.0 8.4 8.0 8.4 Bits
IN
f
= 15.3 MHz +25°C IV 7.5 8.0 7.5 8.0 Bits
IN
Signal-to-Noise Ratio
6
fIN = 2.3 MHz +25°C I 54 56 54 56 dB
f
= 10.3 MHz +25°C I 50 53 50 53 dB
IN
f
= 15.3 MHz +25°C I 47 50 47 50 dB
IN
Signal-to-Noise Ratio
6
(Without Harmonics)
f
= 2.3 MHz +25°C I 54 56 54 56 dB
IN
f
= 10.3 MHz +25°C I 51 54 51 54 dB
IN
fIN = 15.3 MHz +25°C I 48 52 48 52 dB
–2–
REV. A
Page 3
AD9020
Test AD9020JE/JZ AD9020KE/KZ
Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Units
DYNAMIC PERFORMANCE (continued)
Harmonic Distortion
= 2.3 MHz +25°C I 61 67 61 67 dBc
f
IN
= 10.3 MHz +25°C I 55 59 55 59 dBc
f
IN
= 15.3 MHz +25°C I 49 53 49 53 dBc
f
IN
Two-Tone Intermodulation
Distortion Rejection
Differential Phase +25°C V 0.5 0.5 Degree
Differential Gain +25°CV 1 1 %
ENCODE INPUT
Logic “1” Voltage Full VI 2.0 2.0 V
Logic “0” Voltage Full VI 0.8 0.8 V
Logic “1” Current Full VI 20 20 µA
Logic “0” Current Full VI 800 800 µA
Input Capacitance +25°CV 5 5 pF
Pulse Width (High) +25°CI66ns
Pulse Width (Low) +25°CI66ns
DIGITAL OUTPUTS
Logic “1” Voltage (I
Logic “0” Voltage (IOL = 6 mA) Full VI 0.4 V
POWER SUPPLY
+V
Supply Current +25°C I 440 530 440 530 mA
S
–V
Supply Current +25°C I 140 170 140 170 mA
S
Power Dissipation +25°C I 2.8 3.3 2.8 3.3 W
Power Supply Rejection
Ratio (PSRR)
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and beyond which the service ability of the circuit may be impaired. Functional operability is
not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances (part soldered onto board): 68-pin leaded ceramic chip carrier: θJC = 1°C/W; θJA = 17°C/W (no air flow); θJA = 15°C/W
(air flow = 500 LFM). 68-pin ceramic LCC: θJC = 2.6°C/W; θJA = 15°C/W (no air flow); θJA = 13°C/W (air flow = 500 LFM).
3
3/4
, 1/2
REF
tested and not included in linearity specifications.
4
Measured with ANALOG IN = +V
5
Output delay measured as worst-case time from 50% point of the rising edge of ENCODE to 50% point of the slowest rising or falling edge of D0–D9. Output skew
measured as worst-case difference in output delay among D0–D9.
6
RMS signal to rms noise with analog input signal 1 dB below full scale at specified frequency.
7
Intermodulation measured with analog input frequencies of 2.3 MHz and 3.0 MHz at 7 dB below full scale.
8
Measured as the ratio of the worst-case change in transition voltage of a single comparator for a 5% change in +V
Specifications subject to change without notice.
, and 1/4
REF
7
= 2 mA) Full VI 2.4 2.4 V
OH
+25°C V 70 70 dBc
Full VI 542 542 mA
Full VI 177 177 mA
Full VI 3.4 3.4 W
8
reference ladder taps are driven from dc sources at +0.875 V, 0 V, and –0.875 V, respectively. Accuracy of the overflow comparator is not
REF
SENSE
Full VI 6 10 6 10 mV/V
.
or –VS.
S
REV. A
–3–
Page 4
AD9020
AD9020
4,5,13,17,
27,31,32,
36,38,39,
43,53,66,67
100Ω
510Ω
ANALOG IN
ENCODE
GROUND
2,16,28,29,35,
41,42,54,64
0.1µF
0.1 µF
510Ω
510Ω
AD1
AD2
3,6,15,18,25,30,33,34,
37,40,45,52,55,65,68
STATIC:
DYNAMIC:
AD1 = –2V; AD2 = +2.4V
AD1 = ±2V TRIANGLE WAVE
AD2 = TTL PULSE TRAIN
9
46
19
14
23
51
12
8
56
59
61
+2V
–2V
REF
V
+
REF
V
_
S
–
V
D
59
– D
D
04
– D
S
+
V
5.0V
+
5.2V
–
LSBs INVERT
MSB INVERT
EXPLANATION OF TEST LEVELS
Test Level
I – 100% production tested.
II – 100% production tested at +25°C, and sample tested at
specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature ex-
tremes for commercial/industrial devices.
DIE LAYOUT AND MECHANICAL INFORMATION
Die Dimensions . . . . . . . . . . . . . . . 206 3 140 3 15 (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V
S
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
ORDERING GUIDE
Temperature Package
Device Range Description Option*
AD9020JZ 0°C to +70°C 68-Pin Leaded Ceramic Z-68
AD9020JE 0°C to +70°C 68-Terminal Ceramic LCC E-68A
AD9020KZ 0°C to +70°C 68-Pin Leaded Ceramic Z-68
AD9020KE 0°C to +70°C 68-Terminal Ceramic LCC E-68A
AD9020SZ/883 –55°C to +125°C 68-Pin Leaded Ceramic Z-68
AD9020SE/883 –55°C to +125°C 68-Terminal Ceramic LCC E-68A
AD9020TZ/883 –55°C to +125°C 68-Pin Leaded Ceramic Z-68
AD9020TE/883 –55°C to +125°C 68-Terminal Ceramic LCC E-68A
AD9020/PCB 0°C to +70°C Evaluation Board
*E = Ceramic Leadless Chip Carrier; Z = Ceramic Leaded Chip Carrier.
–4–
AD9020 Burn-In Circuit
REV. A
Page 5
AD9020
NC
+V
SENSE
+V
REF
GND
ENCODE
+V
–V
GND
+V
(LSB) D
NC
+V
NC
REF
ANALOG IN
3/4
ANALOG IN
9
10
S
S
S
0
D
1
D
2
D
3
D
4
S
26
S
S
–V
–V
GND
S
GND
+V
S
+V
GND
S
+V
GND
AD9020
TOP VIEW
(Not to Scale)
S
+V
GND
AD9020 PIN FUNCTION DESCRIPTIONS
Pin No. Name Function
1 1/2
2, 16, 28, 29, 35, 41, 42, –V
REF
S
Midpoint of internal reference ladder.
Negative supply voltage; nominally –5.0 V ± 5%.
54, 64
REF
S
S
+V
GND
1/2
–V
S
S
S
–V
+V
+V
GND
GND
GND
S
+V
GND
S
–V
S
+V
REF
NC
1/4
61
4327
S
S
–V
–V
MSB INVERT
60
44
NC = NO CONNECT
GND
NC
LSBs INVERT
NC
–V
SENSE
–V
REF
+V
S
–V
S
GND
+V
S
OVERFLOW
(MSB)
D
9
D
8
D
7
D
6
D
5
+V
S
NC
3, 6, 15, 18, 25, 30, 33, 34, +V
S
Positive supply voltage; nominally +5 V ± 5%.
37, 40, 45, 52, 55, 65, 68
4, 5, 13, 17, 27, 31, 32, GROUND All ground pins should be connected together and to low impedance ground
36, 38, 39, 43, 53, 66, 67 plane.
7 3/4
REF
Three-quarter point of internal reference ladder.
8, 9 ANALOG IN Analog input; nominally between ±1.75 V.
11 +V
SENSE
Voltage sense line to most positive point on internal resistor ladder.
Normally +1.75 V.
12 +V
REF
Voltage force connection for top of internal reference ladder. Normally driven
to provide +1.75 V at +V
SENSE
.
14 ENCODE TTL-compatible convert command used to begin digitizing process.
19–23, 46–50 D
0–D9
51 OVERFLOW TTL-compatible output indicating ANALOG IN > +V
56 –V
57 –V
REF
SENSE
TTL-compatible digital output data.
.
SENSE
Voltage force connection for bottom of internal reference ladder. Normally
driven to provide –1.75 V at –V
SENSE
.
Voltage sense line to most negative point on internal resistor ladder.
Normally –1.75 V.
59 LSBs INVERT Normally grounded. When connected to +V
, lower order bits (D0–D8) are
S
inverted.
61 MSB INVERT Normally grounded. When connected to +V
, most significant bit (MSB; D9)
S
is inverted.
63 1/4
REV. A
REF
One-quarter point of internal reference ladder.
–5–
Page 6
AD9020
THEORY OF OPERATION
Refer to the AD9020 block diagram. As shown, the AD9020
uses a modified “flash,” or parallel, A/D architecture. The analog input range is determined by an external voltage reference
(+V
REF
and –V
), nominally ±1.75 V. An internal resistor lad-
REF
der divides this reference into 512 steps, each representing two
quantization levels. Taps along the resistor ladder (1/4
1/2
and 3/4
REF
) are provided to optimize linearity. Rated per-
REF
REF
,
formance is achieved by driving these points at 1/4, 1/2 and 3/4,
respectively, of the voltage reference range.
The A/D conversion for the nine most significant bits (MSBs) is
performed by 512 comparators. The value of the least significant bit (LSB) is determined by a unique interpolation scheme
between adjacent comparators. The decoding logic processes
the comparator outputs and provides a 10-bit code to the output
stage of the converter.
Flash architecture has an advantage over other A/D architectures because conversion occurs in one step. This means the
performance of the converter is primarily limited by the speed
and matching of the individual comparators. In the AD9020, an
innovative interpolation scheme takes advantage of flash architecture but minimizes the input capacitance, power and device
count usually associated with that method of conversion.
These advantages occur by using only half the normal number
of input comparator cells to accomplish the conversion. In addition, a proprietary decoding scheme minimizes error codes. Input control pins allow the user to select from among Binary,
Inverted Binary, Twos Complement and Inverted Twos
Complement coding (see AD9020 Truth Table).
APPLICATIONS
Many of the specifications used to describe analog/digital converters have evolved from system performance requirements in
these applications. Different systems emphasize particular specifications, depending on how the part is used. The following applications highlight some of the specifications and features that
make the AD9020 attractive in these systems.
Wideband Receivers
Radar and communication receivers (baseband and direct IF
digitization), ultrasound medical imaging, signal intelligence
and spectral analysis all place stringent ac performance requirements on analog-to-digital converters (ADCs). Frequency domain characterization of the AD9020 provides signal-to-noise
ratio (SNR) and harmonic distortion data to simplify selection
of the ADC.
Receiver sensitivity is limited by the Signal-to-Noise Ratio of the
system. The SNR for an ADC is measured in the frequency domain and calculated with a Fast Fourier Transform (FFT). The
SNR equals the ratio of the fundamental component of the signal (rms amplitude) to the rms value of the noise. The noise is
the sum of all other spectral components, including harmonic
distortion, but excluding dc.
Good receiver design minimizes the level of spurious signals in
the system. Spurious signals developed in the ADC are the result of imperfections in the device transfer function (nonlinearities, delay mismatch, varying input impedance, etc.). In
the ADC, these spurious signals appear as Harmonic Distortion.
Harmonic Distortion is also measured with an FFT and is specified as the ratio of the fundamental component of the signal
(rms amplitude) to the rms value of the worst case harmonic
(usually the 2nd or 3rd).
Two-Tone Intermodulation Distortion (IMD) is a frequently cited
specification in receiver design. In narrow-band receivers, thirdorder IMD products result in spurious signals in the pass band
of the receiver. Like mixers and amplifiers, the ADC is characterized with two, equal-amplitude, pure input frequencies. The
IMD equals the ratio of the power of either of the two input signals to the power of the strongest third-order IMD signal. Unlike mixers and amplifiers, the IMD does not always behave as it
does in linear devices (reduced input levels do not result in predictable reductions in IMD).
Performance graphs provide typical harmonic and SNR data for
the AD9020 for increasing analog input frequencies. In choosing an A/D converter, always look at the dynamic range for the
analog input frequency of interest. The AD9020 specifications
provide guaranteed minimum limits at three analog test
frequencies.
Aperture Delay is the delay between the rising edge of the ENCODE command and the instant at which the analog input is
sampled. Many systems require simultaneous sampling of more
than one analog input signal with multiple ADCs. In these situations, timing is critical and the absolute value of the aperture
delay is not as critical as the matching between devices.
Aperture Uncertainty, or jitter, is the sample-to-sample variation
in aperture delay. This is especially important when sampling
high slew rate signals in wide bandwidth systems. Aperture uncertainty is one of the factors that degrade dynamic performance
as the analog input frequency is increased.
–6–
REV. A
Page 7
AD9020
Digitizing Oscilloscopes
Oscilloscopes provide amplitude information about an observed
waveform with respect to time. Digitizing oscilloscopes must accurately sample this signal, without distorting the information to
be displayed.
One figure of merit for the ADC in these applications is Effective
Number of Bits (ENOBs). ENOB is calculated with a sine wave
curve fit and equals:
ENOB = N – LOG
[Error (measured)/Error (ideal)]
2
N is the resolution (number of bits) of the ADC. The measured
error is the actual rms error calculated from the converter outputs with a pure sine wave input.
The Analog Bandwidth of the converter is the analog input fre-
quency at which the spectral power of the fundamental signal is
reduced 3 dB from its low frequency value. The analog bandwidth is a good indicator of a converter’s stewing capabilities.
The Maximum Conversion Rate is defined as the encode rate at
which the SNR for the lowest analog signal test frequency tested
drops by no more than 3 dB below the guaranteed limit.
Imaging
Visible and infrared imaging systems both require similar characteristics from ADCs. The signal input (from a CCD camera,
or multiplexer) is a time division multiplexed signal consisting of
a series of pulses whose amplitude varies in direct proportion to
the intensity of the radiation detected at the sensor. These varying levels are then digitized by applying encode commands at
the correct times, as shown below.
The actual resolution of the converter is limited by the thermal
and quantization noise of the ADC. The low frequency test for
SNR or ENOB is a good measure of the noise of the AD9020.
At this frequency, the static errors in the ADC determine the
useful dynamic range of the ADC.
Although the signal being sampled does not have a significant
slew rate, this does not imply dynamic performance is not important. The Transient Response and Overvoltage Recovery Time
specifications insure that the ADC can track full-scale changes
in the analog input sufficiently fast to capture a valid sample.
Transient Response is the time required for the AD9020 to
achieve full accuracy when a step function is applied. Overvoltage Recovery Time is the time required for the AD9020 to recover to full accuracy after an analog input signal 150% of full
scale is reduced to the full-scale range of the converter.
Professional Video
Digital Signal Processing (DSP) is now common in television
production. Modern studios rely on digitized video to create
state-of-the-art special effects. Video instrumentation also requires high resolution ADCs for studio quality measurement
and frame storage.
The AD9020 provides sufficient resolution for these demanding
applications. Conversion speed, dynamic performance and analog bandwidth are suitable for digitizing both composite and
RGB video sources.
FS
+
FS
–
ENCODE
A
IN
Imaging Application Using AD9020
AD9020
REV. A
–7–
Page 8
AD9020
USING THE AD9020
Voltage References
The AD9020 requires that the user provide two voltage references: +V
and –V
REF
. These two voltages are applied across
REF
an internal resistor ladder (nominally 37 Ω) and set the analog
input voltage range of the converter. The voltage references
should be driven from a stable, low impedance source. In addition to these two references, three evenly spaced taps on the resistor ladder (1/4
REF
, 1/2
REF
, 3/4
) are available. Providing a
REF
reference to these quarter points on the resistor ladder will improve the integral linearity of the converter and improve ac performance. (AC and dc specifications are tested while driving the
quarter points at the indicated levels.) The figure below is not
intended to show the transfer function of the ADC, but illustrates how the linearity of the device is affected by reference
voltages applied to the ladder.
The select resistors (R
) shown in the schematic (each pair can
S
be a potentiometer) are chosen to adjust the quarter-point voltage references, but are not necessary if R1–R4 match within
0.05%.
An alternative approach for defining the quarter-point refer-
ences of the resistor ladder is to evaluate the integral linearity
error of an individual device, and adjust the voltage at the
quarter-points to minimize this error. This may improve the low
frequency ac performance of the converter.
Performance of the AD9020 has been optimized with an analog
input voltage of ±1.75 V (as measured at ± V
). If the ana-
SENSE
log input range is reduced below these values, relatively larger
differential nonlinearity errors may result because of comparator
mismatches. As shown in the figure below, performance of the
converter is a function of ±V
62
56
50
44
SENSE
.
10.0
9.0
8.0
7.0
Effect of Reference Taps on Linearity
Resistance between the reference connections and the taps of
the first and last comparators causes offset errors. These errors,
called “top and bottom of the ladder offsets,” can be nulled by
using the voltage sense lines, +V
SENSE
and –V
, to adjust the
SENSE
reference voltages. Current through the sense lines should be
limited to less than 100 µA. Excessive current drawn through
the voltage sense lines will affect the accuracy of the sense line
voltage.
The next page shows a reference circuit which nulls out the offset errors using two op amps and provides appropriate voltage
references to the quarter-point taps. Feedback from the sense
lines causes the op amps to compensate for the offset errors.
The two transistors limit the amount of current drawn directly
from the op amps; resistors at the base connections stabilize
their operation. The 10 kΩ resistors (R1–R4) between the voltage sense lines form an external resistor ladder; the quarter
point voltages are taken off this external ladder and buffered by
an op amp. The actual values of resistors R1–R4 are not critical,
but they should match well and be large enough (≥10 kΩ) to
limit the amount of current drawn from the voltage sense lines.
SIGNAL-TO-NOISE (SNR) – dB
38
32
0.4 0.8 1.0 1.4 1.8 2.0
0.6 1.2 1.6
±V
SENSE
– Volts
6.0
EFFECTIVE NUMBER OF BITS (ENOB)
5.0
AD9020 SNR and ENOB vs. Reference Voltage
Applying a voltage greater than 4 V across the internal resistor
ladder will cause current densities to exceed rated values, and
may cause permanent damage to the AD9020. The design of
the reference circuit should limit the voltage available to the
references.
Analog Input Signal
The signal applied to ANALOG IN drives the inputs of 512
parallel comparator cells (see Equivalent Analog Input figure).
This connection typically has an input resistance of 7 kΩ, and
input capacitance of 45 pF. The input capacitance is nearly
constant over the analog input voltage range, as shown in the
graph which illustrates that characteristic.
The analog input signal should be driven from a low distortion,
low noise amplifier. A good choice is the AD9617, a wide bandwidth, monolithic operational amplifier with excellent ac and dc
performance. The input capacitance should be isolated by a
small series resistor (24 Ω for the AD9617) to improve the ac
performance of the amplifier (see AD9020/PCB Evaluation
Board Block Diagram).
–8–
REV. A
Page 9
AD9020
13k
14ENCODE
5.0V
+
+1.75V
356Ω
150Ω
+2.5V
AD580
1/2 AD708
R1
10kΩ
R2
10kΩ
R3
10kΩ
R4
10kΩ
R
R
R
R
S
S
S
S
150Ω
+1.75V
1/2 AD708
1/2 AD708
1/2 AD708
+5V
0.1µF
–0.875V
+0.875V
0V
0.1µF
0.1 µF
0.1 µF
+V
+V
SENSE
3/4
1/2
1/4
REF
REF
REF
REF
ANALOG INPUT
*
12
11
R/2
R
R/2
7
R/2
R
R
R/2
1
R/2
R
R
R/2
63
R/2
R
R
TO COMPARATORS
AD9020 Equivalent Analog Input
+
V
S
+V
3/4
1/2
1/4
–V
SENSE
REF
REF
REF
SENSE
R
20kΩ
20kΩ
1/2 AD708
–1.75V
150Ω
0.1µF
–V
SENSE
–V
REF
57
56
R/2
*
*
= WIRING
RESISTANCE = < 5Ω
DIGITAL BITS
AND OVERFLOW
AD9020
–
5V
AD9020 Reference Circuit
AD9020 Equivalent Digital Outputs
AD9020 Equivalent Encode Circuit
REV. A
–9–
Page 10
AD9020
ANALOG
INPUT
ENCODE
DATA
OUTPUT
N
t
a
N N + 1
t
OD
DATA FOR N DATA FOR N + 1
AD9020 Timing Diagram
Timing
In the AD9020, the rising edge of the ENCODE signal triggers
the A/D conversion by latching the comparators. (See the
AD9020 Timing Diagram.)
The ENCODE is TTL/CMOS compatible and should be driven
from a low jitter (phase noise) source. Jitter on the ENCODE
signal will raise the noise floor of the converter. Fast, clean
edges will reduce the jitter in the signal and allow optimum ac
performance. Locking the system clock to a crystal oscillator
also helps reduce jitter. The AD9020 is designed to operate with
a 50% duty cycle; small (10%) variations in duty cycle should
not degrade performance.
Data Format
The format of the output data (D0–D9) is controlled by the
MSB INVERT and LSBs INVERT pins. These inputs are dc
control inputs, and should be connected to GROUND or +V
.
S
The AD9020 Truth Table gives information to choose from
among Binary, Inverted Binary, Twos Complement and Inverted Twos Complement coding.
The OVERFLOW output is an indication that the analog input
signal has exceeded the voltage at +V
. The accuracy of the
SENSE
overflow transition voltage and output delay are not tested or included in the data sheet limits. Performance of the overflow indicator is dependent on circuit layout and slew rate of the
encode signal. The operation of this function does not affect the
other data bits (D
). It is not recommended for applications
0–D9
requiring a critical measure of the analog input voltage.
N + 1
t
– Aperture Delay
a
t
– Output Delay
OD
Layout and Power Supplies
Proper layout of high speed circuits is always critical but is particularly important when both analog and digital signals are
involved.
Analog signal paths should be kept as short as possible and be
properly terminated to avoid reflections. The analog input voltage and the voltage references should be kept away from digital
signal paths; this reduces the amount of digital switching noise
that is capacitively coupled into the analog section of the circuit.
Digital signal paths should also be kept short, and run lengths
should be matched to avoid propagation delay mismatch.
In high speed circuits, layout of the ground circuit is a critical
factor. A single, low impedance ground plane, on the component side of the board, will reduce noise on the circuit ground.
Power supplies should be capacitively coupled to the ground
plane to reduce noise in the circuit. Multilayer boards allow
designers to lay out signal traces without interrupting the
ground plane and provide low impedance power planes.
It is especially important to maintain the continuity of the
ground plane under and around the AD9020. In systems with
dedicated digital and analog grounds, all grounds of the
AD9020 should be connected to the analog ground plane.
The power supplies (+V
and –VS) of the AD9020 should be iso-
S
lated from the supplies used for external devices; this further reduces the amount of noise coupled into the A/D converter.
Sockets limit the dynamic performance and should be used only
for prototypes or evaluation—PCK Elastomerics Part # CCS-6855 is recommended for the LCC package. (Tel. 215-672-0787)
An evaluation board is available to aid designers and provide a
suggested layout.
–10–
REV. A
Page 11
AD9020
62
ENCODE RATE = 40MSPS
56
50
44
38
32
SIGNAL-TO-NOISE (SNR) – dB
26
20
1 2 4 6 8 10 20 60 100 20040
+55°C & +125°C
INPUT FREQUENCY – MHz
+25°C
10.0
9.0
8.0
7.0
6.0
5.0
4.0
AD9020 SNR and ENOB vs. Input Frequency
30
35
40
+
125
45
50
55
HARMONICS – dBc
60
65
C
–
55
C
+
C
25
62
56
50
44
38
32
SIGNAL-TO-NOISE (SNR) – dB
EFFECTIVE NUMBER OF BITS (ENOB)
26
20
1 2 4 6 8 10 20 40 100
AD9020 SNR and ENOB vs. Conversion Rate
48
47
46
45
INPUT CAPACITANCE – pF
44
ANALOG INPUT = 2.3MHz
CONVERSION RATE – MSPS
RESISTANCE
60
CAPACITANCE
10.0
9.0
8.0
7.0
6.0
5.0
EFFECTIVE NUMBER OF BITS (ENOB)
4.0
70
60
50
40
30
20
INPUT RESISTANCE – kΩ
10
70
AD9020 Harmonics vs. Input Frequency
2
1
6 8 10 20 60 10040
4
INPUT FREQUENCY – MHz
–1.8 –1.2 –0.6 0
ANALOG INPUT – Volts(A )
0.6+1.2+1.8
IN
+
Input Capacitance/Resistance vs. Input Voltage
AD9020 Truth Table
Offset Binary Twos Complement
Step Range True Inverted True Inverted
0 = –1.75 V MSB INV = “0” MSB INV = “1” MSB INV = “1” MSB INV = “0”
FS = +1.75 V LSBs INV = “0” LSBs INV = “1” LSBs INV = “0” LSBs INV = “1”
1024 > +1.7500 (1)1111111111 (1)0000000000 (1)0111111111 (1)1000000000
1023 +1.7466 1111111111 0000000000 0111111111 1000000000
1022 +1.7432 1111111110 0000000001 0111111110 1000000001
•• • • • •
•• • • • •
•• • • • •
512 +0.0034 1000000000 0111111111 0000000000 1111111111
511 0.000 0111111111 1000000000 1111111111 0000000000
510 –0.0034 0111111110 1000000001 1111111110 0000000001
•• • • • •
•• • • • •
•• • • • •
02 –1.7432 0000000010 1111111101 1000000010 0111111101
01 –1.7466 0000000001 1111111110 1000000001 0111111110
00 <–1.7466 0000000000 1111111111 1000000000 0111111111
The overflow bit is always 0 except where noted in parentheses ( ). MSB INVERT and LSBs INVERT are considered dc controls.
REV. A
–11–
Page 12
AD9020
AD9020/PCB EVALUATION BOARD
The AD9020/PCB Evaluation Board is available from the factory and is shown here in block diagram form. The board includes a reference circuit that allows the user to adjust both
references and the quarter-point voltages. The AD9617 is included as the drive amplifier, and the user can configure the
gain from –1 to –15.
+
5V–5V
BUFFERED
ANALOG
INPUT
TO ERROR
WAVEFORM
CIRCUIT
50Ω
200Ω
400Ω
U5
AD9617
ANALOG
J2
24Ω
REFERENCE
CIRCUIT
DUT
INPUT
–V
S
ANALOG
INPUT
+V
REF
+V
SENSE
3/4
REF
1/2
REF
1/4
REF
–V
SENSE
–V
REF
+V
S
AD9020
On-board reconstruction of the digital data is provided through
the AD9713, a 12-bit monolithic DAC. The analog and reconstructed waveforms can be summed on the board to allow the
user to observe the linearity of the AD9020 and the effects of
the quarterpoint voltages. The digital data and an adjustable
Data Ready signal are available through a 37-pin edge connector.
DAC
OUT
I
D
TIMING
CIRCUIT
OUT
50Ω
OUTPUT
CONNECTOR
DATA
DATA
READY
TO ERROR
WAVEFORM
CIRCUIT
GND
DUT
MSB INVERT
LSBs INVERT
(LSB) D
(MSB) D
OVERFLOW
ENCODE
AD9713 DAC
+
5V
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
9
D
D
D
D
D
D
D
D
D
D
D
TTL
LATCHES
TTL CLK
Q
CLK
C1348b–0–6/97
AD9020/PCB Evaluation Board Block Diagram
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
68-Leaded Ceramic Chip Carrier 68-Terminal
(Z-68) Leadless Chip Carrier (LCC)
(E-68A)
PRINTED IN U.S.A.
–12–
REV. A
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