Datasheet AD9012 Datasheet (Analog Devices)

High Speed 8-Bit

a

FEATURES
100 MSPS Encode Rate
Very Low Input Capacitance—16 pF
Low Power—1 W
TTL Compatible Outputs
MIL-STD-883 Compliant Versions Available

APPLICATIONS
Radar Guidance
Digital Oscilloscopes/ATE Equipment
Laser/Radar Warning Receivers
Digital Radio
Electronic Warfare (ECM, ECCM, ESM)
Communication/Signal Intelligence

GENERAL DESCRIPTION

The AD9012 is an 8-bit, ultrahigh speed, analog-to-digital
converter. The AD9012 is fabricated in an advanced bipolar
process that allows operation at sampling rates up to one hun­dred megasamples/second. Functionally, the AD9012 is com­prised of 256 parallel comparator stages whose outputs are
decoded to drive the TTL compatible output latches.

The exceptionally wide large-signal analog input bandwidth of
160 MHz is due to an innovative comparator design and very
close attention to device layout considerations. The wide input
bandwidth of the AD9012 allows very accurate acquisition of
high speed pulse inputs without an external track-and-hold. The
comparator output decoding scheme minimizes false codes,
which is critical to high speed linearity.

The AD9012 is available in two grades: one with 0.5 LSB linear­ity and one with 0.75 LSB linearity. Both versions are offered in

TTL A/D Converter

AD9012

FUNCTIONAL BLOCK DIAGRAM

OVERFLOW

INHIBIT

ANALOG IN

1V

REF

REF

MID

2V

REF

ENCODE

R

R

R

R/2

R/2

R

R

256

255

128

127

2

1

GND HYSTERESIS

an industrial grade, –25°C to +85°C, packaged in a 28-lead DIP

and a 28-lead JLCC. The military temperature range devices,

–55°C to +125°C, are available in ceramic DIP and LCC pack-

ages and are compliant to MIL-STD-883 Class B.

The AD9012 is available in versions compliant with MIL-STD-

883. Refer to the Analog Devices Military Products Databook
or current AD9012/883B data sheet for detailed specifications.

D
E
C
O
D

I
N
G

L
O
G

I
C

AD9012

L
A
T
C
H

2V

1V

S

OVERFLOW

D8 (MSB)

D

D

D

D

D

D

D1 (LSB)

S

7

6

5

4

3

2

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD9012–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(+VS = +5.0 V; –VS = –5.2 V; Differential Reference Voltage = 2.0 V; unless otherwise noted)

Test AD9012AQ/AJ AD9012BQ/BJ AD9012SQ/SE AD9012TQ/TE

Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units

RESOLUTION 8 8 8 8 Bits

DC ACCURACY

Differential Linearity +25°C I 0.6 0.75 0.4 0.5 0.6 0.75 0.4 0.5 LSB

Full VI 1.0 0.75 1.0 0.75 LSB

Integral Linearity +25°C I 0.6 1.0 0.4 0.5 0.6 1.0 0.4 0.5 LSB

Full VI 1.2 1.2 1.2 1.2 LSB

No Missing Codes Full VI GUARANTEED GUARANTEED GUARANTEED GUARANTEED

INITIAL OFFSET ERROR

Top of Reference Ladder +25°C I 7 15 7 15 7 15 7 15 mV

Full VI 18 18 18 18 mV

Bottom of Reference Ladder +25°C I 6 10 6 10 6 10 6 10 mV

Full VI 13 13 13 13 mV

Offset Drift Coefficient Full V 25 25 25 25 µV/°C

ANALOG INPUT

Input Bias Current

1

+25°C I 60 200 60 200 60 200 60 200 µA

Full VI 200 200 200 200 µA
Input Resistance +25°C I 25 200 25 200 25 200 25 200 kΩ
Input Capacitance +25°C III 16 18 16 18 16 18 16 18 pF

Large Signal Bandwidth
Analog Input Slew Rate

2

3

+25°C V 160 160 160 160 MHz

+25°C V 440 440 440 440 V/µs

REFERENCE INPUT

Reference Ladder Resistance +25°C VI 40 80 110 40 80 110 40 80 110 40 80 110 Ω
Ladder Temperature Coefficient V 0.25 0.25 0.25 0.25 Ω/°C
Reference Input Bandwidth +25°C V 10 10 10 10 MHz

DYNAMIC PERFORMANCE

Conversion Rate +25°C I 75 100 75 100 75 100 75 100 MSPS
Aperture Delay +25°C V 3.8 3.8 3.8 3.8 ns
Aperture Uncertainty (Jitter) +25°C V 15 15 15 15 ps

Output Delay (tPD)
Transient Response
Overvoltage Recovery Time
Output Rise Time
Output Fall Time
Output Time Skew

ENCODE INPUT

Logic “1” Voltage
Logic “0” Voltage

4, 5

6

4

4

4, 8

4

4

+25°C I 4 4.9 11 4 4.9 11 4 4.9 11 4 4.9 11 ns

+25°CV 8 8 8 8 ns

7

+25°CV 8 8 8 8 ns

+25°C I 6.6 8.0 6.6 8.0 6.6 8.0 6.6 8.0 ns

+25°C I 3.3 4.3 3.3 4.3 3.3 4.3 3.3 4.3 ns

+25°C V 3.0 3.0 3.0 3.0 ns

Full VI 2.0 2.0 2.0 2.0 V

Full VI 0.8 0.8 0.8 0.8 V

Logic “1” Current Full VI 250 250 250 250 µA
Logic “0” Current Full VI 400 400 400 400 µA
Input Capacitance +25°C V 2.5 2.5 2.5 2.5 pF

Encode Pulsewidth (Low)
Encode Pulsewidth (High)

9

+25°C I 2.5 2.5 2.5 2.5 ns

9

+25°C I 2.5 2.5 2.5 2.5 ns

OVERFLOW INHIBIT INPUT

0 V Input Current Full VI 200 250 200 250 200 250 200 250 µA

AC LINEARITY

Effective Bits

10

11

+25°C V 7.5 7.5 7.5 7.5 Bits

In-Band Harmonics

dc to 1.23 MHz +25°C I 48 55 48 55 48 55 48 55 dBc
dc to 9.3 MHz +25°C V 50 50 50 50 dBc
dc to 19.3 MHz +25°C V 44 44 44 44 dBc

Signal-to-Noise Ratio
Noise Power Ratio

12

13

+25°C I 46 47.6 46 47.6 46 47.6 46 47.6 dBc

+25°C V 37 37 37 37 dBc

DIGITAL OUTPUT

Logic “1” Voltage Full VI 2.4 2.4 2.4 2.4 V
Logic “0” Voltage Full VI 0.4 0.4 0.4 0.4 V

POWER SUPPLY

14

Positive Supply Current (+5.0 V) +25°C I 33 45 33 45 33 45 33 45 mA

Full VI 48 48 48 48 mA

Supply Current (–5.2 V) +25°C I 152 179 152 179 152 179 152 179 mA

Full VI 191 191 191 191 mA

Nominal Power Dissipation +25°C V 955 955 955 955 mW
Reference Ladder Dissipation +25°C V 44 44 44 44 mW

Power Supply Rejection Ratio

15

+25°C I 0.85 2.5 0.85 2.5 0.8 2.5 0.8 2.5 mV/V

–2–

REV. D

AD9012

NOTES

1

Measured with Analog Input = 0 V.

2

Measured by FFT analysis where fundamental is –3 dBc.

3

Input slew rate derived from rise time (10% to 90%) of full-scale step input.

4

Outputs terminated with two equivalent ’LS00 type loads. (See load circuit.)

5

Measured from ENCODE into data out for LSB only.

6

For full-scale step input, 8-bit accuracy is attained in specified time.

7

Recovers to 8-bit accuracy in specified time, after 150% full-scale input overvoltage.

8

Output time skew includes high-to-low and low-to-high transitions as well a
bit-to-bit time skew differences.

ABSOLUTE MAXIMUM RATINGS

1

s

Positive Supply Voltage (+VS) . . . . . . . . . . . . . . . . . . . . . +6 V

Analog to Digital Supply Voltage Differential (–V
Negative Supply Voltage (–V

) . . . . . . . . . . . . . . . . . . . . –6 V

S

Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . –V

) . . . . 0.5 V

S

to +0.5 V

S

ENCODE Input Voltage . . . . . . . . . . . . . . . . . –0.5 V to +5 V

OVERFLOW INH Input Voltage . . . . . . . . . . . –5.2 V to 0 V

Reference Input Voltage (+V

REF –VREF

)2 . . . . –3.5 V to +0.1 V

Differential Reference Voltage . . . . . . . . . . . . . . . . . . . . .2.1 V

Reference Midpoint Current . . . . . . . . . . . . . . . . . . . . ±4 mA

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 30 mA

Operating Temperature Range

AD9012AQ/BQ/AJ/BJ . . . . . . . . . . . . . . . . –25°C to +85°C

AD9012SE/SQ/TE/TQ . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature

3

. . . . . . . . . . . . . . . . . . . . . . . . +175°C

Lead Soldering Temperature (10 sec) . . . . . . . . . . . . . +300°C

NOTES

1

Absolute maximum ratings are limiting values, to be applied individually, and

beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.

2

+V

≥ –V

REF

3

Maximum junction temperature (t

packages, and +150°C for plastic packages:
t

= PD (θ

J

PD (θ
where
PD = power dissipation
θJA = thermal impedance from junction to ambient (°C/W)
θJC = thermal impedance from junction to case (°C/W)
t
t
typical thermal impedances are:
Ceramic DIP θ
Ceramic LCC θJA = 50°C/W; θJC = 15°C/W
JLCC θJA = 59°C/W; θ

under all circumstances.

REF

) + t

JA

A

) + tc

JC

= ambient temperature (°C)

A

= case temperature (°C)

C

= 42°C/W; θ

JA

= 15°C/W.

JC

max) should not exceed +175°C for ceramic

J

= 10°C/W

JC

Recommended Operating Conditions

Input Voltage

Parameter Min Nominal Max

–V

S

+V

S

+V

REF

–V

REF

Analog Input –V

–5.46 –5.20 –4.94
+4.75 5.00 +5.25
–V

REF

–2.1 –2.0 +V

REF

0.0 V +0.1

+V

REF

REF

9

ENCODE signal rise/fall times should be less than 30 ns for normal operation.

10

Measured at 75 MSPS encode rate. Harmonic data based on worst case harmonics.

11

Analog input frequency = 1.23 MHz.

12

RMS signal to rms noise, including harmonics with 1.23 MHz. analog input
signal.

13

NPR measured @ 0.5 MHz. Noise Source is 250 mW (rms) from 0.5 MHz
to 8 MHz.

14

Supplies should remain stable within ±5% for normal operation.

15

Measured at –5.2 V ± 5% and +5.0 V ± 5%.

Specifications subject to change without notice.

V

S

TTL

OUTPUT

15pF

1kV

Figure 1. Load Circuit

EXPLANATION OF TEST LEVELS
Test Level

I – 100% production tested.

II – 100% production tested at +25°C, and sample tested at

specified temperatures. AC testing done on sample basis.

III – Sample tested only.

IV – Parameter is guaranteed by design and characterization

testing.

V – Parameter is a typical value only.

VI – All devices are 100% production tested at +25°C. 100%

production tested at temperature extremes for extended
temperature devices; guaranteed by design and
characterization testing for industrial devices.

ORDERING GUIDE

Temperature Package

Device Linearity Ranges Options*

AD9012AQ 0.75 LSB –25°C to +85°C Q-28
AD9012BQ 0.50 LSB –25°C to +85°C Q-28
AD9012AJ 0.75 LSB –25°C to +85°C J-28A
AD9012BJ 0.50 LSB –25°C to +85°C J-28A
AD9012SQ 0.75 LSB –55°C to +125°C Q-28
AD9012SE 0.75 LSB –55°C to +125°C E-28A
AD9012TQ 0.50 LSB –55°C to +125°C Q-28
AD9012TE 0.50 LSB –55°C to +125°C E-28A

*E = Leadless Ceramic Chip Carrier; J = Ceramic Leaded Chip Carrier;

Q = Cerdip.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9012 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. D

–3–

WARNING!

ESD SENSITIVE DEVICE

AD9012

PIN FUNCTION DESCRIPTIONS

Pin # Name Description

11 DIGITAL +V

S

12 OVERFLOW INH OVERFLOW INHIBIT controls the data output coding for overvoltage inputs (AIN ≥ + V

13 HYSTERESIS The Hysteresis control voltage varies the comparator hysteresis from 0 mV to 10 mV, for a

14+V

REF

15 ANALOG INPUT One of two analog input pins. Both analog input pins should be connected together.
16 ANALOG GROUND One of two analog ground pins. Both analog ground pins should be connected together.
17 ENCODE TTL level encode command input. ENCODE is rising edge sensitive.
18 DIGITAL +V

S

19 ANALOG GROUND One of two analog ground pins. Both analog ground pins should be connected together.

10 ANALOG INPUT One of two analog input pins. Both analog inputs should be connected together.
11 –V
12 REF
13 DIGITAL +V
14 DIGITAL –V

15 D
16–19 D

REF

MID

S

S

(LSB) Digital data output. D1 (LSB) is the least significant bit of the digital output word.

1

2–D5

20 DIGITAL GROUND One of two digital ground pins. Both digital grounds pins should be connected together.
21, 22 ANALOG –V

S

23 DIGITAL GROUND One of two digital ground pins. Both digital ground pins should be connected together.
24, 25 D
26 D

, D

6

7

(MSB) Digital data output D8 (MSB) is the most significant bit of the digital output word.

8

27 OVERFLOW Overflow data output. Logic HIGH indicates an input overvoltage (V

28 DIGITAL –V

S

One of three positive digital supply pins (nominally +5.0 V).

).

REF

ANALOG OVERFLOW ENABLED (FLOATING) OVERFLOW INHIBITED (GND)
INPUT OF Dl D2 D3 D4 D5 D6 D7 D

V
V

≥ + V

IN

< + V

IN

1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

REF

0 X X X X X X X X 0 X X X X X X X X

REF

8

OF Dl D2 D3 D4 D5 D6 D7 D

8

change from –5.2 V to –2.2 V at the Hysteresis control pin.
The most positive reference voltage for the internal resistor ladder.

One of three positive digital supply pins (nominally +5.0 V).

The most negative reference voltage for the internal resistor ladder.
The midpoint tap on the internal resistor ladder.
One of three positive digital supply pins (nominally +5.0 V).
One of two negative digital supply pins (nominally –5.2 V). Both digital supply pins should be
connected together.

Digital data output.

One of two negative analog supply pins (nominally –5.2 V). Both analog supply pins should be
connected together.

Digital data output.

IN

> + V

REF

), if
OVERFLOW INHIBIT is enabled (overflow enabled, floating). See OVERFLOW INHIBIT.
One of two negative digital supply pins (nominally –5.2 V). Both digital supply pins should be
connected together.

DIGITAL V

OVERFLOW INH

HYSTERESIS

+V

REF

ANALOG INPUT

ANALOG GROUND

ENCODE

DIGITAL V

ANALOG GROUND

ANALOG INPUT

–V

REF

REF

MID

DIGITAL VS+
DIGITAL VS–

+

S

+

S

1

2

3

4

5

6

AD9012

7

TOP VIEW

(Not to Scale)

8

9

10

11

12

13

14

28

DIGITAL V

27

OVERFLOW

26

(MSB)

D

8

25

D

7

D

24

6

23

DIGITAL GROUND

22

ANALOG VS–

21

ANALOG V

20

DIGITAL GROUND

19

D

5

18

D

4

17

D

3

16

D

2

15

(LSB)

D

1

PIN CONFIGURATIONS

–

S

ANALOG INPUT

ANALOG GROUND

ENCODE

–

S

DIGITAL V

ANALOG GROUND

ANALOG INPUT

–V

–4–

REF

–

+

S

S

REF

+V

HYSTERESIS

OVERFLOW INH

3426

2

5
6
7
8

+

S

9

10
11

AD9012

TOP VIEW

(Not to Scale)

12

13 14 15 16 17 18

–

+

S

S

MID

REF

DIGITAL V

DIGITAL V

OVERFLOW

DIGITAL V

DIGITAL V

28 271

3

2

D

D

(LSB)

1

D

(MSB)

8

D

4

D

25
24

23
22

21
20
19

D

7

D

6

DIGITAL GROUND
ANALOG V
ANALOG V
DIGITAL GROUND
D

5

–

S

–

S

REV. D

AD9012

ENCODE

15.0V

ANALOG

INPUT

ENCODE

OUTPUT

DATA

ANALOG

INPUT

N + 1

N

APERTURE
DELAY

t

PD

N – 1

Figure 2. Timing Diagram

256 COMPARATOR

25.2V

CELLS

Figure 3. Input Output Circuits

R

R/2

R/2

R

N

2V

1V

REF

REF

REF

MID

N + 2

15.0V

N + 1

DIGITAL
OUTPUTS

DIE LAYOUT AND MECHANICAL INFORMATION

Die Dimensions . . . . . . . . . . . . . . . . 111 × 123 × 15 (±2) mils

Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils

Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold

Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None

Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V

S

Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride

Die Attach . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic)

Epoxy (Plastic)

Bond Wire . . . . . . . . . . . . . 1–1.3 mil Gold; Gold Ball Bonding

AD1

AD2

–2.0V

–5.2V

0.1mF

ONE JUMPER

PER BOARD

100V

AIN

–V

S

OVERFLOW

D8 (MSB)

AD9012

510V

ENCODE

–V

REF

V

H

+V

REF

DIGITAL

GROUND

ALL RESISTORS 6 5%
ALL CAPACITORS 6 20%
ALL SUPPLY VOLTAGES 6 5%
OPTION #1 (STATIC) AD1 = –2.0V; AD2 = +2.4V
OPTION #2 (DYNAMIC) SEE WAVEFORMS

AD1

AD2

640ms

5ms

D1 (LSB)

Figure 4. Burn-In Diagram

+5.0V

+V

S

D
D

D
D

D
D

D1 (LSB)

ANALOG
GROUND

7
6

5

4
3
2

0.1mF

1kV
1kV
1kV
1kV
1kV
1kV
1kV
1kV
1kV

LOAD
RESISTORS

0V

–2V

+2.4V
+0.4V

REV. D

–5–

AD9012

APPLICATION INFORMATION

The AD9012 is compatible with all standard TTL logic fami­lies. However, to operate at the highest encode rates, the sup­porting logic around the AD9012 will need to be equally fast.
Two possible choices are the AS and the ALS families. Which­ever of the TTL logic families is used, special care must be
exercised to keep digital switching noise away from the analog
circuits around the AD9012. The two most critical items are the
digital supply lines and the digital ground return.

The input capacitance of the AD9012 is an exceptionally low
16 pF. This allows the use of a wide range of input amplifiers,
both hybrid and monolithic. To take full advantage of the
160 MHz input bandwidth of the AD9012, a hybrid amplifier
like the AD9610/AD9611 will be required. For those applica­tions that do not require the full input bandwidth of the AD9012,
some of the more traditional monolithic amplifiers, like the
AD846, should work very well. Overall performance with mono-

lithic amplifiers can be improved by inserting a 40 Ω resistor in

series with the amplifier output.

The output data is buffered through the TTL compatible out­put latches. In addition to the latch propagation delay (t

PD

), all
data is delayed by one clock cycle, before becoming available at
the outputs. Both the analog-to-digital conversion cycle and the
data transfer to the output latches are triggered on the rising edge
of the TTL-compatible ENCODE signal (see timing diagram).

The AD9012 also incorporates a HYSTERESIS control pin
which provides from 0 mV to 10 mV of additional hysteresis in
the comparator input stages. Adjustments in the HYSTERESIS
control voltage may help to improve noise immunity and overall
performance in harsh environments.

The OVERFLOW INHIBIT pin of the AD9012 determines

how the converter handles overrange inputs (AIN ≥ + V

REF

). In
the “enabled” state (floating at –5.2 V), the OVERFLOW out­put will be at logic HIGH and all other outputs will be at logic
LOW for overrange inputs (return-to-zero operation). In the
“inhibited” state (tied to ground), the OVERFLOW output will
be at logic LOW for overrange inputs, and all other digital out­puts will be at logic HIGH (nonreturn-to-zero operation).

The AD9012 provides outstanding error rate performance. This
is due to tight control of comparator offset matching and a fault
tolerant decoding stage. Additional improvements in error rate
are possible through the addition of hysteresis (see HYSTER­ESIS control pin). This level of performance is extremely impor­tant in fault sensitive applications such as digital radio (QAM).

Dramatic improvements in comparator design and construction
give the AD9012 excellent dynamic characteristics, namely SNR
(signal-to-noise ratio). The 160 MHz input bandwidth and low
error rate performance give the AD9012 an SNR of 47 dB with
a 1.23 MHz input. High SNR performance is particularly im­portant in broadcast video applications where signals may pass
through the converter several times before the processing is
complete. Pulse signature analysis, commonly performed in
advanced radar receivers, is another area that is especially
dependent on high quality dynamic performance.

LAYOUT SUGGESTIONS

Designs using the AD9012, like all high-speed devices, must
follow a few basic layout rules to insure optimum performance.
Essentially, these guidelines are meant to avoid many of the
problems associated with high-speed designs. The first require­ment is for a substantial ground plane around and under the
AD9012. Separate ground plane areas for the digital and analog
components may be useful, but the separate grounds should
be connected together at the AD9012 to avoid the effects of
“ground loop” currents.

The second area that requires an extra degree of attention
involves the three reference inputs, +V
The +V

input and the –V

REF

input should both be driven

REF

from a low impedance source (note that the +V

REF

, REF

, and –V

MID

input is

REF

REF

.

typically tied to analog ground). A low drift amplifier should
provide satisfactory results, even over an extended temperature
range. Adjustments at the REF

input may be useful in im-

MID

proving the integral linearity by correcting any reference ladder
skews.

The reference inputs should be adequately decoupled to ground

through 0.1 µF chip capacitors to limit the effects of system

noise on conversion accuracy. The power supply pins must also

be decoupled to ground to improve noise immunity; 0.1 µF and

0.01 µF chip capacitors should be very effective.

The analog input signal is brought into the AD9012 through
two separate input pins. It is very important that the two input
pins be driven symmetrically with equal length electrical
connections. Otherwise, aperture delay errors may degrade
converter performance at high frequencies.

–15V

1kV

4kV

100V

2N3906

–V

REF

A

IN

A

IN

AD9012

ENCODE

+5.0V

0.1mF

10V

0.1mF

+V

REF

OVERFLOW

D

(MSB)

8

D1 (LSB)

–5.2V

0.1mF0.01mF

D

7

D

6

D

5

D

4

D

3

D

2

0.01mF

ANALOG

INPUT

(0 TO +2V)

TTL

ENCODE

INPUT

NYQUEST

FILTER

50V

50V

1.5kV

AD9611

0.1mF

40V

AD741

EQUAL

DISTANCE

Figure 5. Typical Application

–6–

REV. D

AD9012

ANALOG

INPUT

(2V p-p MAX)

TTL

ENCODE

INPUT

50V

50V

100V

82V

1N747

500V

–5.2V

2N3906

HOS200

1kV

560V

1kV

AD642

AD741

0.01mF

EQUAL

DISTANCE

0.1mF

0.01mF

74AS04

LINEARITY OUTPUT

(ERROR WAVEFORM)

430V

100V

160V

2N3906

10V

240V

0.1mF

0.1mF

–V

REF

A

IN

AD9012

A

IN

ENCODE
OVERFLOW

INH
HYSTERESIS

+5.0V

0.1mF

430V

–5.2V

100V

REF

MID

OVERFLOW

–5.2V

AD642

240V

0.1mF
+V

D8 (MSB)

D1 (LSB)

REF

D
D
D
D
D
D

RECONSTRUCTED

OUTPUT

50V

NOTE:
10124, ECL OUTPUTS,
SHOULD BE TERMINATED
TO –2V WITH
100V REGISTERS.

37.5V

AD9768

10124 10124

7
6

LATCH

5

74AS843

4
3
2

CLK

0.01mF0.1mF
1kV

25 PIN

D

CONNECTOR

Figure 6. Evaluation Circuit

70

65

60

55

3RD HARMONIC

50

dBc

45

40

*WITH HARMONICS
INPUT = 0.1dB BELOW FULL SCALE

35

ENCODE RATE = 75MSPS

30

1

2ND HARMONIC

SNR*

ANALOG INPUT FREQUENCY – MHz

Figure 7. Dynamic Performance

10

100

REV. D

–7–

AD9012

BOTTOM VIEW

0.025 (0.635)

0.019 (0.483)

PIN 1

0.22

(5.59)

MAX

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead JLCC

(J-28A)

18

12

0.300

(7.62)

0.171 (4.34)

TYP

0.112 (1.702)

0.092 (1.194)

0.050

(1.27)

BSC

0.456 (11.582)

SQ

0.444 (11.278)

25 19

26

PIN 1

TOP VIEW

(PINS DOWN)

4

5

0.498 (12.649)

SQ

0.478 (12.141)

11

28-Lead Cerdip

(Q-28)

1.490 (37.84) MAX

28

114

GLASS SEALANT

0.02 (0.5)

0.016 (0.406)

0.11 (2.79)

0.099 (2.28)
LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH

LEADS ARE SOLDER OR TIN PLATED KOVAR OR ALLOY 42

0.06 (1.52)

0.05 (1.27)

15

0.525 (13.33)

0.515 (13.08)

0.18 (4.57)
MAX

0.125
(3.175)
MIN

SEATING
PLANE

158

08

MAX

0.62 (15.74)

0.59 (14.93)

0.044 (1.118)

0.034 (0.864)

0.030 (0.762)

0.026 (0.660)

0.021 (0.534)

0.017 (0.432)

0.0066 (0.167)

0.0054 (0.137)

0.012 (0.305)

0.008 (0.203)

0.430 (10.922)

0.410 (10.414)

C1169c–0–8/99

28-Terminal Leadless Chip Carrier

(E-28A)

0.100 (2.54)

0.458 (11.63)

0.442 (11.23)

NOTES

1
2

TERMINALS ARE GOLD PLATED OR SOLDER DIPPED.

2

0.064 (1.63)

TOP

VIEW

THIS DIMENSION CONTROLS THE OVERALL PACKAGE THICKNESS.
APPLIES TO ALL FOUR SIDES.

1

0.055 (1.40)

0.045 (1.14)

0.075 (1.91)
REF

26

25

19

18

0.055 (1.40)

0.045 (1.14)

PIN 1
INDEX

28

1

BOTTOM

VIEW

4

5

12

11

–8–

0.020 3 458
(0.51 3 458)
REF

0.028 (0.71)

0.022 (0.56)

0.040 3 458
(1.02 3 458)
REF 3 PLCS

PRINTED IN U.S.A.

REV. D