Datasheet AD9002TE-883B, AD9002TD-883B, AD9002SE-883B, AD9002SD-883B, AD9002BJ Datasheet (Analog Devices)

High-Speed 8-Bit

a

FEATURES
150 MSPS Encode Rate
Low Input Capacitance: 17 pF
Low Power: 750 mW
–5.2 V Single Supply
MIL-STD-883 Compliant Versions Available

APPLICATIONS
Radar Systems
Digital Oscilloscopes/ATE Equipment
Laser/Radar Warning Receivers
Digital Radio
Electronic Warfare (ECM, ECCM, ESM)
Communication/Signal Intelligence

GENERAL DESCRIPTION

The AD9002 is an 8-bit, high-speed, analog-to-digital converter.
The AD9002 is fabricated in an advanced bipolar process that
allows operation at sampling rates in excess of 150 megasamples/
second. Functionally, the AD9002 is comprised of 256 parallel
comparator stages whose outputs are decoded to drive the ECL
compatible output latches.

An exceptionally wide large signal analog input bandwidth of
160 MHz is due to an innovative comparator design and very
close attention to device layout considerations. The wide input
bandwidth of the AD9002 allows very accurate acquisition of
high speed pulse inputs, without an external track-and-hold.
The comparator output decoding scheme minimizes false codes,
which is critical to high speed linearity.

The AD9002 provides an external hysteresis control pin that
can be used to optimize comparator sensitivity to further improve
performance. Additionally, the AD9002’s low power dissipation
of 750 mW makes it usable over the full extended temperature
range. The AD9002 also incorporates an overflow bit to indicate
overrange inputs. This overflow output can be disabled with the
overflow inhibit pin.

Monolithic A/D Converter

AD9002

FUNCTIONAL BLOCK DIAGRAM

OVERFLOW

INHIBIT

ANALOG IN

+V

REF

REF

MID

–V

REF

ENCODE

ENCODE

R

R

R

R/2

R/2

R

R

256

255

128

127

2

1

GND HYSTERESIS

The AD9002 is available in two grades, one with 0.5 LSB linearity
and one with 0.75 LSB linearity. Both versions are offered in an
industrial grade, –25°C to +85°C, packaged in a 28-lead DIP
and a 28-leaded JLCC. The military temperature range devices,
–55°C to +125°C, are available in ceramic DIP and LCC pack­ages and comply with MIL-STD-883 Class B.

D
E
C
O
D

I
N
G

L
O
G

I
C

AD9002

L
A
T
C
H

–V

S

OVERFLOW

BIT 8 (MSB)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1 (LSB)

REV. F

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD9002–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(–VS = –5.2 V; Differential Reference Voltage = 2.0 V; unless otherwise noted)

AD9002AD/AJ AD9002BD/BJ AD9002SD/SE AD9002TD/TE

Parameter Temp Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit

RESOLUTION 8 8 8 8 Bits

DC ACCURACY

Differential Linearity 25°C 0.6 0.75 0.4 0.5 0.6 0.75 0.4 0.5 LSB

Full 1.0 0.75 1.0 0.75 LSB

Integral Linearity 25°C 0.6 1.0 0.4 0.5 0.6 1.0 0.4 0.5 LSB

Full 1.2 1.2 1.2 1.2 LSB

No Missing Codes Full GUARANTEED GUARANTEED GUARANTEED GUARANTEED

INITIAL OFFSET ERROR

Top of Reference Ladder 25°C 8 14 8 14 8 14 8 14 mV

Full 17 17 17 17 mV

Bottom of Reference Ladder 25°C 4 10 4 10 4 10 4 10 mV

Full 12 12 12 12 mV

Offset Drift Coefficient Full 20 20 20 20 µV/°C

ANALOG INPUT

Input Bias Current

1

25°C 60 200 60 200 60 200 60 200 µA

Full 200 200 200 200 µA
Input Resistance 25°C 25 200 25 200 25 200 25 200 kΩ
Input Capacitance 25°C 1722 1722 1722 1722 pF
Large Signal Bandwidth
Input Slew Rate

2

3

25°C 160 160 160 160 MHz

25°C 440 440 440 440 V/µs

REFERENCE INPUT

Reference Ladder Resistance 25°C 40 80 110 40 80 110 40 80 110 40 80 110 Ω
Ladder Temperature Coefficient 0.25 0.25 0.25 0.25 Ω/°C
Reference Input Bandwidth 25°C10101010MHz

DYNAMIC PERFORMANCE

Conversion Rate 25°C 125 150 125 150 125 150 125 150 MSPS
Aperture Delay 25°C 1.3 1.3 1.3 1.3 ns
Aperture Uncertainty (Jitter) 25°C15151515ps
Output Delay (tPD)
Transient Response
Overvoltage Recovery Time725°C6666ns
Output Rise Time
Output Fall Time
Output Time Skew

ENCODE INPUT

Logic “1” Voltage
Logic “0” Voltage

4, 5

6

4

4

4, 8

4

4

25°C 2.5 3.7 5.5 2.5 3.7 5.5 2.5 3.7 5.5 2.5 3.7 5.5 ns

25°C6666ns

25°C 3.0 3.0 3.0 3.0 ns

25°C 2.5 2.5 2.5 2.5 ns

25°C 0.6 0.6 0.6 0.6 ns

Full –1.1 –1.1 –1.1 –1.1 V

Full –1.5 –1.5 –1.5 –1.5 V
Logic “1” Current Full 150 150 150 150 µA
Logic “0” Current Full 120 120 120 120 µA
Input Capacitance 25°C3333pF
Encode Pulsewidth (Low)
Encode Pulsewidth (High)

9

25°C 1.5 1.5 1.5 1.5 ns

9

25°C 1.5 1.5 1.5 1.5 ns

OVERFLOW INHIBIT INPUT

0 V Input Current Full 144 300 144 300 144 300 144 300 µA

AC LINEARITY

Effective Bits

10

11

25°C 7.6 7.6 7.6 7.6 Bits
In-Band Harmonics

dc to 1.23 MHz 25°C4855 4855 4855 4855 dB
dc to 9.3 MHz 25°C50505050dB
dc to 19.3 MHz 25°C44444444dB

Signal-to-Noise Ratio

12

25°C 46 47.6 46 47.6 46 47.6 46 47.6 dB
Two Tone Intermod Rejection1325°C60606060dB

DIGITAL OUTPUTS

4

Logic “1” Voltage Full –1.1 –1.1 –1.1 –1.1 V
Logic “0” Voltage Full –1.5 –1.5 –1.5 –1.5 V

POWER SUPPLY

14

Supply Current (–5.2 V) 25°C 145 175 145 175 145 175 145 175 mA

Full 200 200 200 200 mA
Nominal Power Dissipation 25°C 750 750 750 750 mW
Reference Ladder Dissipation 25°C50505050mW
Power Supply Rejection Ratio1525°C 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 mV/V

NOTES

1

Measured with AIN = 0 V.

2

Measured by FFT analysis where fundamental is –3 dBc.

3

Input slew rate derived from rise time (10 to 90%) of full scale input.

4

0utputs terminated through 100 Ω to –2 V.

5

Measured from ENCODE in to data out for LSB only.

6

For full-scale step input, 8-bit accuracy is attained in specified time.

7

Recovers to 8-bit accuracy in specified time after 150% full-scale input overvoltage.

8

Output time skew includes high-to-low and low-to-high transitions as well as

bit-to-bit time skew differences.

9

ENCODE signal rise/fall times should be less than 10 ns for normal operation.

10

Measured at 125 MSPS encode rate.

11

Analog input frequency = 1.23 MHz.

12

RMS signal to rms noise, with 1.23 MHz analog input signal.

13

Input signals 1 V p-p @ 1.23 MHz and 1 V p-p @ 2.30 MHz.

14

Supplies should remain stable within ± 5% for normal operation.

15

Measured at –5.2 V ± 5%.

Specifications subject to change without notice.

–2–

REV. 0

AD9002

ABSOLUTE MAXIMUM RATINGS

1

Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V

Analog-to-Digital Supply Voltage Differential . . . . . . . . 0.5 V

Analog Input Voltage . . . . . . . . . . . . . . . . . . . . –V

Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . –V

Reference Input Voltage (+V

REF

– V

)2 . . . –3.5 V to +0.1 V

REF

to +0.5 V

S

to 0 V

S

Differential Reference Voltage . . . . . . . . . . . . . . . . . . . . 2.1 V

Reference Midpoint Current . . . . . . . . . . . . . . . . . . . . ±4 mA

ENCODE to ENCODE Differential Voltage . . . . . . . . . . . 4 V

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Operating Temperature Range

AD9002AD/BD/AJ/BJ . . . . . . . . . . . . . . . –25°C to +85°C

AD9002SE/SD/TD/TE . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature

3

. . . . . . . . . . . . . . . . . . . . . . . . 150°C

Lead Soldering Temperature (10 sec) . . . . . . . . . . . . . 300°C

NOTES

1

Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect device
reliability.

2

+V

≥ –V

REF

3

Maximum junction temperature (tJ max) should not exceed 175°C for ceramic
packages, and 150°C for plastic packages:

tJ = PD (θJA) + t
PD (θJC) + t

where

PD = power dissipation

θJA = thermal impedance from junction to ambient (°C/W)
θJC = thermal impedance from junction to case (°C/W)

tA = ambient temperature (°C)
tC = case temperature (°C)

Typical thermal impedances are:

Ceramic DIP θJA = 56°C/W; θJC = 20°C/W
Ceramic LCC θ
PLCC θJA = 60°C/W; θJC = 19°C/W.

under all circumstances.

REF

A

C

= 69°C/W; θ

JA

= 23°C/W

JC

Recommended Operating Conditions

Input Voltage

Parameter Min Nominal Max

–V

S

+V

REF

–V

REF

Analog Input –V

–5.46 –5.20 –4.94
–V

REF

–2.1 –2.0 +V

REF

0.0 V +0.1

+V

REF

REF

EXPLANATION OF TEST LEVELS

Test Level I – 100% production tested.
Test Level II – 100% production tested at 25°C, and sample

tested at specified temperatures.
Test Level III – Sample tested only.
Test Level IV – Parameter is guaranteed by design and

characterization testing.
Test Level V – Parameter is a typical value only.
Test Level VI –

All devices are 100% production tested at

25°C. 100% production tested at temperature

extremes for extended temperature devices;

sample tested at temperature extremes for

commercial/industrial devices.

ORDERING GUIDE

Package

Model Linearity Temperature Range Option*

AD9002AD 0.75 LSB –25°C to +85°C D-28
AD9002BD 0.50 LSB –25°C to +85°C D-28
AD9002AJ 0.75 LSB –25°C to +85°C J-28
AD9002BJ 0.50 LSB –25°C to +85°C J-28
AD9002SD/883B 0.75 LSB –55°C to +125°C D-28
AD9002SE/883B 0.75 LSB –55°C to +125°C E-28A
AD9002TD/883B 0.50 LSB –55°C to +125°C D-28
AD9002TE/883B 0.50 LSB –55°C to +125°C E-28A

*D = Ceramic DIP; E = Leadless Ceramic Chip Carrier; J = Ceramic Chip

Carrier, J-Formed Leads.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9002 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. F

–3–

WARNING!

ESD SENSITIVE DEVICE

AD9002

FUNCTIONAL DESCRIPTION

Pin # Mnemonic Description

1 DIGITAL GROUND One of four digital ground pins. All digital ground pins should be connected together.
2 OVERFLOW INH OVERFLOW INHIBIT controls the data output polarity for overvoltage inputs.

delbanEwolfrevO

)V2.5–rognitaolF(

tupnIgolanA

V

V+>

NI

FER

Dfo8D–1

000000001111111110

wolfrevO)DNG(detibihnI

Dfo8D–1

VNI≤ V+

FER

XXXXXXXX0XXXXXXXX0

3 HYSTERESIS The Hysteresis control voltage varies the comparator hysteresis from 0 mV to 10 mV, for a change

from –5.2 V to –2.2 V at the Hysteresis control pin. Normally converted to –5.2 V.

4+V

REF

The most positive reference voltage for the internal resistor ladder.
5 ANALOG INPUT One of two analog input pins. Both analog input pins should be connected together.
6 ANALOG GROUND One of two analog ground pins. Both analog ground pins should be connected together.
7 ENCODE Noninverted input of the differential encode input. This pin is driven in conjunction with

ENCODE. Data is latched on the rising edge of the ENCODE signal.
8 ENCODE Inverted input of the differential encode input. This pin is driven in conjunction with ENCODE.
9 ANALOG GROUND One of two analog ground pins. Both analog ground pins should be connected together.
10 ANALOG INPUT One of two analog input pins. Both analog inputs should be connected together.
11 –V

REF

12 REF

MID

The most negative reference voltage for the internal resistor ladder.

The midpoint tap on the internal resistor ladder.
13 DIGITAL GROUND One of four digital ground pins. All digital ground pins should be connected together.
14 DIGITAL –V

S

One of two negative digital supply pins (nominally –5.2 V). Both digital supply pins should be con-

nected together.
15 D1 (LSB) Digital Data Output
16–19 D2–D5 Digital Data Output
20 DIGITAL GROUND One of four digital ground pins. All digital ground pins should be connected together.
21, 22 ANALOG –V

S

One of two negative analog supply pins (nominally –5.2 V). Both analog supply pins should be con-

nected together
23 DIGITAL GROUND One of four digital ground pins. All digital ground pins should be connected together.
24, 25 D6, D7 Digital Data Output
26 D8 (MSB) Digital Data Output
27 OVERFLOW Overflow data output. Logic high indicates an input overvoltage (V

> +V

IN

) if OVERFLOW

REF

INHIBIT is enabled (overflow enabled, –5.2 V). See OVERFLOW INHIBIT.

28 DIGITAL –V

S

One of two negative digital supply pins (nominally –5.2 V). Both digital supply pins should be

connected together.

DIGITAL

GROUND

OVERFLOW INH

HYSTERESIS

+V

ANALOG

GROUND

ENCODE

ENCODE

ANALOG
GROUND

–V

REF

DIGITAL

GROUND

DIGITAL –V

REF

REF

MID

ANALOG INPUT

ANALOG INPUT

1

2

3

4

5

6

7

8

9

10

11

12

13

14

S

DIP

AD9002

TOP VIEW

(Not to Scale)

28

DIGITAL –V

27

OVERFLOW

26

D8(MSB)

25

D7

24

D6

DIGITAL

23

GROUND

22

ANALOG –V

21

ANALOG –V

DIGITAL

20

GROUND

19

D5

18

D4

17

D3

16

D2

15

D1(LSB)

S

ANALOG INPUT

S

S

ANALOG INPUT

ANALOG

GROUND

ENCODE

ENCODE

ANALOG

GROUND

–V

REF

PIN DESIGNATIONS

LCC

S

REF

+V

OVERFLOW INH

HYSTERESIS

2

3426

5

6

7

8

9

10

11

AD9002

TOP VIEW

(Not to Scale)

13 14 15 16 17 18

12

S

MID

REF

DIGITAL –V

DIGITAL GROUND

D8(MSB)

DIGITAL –V

DIGITAL GROUND

OVERFLOW

28 271

D3

D2

D4

D1(LSB)

–4–

25

D7

24

D6
DIGITAL

23

GROUND

22

ANALOG –V

21

ANALOG –V
DIGITAL

20

GROUND

19

D5

OVERFLOW

DIGITAL –V

S

OVERFLOW INH

S

HYSTERESIS

D8(MSB)

DIGITAL

GROUND

+V

REF

D7

25

24 23 22 21 20 19

26

27

28

S

1

2

3

4

5 6 7 8 9 10 11

ANALOG INPUT

JLCC

S

S

DIGITAL GROUND

ANALOG –V

D6

ANALOG –V

DIGITAL GROUND

AD9002

TOP VIEW

(Not to Scale)

ENCODE

ENCODE

ANALOG GROUND

ANALOG INPUT

ANALOG GROUND

D5

REF

–V

18

17

16

15

14

13

12

D4

D3

D2
D1(LSB)

DIGITAL –V
DIGITAL

GROUND
REF

MID

REV. F

S

AD9002

ENCODE

ENCODE

AD9002

–5.2V

ANALOG

INPUT

ENCODE

OUTPUT

DATA

ANALOG

INPUT

N + 1

N

APERTURE

DELAY

t

PD

N – 1

Figure 1. Timing Diagram

AD9002

–5.2V

–5.2V

COMPARATOR CELLS

–5.2V

Figure 2. Input/Output Circuits

–5.2V

N + 2

N

R

N + 1

+V

REF

AD9002

R/2

REF

R/2

R

MID

DIGITAL

OUTPUT

–V

REF

0.1F

–V

S

HYSTERESIS

100

AD1

1k

AD2

1k

AD3

–2V

STATIC BURN IN

DYNAMIC BURN IN

ALL RESISTORS  5%, 
ALL CAPACITORS  20%, F
ALL SUPPLIES  5%

OVERFLOW INH

ANALOG IN

ENCODE

ENCODE

–V

0.1F

AD1 = 0V AD2 = ECL HIGH AD3 = ECL LOW

AD1

AD2

AD3

REF

+V

REF

GROUND

OVERFLOW

AD9002

Figure 3. Burn-in Diagram

OVERFLOW

INHIBIT

HYSTERESIS

–5.2V

1k

1k

D8

1k

D7

1k

D6

1k

D5

1k

D4

1k

D3

1k

D2

1k

D1

0V

–2V

ECL HIGH

ECL LOW

ECL HIGH

ECL LOW

+V

REF

ANALOG

INPUT

ANALOG

GROUND

ENCODE

ENCODE

ANALOG

GROUND

ANALOG

INPUT

–V

REF

REF

Figure 4. Die Layout and Mechanical Information

DIGITAL

GROUND

MID

DIGITAL

GROUND

D1 (LSB)

DIGITAL

–V

S

DIGITAL –V

OVERFLOW

S

(MSB)

D8

D7

D6

DIGITAL
GROUND

ANALOG –V

DIGITAL
GROUND

D5

D4

D2

D3

S

Die Dimensions . . . . . . . . . . . . . . . . . 106 × 114 × 15 (± 2) mils

Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 × 4 mils

Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold

Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None

Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V

S

Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Nitride

Die Attach . . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Epoxy (Plastic)

Bond Wire . . . . . . . . . . . . . 1-1.3 mil Gold; Gold Ball Bonding

REV. F

–5–

AD9002

APPLICATION INFORMATION

The AD9002 is compatible with all standard ECL logic families,
including 10K and 10KH. 100K ECL’s logic levels are tempera­ture compensated, and are therefore compatible with the AD9002
(and most other ECL device families) only over a limited tempera­ture range. To operate at the highest encode rates, the supporting
logic around the AD9002 will need to be equally fast. Which­ever of the ECL logic families is used, special care must be
exercised to keep digital switching noise away from the ana­log circuits around the AD9002. The two most critical items
are digital supply lines and digital ground return.

The input capacitance of the AD9002 is an exceptionally low
17 pF. This allows the use of a wide range of input amplifiers,
both hybrid and monolithic. To take full advantage of the wide
input bandwidth of the AD9002, a hybrid amplifier such as the
AD9610 will be required. For those applications that do not
require the full input bandwidth of the AD9002, more tradi­tional monolithic amplifiers, such as the AD846, will work very
well. Overall performance with any amplifier can be improved
by inserting a 10 Ω resistor in series with the amplifier output.

The output data is buffered through the ECL compatible output
latches. All data is delayed by one clock cycle, in addition to the
latch propagation delay (t

), before becoming available at the

PD

outputs. Both the analog-to-digital conversion cycle and the
data transfer to the output latches are triggered on the rising
edge of the differential, ECL compactible ENCODE signal (see
timing diagram). In applications where only a single-ended signal is
available, the AD96685, a high speed, ECL voltage comparator,
can be employed to generate the differential signals. All ECL
signals (including the overflow bit) should be terminated prop­erly to avoid ringing and reflection.

The AD9002 also incorporates a HYSTERESIS control pin
which provides from 0 mV to 10 mV of additional hysteresis in
the comparator input stages. Adjustments in the HYSTERESIS
control voltage may help improve noise immunity and overall
performance in harsh environments.

The OVERFLOW INHIBIT pin of the AD9002 determines
how the converter handles overrange inputs (AIN ≥ +V

REF

). In
the “enabled” state (floating at –5.2 V), the OVERFLOW out­put will be at logic HIGH and all other outputs will be at logic
LOW for overrange inputs (return-to-zero operation). In the
“inhibited” state (tied to ground), the OVERFLOW output will
be at logic LOW, and all other outputs will be at logic HIGH
for overrange inputs (nonreturn-to-zero operation).

The AD9002 provides outstanding error rate performance. This
is due to tight control of comparator offset matching and a fault
tolerant decoding stage. Additional improvements in error rate
are possible through the addition of hysteresis (see HYSTERESIS
control pin). This level of performance is extremely important in
fault-sensitive applications such as digital radio (QAM).

Dramatic improvements in comparator design and construction
give the AD9002 excellent dynamic characteristics, especially
SNR (signal-to-noise ratio). The 160 MHz input bandwidth
and low error rate performance give the AD9002 an SNR of
48 dB with a 1.23 MHz input. High SNR performance is par­ticularly important in wide bandwidth applications, such as
pulse signature analysis, commonly performed in advanced
radar receivers.

LAYOUT SUGGESTIONS

Designs using the AD9002, like all high speed devices, must
follow a few basic layout rules to insure optimum performance.
Essentially, these guidelines are meant to avoid many of the
problems associated with high speed designs. The first require­ment is for a substantial ground plane around and under the
AD9002. Separate ground plane areas for the digital and analog
components may be useful, but these separate grounds should
be connected together at the AD9002 to avoid the effects of
“ground loop” currents.

The second area that requires an extra degree of attention involves
the three reference inputs, +V
+V

input and the –V

REF

REF

low impedance source (note that the +V

REF

, REF

MID

, and –V

REF

. The

input should both be driven from a

input is typically

REF

tied to analog ground). A low drift amplifier should provide
satisfactory results, even over an extended temperature range.
Adjustments at the REF

input may be useful in improving the

MID

integral linearity by correcting any reference ladder skews. The
application circuit shown below demonstrates a simple and
effective means of driving the reference circuit.

The reference inputs should be adequately decoupled to ground
through 0.1 µF chip capacitors to limit the effects of system noise
on conversion accuracy. The power supply pins must also be
decoupled to ground to improve noise immunity; 0.1 µF and

0.01 µF chip capacitors are recommended.

The analog input signal is brought into the AD9002 through
two separate input pins. It is very important that the two input
pins be driven symmetrically with equal length electrical connec­tions. Otherwise, aperture delay errors may degrade converter
performance at high frequencies.

–15V

1k

4k

100

2N3906

10

0.1F

–V

REF

A

IN

A

IN

AD9002

ENCODE

ENCODE

–5.2A

0.1F

+V

–5.2D

REF

OVERFLOW
D8 (MSB)
D7
D6
D5
D4
D3
D2
D1 (LSB)

0.1F

0.01F

ANALOG

INPUT

(0V TO 2V)

NYQUEST

FILTER

50

ENCODE

INPUT

(GROUND

THRESHOLD)

1.5k

AD9611

50

40

0.1F

0.01F

AD741

EQUAL

DISTANCE

AD96685

Figure 5. Typical Application

–6–

REV. F

AD9002

150

2N3906

OVERFLOW

D8(MSB)

D7

D6

D5

D4

D3

D2

D1(LSB)

–5.2D

–5.2A

0.01F

0.1F

0.1F

0.01F

ENCODE

ENCODE

A

IN

A

IN

–V

REF

+V

REF

AD741

HOS200

AD96687

75

AD9002*

EQUAL

DISTANCE

2k

ENCODE INPUT

(GROUND

THRESHOLD)

ANALOG

INPUT

1k

4.3k

–15V

50

AD9768

DAC

OVERFLOW

INH

10F

3.9k

1k

0.1F

–15V

625

1k

–5.2V

AD96687

50

0.1F

HYSTERESIS

–5.2V

510

0.1F

510

–5.2V

1k

DELAY

50

0.1F0.01F

90

2090

LINE

DRIVER

100114

HOS100 HOS100

LINEARITY OUTPUT
(ERROR WAVEFORM)

RECONSTRUCTED

OUTPUT

3.75

50

1k

AD96687

AD96687

NOTE:
100114 LINE DRIVER OUTPUTS
REQUIRE 510 PULL-DOWN
RESISTORS TO –5.2V. ALL OTHER
ECL OUTPUTS SHOULD BE
TERMINATED TO –2V WITH
100 RESISTERS, UNLESS
OTHERWISE SPECIFIED.
RESISTORS ARE IN .
CAPACITORS ARE IN F.

REGISTER

100151

0.1F

REF

MID

*CONTACT FACTORY ABOUT
EVALUATION BOARD AVAILABILITY

37-PIN

D

CONNECTOR

88013k

–15V

1k

DELAY

88013k

–15V

REV. F

Figure 6. AD9002 Evaluation Circuit

RMS SIGNAL-TO-NOISE RATIO (dB)

65

60

55

50

45

40

AND HARMONIC LEVELS (–dBc)

35

30

1MHz

ANALOG INPUT FREQUENCY (0.1dB BELOW FULL SCALE)

Figure 7. Dynamic Performance

3RD HARMONIC

SNR

10MHz

125 MSPS ENCODE RATE

–7–

2ND HARMONIC

100MHz

AD9002

0.005 (0.13) MIN

PIN 1

0.225 (5.72)
MAX

0.200 (5.08)

0.125 (3.18)

0.458 (11.63)

0.442 (11.23)
SQ

TOP

VIEW

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead Ceramic Side-Brazed DIP

(D-28)

0.100 (2.54) MAX

28

114

1.490 (37.85) MAX

0.026 (0.66)

0.014 (0.36)

0.100 (2.54)
BSC

15

0.070 (1.78)

0.030 (0.76)

0.610 (15.49)

0.500 (12.70)

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MIN

SEATING
PLANE

0.620 (15.75)

0.590 (14.99)

28-Lead Ceramic Leadless Chip Carrier

(E-28A)

0.300 (7.62)

26

25 1

19

18

BSC

0.150
(3.51)

BSC

28

BOTTOM

VIEW

0.200
(5.08)

BSC

5

12

0.458

(11.63)

MAX

SQ

0.100 (2.54)

0.064 (1.63)

0.088 (2.24)

0.054 (1.37)

0.095 (2.41)

0.075 (1.90)

0.011 (0.28)

0.007 (0.18)
R TYP

0.075
(1.91)

REF

0.055 (1.40)

0.045 (1.14)

0.075
(1.91)

REF

0.018 (0.46)

0.008 (0.20)

0.015 (0.38)
MIN

4

11

45 TYP

0.028 (0.71)

0.022 (0.56)

0.050
(1.27)
BSC

C00545d–0–9/01(F)

28-Leaded JLCC

(J-28)

0.171 (4.34)

BOTTOM VIEW

0.022 0.003

(0.559 0.076)

0.050
(1.27)

BSC

25

26

4

0.450 0.006

(11.43 0.152)

PIN 1

TOP VIEW

(PINS DOWN)

5

0.488 0.010

(11.43 0.254)

SQ

SQ

19

18

12

11

0.300
(7.62)

TYP

0.102 0.010

(1.448 0.254)

MAX

0.039 0.005

(0.991 0.127)

0.028 0.002

(0.711 0.051)

0.420 0.010

(10.668 0.254)

0.019 0.002

(0.483 0.051)

0.006 0.0006
(0.152 0.015)

Revision History

Location Page

Data Sheet changed from REV. E to REV. F.

Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

PRINTED IN U.S.A.

–8–

REV. F