Datasheet AD871SE, AD871SD, AD871JE, AD871JD Datasheet (Analog Devices)

Complete 12-Bit 5 MSPS

a

FEATURES
Monolithic 12-Bit 5 MSPS A/D Converter
Low Noise: 0.17 LSB RMS Referred to Input
No Missing Codes Guaranteed
Differential Nonlinearity Error: 0.5 LSB
Signal-to-Noise and Distortion Ratio: 68 dB
Spurious-Free Dynamic Range: 73 dB
Power Dissipation: 1.03 W
Complete: On-Chip Track-and-Hold Amplifier and

Voltage Reference
Pin Compatible with the AD872
Twos Complement Binary Output Data
Out of Range Indicator
28-Lead Side Brazed Ceramic DIP or 44-Terminal

Surface Mount Package

PRODUCT DESCRIPTION

The AD871 is a monolithic 12-bit, 5 MSPS analog-to-digital
converter with an on-chip, high performance track-and-hold
amplifier and voltage reference. The AD871 uses a multistage
differential pipelined architecture with error correction logic to
provide 12-bit accuracy at 5 MSPS data rates and guarantees no
missing codes over the full operating temperature range. The
AD871 is a redesigned variation of the AD872 12-bit, 10 MSPS
ADC, optimized for lower noise in applications requiring sam­pling rates of 5 MSPS or less. The AD871 is pin compatible
with the AD872, allowing the parts to be used interchangeably
as system requirements change.

The low-noise input track-and-hold (T/H) of the AD871 is ide­ally suited for high-end imaging applications. In addition, the
T/H’s high input impedance and fast settling characteristics
allow the AD871 to easily interface with multiplexed systems
that switch multiple signals through a single A/D converter. The
dynamic performance of the input T/H also renders the AD871
suitable for sampling single channel inputs at frequencies up to
and beyond the Nyquist rate. The AD871 provides both refer­ence output and reference input pins, allowing the onboard ref­erence to serve as a system reference. An external reference can
also be chosen to suit the dc accuracy and temperature drift
requirements of the application. A single clock input is used to
control all internal conversion cycles. The digital output data is
presented in twos complement binary output format. An out-of­range signal indicates an overflow condition, and can be used
with the most significant bit to determine low or high overflow.

Monolithic A/D Converter

AD871

FUNCTIONAL BLOCK DIAGRAM

DV

SS

T/H

A/D4D/A

CORRECTION LOGIC

*

OUTPUT

ENABLE

DGND

DD

T/H

OUTPUT BUFFERS

OTR *MSB

*

DRV

AD871

A/D3D/A

MSB–BIT 12
(LSB)

*

DRGND

DD

A/D

4

12

V

INA

V

INB

CLOCK

REF IN

REF OUT

AV

DD

T/H

A/D4D/A

+2.5V

REFERENCE

REF OUT

*ONLY AVAILABLE ON 44-TERMINAL SURFACE MOUNT PACKAGE

AGND

AV

The AD871 is fabricated on Analog Devices’ ABCMOS-1 pro­cess, which uses high speed bipolar and CMOS transistors on a
single chip. High speed, precision analog circuits are now com­bined with high density logic circuits.

The AD871 is packaged in a 28-lead ceramic DIP and a
44-terminal leadless ceramic surface mount package and is

specified for operation from 0°C to +70°C and –55°C to
+125°C.

PRODUCT HIGHLIGHTS

The AD871 offers a complete single-chip sampling 12-bit,
5 MSPS analog-to-digital conversion function in a 28-lead DIP
or 44-terminal leadless ceramic surface mount package (LCC).

Low Noise—The AD871 features 0.17 LSB referred-to-input
noise, producing essentially a “1 code wide” histogram for a
code-centered dc input.

Low Power—The AD871 at 1.03 W consumes a fraction of the
power of presently available hybrids.

On-Chip Track-and-Hold (T/H)—The low noise, high imped­ance T/H input eliminates the need for external buffers and can
be configured for single ended or differential inputs.

Ease of Use—The AD871 is complete with T/H and voltage ref­erence and is pin-compatible with the AD872 (12-bit, 10 MSPS
monolithic ADC).

Out of Range (OTR)—The OTR output bit indicates when the
input signal is beyond the AD871’s input range.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

AD871–SPECIFICATIONS

AD871

(T

to T

with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, AVSS = –5 V, f

MAX

DC SPECIFICATIONS

MIN

noted)

Parameter J Grade

1

S Grade

l

= 5 MHz, unless otherwise

SAMPLE

Units

RESOLUTION 12 12 Bits min

MAX CONVERSION RATE 5 5 MHz min

INPUT REFERRED NOISE 0.17 0.17 LSB rms typ

ACCURACY

Integral Nonlinearity (INL) ± 1.5 ±1.5 LSB typ
Differential Nonlinearity (DNL) ±0.5 ± 0.5 LSB typ

No Missing Codes 12 12 Bits Guaranteed

Zero Error (@ +25°C)
Gain Error (@ +25°C)

TEMPERATURE DRIFT

Zero Error ±0.15 ±0.3 % FSR max

Gain Error
Gain Error

3, 4

3, 5

POWER SUPPLY REJECTION

AVDD, DV
AV

(–5 V ± 0.25 V) ±0.125 ±0.125 % FSR max

SS

(+5 V ± 0.25 V) ±0.125 ±0.125 % FSR max

DD

2

2

3

±0.75 ±0.75 % FSR max
±1.25 ±1.25 % FSR max

±0.80 ±1.75 % FSR max
±0.25 ±0.50 % FSR max

6

ANALOG INPUT

Input Range ±1 ±1 Volts max
Input Resistance 50 50 kΩ typ

Input Capacitance 10 10 pF typ

INTERNAL VOLTAGE REFERENCE

Output Voltage 2.5 2.5 Volts typ

Output Voltage Tolerance ±20 ±40 mV max

Output Current (Available for External Loads) 2.0 2.0 mA typ
(External load should not change during conversion.)

REFERENCE INPUT RESISTANCE 5 5 kΩ typ

POWER SUPPLIES

Supply Voltages

AV

DD

AV

SS

DV

DD

DRV

DD

7

+5 +5 V (±5% AV
–5 –5 V (±5% AV
+5 +5 V (±5% DV
+5 +5 V (±5% DRV

Supply Current

IAV

DD

IAV

SS

IDV

DD

IDRV

DD

7

87 88 mA max (82 mA typ)
147 150 mA max (115 mA typ)
20 21 mA max (7 mA typ)
2 2 mA max

POWER CONSUMPTION 1.03 1.03 W typ

1.25 1.3 W max

NOTES

1

Temperature ranges are as follows: J Grade: 0°C to +70°C, S Grade: –55°C to +125°C.

2

Adjustable to zero with external potentiometers (see Zero and Gain Error Calibration section).

3

+25°C to T

4

Includes internal voltage reference error.

5

Excludes internal reference drift.

6

Change in Gain Error as a function of the dc supply voltage (V

7

LCC package only.

Specifications subject to change without notice.

and +25°C to T

MIN

MAX

.

to V

NOMINAL

MIN

, V

NOMINAL

to V

MAX

).

Operating)

DD

Operating)

SS

Operating)

DD

Operating)

DD

–2–

REV. A

AD871

(T

to T

with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, AVSS = –5 V, f

MAX

1

AC SPECIFICATIONS

MIN

noted)

J Grade S Grade Units

SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D)

f

= 750 kHz 68 68 dB typ

INPUT

f

= 1 MHz 66 66 dB typ

INPUT

63 62 dB min

f

= 2.49 MHz 60 60 dB typ

INPUT

TOTAL HARMONIC DISTORTION (THD)

f

= 750 kHz –72 –72 dB typ

INPUT

f

= 1 MHz –69 –69 dB typ

INPUT

–64 –63 dB max

f

= 2.49 MHz –62 –62 dB typ

INPUT

SPURIOUS FREE DYNAMIC RANGE (SFDR)

f

= 750 kHz 73 73 dB typ

INPUT

f

= 1 MHz 70 70 dB typ

INPUT

f

= 2.49 MHz 62 62 dB typ

INPUT

INTERMODULATION DISTORTION (IMD)

2

Second Order Products –80 –80 dB typ
Third Order Products –73 –73 dB typ

FULL POWER BANDWIDTH 15 15 MHz typ

= 5 MSPS, unless otherwise

SAMPLE

SMALL SIGNAL BANDWIDTH 15 15 MHz typ

APERTURE DELAY 6 6 ns typ

APERTURE JITTER 16 16 ps rms typ

ACQUISITION TO FULL-SCALE STEP 80 80 ns typ

OVERVOLTAGE RECOVERY TIME 80 80 ns typ

NOTES

1

fIN amplitude = –0.5 dB full scale unless otherwise indicated. All measurements referred to a 0 dB (1 V pk) input signal unless otherwise indicated.

2

fa = 1.0 MHz, fb = 0.95 MHz with f

Specifications subject to change without notice.

DIGITAL SPECIFICATIONS

SAMPLE

= 5 MHz.

(T

MIN

to T

with AVDD = +5 V, DVDD = +5 V, AVSS = –5 V unless otherwise noted)

MAX

Parameter Symbol J, S Grades Units

LOGIC INPUTS

High Level Input Voltage V
Low Level Input Voltage V
High Level Input Current (V
Low Level Input Current (V

= DVDD)I

IN

= 0 V) I

IN

Input Capacitance C

IH

IL

IH

IL

IN

+2.0 V min
+0.8 V max

±115 µA max
±115 µA max

5 pF typ

LOGIC OUTPUTS

High Level Output Voltage (I
Low Level Output Voltage (I
Output Capacitance C

= 0.5 mA) V

OH

= 1.6 mA) V

OL

OH

OL

OUT

+2.4 V min
+0.4 V max
5 pF typ

Leakage (Three-State, LCC Only) IZ ±10 µA max

Specifications subject to change without notice.

REV. A

–3–

AD871

WARNING!

ESD SENSITIVE DEVICE

(T

to T

MIN

SWITCHING SPECIFICATIONS

VIH = 2.0 V, VOL = 0.4 V and VOH = 2.4 V)

Parameter Symbol J, S Grades Units

Clock Period

l

CLOCK Pulsewidth High t
CLOCK Pulsewidth Low t
Clock Duty Cycle

2

Output Delay t
Pipeline Delay (Latency) 3 Clock Cycles
Data Access Time (LCC Package Only)
Output Float Delay (LCC Package Only)

NOTES

1

Conversion rate is operational down to 10 kHz without degradation in specified performance.

2

For clock periods of 200 ns or greater, see Clock Input section.

3

See section on Three-State Outputs for timing diagrams and application information.

Specifications subject to change without notice.

VIN

CLOCK

BIT 2–12

MSB, OTR

N

3

t

tCHt

3

N+1

C

N+1N

CL

with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, AVSS = –5 V; VIL = 0.8 V,

MAX

t

C

CH

CL

200 ns min
95 ns min
95 ns min
40 % min (50% typ)
60 % max

OD

t

DD

t

HL

DATA

N

10 ns min (20 ns typ)

50 ns typ (100 pF Load)
50 ns typ (10 pF Load)

t

OD

DATA

N+1

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS

1

Parameter With Respect to Min Max Units

AV

DD

AV

SS

DV

, DRV

DD

DD

2

DRV
DRGND

DD

2

AGND –0.5 +6.5 Volts
AGND –6.5 +0.5 Volts
DGND, DRGND –0.5 +6.5 Volts
DV

DD

–6.5 +6.5 Volts

DGND –0.3 +0.3 Volts
AGND DGND –1.0 +1.0 Volts
AV

DD

Clock Input, OEN DGND –0.5 DV
Digital Outputs DGND –0.5 DV
V

, V

INA

REF IN AGND –6.5 +6.5 Volts

INB

REF IN AGND AV

DV

DD

–6.5 +6.5 Volts

+ 0.5 Volts

DD

+ 0.3 Volts

DD

SS

AV

DD

Volts

Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature (10 sec) +300 °C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.

2

LCC Package Only.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD871 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. A

PIN FUNCTION DESCRIPTIONS

DIP LCC

Symbol Pin No. Pin No. Type Name and Function

AD871

V
V
AV
AV

INA

INB

SS

DD

1 1 AI (+) Analog Input Signal on the differential input amplifier.
2 2 AI (–) Analog Input Signal on the differential input amplifier.
3, 25 5, 40 P –5 V Analog Supply.

4 6, 38 P +5 V Analog Supply.
AGND 5, 24 9, 36 P Analog Ground.
DGND 6, 23 10 P Digital Ground.
DV

DD

7, 22 33 P +5 V Digital Supply.
BIT 12 (LSB) 8 16 DO Least Significant Bit.
BIT 2–BIT 11 18–9 26–17 DO Data Bits 2 through 11.
MSB 19 29 DO Inverted Most Significant Bit. Provides twos complement output

data format.

OTR 20 30 DO Out of Range is Active HIGH on the leading edge of code 0 or

the trailing edge of code 4096. See Output Data Format Table III.

CLK 21 31 DI Clock Input. The AD871 will initiate a conversion on the rising

edge of the clock input. See the Timing Diagram for details.
REF OUT 26 41 AO +2.5 V Reference Output. Tie to REF IN for normal operation.
REF GND 27 42 AI Reference Ground.

REF IN 28 43 AI Reference Input. +2.5 V input gives ±1 V full-scale range.

BIT 1 (MSB) N/A 27 DO Most Significant Bit.
DRV

DD

N/A 12, 32 P +5 V Digital Supply for the output drivers.

DRGND N/A 11, 34 P Digital Ground for the output drivers.

(See section on Power Supply Decoupling for details on

DRV

and DRGND.)

DD

OEN N/A 13 DI Output Enable. See the Three State Output Timing Diagram for details.
NC N/A 3, 4, 7, 8, 14, 15, No Connect.

28, 35, 37, 39, 44

TYPE: AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; P = Power; N/A = Not Available on 28-lead DIP, available only on
44-terminal surface mount package.

PIN CONFIGURATIONS

28-Lead Side Brazed Ceramic DIP

V

INA

V

INB

AV

AV

AGND
DGND

DV

BIT 12 (LSB)

BIT 11
BIT 10

BIT 9
BIT 8
BIT 7
BIT 6

SS
DD

DD

AD871

TOP VIEW

(Not to Scale)

REF IN
REF GND
REF OUT
AV

SS

AGND
DGND

DV

DD

CLK
OTR

MSB

BIT 2
BIT 3
BIT 4
BIT 5

AGND
DGND

DRGND

DRV

OEN

BIT 12 (LSB)

BIT 11

44-Terminal LCC

(Not to Scale)

BIT 9

BIT 8

INBVINA

AD871

TOP VIEW

BIT 7

BIT 6

AVDDAVSSNCNCV

6 5 4 3 2 1 44 43 42 41 40

7

NC

8

NC

9
10
11
12

DD

13

NC

14

NC

15
16
17

18 19 20 21 22 23 24 25 26 27 28

BIT 10

NC = NO CONNECT

BIT 5

NC

BIT 4

REF IN

REF GND

PIN 1
IDENTIFIER

BIT 3

BIT 2

SS

REF OUT

AV

39

NC

38

AV

37

NC

36

AGND

35

NC

34

DRGND

33

DV
DRV

32
31

CLK
OTR

30
29

MSB

NC

BIT 1 (MSB)

DD

DD

DD

REV. A

–5–

AD871

DEFINITIONS OF SPECIFICATIONS

LINEARITY ERROR

Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as “negative full scale” occurs
1/2 LSB before the first code transition. “Positive full scale” is
defined as a level 1 1/2 LSB beyond the last code transition.
The deviation is measured from the middle of each particular
code to the true straight line.

DIFFERENTIAL LINEARITY ERROR (DNL, NO MISSING CODES)

An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes must be present over all operating ranges.

ZERO ERROR

The major carry transition should occur for an analog value 1/2
LSB below analog common. Zero error is defined as the devia­tion of the actual transition from that point. The zero error and
temperature drift specify the initial deviation and maximum
change in the zero error over temperature.

GAIN ERROR

The first code transition should occur for an analog value 1/2
LSB above nominal negative full scale. The last transition
should occur for an analog value 1 1/2 LSB below the nominal
positive full scale. Gain error is the deviation of the actual dif­ference between first and last code transitions and the ideal dif­ference between first and last code transitions.

OVERVOLTAGE RECOVERY TIME

Overvoltage recovery time is defined as that amount of time
required for the ADC to achieve a specified accuracy after an
overvoltage (50% greater than full-scale range), measured from
the time the overvoltage signal reenters the converter’s range.

DYNAMIC SPECIFICATIONS

SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO

S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/N+D is expressed in decibels.

TOTAL HARMONIC DISTORTION (THD)

THD is the ratio of the rms sum of the first six harmonic com­ponents to the rms value of the measured input signal and is
expressed as a percentage or in decibels.

INTERMODULATION DISTORTION (IMD)

With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,

of order (m + n), at sum and difference frequencies of mfa ±

nfb, where m, n = 0, 1, 2, 3 . . . . Intermodulation terms are

those for which m or n is not equal to zero. For example, the
second order terms are (fa + fb) and (fa – fb), and the third or­der terms are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (2 fb – fa).
The IMD products are expressed as the decibel ratio of the rms
sum of the measured input signals to the rms sum of the distor­tion terms. The two signals are of equal amplitude and the peak
value of their sums is –0.5 dB from full scale. The IMD prod­ucts are normalized to a 0 dB input signal.

TEMPERATURE DRIFT

The temperature drift for zero error and gain error specifies the

maximum change from the initial (25°C) value to the value at

T

or T

MIN

POWER SUPPLY REJECTION

MAX

.

The specifications show the maximum change in the converter’s
full-scale as the supplies are varied from nominal to min/max
values.

APERTURE JITTER

Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.

APERTURE DELAY

Aperture delay is a measure of the Track-and-Hold Amplifier
(THA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.

FULL-POWER BANDWIDTH

The full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.

SPURIOUS FREE DYNAMIC RANGE

The difference, in dB, between the rms amplitude of the input
signal and the peak spurious signal.

ORDERING GUIDE

Model Temperature Range Package Option

1

AD871JD 0°C to +70°C D-28
AD871JE 0°C to +70°C E-44A

AD871SD
AD871SE

NOTES

1

D = Side Brazed Ceramic DIP, E = Leadless Ceramic Chip Carrier.

2

MIL-STD-883 version will be available; contact factory.

2

–55°C to +125°C D-28

2

–55°C to +125°C E-44A

–6–

REV. A

69.5

62

80

98

89

74

92

83

65

77

95

86

68
71

AMPLITUDE – dB

THD

3RD
HARMONIC

2ND
HARMONIC

10k 100k 10M1M

INPUT FREQUENCY – Hz

68.5

67.5

66.5

Dynamic Characteristics–Sample Rate: 5 MSPS–AD871

–0.5dB

65.5

S/ (N+D) – dB

64.5

63.5

62.5

61.5
10k 100k 10M1M

INPUT FREQUENCY – Hz

–0.6dB

Figure 2. AD871 S/(N+D) vs. Input Frequency

f

= 1MHz

IN

f

Amplitude = –0.5dB

IN

THD = –69dB
S/(N+D) = 66dB
SFDR = 70dB

15dB/ DIV

5

Figure 3. AD871 Distortion vs. Input Frequency,
Full-Scale Input

1

HARMONICS – dB

2ND
3RD
4TH
5TH
6TH
7TH
8TH
9TH

6

4

9

–80
–70
–96
–85
–90
–95
–90
–101

3

2

8

7

REV. A

f

= 1MHz

IN

f

AMPLITUDE = –6.0dB

IN

THD = –77dB
S/(N+D) = 65dB
SFDR = 74dB

15dB/ DIV

5

Figure 4. AD871 Typical FFT, fIN = 1 MHz, fIN Amplitude = –0.5 dB

1

HARMONICS – dB

2ND
3RD
4TH
5TH
6TH
7TH
8TH
9TH

4

6

9

–82
–79
–93
–95
–94
–95
–98
–94

Figure 5. AD871 Typical FFT, fIN = 1 MHz, fIN Amplitude = –6 dB

–7–

3

2

8

7

AD871–Dynamic Characteristics–Sample Rate: 5 MSPS

1

f

THD = –72dB
S/(N+D) = 68dB
SFDR = 73dB

15dB/ DIV

THD = –63dB
S/(N+D) = 61dB
SFDR = 63dB

IN

f

IN

f

IN

f

IN

= 750kHz

Amplitude = –0.5dB

6

2

= 2MHz

AMPLITUDE = –0.5dB

8

5

Figure 6. AD871 Typical FFT, fIN = 750 kHz

HARMONICS – dB

2ND
3RD
4TH
5TH
6TH
7TH

3

8TH
9TH

2

–87
–63
–95
–83
–88
–91
–88
–95

HARMONICS – dB

2ND
3RD
4TH
5TH
6TH
7TH
8TH
9TH

9

–81
–73
–94
–85
–90
–99
–90
–103

3

4

1

5

15dB/ DIV

1635819

1500000

1000000

500000

NUMBER OF CODE HITS

0

1094 1487

0 –1 1

DEVIATION FROM CORRECT CODE (LSB)

2

8

7

Figure 7. AD871 Typical FFT, fIN = 2 MHz

100

90

80

70

60

50

40

30

100 x p ($ CODE X + 1)

20

10

0

CODE X

6

9

s = 0.166 LSB RMS

CODE X + 1

Figure 8. AD871 Output Code Histogram for DC Input

–8–

Figure 9. AD871 Code Probability at a Transition

REV. A

AD871

0

–100

1

–70

–90

–80

–1

–40

–60

–50

–30

–20

–10

0

THD – dB

CM INPUT VOLTAGE – Volts

THEORY OF OPERATION

The AD871 is implemented using a 4-stage pipelined multiple
flash architecture. A differential input track-and-hold amplifier
(THA) acquires the input and converts the input voltage into a
differential current. A 4-bit approximation of the input is made
by the first flash converter, and an accurate analog representa­tion of this 4-bit guess is generated by a digital-to-analog con­verter. This approximation is subtracted from the THA output
to produce a remainder, or residue. This residue is then sampled
and held by the second THA, and a 4-bit approximation is gen­erated and subtracted by the second stage. Once the second
THA goes into hold, the first stage goes back into track to ac­quire a new input signal. The third stage provides a 3-bit ap­proximation/subtraction operation, and produces the final
residue, which is passed to a final 4-bit flash converter. The 15
output bits from the four flash converters are accumulated in
the correction logic block, which adds the bits together using the
appropriate correction algorithm, to produce the 12-bit output
word. The digital output, together with overrange indicator, is
latched into an output buffer to drive the output pins.

The additional THA inserted in each stage of the AD871 archi­tecture allows pipelining of the conversion. In essence, the con­verter is simultaneously converting multiple inputs serially,
processing them through the converter chain. This means that
while the converter is capable of capturing a new input sample
every clock cycle, it actually takes three clock cycles for the con­version to be fully processed and appear at the output. This
“pipeline delay” is often referred to as latency, and is not a con­cern in most applications; however, there are some cases where
it may be a consideration. For example, some applications call
for the A/D converter to be placed in a high speed feedback
loop, where its input is servoed to provide a desired result at the
digital output (e.g., offset calibration or zero restoration in video
applications). In these cases the 3 clock cycle delay through
the pipeline must be accounted for in the loop stability calcula­tions. Also, because the converter is simultaneously working on
three conversions, major disruptions to the part (such as a large
glitch on the supplies or reference) may corrupt three data
samples. Finally, there will be a minimum clock rate below
which the THA droop corrupts the signal in the pipeline. In the
case of the AD871, this minimum clock rate is 10 kHz.

The high impedance differential inputs of the AD871 allow a
variety of input configurations (see Applying the AD871). The
AD871 converts the voltage difference between the V
V

pins. For single-ended applications, one input pin (V

INB

V

) may be grounded, but even in this case the differential in-

INB

INA

and

INA

or

put can provide a performance boost: for example, for an input
coming from a coaxial cable, V

can be tied to the shield

INB

ground, allowing the AD871 to reject shield noise as common
mode. The high input impedance of the device minimizes exter­nal driving requirements and allows the user to externally select
the appropriate termination impedance for the application.

The AD871 clock circuitry uses both edges of the clock in its in­ternal timing circuitry (see Specifications page for exact timing
requirements.) The AD871 samples the analog input on the ris­ing edge of the clock input. During the clock low time (between
the falling edge and rising edge of the clock) the input THA is in
track mode; during the clock high time it is in hold. System dis­turbances just prior to the rising edge of the clock may cause the
part to acquire the wrong value, and should be minimized.

REV. A

–9–

While the part uses both clock edges for its timing, jitter is only
a significant issue for the rising edge of the clock (see CLOCK
INPUT section).

APPLYING THE AD871

ANALOG INPUTS

The AD871 features a high impedance differential input that
can readily operate on either single-ended or differential input
signals. Table I summarizes the nominal input voltage span for
both single-ended and differential modes, assuming a 2.5 V ref­erence input.

Table I. Input Voltage Span

V

INA

V

INB

V

INA–VINB

Single-Ended +1 V GND +1 V (Positive Full Scale)

–1 V GND –1 V (Negative Full Scale)

Differential +0.5 V –0.5 V +1 V (Positive Full Scale)

–0.5 V +0.5 V –1 V (Negative Full Scale)

Figure 10 shows an approximate model for the analog input cir­cuit. As this model indicates, when the input exceeds 1.6 V
(with respect to AGND), the input device may saturate, causing
the input impedance to drop substantially and significantly re­ducing the performance of the part. Input compliance in the
negative direction is somewhat larger, showing virtually no deg­radation in performance for inputs as low as –1.9 V.

+5V

1.75mA

V

OR V

INA

INB

61V

5pF

–1.9V

1.75mA

–5V

+1.6V

AD871

Figure 10. AD871 Equivalent Analog Input Circuit

Figure 11 illustrates the effect of varying the common-mode
voltage of a –0.5 dB input signal on total harmonic distortion.

Figure 11. AD871 Total Harmonic Distortion vs. CM Input
Voltage, f

= 1 MHz, FS = 5 MSPS

IN

AD871

Figure 12 shows the common-mode rejection performance vs.
frequency for a 1 V p-p common-mode input. This excellent
common-mode rejection over a wide bandwidth affords the user
the opportunity to eliminate many potential sources of input
noise as common mode by using the differential input structure
of the AD871.

–40

–50

–60

–70

CMR – dB

–80

–90

–100

10k 100k 10M1M

INPUT FREQUENCY – Hz

Figure 12. Common-Mode Rejection vs. Input Frequency,
1 V p-p Input

Figures 13 and 14 illustrate typical input connections for single
ended inputs.

562V

562V

V

INA

AD871

V

INB

V

IN

(60.5V)

U1

536V

536V

U2

Figure 15. Single-Ended to Differential Connections;
U1, U2 = AD811 or AD9617

The use of the differential input signal can help to minimize
even-order distortion from the input THA where performance
beyond –70 dB is desired.

Figure 16 shows the AD871 large signal (–0.5 dB) and small
signal (–20 dB) frequency response.

10

0

1

61V

V

INA

AD871

2

V

INB

Figure 13. AD871 Single-Ended Input Connection

1

61V

V

INA

R

T

AD871

2

V

INB

Figure 14. AD871 Single-Ended Input Connection Using a
Shielded Cable

The cable shield is used as the ground connection for the V

INB

input, providing the best possible rejection of the cable noise
from the input signal. Note also that the high input impedance
of the AD871 allows the user to select the termination imped­ance, be it 50 ohms, 75 ohms, or some other value. Further­more, unlike many flash converters, most AD871 applications
will not require an external buffer amplifier. If such an amplifier
is required, we suggest either the AD811 or AD9617.

Figure 15 illustrates how external amplifiers may be used to
convert a single-ended input into a differential signal. The resis-

tor values of 536 Ω and 562 Ω were selected to provide opti-

mum phase matching between U1 and U2.

–10

FUND AMP – dB

–20

–30

4

10

5

10

INPUT FREQUENCY – Hz

10

6

7

10

8

10

Figure 16. Full Power (–0.5 dB) and Small Signal
Response (–20 dB) vs. Input Frequency

The AD871’s wide input bandwidth facilitates rapid acquisition
of transient input signals: the input THA can typically settle to
12-bit accuracy from a full-scale input step in less than 80 ns. Fig­ure 17 illustrates the typical acquisition of a full-scale input step.

4400
4000
3600
3200
2800
2400
2000
1600

MAGNITUDE – LSB

1200

800
400

0

0

TIME – ns

80604020

100

Figure 17. Typical AD871 Settling Time

–10–

REV. A

AD871

1.5 2 3.532.5

70

60

50

REFERENCE INPUT VOLTAGE – Volts

S/(N + D) – dB

The wide input bandwidth and superior dynamic performance of
the input THA make the AD871 suitable for sampling inputs at
frequencies up to the Nyquist Rate. The input THA is designed
to recover rapidly from input overdrive conditions, returning
from a 50% overdrive in less than 100 ns.

Because of the THA’s exceptionally wide input bandwidth, some
users may find the AD871 is sensitive to noise at frequencies
from 10 MHz to 50 MHz that other converters are incapable of
responding to. This sensitivity can be mitigated by careful use of
the differential inputs (see previous paragraphs). Additionally,

Figure 18 shows how a small capacitor (10 pF – 20 pF for 50 Ω

terminated inputs) may be placed between V

INA

and V

to help

INB

reduce high frequency noise in applications where limiting the
input bandwidth is acceptable.

61V

10 OR 20pF

1

V

INA

AD871

2

V

INB

Figure 18. Optional High Frequency Noise Reduction

The AD871 will contribute its own wideband thermal noise. As
a result of the integrated wideband noise (0.17 LSB rms,
referred-to-input), applying a dc analog input may produce more
than one code at the output. A histogram of the ADC output
codes, for a dc input voltage, will be between 1 and 3 codes
wide, depending on how well the input is centered on a given
code and how many samples are taken. Figure 8 shows a typical
AD871 code histogram, and Figure 9 illustrates the AD871’s
transition noise.

REFERENCE INPUT

The nominal reference input should be 2.5 V, taken with respect
to REFERENCE GROUND (REF GND). Figure 19 illustrates
the equivalent model for the reference input: there is no clock or
signal-dependent activity associated with the reference input cir­cuitry, therefore no “kickback” into the reference.

with an rms noise of 28 µV (using an external 1 µF capacitor),
contributes 24 µV (0.05 LSB) of noise to the transfer function

of the AD871.

The full-scale peak-to-peak input voltage is a function of the ref­erence voltage, according to the equation:

(V

– V

INA

) Full Scale = 0.8 × (V

INB

– REF GND)

REF

Note that the AD871’s performance was optimized for a 2.5 V
reference input: performance may degrade somewhat for other
reference voltages. Figure 20 illustrates the S/(N+D) perfor­mance vs. reference voltage for a 1 MHz, –0.5 dB input signal.
Note also that if the reference is changed during a conversion,
all three conversions in the pipeline will be invalidated.

Figure 20. S/(N+D) vs. Reference Input Voltage,
f

= 1 MHz, FS = 5 MHz

IN

Table II summarizes various 2.5 V references suitable for use
with the AD871, including the onboard bandgap reference (see
REFERENCE OUTPUT section).

Table II. Suitable 2.5 V References

Drift (PPM/8C) Initial Accuracy %

Figure 19. Equivalent Reference Input Circuit

However, in order to realize the lowest noise performance of the
AD871, care should be taken to minimize noise at the reference
input.

The AD871’s reference input impedance is equal to 5 kΩ (±20%),

and its effective noise bandwidth is 10 MHz, with a referred­to-input noise gain of 0.8. For example, the internal reference,

REV. A

REF IN

REF GND

REF-43B 6 (max) 0.2

AD871

1

5kV
(620%)

AD680JN 10 (max) 0.4
Internal 30 (typ) 0.4

If an external reference is connected to REF IN, REF OUT
must be connected to +5 V. This should lower the current in

2

AV

SS

REF GND to less than 350 µA and eliminate the need for a
1 µF capacitor, although decoupling the reference for noise

reduction purposes is recommended.

Alternatively, Figure 21 shows how the AD871 may be driven
from other references by use of an external resistor. The exter-

nal resistor forms a resistor divider with the on-chip 5 kΩ resis-

tor to realize 2.5 V at the reference input pin (REF IN). A trim
potentiometer is needed to accommodate the tolerance of the

AD871’s 5 kΩ resistor.

–11–

AD871

R

T

+5V REF

2kV

2.5V

R

3.9kV

REF IN

REF GND

AD871

5kV

Figure 21. Optional +5 V Reference Input Circuit

REFERENCE GROUND

The REF GND pin provides the reference point for both the
reference input and the reference output. When the internal ref-

erence is operating, it will draw approximately 500 µA of current

through the reference ground, so a low impedance path to the
external common is desirable. The AD871 can tolerate a fairly
large difference between REF GND and AGND, up to

±1 V, without any performance degradation.

REFERENCE OUTPUT

The AD871 features an onboard, curvature compensated band­gap reference that has been laser trimmed for both absolute
value and temperature drift. The output stage of the reference
was designed to allow the use of an external capacitor to limit

the wideband noise. As Figure 22 illustrates, a 1 µF capacitor on

the reference output is required for stability of the reference out­put buffer. Note: If used, an external reference may become un­stable with this capacitor in place.

2.55

2.54

2.53

2.52

2.51

2.50

2.49

2.48

REFERENCE VOLTAGE – Volts

2.47

2.46

2.45
–55

–35

TEMPERATURE – 8C

125

105856545255–15

Figure 23. Reference Output Voltage vs. Temperature

2.50

2.48

2.46

2.44

REFERENCE VOLTAGE – V

2.42

REF IN

0.1mF

1mF

REF GND

+

REF OUT

AD871

Figure 22. Typical Reference Decoupling Connection

With this capacitor in place, the noise on the reference output is

approximately 28 µV rms at room temperature. Figure 23 shows

the typical temperature drift performance of the reference, while
Figure 24 illustrates the variation in reference voltage with load
currents.

The output stage is designed to provide at least 2 mA of output
current, allowing a single reference to drive up to four AD871s
or other external loads. The power supply rejection of the refer­ence is better than 54 dB at dc.

2.40

1k

10k

REFERENCE OUTPUT LOAD – V

100k

1M

Figure 24. Reference Output Voltage vs. Output Load

DIGITAL OUTPUTS

In 28-lead packages, the AD871 output data is presented in
twos complement format. Table III indicates offset binary and
twos complement output for various analog inputs.

Table III. Output Data Format

Analog Input
V

INA–VINB

Offset Binary Twos Complement OTR

Digital Output

≥0.999756 V 1111 1111 1111 0111 1111 1111 1

0.999268 V 1111 1111 1111 0111 1111 1111 0
0 V 1000 0000 0000 0000 0000 0000 0
–1 V 0000 0000 0000 1000 0000 0000 0
–1.000244 V 0000 0000 0000 1000 0000 0000 1

Users requiring offset binary encoding may simply invert the
MSB pin. In the 44-terminal surface mount packages, both
MSB and

MSB bits are provided.

The AD871 features a digital out-of-range (OTR) bit that goes
high when the input exceeds positive full scale or falls below
negative full scale. As Table III indicates, the output bits will be
set appropriately according to whether it is an out-of-range high
condition or an out-of-range low condition. Note that if the in­put is driven beyond +1.5 V, the digital outputs may not stay at
+FS, but may actually fold back to midscale.

–12–

REV. A

AD871

75

55

133

65

8

FREQUENCY – MHz

S/(N+D) – dB

1.03

1.02

1.01

0.100 1.100 2.100 3.100 4.100 5.100
FREQUENCY – MHz

POWER – W

The AD871’s CMOS digital output drivers are sized to provide
sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause glitches on the sup­plies and may affect S/(N+D) performance. Applications requir­ing the AD871 to drive large capacitive loads or large fanout
may require additional decoupling capacitors on DRV
DV

. In extreme cases, external buffers or latches could be

DD

DD

and

used.

THREE-STATE OUTPUTS

The 44-terminal surface mount AD871 offers three-state out­puts. The digital outputs can be placed into a three-state mode
by pulling the OUTPUT ENABLE (OEN) pin LOW. Note that
this function is not intended to be used to pull the AD871 on
and off a bus at 5 MHz. Rather, it is intended to allow the ADC
to be pulled off the bus for evaluation or test modes. Also, to
avoid corruption of the sampled analog signal during conversion
(three clock cycles), it is highly recommended that the AD871
be placed on the bus prior to the first sampling.

OEN

DATA

OUTPUT

t

THREE-STATE

DD

ACTIVE

t

HL

Figure 25. Three-State Output Timing Diagram

For timing budgetary purposes, the typical access and float de­lay times for the AD871 are 50 ns.

CLOCK INPUT

The AD871 internal timing control uses the two edges of the
clock input to generate a variety of internal timing signals. The
optimal clock input should have a 50% duty cycle; however,
sensitivity to duty cycle is significantly reduced for clock rates of
less than 5 megasamples per second.

+5V

As a result, careful selection of the logic family for the clock
driver, as well as the fanout and capacitive load on the clock
line, is important. Jitter-induced errors become more pro­nounced at higher frequency, large amplitude inputs, where the
input slew rate is greatest.

The AD871 is designed to support a sampling rate of 5 MSPS;
running at slightly faster clock rates may be possible, although at
reduced performance levels. Conversely, some slight perfor­mance improvements might be realized by clocking the AD871
at slower clock rates. Figure 27 presents the S/(N+D) vs. clock
frequency for a 1 MHz analog input.

Figure 27. Typical S/(N+D) vs. Clock Frequency
f

= 1 MHz, Full-Scale Input

IN

The power dissipated by the correction logic and output buffers
is largely proportional to the clock frequency; running at re­duced clock rates provides a slight reduction in power consump­tion. Figure 28 illustrates this tradeoff.

D

75XX74

10MHz

+5V

Figure 26. Divide-by-Two Clock Circuit

Due to the nature of on-chip compensation circuitry, the duty
cycle should be maintained between 40% and 60%, even for
clock rates less than 5 MSPS. One way to realize a 50% duty
cycle clock is to divide down a clock of higher frequency, as
shown in Figure 26.

In this case, a 10 MHz clock is divided by 2 to produce the 5 MHz
clock input for the AD871. In this configuration, the duty cycle
of the 10 MHz clock is irrelevant.

The input circuitry for the CLKIN pin is designed to accommo­date both TTL and CMOS inputs. The quality of the logic in­put, particularly the rising edge, is critical in realizing the best
possible jitter performance for the part: the faster the rising
edge, the better the jitter performance.

REV. A

R

Q

Q

S

CLK

Figure 28. Typical Power Dissipation vs. Clock Frequency

ANALOG SUPPLIES AND GROUNDS

The AD871 features separate analog and digital supply and
ground pins, helping to minimize digital corruption of sensitive
analog signals. In general, AV

and AVDD, the analog supplies,

SS

should be decoupled to AGND, the analog common, as close to
the chip as physically possible. Care has been taken to minimize
the signal dependence of the power supply currents; however,
the analog supply currents will be proportional to the reference
input. With REFIN at 2.5 V, the typical current into AV

–13–

DD

is

AD871

82 mA, while the typical current out of AVSS is 115 mA. Typi­cally, 33 mA will flow into the AGND pin.

Careful design and the use of differential circuitry provide the
AD871 with excellent rejection of power supply noise over a
wide range of frequencies, as illustrated in Figure 29.

–75

–80

AV

DD

–85

AV

–90

SUPPLY REJECTION – dB

–95

–100

10k

SS

100k

FREQUENCY – Hz

DV

DD

10M1M

Figure 29. Power Supply Rejection vs. Frequency,
100 mV p-p Signal on Power Supplies

Figure 30 shows the degradation in SNR resulting from 100 mV
of power supply ripple at various frequencies. As Figure 30
shows, careful decoupling is required to realize the specified dy­namic performance. Figure 34 demonstrates the recommended
decoupling strategy for the supply pins. Note that in extremely
noisy environments, a more elaborate supply filtering scheme
may be necessary.

72

70

68

66

SNR – dB

64

AV

AV

DD

DV

DD

SS

function of the load on the output bits: large capacitive loads are
to be avoided. In the 44-terminal package, the output drivers are
supplied through dedicated pins DRGND and DRV

DD

. Pin
count constraints in the 28-lead packages require that the digital
and driver supplies share package pins (although they have sepa­rate bond wires and on-chip routing). The decoupling shown in
Figure 34 is appropriate for a reasonable capacitive load on the
digital outputs (typically 20 pF on each pin). Applications
involving greater digital loads should consider increasing the
digital decoupling proportionately, and/or using external
buffers/latches.

APPLICATIONS

OPTIONAL ZERO AND GAIN TRIM

The AD871 is factory trimmed to minimize zero error, gain
error and linearity errors. In some applications the zero and gain
errors of the AD871 need to be externally adjusted to zero. If
required, both zero error and gain error can be trimmed with
external potentiometers as shown in Figure 31. Note that gain
error adjustments must be made with an external reference.

Zero trim should be adjusted first. Connect V

to ground and

INA

adjust the 10 kΩ potentiometer so that a nominal digital output

code of 0000 0000 0000 (twos complement output) exists. Note
that the zero trim should be decoupled and that the accuracy of

the ±2.5 V reference signals will directly affect the offset.

Gain error may then be calibrated by adjusting the REF IN volt­age. The REF IN voltage should be adjusted such that a +1 V
input on V

results in the digital output code 01111 1111

INA

1111 (twos complement output).

10kV

+2.5V

–2.5V

0.1mF10mF

(a) ZERO TRIM

AD871

V

INB

V

AD

REF43

TRIM

OUT

(b) GAIN TRIM

AD871

REF IN

100kV

Figure 31. Zero and Gain Error Trims

62

60

10k 100k 10M1M

FREQUENCY – Hz

Figure 30. SNR vs. Supply Noise Frequency (fIN = 1 MHz)

DIGITAL SUPPLIES AND GROUNDS

The digital activity on the AD871 chip falls into two general cat­egories: CMOS correction logic, and CMOS output drivers.
The internal correction logic draws relatively small surges of
current, mainly during the clock transitions; in the 44-terminal
package, these currents flow through pins DGND and DV

DD

.
The output drivers draw large current impulses while the output
bits are changing. The size and duration of these currents is a

–14–

DIGITAL OFFSET CORRECTION

The AD871 provides differential inputs that may be used to cor­rect for any offset voltages on the analog input. For applications
where the input signal contains a dc offset, it may be advanta­geous to apply a nulling voltage to the V

input. Applying a

INB

voltage equal to the dc offset will maximize the full-scale input
range and therefore the dynamic range. Offsets ranging from
–0.7 V to +0.5 V can be corrected.

Figure 32 shows how a dc offset can be applied using the AD568
12-bit, high speed digital-to-analog converter (DAC). This cir­cuit can be used for applications requiring offset adjustments on
every clock cycle. The AD568 connection scheme is used to
provide a –0.512 V to +0.512 V output range. The offset voltage
must be stable on the rising edge of the AD871 clock input.

REV. A

AD871

1

V

IN

V

INA

AD871

DIGITAL
OFFSET
WORD

74

8 8

HC

574

74

HC

574

AD568

IBPO
IOUT

RL

44

ACOM
LCOM

REF COM

2

V

INB

Figure 32. Offset Correction Using the AD568

UNDERSAMPLING USING THE AD871 AND AD9100

The AD871’s on-chip THA optimizes transient response while
maintaining low noise performance. For super-Nyquist (under­sampling) applications it may be necessary to use an external
THA with fast track-mode slew rate and hold mode settling
time. An excellent choice for this application is the AD9100, an
ultrahigh speed track-and-hold amplifier.

In order to maximize the spurious free dynamic range of the cir­cuit in Figure 33, it is advantageous to present a small signal to
the input of the AD9100 and then amplify the output to the
AD871’s full-scale input range. This can be accomplished with
a low distortion, wide bandwidth amplifier such as the AD9617.
The circuit uses a gain of 3.5 to optimize S/(N+D).

The peak performance of this circuit is obtained by driving the
AD871 + AD9100 combination with a full-scale input. For
small scale input signals (–20 dB, –40 dB), the AD871 performs
better without the track-and-hold because slew-limiting effects
are no longer dominant. To gain the advantages of the added
track-and-hold, it is important to give the AD871 a full-scale
input.

An alternative to the configuration presented above is to use the
AD9101 track-and-hold amplifier. The AD9101 provides a
built-in post amplifier with a gain of 4, providing excellent ac
characteristics in conjunction with a high level of integration.

As illustrated in Figure 33, it is necessary to skew the AD871
sample clock and the AD9100 sample/hold control. Clock skew
(t

) is defined as the time starting at the AD9100’s transition

S

into hold mode and ending at the moment the AD871 samples.
The AD871 samples on the rising edge of the sample clock, and
the AD9100 samples on the falling edge of the sample/hold con­trol. The choice of t

is primarily determined by the settling

S

time of the AD9100. The droop rate of the AD9100 must also
be taken into consideration. Using these values, the ideal t

is

S

17 ns. When choosing clock sources, it is extremely important
that the front end track-and-hold sample/hold control is given a
very low jitter clock source. This is not as crucial for the AD871
sample clock, because it is sampling a dc signal.

CLOCK 1

+V

–V

S

S

IN

R

AD96685

T

+VS = 5.0V
–V

= –5.2V

S

ALL CAPACITORS ARE 0.01mF
(LOW INDUCTANCE - DECOUPLING)
UNLESS OTHERWISE NOTED.

CLOCK 2

t

= 17ns

S

CLOCK 1

Figure 33. Undersampling Using the AD871 and AD9100

Q

Q

–V

V

IN

510V 510V

–V

S

S

R

T

AD9100

T = 200ns

t

S

T = 200ns

10mF

442V

+5V

AD9617

–5V

3.3mF

0.1mF

0.1mF

*

*

0.1mF

0.1mF

3.3mF

*OPTIONAL, SEE
AD9617 DATA SHEET

+1V

–1V

+V

S

127V

–V

10mF

S

+5V

0V

A

IN

CLOCK 2

IN

AD871

EB

REV. A

–15–

AD871

ANALOG IN

J1

TP1

+5A

C22

0.1mF

+5VA

AGND

–5VA

+5VD

DGND

R1

49.9V

C7

10mF

REF43

1
2

V

IN

3
4

GND

*

NOTE: JP11 SHOULD BE OPEN

C1

0.01mF

U2

V

OUT

C2

0.01mF

C3

0.01mF

8
7
6
5

FB1

FB2

FB3

JP1

C5
22mF

0.1mF

10pF

0.1mF

JP2

C21
1mF

C6
22mF

C12

C20

C18

+5A

C4
22mF

27

28

26

*

JP
11

4

5

1

2

0.1mF

C9

0.1mF

AV

AGND

V

INA

V

INB

REF GND

REF IN

REF OUT

AV

C11

TP5

TP6

C10

0.1mF

DD

3

C8

0.1mF

AD871

SS

–5A

+5A

TP3

DV

DGND

DRV

DGND

BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8

BIT 9
BIT 10
BIT 11
BIT 12

AGND

AV

–5A

+5D

CLK
OTR

MSB

SS

25

DD

DD

C17

0.1mF

6

22

23

21
20

19
18

17
16
15
14
13
12

11
10

8

24

+5D

7

9

R3
10V

C13

0.1mF

C15

0.1mF

TP4

TP7

+5D

JP6

C14

0.1mF

C16

0.1mF

CLOCK INPUT

J2

R2

49.9V

U3

74HC04

1

2

JP5

TP2

JP3

P1

JP8

JP7

3

4

JP9

5

6

JP10

JP4

R5 20V

R6 20V

R7 20V

R8 20V

R9 20V

R4

40-PIN

IDC CONN.

1

C1848–0–11/97

R10 20V

R11 20V

R12 20V

R13 20V

R14 20V

R15 20V

R16 20V

R17 20V

40

0.005 (0.13) MIN

PIN 1

0.225
(5.72)

MAX

0.200 (5.08)

0.125 (3.18)

Figure 34. AD872/AD871 Evaluation Board Schematic

Dimensions shown in inches and (mm).

28-Lead Side Brazed Ceramic DIP (D-28)

0.100 (2.54) MAX

28

1

0.026 (0.66)

0.014 (0.36)

1.490 (37.85) MAX

0.110 (2.79)

0.090 (2.29)

0.070 (1.78)

0.030 (0.76)

15

14

0.610 (15.49)

0.500 (12.70)

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MIN

SEATING
PLANE

OUTLINE DIMENSIONS

0.620 (15.75)

0.590 (14.99)

0.018 (0.46)

0.008 (0.20)

–16–

0.100 (2.54)

0.064 (1.63)

44-Terminal LCC (E-44A)

0.050
(1.27)

BSC

0.055 (1.40)

0.045 (1.14)

28

6

TOP VIEW

0.662 (16.82)

0.640 (16.27)

1

0.075 (1.91) REF

40

18

SQ

0.020 (0.51)
REF x 45

0.028 (0.71)

0.022 (0.56)

0.040 (1.02)
REF x 45
3 PLACES

°

PRINTED IN U.S.A.

°

REV. A