Datasheet AD8652 Datasheet (ANALOG DEVICES)

50 MHz, Precision, Low Distortion,

O

www.BDTIC.com/ADI

FEATURES

Bandwidth: 50 MHz @ 5 V
Low noise: 4.5 nV/√Hz
Offset voltage: 100 μV typical, specified over

entire common-mode range
Slew rate: 41 V/μs
Rail-to-rail input and output swing
Input bias current: 1 pA
Single-supply operation: 2.7 V to 5.5 V
Space-saving MSOP and SOIC_N packaging

APPLICATIONS

Optical communications
Laser source drivers/controllers
Broadband communications
High speed ADCs and DACs
Microwave link interface
Cell phone PA control
Video line drivers
Audio

Low Noise CMOS Amplifiers

AD8651/AD8652

PIN CONFIGURATIONS

+

UT A

NC

1

AD8651

–IN

2

TOP VIEW

+IN

3

(Not to Scale)

–

4

V

NC = NO CONNECT

NC

8

+

7

V

OUT

6

NC

5

03301-001

–IN A

+IN A

–

V

1

AD8652

2

TOP VIEW

3

(Not to Scale)

4

Figure 1. 8-Lead MSOP (RM-8) Figure 2. 8-Lead MSOP (RM-8)

1

NC

AD8651

–IN

2

+IN

3

TOP VIEW

(Not to Scale)

–

4

V

NC = NO CONNECT

8

NC

+

7

V

OUT

6

NC

5

03301-002

OUT A

–IN A

+IN A

–

V

1

AD8652

2

3

TOP VIEW

(Not to Scale)

4

Figure 3. 8-Lead SOIC_N (R-8) Figure 4. 8-Lead SOIC_N (R-8)

8

7

6

5

8

7

6

5

V

OUT B

–IN B

+IN B

+

V

OUT B

–IN B

+IN B

03301-003

03301-004

GENERAL DESCRIPTION

The AD865x family consists of high precision, low noise, low
distortion, rail-to-rail CMOS operational amplifiers that run
from a single-supply voltage of 2.7 V to 5.5 V.

The AD865x family is made up of rail-to-rail input and output

mplifiers with a gain bandwidth of 50 MHz and a typical

a
voltage offset of 100 μV across common mode from a 5 V
supply. It also features low noise—4.5 nV/√Hz.

The AD865x family can be used in communications
ap

plications, such as cell phone transmission power control, fiber
optic networking, wireless networking, and video line drivers.

The AD865x family features the newest generation of DigiTrim®

ackage trimming. This new generation measures and

in-p
corrects the offset over the entire input common-mode range,
providing less distortion from V

variation than is typical of

OS

other rail-to-rail amplifiers. Offset voltage and CMRR are both
specified and guaranteed over the entire common-mode range
as well as over the extended industrial temperature range.

The AD865x family is offered in the narrow 8-lead SOIC

ackage and the 8-lead MSOP package. The amplifiers are

p
specified over the extended industrial temperature range
(−40°C to +125°C).

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD8651/AD8652

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Input Protection ..................................................................... 15

Applications....................................................................................... 1

Pin Configurations ...........................................................................1

General Description......................................................................... 1

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Typical Performance Characteristics .............................................6

Applications..................................................................................... 14

Theory of Operation ..................................................................14

Rail-to-Rail Output Stage...................................................... 14

Rail-to-Rail Input Stage......................................................... 14

REVISION HISTORY

8/06—Rev. B. to Rev. C

Changes to Figure 1 to Figure 4...................................................... 1

Changes to Figure 7 and Figure 9................................................... 6

Changes to Figure 23........................................................................ 9

Changes to Figure 53...................................................................... 14

Updated Outline Dimensions....................................................... 18

Changes to Ordering Guide.......................................................... 19

9/04—Rev. A to Rev. B

dded AD8652 ....................................................................Universal

A

Change to General Description....................................................... 1

Changes to Electrical Characteristics ............................................. 3

Changes to Absolute Maximum Ratings........................................ 5

Change to Figure 23 .......................................................................... 9

Change to Figure 26 .......................................................................... 9

Change to Figure 36 ........................................................................ 11

Change to Figure 42 ........................................................................ 12

Change to Figure 49 ........................................................................ 13

Change to Figure 51 ........................................................................ 13

Inserted Figure 52............................................................................ 13

Change to Theory of Operation section....................................... 14

Overdrive Recovery ............................................................... 15

Layout, Grounding, and Bypassing Considerations.............. 15

Power Supply Bypassing........................................................ 15

Grounding............................................................................... 15

Leakage Currents.................................................................... 15

Input Capacitance .................................................................. 16

Output Capacitance............................................................... 16

Settling Time........................................................................... 16

THD Readings vs. Common-Mode Voltage ...................... 16

Driving a 16-Bit ADC............................................................ 17

Outline Dimensions .......................................................................18

Ordering Guide .......................................................................... 19

Change to Input Protection section.............................................. 15

Changes to Ordering Guide........................................................... 20

6/04—Rev. 0 to Rev. A

C

hange to Figure 18.............................................................................8

Change to Figure 21.............................................................................9

Change to Figure 29.............................................................................10

Change to Figure 30.............................................................................10

Change to Figure 43.............................................................................12

Change to Figure 44.............................................................................12

Change to Figure 47.............................................................................13

Change to Figure 57.............................................................................17

10/03 Revision 0: Initial Version

Rev. C | Page 2 of 20

AD8651/AD8652

www.BDTIC.com/ADI

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

V+ = 2.7 V, V– = 0 V, VCM = V+/2, TA = 25°C, unless otherwise specified.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V

AD8651 0 V ≤ VCM ≤ 2.7 V 100 350 V
–40°C ≤ TA ≤ +85°C, 0 V ≤ VCM ≤ 2.7 V 1.4 mV
–40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 2.7 V 1.6 mV

AD8652 0 V ≤ VCM ≤ 2.7 V 90 300 V
–40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 2.7 V 0.4 1.3 mV

Offset Voltage Drift TCV
Input Bias Current I

–40°C ≤ TA ≤ +125°C 600 pA

Input Offset Current I
–40°C ≤ TA ≤ +85°C 30 pA
–40°C ≤ TA ≤ +125°C 600 pA

Input Voltage Range V

Common-Mode Rejection Ratio CMRR

AD8651 V+ = 2.7 V, –0.1 V < VCM < +2.8 V 75 95 dB
–40°C ≤ TA ≤ +85°C, –0.1 V < VCM < +2.8 V 70 88 dB
–40°C ≤ TA ≤ +125°C, –0.1 V < VCM < +2.8 V 65 85 dB

AD8652 V+ = 2.7 V, –0.1 V < VCM < +2.8 V 77 95 dB
–40°C ≤ TA ≤ +125°C, –0.1 V < VCM < +2.8 V 73 90 dB

Large Signal Voltage Gain A
R
R
OUTPUT CHARACTERISTICS

Output Voltage High V

Output Voltage Low V

Short-Circuit Limit I
Sinking 80 mA

Output Current I
POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 2.7 V to 5.5 V, VCM = 0 V 76 94 dB
–40°C ≤ TA ≤ +125°C 74 93 dB

Supply Current I

AD8651 IO = 0 9 12 mA

–40°C ≤ TA ≤ +125°C 14.5 mA

AD8652 IO = 0 17.5 19.5 mA
–40°C ≤ TA ≤ +125°C 22.5 mA
INPUT CAPACITANCE C

Differential 6 pF
Common Mode 9 pF

DYNAMIC PERFORMANCE

Slew Rate SR G = 1, RL = 10 kΩ 41 V/s
Gain Bandwidth Product GBP G = 1 50 MHz
Settling Time, 0.01% G = ±1, 2 V step 0.2 s
Overload Recovery Time VIN × G = 1.48 V
Total Harmonic Distortion + Noise THD + N G = 1, RL = 600 Ω, f = 1 kHz, VIN = 2 V p-p 0.0006 %

NOISE PERFORMANCE

Voltage Noise Density e

f = 100 kHz 4.5 nV/√Hz

Current Noise Density i

OS

OS

B

OS

CM

VO

OH

OL

SC

O

SY

IN

n

n

4 V/°C
1 10 pA

1 10 pA

–0.1 +2.8 V

RL = 1 kΩ, 200 mV < VO < 2.5 V 100 115 dB

= 1 kΩ, 200 mV < VO < 2.5 V, TA = 85°C 100 114 dB

L

= 1 kΩ, 200 mV < VO < 2.5 V, TA = 125°C 95 108 dB

L

IL = 250 A, –40°C ≤ TA ≤ +125°C 2.67 V
IL = 250 A, –40°C ≤ TA ≤ +125°C 30 mV
Sourcing 80 mA

40 mA

+

f = 10 kHz 5 nV/√Hz

f = 10 kHz 4 fA/√Hz

0.1 s

Rev. C | Page 3 of 20

AD8651/AD8652

www.BDTIC.com/ADI

V+ = 5 V, V– = 0 V, VCM = V+/2, TA = 25°C, unless otherwise specified.

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V

AD8651 0 V ≤ VCM ≤ 5 V 100 350 V

–40°C ≤ TA ≤ +85°C, 0 V ≤ VCM ≤ 5 V 1.4 mV
–40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 5 V 1.7 mV

AD8652 0 V ≤ VCM ≤ 5 V 90 300 V

–40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 5 V 0.4 1.4 mV

Offset Voltage Drift TCV

Input Bias Current I
–40°C ≤ TA ≤ +85°C 30 pA
–40°C ≤ TA ≤ +125°C 600 pA

Input Offset Current I
–40°C ≤ TA ≤ +85°C 30 pA
–40°C ≤ TA ≤ +125°C 600 pA

Input Voltage Range V

Common-Mode Rejection Ratio CMRR

AD8651 0.1 V < VCM < 5.1 V 80 95 dB
–40°C ≤ TA ≤ +85°C, 0.1 V < VCM < 5.1 V 75 94 dB
–40°C ≤ TA ≤ +125°C, 0.1 V < VCM < 5.1 V 70 90 dB

AD8652 0.1 V < VCM < 5.1 V 84 100 dB
–40°C ≤ TA ≤ +125°C, 0.1 V < VCM < 5.1 V 76 95 dB

Large Signal Voltage Gain A
R
R
OUTPUT CHARACTERISTICS

Output Voltage High V

Output Voltage Low V

Short-Circuit Limit I
Sinking 80 mA

Output Current I
POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 2.7 V to 5.5 V, V
–40°C ≤ TA ≤ +125°C 74 93 dB

Supply Current I

AD8651 IO = 0 9.5 14.0 mA

–40°C ≤ TA ≤ +125°C 15 mA

AD8652 IO = 0 17.5 20.0 mA
–40°C ≤ TA ≤ +125°C 23.5 mA
INPUT CAPACITANCE C

Differential 6 pF
Common Mode 9 pF

DYNAMIC PERFORMANCE

Slew Rate SR G = 1, RL = 10 kΩ 41 V/µs
Gain Bandwidth Product GBP G = 1 50 MHz
Settling Time, 0.01% G = ±1, 2 V step 0.2 s
Overload Recovery Time VIN × G = 1.2 V
Total Harmonic Distortion + Noise THD + N G = 1, RL = 600 Ω, f = 1 kHz, VIN = 2 V p-p 0.0006 %

NOISE PERFORMANCE

Voltage Noise Density e

f = 100 kHz 4.5 nV/√Hz

Current Noise Density i

OS

OS

B

OS

CM

VO

OH

OL

SC

O

SY

IN

n

n

4 V/°C
1 10 pA

1 10 pA

–0.1 +5.1 V

RL = 1 kΩ, 200 mV < VO < 4.8 V 100 115 dB

= 1 kΩ, 200 mV < VO < 4.8 V, TA = 85°C 98 114 dB

L

= 1 kΩ, 200 mV < VO < 4.8 V, TA = 125°C 95 111 dB

L

IL = 250 µA, –40°C ≤ TA ≤ +125°C 4.97 V
IL = 250 µA, –40°C ≤ TA ≤ +125°C 30 mV
Sourcing 80 mA

40 mA

= 0 V 76 94 dB

CM

+

f = 10 kHz 5 nV/√Hz

f = 10 kHz 4 fA/√Hz

0.1 s

Rev. C | Page 4 of 20

AD8651/AD8652

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings apply at 25°C, unless otherwise noted.

Table 3.

Parameter Rating

Supply Voltage 6.0 V

Input Voltage GND to V

Differential Input Voltage ±6.0 V

Output Short-Circuit Duration to GND Indefinite

Electrostatic Discharge (HBM) 4000 V

Storage Temperature Range

RM, R Package −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range

RM, R Package −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

+ 0.3 V

S

THERMAL RESISTANCE

JA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θ

8-Lead MSOP (RM) 210 45 °C/W
8-Lead SOIC_N (R) 158 43 °C/W

JA

θ

JC

Unit

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. C | Page 5 of 20

AD8651/AD8652

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

60

50

VS = ±2.5V
V

= 0V

CM

100

VS = 5V

80

NUMBER OF AMPLIF IERS

(µV)

OS

V

–100

–200

300

200

100

40

30

20

10

0

–200

–160

–120

–80

–40

VOS (µV)

0

Figure 5. Input Offset Voltage Distribution

VS = ±2.5V
V

= 0V

CM

0

60

40

(µV)

OS

V

20

0

–20

40

80

120

160

200

03301-005

0123456

COMMON-MODE VOLTAGE (V)

3301-008

Figure 8. Input Offset Voltage vs. Common-Mode Voltage

500

VS = ±2.5V

400

300

200

INPUT BIAS CURRENT (pA)

100

–300

–50 0 50 100 150

TEMPERATURE (°C)

Figure 6. Input Offset Voltage vs. Temperature

60

50

40

30

20

NUMBER OF AMPLIFI ERS

10

0

01234567891011

TCVOS(µV/°C)

Figure 7. TCV

OS

VS= ±2.5V
V
T

Distribution

=0V

CM

: –40°C TO +125°C

A

0

3301-006

040 120100806020

TEMPERATURE (°C)

140

3301-009

Figure 9. Input Bias Current vs. Temperature

10

8

6

4

SUPPLY CURRENT (mA)

2

0

02 5431

3301-007

SUPPLY VOLTAGE (V)

6

3301-010

Figure 10. Supply Current vs. Supply Voltage

Rev. C | Page 6 of 20

AD8651/AD8652

V

V

www.BDTIC.com/ADI

12

VS = ±2.5V

11

2.50

2.00

VS = 5V
I

= 250µA

L

10

9

8

SUPPLY CURRENT (mA)

7

6
–50 0 50 100 150

TEMPERATURE (°C)

Figure 11. Supply Current vs. Temperature

500

400

300

) (mV)

OUT

–

200

SY

(

100

V

OH

V

OL

VS=±2.5V

1.50

1.00

OUTPUT SWING LOW (mV)

0.50

0

3301-011

–50 0 50 100 150

TEMPERATURE (°C)

03301-014

Figure 14. Output Voltage Swing Low vs. Temperature

100

80

60

40

CMRR (dB)

20

VS = ±2.5V

0

0204060 1080

CURRENT LOAD (mA)

Figure 12. Output Voltage to Supply Rail vs. Load Current

4.997

4.996

4.995

4.994

4.993

4.992

OUTPUT SWING HIGH (V)

4.991

4.990
–50 0 50 100 150

TEMPERATURE (°C)

VS = 5V
I

L

Figure 13. Output Voltage Swing High vs. Temperature

= 250µA

0

3301-012

3301-013

0

10 1k 10M1M100k10k100

FREQUENCY (Hz)

Figure 15. CMRR vs. Frequency

110

105

100

CMRR (dB)

95

90

–50 0 50 100 150

TEMPERATURE (°C)

VS = ±2.5V

Figure 16. CMRR vs. Temperature

3301-015

3301-016

Rev. C | Page 7 of 20

AD8651/AD8652

www.BDTIC.com/ADI

100

97

94

100

VS = ±2.5V

91

CMRR (dB)

88

85

82

–50 0 50 100 150

TEMPERATURE (°C)

Figure 17. CMRR vs. Temperature

100

80

60

40

PSRR (dB)

20

0

1 10 100 1k 10k 100k 1M 10M 100M

+PSRR

–PSRR

FREQUENCY ( Hz)

Figure 18. PSRR vs. Frequency

100

95

VS = ±2.5V

VS = ±2.5V

10

VOLTAGE NOISE DENSITY (nV/ √Hz)

1

3301-017

10 1k 100k10k100

FREQUENCY ( Hz)

3301-020

Figure 20. Voltage Noise Density vs. Frequency

80

60

40

20

CURRENT NOISE DENSITY (f A/√Hz)

0

3301-018

100 1k 100k10k

FREQUENCY ( Hz)

VS = ±2.5V

3301-021

Figure 21. Current Noise Density vs. Frequency

VS = ±2.5V
V

= 6.4V

IN

V

IN

V

OUT

90

PSRR (dB)

85

80

–50 0 50 100 150

TEMPERATURE (°C)

Figure 19. PSRR vs. Temperature

3301-019

0

VOLTAGE (1V/DIV)

Figure 22. No Phase Reversal

Rev. C | Page 8 of 20

TIME (200µs/DIV)

3301-022

AD8651/AD8652

www.BDTIC.com/ADI

140

120

100

80

60

40

OPEN-LOOP GAIN (dB)

20

0

–20

10 100 1k 10k 100k 1M 10M 100M

FREQUENCY ( Hz)

Figure 23. Open-Loop Gain and Phase vs. Frequency

117

116

115

114

OPEN-LOOP GAIN (dB)

113

VS = ±2.5V

VS = ±2.5V
R

= 1kΩ

L

0

–45

–90

–135

–180

PHASE (Degrees)

03301-023

60

40

G = 100

20

G = 10

0

G = 1

CLOSED-LOOP GAIN (dB)

–20

–40

5k

50k 5M500k 50M 300M

FREQUENCY ( Hz)

VS = ±2.5V

= 1MΩ

R

L

= 47pF

C

L

3301-026

Figure 26. Closed-Loop Gain vs. Frequency

6

5

4

3

2

MAXIMUM OUTPUT SWING (V)

1

VS = 5V

VS = 2.7V

112

–50 0 50 100 150

TEMPERATURE (°C)

Figure 24. Open-Loop Gain vs. Temperature

140

I

=250µA

130

120

110

100

90

OPEN-LOOP GAIN (dB)

80

70

60

0 100 150 250200

50

OUTPUT VOLTAGE SWING FROM THE RAILS (mV)

L

IL=2.5mA

IL=4.2mA

V

S

Figure 25. Open-Loop Gain vs. Output Voltage Swing

=±2.5V

0

100k 100M10M1M

03301-024

FREQUENCY ( Hz)

3301-027

Figure 27. Maximum Output Swing vs. Frequency

VS = ±2.5V

= 47pF

C

L

= 1

A

V

VOLTAGE (1V/DIV)

03301-025

TIME (100µ s/DIV)

3301-028

Figure 28. Large Signal Response

Rev. C | Page 9 of 20

AD8651/AD8652

A

2

V

www.BDTIC.com/ADI

VS = ±2.5V
V

= 200mV

IN

A

= 1

V

–2.5V

VS = ±2.5V

= 200mV

V

IN

0V

GAIN = –15

OUTPUT

VOLTAGE (100mV/DIV)

TIME (10µ s/DIV)

Figure 29. Small Signal Response

30

VS = ±2.5V
V

= 200mV

IN

A

= 1

25

V

L OVERSHOOT (%)

SMALL SIGN

20

15

10

5

0

020 6050403010

CAPACITANCE (pF)

–OS

Figure 30. Small Signal Overshoot vs. Load Capacitance

2.5V

+OS

VS = ±2.5V
V

IN

GAIN = –15

= 200mV

3301-029

70

3301-030

00m

0V

40

VS = ±2.5V

30

20

10

OUTPUT IMPEDANCE (Ω)

0

10 1k 100k10k100

60

50

INPUT

TIME (200ns/DIV)

Figure 32. Positive Overload Recovery Time

GAIN = 10

GAIN = 1

GAIN = 100

FREQUENCY ( Hz)

Figure 33. Output Imped

ance vs. Frequency

VS = ±1.35V

= 0V

V

CM

3301-032

3301-033

–200mV

0V

0V

TIME (200n s/DIV)

3301-031

NUMBER OF AMPLIF IERS

40

30

20

10

0

–200

–160

–120

–80

Figure 31. Negative Overload Recovery Time

Figure 34. Input Offset Voltage Distribution

Rev. C | Page 10 of 20

–40

VOS (µV)

0

40

80

120

160

200

03301-034

AD8651/AD8652

V

V

www.BDTIC.com/ADI

300

200

VS = ±1.35V

= 0V

V

CM

500

400

VS= ±1.35V

100

0

(µV)

OS

V

–100

–200

–300

–50 0 50 100 150

TEMPERATURE (°C)

Figure 35. Input Offset Voltage vs. Temperature

80

60

40

20

0

INPUT OFFSET VOLTAGE (µV)

VS = 2.7V

300

) (mV)

OUT

–

200

SY

(

100

0

3301-035

0204060 1080

V

OH

CURRENT LOAD (mA)

V

OL

0

3301-038

Figure 38. Output Voltage to Supply Rail vs. Load Current

OUTPUT SWING HIGH (V)

2.697

2.696

2.695

2.694

2.693

2.692

2.691

VS = 2.7V

= 250µA

I

L

–20

012

INPUT COMMON-MODE VOLTAGE (V)

Figure 36. Input Offset Voltage vs. Common-Mode Voltage

11

VS = ±1.35V

10

9

8

SUPPLY CURRENT (mA)

7

6
–50 0 50 100 150

TEMPERATURE (°C)

Figure 37. Supply Current vs. Temperature

3

3301-036

3301-037

2.690
–50 0 50 100 150

TEMPERATURE (°C)

Figure 39. Output Voltage Swing High vs. Temperature

3.00

2.50

2.00

1.50

1.00

OUTPUT SWING LOW (mV)

0.50

0

–50 0 50 100 150

TEMPERATURE (°C)

Figure 40. Output Voltage Swing Low vs. Temperature

VS = 2.7V

= 250µA

I

L

3301-039

3301-040

Rev. C | Page 11 of 20

AD8651/AD8652

A

V

www.BDTIC.com/ADI

VS = ±1.35V

= 1

A

V

30

25

20

VS = ±1.35V

= 200mV

V

IN

15

L OVERSHOOT (%)

VOLTAGE (1V/DIV)

TIME (200µs/DIV)

3301-041

Figure 41. No Phase Reversal

VS = ±1.35V

= 47pF

C

L

= 1

A

V

VOLTAGE (500mV/DIV)

TIME (100µs/DIV)

3301-042

Figure 42. Large Signal Response

10

5

SMALL SIGN

0

020 6050403010

CAPACITANCE (pF)

Figure 44. Small Signal Overshoot vs. Load Capacitance

1.35V

0V

0V

–200mV

Figure 45. Negative Overload Recovery Time

–OS

TIME (200n s/DIV)

+OS

VS = ±1.35V
V

= 200mV

IN

GAIN = –10

70

3301-044

3301-045

VS = ±1.35V

= 200mV

V

IN

= 47pF

C

L

= 1

A

V

VOLTAGE (100mV/DIV)

TIME (10µ s/DIV)

3301-043

Figure 43. Small Signal Response

0V

–1.35V

200m

0V

TIME (200n s/DIV)

Figure 46. Positive Overload Recovery Time

VS = ±1.35V
V

= 200mV

IN

GAIN = –10

03301-046

Rev. C | Page 12 of 20

AD8651/AD8652

R
A

www.BDTIC.com/ADI

100

VS = ±1.35V

80

120

118

VS = ±1.35V
R

= 1kΩ

L

60

40

CMRR (dB)

20

0

10 1k 10M1M100k10k100

FREQUENCY (Hz)

Figure 47. CMRR vs. Frequency

100

80

60

40

PSRR (dB)

20

0

1 10 100 1k 10k 100k 1M 10M

+PSRR

–PSRR

FREQUENCY (Hz)

Figure 48. PSRR vs. Frequency

140

120

100

80

60

40

OPEN-LOOP GAIN (dB)

20

0

–20

10 100 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 49. Open-Loop Gain and Phase vs. Frequency

VS = ±1.35V

VS = ±1.35V

0

–45

–90

–135

–180

116

114

(dB)

VO

A

112

110

108

3301-047

–50 0 50 100 150

TEMPERATURE (°C)

3301-050

Figure 50. Open-Loop Gain vs. Temperature

60

40

G = 100

20

G = 10

0

G = 1

CLOSED-LOOP GAIN (dB)

–20

–40

3301-048

5k

50k 5M500k 50M 300M

FREQUENCY ( Hz)

VS = ±1.35V
R

= 1MΩ

L

C

= 47pF

L

3301-051

Figure 51. Closed-Loop Gain vs. Frequency

0

–20

V

–40

TION (dB)

–60

–80

PHASE (Degrees)

03301-049

CHANNEL SEPA

–100

–120

–140

28mV p-p

IN

+2.5V

V+

V–

–2.5V

FREQUENCY (Hz)

R1

10kΩ

V–

V

OUT

V+

R2

100Ω

VS = ±2.5V

10M100 1k 10k 100k 1M

03301-052

Figure 52. Channel Separation vs. Frequency.

Rev. C | Page 13 of 20

AD8651/AD8652

www.BDTIC.com/ADI

APPLICATIONS

THEORY OF OPERATION

The AD865x family consists of voltage feedback, rail-to-rail
input and output precision CMOS amplifiers that operate from

2.7 V to 5.5 V of power supply voltage. These amplifiers use
Analog Devices, Inc. DigiTrim technology to achieve a higher
degree of precision than is available from most CMOS
amplifiers. DigiTrim technology, used in a number of Analog
Devices amplifiers, is a method of trimming the offset voltage of
the amplifier after it has been assembled. The advantage of
post-package trimming is that it corrects any offset voltages
caused by the mechanical stresses of assembly.

The AD865x family is available in standard op amp pinouts,
making Dig
stage of the amplifiers is a true rail-to-rail architecture, allowing
the input common-mode voltage range of the op amp to extend
to both positive and negative supply rails. The open-loop gain
of the AD865x with a load of 1 kΩ is typically 115 dB.

The AD865x can be used in any precision op amp application.
The a
voltages within the power supply. With voltage noise of

4.5 nV/√Hz and –105 dB distortion for 10 kHz, 2 V p-p signals,
the AD865x is a great choice for high resolution data
acquisition systems. Their low noise, sub-pA input bias current,
precision offset, and high speed make them superb preamps for
fast photodiode applications. The speed and output drive
capabilities of the AD865x also make the amplifiers useful in
video applications.

Rail-to-Rail Output Stage

The voltage swing of the output stage is rail-to-rail and is
achieved by using an NMOS and PMOS transistor pair con­nected in a common source configuration. The maximum
output voltage swing is proportional to the output current, and
larger currents will limit how close the output voltage can get to
the proximity of the output voltage to the supply rail. This is a
characteristic of all rail-to-rail output amplifiers. With 40 mA of
output current, the output voltage can reach within 5 mV of the
positive and negative rails. At light loads of >100 kΩ, the output
swings within ~1 mV of the supplies.

iTrim completely transparent to the user. The input

mplifiers do not exhibit phase reversal for common-mode

The NMOS and PMOS input stages are separately trimmed
usin

g DigiTrim to minimize the offset voltage in both differen­tial pairs. Both NMOS and PMOS input differential pairs are
active in a 500 mV transition region when the input common­mode voltage is approximately 1.5 V below the positive supply
voltage. A special design technique improves the input offset
voltage in the transition region that traditionally exhibits a
slight V

variation. As a result, the common-mode rejection

OS

ratio is improved within this transition band. Compared to the
Burr Brown OPA350 amplifier, shown in
AD865x, sh
s

hift across the entire input common-mode range, including the

own in Figure 54, exhibits much lower offset voltage

Figure 53, the

transition region.

600

400

200

0

(µV)

OS

V

–200

–400

–600

0

Figure 53. Input Offset Distribution over Common-Mode

214356

COMMON-MODE VOLTAGE (V)

Vo

ltage for the OPA350

3301-053

600

400

200

0

(µV)

OS

V

–200

Rail-to-Rail Input Stage

The input common-mode voltage range of the AD865x extends
to both positive and negative supply voltages. This maximizes
the usable voltage range of the amplifier, an important feature
for single-supply and low voltage applications. This rail-to-rail
input range is achieved by using two input differential pairs, one
NMOS and one PMOS, placed in parallel. The NMOS pair is active

–400

–600

0

Figure 54. Input Offset Distribution over Common-Mode

21435

COMMON-MODE VOLTAGE (V)

Input Protection for the AD865x

at the upper end of the common-mode voltage range, and the
PMOS pair is active at the lower end of the common-mode range.

Rev. C | Page 14 of 20

6

3301-061

AD8651/AD8652

www.BDTIC.com/ADI

Input Protection

As with any semiconductor device, if a condition exists for the
input voltage to exceed the power supply, the device input
overvoltage characteristic must be considered. The inputs of the
AD865x family are protected with ESD diodes to either power
supply. Excess input voltage energizes internal PN junctions in
the AD865x, allowing current to flow from the input to the
supplies. This results in an input stage with picoamps of input
current that can withstand up to 4000 V ESD events (human
body model) with no degradation.

Excessive power dissipation through the protection devices

troys or degrades the performance of any amplifier. Differential

des
voltages greater than 7 V result in an input current of approximately
(| V

– V

CC

| – 0.7 V)/RI, where RI is the resistance in series with

EE

the inputs. For input voltages beyond the positive supply, the
input current is approximately (V

– VCC – 0.7)/RI. For input

IN

voltages beyond the negative supply, the input current is about
(V

– VEE + 0.7)/RI. If the inputs of the amplifier sustain

IN

differential voltages greater than 7 V or input voltages beyond
the amplifier power supply, limit the input current to 10 mA by
using an appropriately sized input resistor (R

), as shown in

I

Figure 55.

(| VCC–VEE|–0.7V)

R

>

I

FOR LARG E | V

30mA

–VIN+

R

|

CC–VEE

Figure 55. Input Protection Method

R

+

AD865x

–

I

R

+V

(V

>

I

(V

>

I

FOR V
SUPPLY VOLTAGES

O

IN–VEE

30mA

IN–VEE

30mA

IN

–0.7V)

+0.7V)

BEYOND

03301-054

Overdrive Recovery

Overdrive recovery is defined as the time it takes for the output
of an amplifier to come off the supply rail after an overload signal is
initiated. This is usually tested by placing the amplifier in a closed­loop gain of 15 with an input square wave of 200 mV p-p while the
amplifier is powered from either 5 V or 3 V. The AD865x family
has excellent recovery time from overload conditions (see
and

Figure 32). The output recovers from the positive supply rail

wi

thin 200 ns at all supply voltages. Recovery from the negative rail

Figure 31

is within 100 ns at 5 V supply.

LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS

Power Supply Bypassing

Power supply pins can act as inputs for noise, so care must be
taken that a noise-free, stable dc voltage is applied. The purpose
of bypass capacitors is to create low impedances from the supply
to ground at all frequencies, thereby shunting or filtering most
of the noise.

Bypassing schemes are designed to minimize the supply

pedance at all frequencies with a parallel combination of

im
capacitors of 0.1 μF and 4.7 μF. Chip capacitors of 0.1 μF (X7R
or NPO) are critical and should be as close as possible to the
amplifier package. The 4.7 μF tantalum capacitor is less critical
for high frequency bypassing, and, in most cases, only one is
needed per board at the supply inputs.

Grounding

A ground plane layer is important for densely packed PC
boards to spread the current-minimizing parasitic inductances.
However, an understanding of where the current flows in a
circuit is critical to implementing effective high speed circuit
design. The length of the current path is directly proportional to
the magnitude of parasitic inductances and, therefore, the high
frequency impedance of the path. High speed currents in an
inductive ground return create an unwanted voltage noise.

The length of the high frequency bypass capacitor leads is
c

ritical. A parasitic inductance in the bypass grounding works
against the low impedance created by the bypass capacitor.
Place the ground leads of the bypass capacitors at the same
physical location. Because load currents also flow from the
supplies, the ground for the load impedance should be at the
same physical location as the bypass capacitor grounds. For the
larger value capacitors, intended to be effective at lower
frequencies, the current return path distance is less critical.

Leakage Currents

Poor PC board layout, contaminants, and the board insulator
material can create leakage currents that are much larger than the
input bias current of the AD865x family. Any voltage differential
between the inputs and nearby traces sets up leakage currents
through the PC board insulator, for example 1 V/100 G = 10 pA.
Similarly, any contaminants on the board can create significant
leakage (skin oils are a common problem).

To significantly reduce leakages, put a guard ring (shield)

round the inputs and the input leads that are driven to the

a
same voltage potential as the inputs. This ensures that there is
no voltage potential between the inputs and the surrounding
area to set up any leakage currents. To be effective, the guard
ring must be driven by a relatively low impedance source and
should completely surround the input leads on all sides, above
and below, using a multilayer board.

Another effect that can cause leakage currents is the charge
ab

sorption of the insulator material itself. Minimizing the
amount of material between the input leads and the guard
ring helps to reduce the absorption. Also, low absorption
materials, such as Teflon® or ceramic, may be necessary in
some instances.

Rev. C | Page 15 of 20

AD8651/AD8652

V

2

%

www.BDTIC.com/ADI

Input Capacitance

Along with bypassing and grounding, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground. A
few picofarads of capacitance reduces the input impedance at high
frequencies, which in turn increases the amplifier gain, causing
peaking in the frequency response or oscillations. With the
AD865x, additional input damping is required for stability with
capacitive loads greater than 47 pF with direct input to output
feedback (see the Output Capacitance section).

Output Capacitance

When using high speed amplifiers, it is important to consider
the effects of the capacitive loading on amplifier stability.
Capacitive loading interacts with the output impedance of the
amplifier, causing reduction of the BW as well as peaking and
ringing of the frequency response. To reduce the effects of the
capacitive loading and allow higher capacitive loads, there are
two commonly used methods.

• As shown in Figure 56, place a small value resistor (R

series with the output to isolate the load capacitor from the
amplifier output. Heavy capacitive loads can reduce the
phase margin of an amplifier and cause the amplifier
response to peak or become unstable. The AD865x is able
to drive up to 47 pF in a unity gain buffer configuration
without oscillation or external compensation. However, if
an application requires a higher capacitive load drive when
the AD865x is in unity gain, the use of external isolation
networks can be used. The effect produced by this resistor
is to isolate the op amp output from the capacitive load.
The required amount of series resistance has been
tabulated in Table 5 for different capacitive loads. While
this technique improves the overall capacitive load drive
for the amplifier, its biggest drawback is that it reduces the
output swing of the overall circuit.

CC

U1

3

V

+

IN

2

+

V

AD865x

–

V

–

0

R

S

C

R

L

0

0

Figure 56. Driving Large Capacitive Loads

V

OUT

L

) in

S

03301-055

• Another way to stabilize an op amp driving a large capacitive

load is to use a snubber network, as shown in Figure 57. Because
there is not any isolation resistor in the signal path, this method
has the significant advantage of not reducing the output swing.
The exact values of R
Figure 57, an optimum R

and CS are derived experimentally. In

S

and CS combination for a capacitive

S

load drive ranging from 50 pF to 1 nF was chosen. For this,
R

= 3 Ω and CS = 10 nF were chosen.

S

+

V

+

+

00mV

V

AD865x

–

V

–

–

V

R

S

C

L

C

S

V

OUT

R

L

3301-056

Figure 57. Snubber Network

Settling Time

The settling time of an amplifier is defined as the time it takes
for the output to respond to a step change of input and enter
and remain within a defined error band, as measured relative to
the 50% point of the input pulse. This parameter is especially
important in measurements and control circuits where amplifi­ers are used to buffer A/D inputs or DAC outputs. The design of
the AD865x family combines a high slew rate and a wide gain
bandwidth product to produce an amplifier with very fast
settling time. The AD865x is configured in the noninverting
gain of 1 with a 2 V p-p step applied to its input. The AD865x
family has a settling time of about 130 ns to 0.01% (2 mV). The
output is monitored with a 10×, 10 M, 11.2 pF scope probe.

THD Readings vs. Common-Mode Voltage

Total harmonic distortion of the AD865x family is well below

0.0004% with any load down to 600 Ω. The distortion is a
function of the circuit configuration, the voltage applied, and
the layout, in addition to other factors. The AD865x family
outperforms its competitor for distortion, especially at
frequencies below 20 kHz, as shown in Figure 58.

)

0.005

0.1

0.05

0.02

0.01

VSY = +3.5V/–1.5V

= 2.0V p-p

V

OUT

Table 5. Optimum Values for Driving Large Capacitive Loads

CL R

S

100 pF 50 Ω
500 pF 35 Ω

1.0 nF 25 Ω

Rev. C | Page 16 of 20

0.002

0.001

THD + NOISE (

0.0005

0.0002

0.0001
20 50 100 500 20k5k2k1k

OPA350

AD8651

FREQUENCY (Hz)

Figure 58. Total Harmonic Distortion

03301-057

AD8651/AD8652

V

www.BDTIC.com/ADI

+3.5V

+

47pF

V

OUT

03301-058

V

2V p-p

AD865x

–

IN

–1.5V

600Ω

Figure 59. THD + N Test Circuit

Driving a 16-Bit ADC

The AD865x family is an excellent choice for driving high
speed, high precision ADCs. The driver amplifier for this type
of application needs low THD + N as well as quick settling time.
Figure 61 shows a complete single-supply data acquisition

olution. The AD865x family drives the AD7685, a 250 kSPS,

s
16-bit data converter.

1

The AD865x is configured in an inverting gain of 1 with a 5 V
single supply. Input of 45 kHz is applied, and the ADC samples
at 250 kSPS. The results of this solution are listed in Tab le 6.
The adva

ntage of this circuit is that the amplifier and ADC can
be powered with the same power supply. For the case of
a noninverting gain of 1, the input common-mode voltage
encompasses both supplies.

1

For more information about the AD7685 data converter, go to

http://www.analog.com/Analog_Root/productPage/productHome/0%2C21
21%2CAD7685%2C00.html

0

–20

–40

–60

–80

–100

f

= 250kSPS

SAMPLE

= 45kHz

f

IN

INPUT RANGE = 0V TO 5V

5

1µF

10kΩ

10kΩ

0V TO 5V

= 45kHz

f

IN

1kΩ

V

IN

3

+

AD865x

2

–

V

+

V

1kΩ

U1

V

2.7nF

IN

CC

AD7685

03301-060

33Ω

–

Figure 61. AD865x Driving a 16-Bit ADC

Table 6. Data Acquisition Solution of Figure 60

Parameter Reading (dB)

THD + N 105.2
SFDR 106.6
2nd Harmonics 107.7
3rd Harmonics 113.6

–120

AMPLITUDE (dB of Full Scale)

–140

–160

10 20 30 40 50 60 70 80 90 100 110 120

0

FREQUE NCY (kHz )

Figure 60. Frequency Response of AD865x Driving a 16-Bit ADC

03301-059

Rev. C | Page 17 of 20

AD8651/AD8652

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

3.20

3.00

2.80

PIN 1

0.95

0.85

0.75

0.15

0.00

COPLANARITY

8

1

0.65 BSC

0.38

0.22

0.10

3.20

3.00

2.80

5

4

SEATING
PLANE

5.15

4.90

4.65

1.10 MAX

0.23

0.08

8°
0°

0.80

0.60

0.40

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 62. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dim

ensions shown in millimeters

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLL ING DIMENSI ONS ARE IN MILLIMETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DES IGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-A A

BSC

6.20 (0.2440)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

Figure 63. 8-Lead Standard Small Outline Package [SOIC_N]

Nar

row Body

(R-8)

Dimensions shown in millimeters and (inches)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

060506-A

Rev. C | Page 18 of 20

AD8651/AD8652

www.BDTIC.com/ADI

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD8651ARM-REEL –40°C to +125°C 8-Lead MSOP RM-8 BEA
AD8651ARM-R2 –40°C to +125°C 8-Lead MSOP RM-8 BEA
AD8651ARMZ-REEL1 –40°C to +125°C 8-Lead MSOP RM-8 BEA#
AD8651ARMZ-R21 –40°C to +125°C 8-Lead MSOP RM-8 BEA#
AD8651AR –40°C to +125°C 8-Lead SOIC_N R-8
AD8651AR-REEL –40°C to +125°C 8-Lead SOIC_N R-8
AD8651AR-REEL7 –40°C to +125°C 8-Lead SOIC_N R-8
AD8651ARZ1 –40°C to +125°C 8-Lead SOIC_N R-8
AD8651ARZ-REEL1 –40°C to +125°C 8-Lead SOIC_N R-8
AD8651ARZ-REEL71 –40°C to +125°C 8-Lead SOIC_N R-8
AD8652ARMZ-R21 –40°C to +125°C 8-Lead MSOP RM-8 A05
AD8652ARMZ-REEL1 –40°C to +125°C 8-Lead MSOP RM-8 A05
AD8652ARZ1 –40°C to +125°C 8-Lead SOIC_N R-8
AD8652ARZ-REEL1 –40°C to +125°C 8-Lead SOIC_N R-8
AD8652ARZ-REEL71 –40°C to +125°C 8-Lead SOIC_N R-8

1

Z = Pb-free part; # denotes lead-free product may be top or bottom marked.

Rev. C | Page 19 of 20

AD8651/AD8652

www.BDTIC.com/ADI

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03301-0-8/06(C)

Rev. C | Page 20 of 20