Datasheet AD8642 Datasheet (ANALOG DEVICES)

Low Power, Rail-to-Rail Output, Precision

A

A

Data Sheet

FEATURES

Low supply current: 250 μA max
Very low input bias current: 1 pA max
Low offset voltage: 750 μV max
Single-supply operation: 5 V to 26 V
Dual-supply operation: ±2.5 V to ±13 V
Rail-to-rail output
Unity-gain stable
No phase reversal
SC70 package

APPLICATIONS

Line-/battery-powered instruments
Photodiode amplifiers
Precision current sensing
Medical instrumentation
Industrial controls
Precision filters
Portable audio
AT E

GENERAL DESCRIPTION

The AD8641/AD8642/AD8643 are low power, precision JFET
input amplifiers featuring extremely low input bias current and
rail-to-rail output. The ability to swing nearly rail-to-rail at the
input and rail-to-rail at the output enables designers to buffer
CMOS DACs, ASICs, and other wide output swing devices in
single-supply systems. The outputs remain stable with
capacitive loads of more than 500 pF.

The AD8641/AD8642/AD8643 are suitable for applications
utilizing multichannel boards that require low power to manage
heat. Other applications include photodiodes, ATE reference
level drivers, battery management, and industrial controls.

The AD8641/AD8642/AD8643 are fully specified over the
extended industrial temperature range of –40°C to +125°C. The
AD8641 is available in 5-lead SC70 and 8-lead SOIC lead-free
packages. The AD8642 is available in 8-lead MSOP and 8-lead
SOIC lead-free packages. The AD8643 is available in 14-lead
SOIC and 16-lead, 3 mm × 3 mm, LFCSP lead-free packages.

JFET Amplifiers

AD8641/AD8642/AD8643

PIN CONFIGURATIONS

OUT

1

AD8641

VEE

2

TOP VIEW

(Not to Scale)

+IN

3

Figure 1. 5-Lead SC70 (KS-5)

1

NC

AD8641

–IN

2

+IN

3

TOP VIEW

(Not to Scale)

VEE

4

NC = NO CONNECT

Figure 2. 8-Lead SOIC (R-8)

1

OUT

–IN A
+IN A

V–

AD8642

2
3

TOP VIEW

(Not to Scale)

4

Figure 3. 8-Lead SOIC (R-8)

OUT A

1

AD8642

2

–IN A
+IN A

V–

TOP VIEW

3

(Not to Scale)

4

Figure 4. 8-Lead MSOP (RM-8)

1

OUT

2

–IN A

3

+IN A

+IN B
–IN B

OUT B

V+

AD8643

TOP VIEW

4

(Not to Scale)

5
6
7

Figure 5. 14-Lead SOIC (R-14)

NC

161514

1

–IN A

+IN A

V+

+IN B

2
3
4

PIN 1
INDICATOR

AD8643

TOP VIEW

5

OUT A

OUT D

678

NC

13

8
7
6
5

14
13
12
11
10

9
8

5

4

8
7
6
5

8
7
6
5

VCC

–IN

NC
VCC
OUT
NC

V+
OUT B
–IN B
+IN B

V+
OUT B
–IN B
+IN B

OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C

12
11
10

9

05072-101

–IN D
+IN D
V–
+IN C

05072-102

05072-105

05072-064

05072-103

–IN B

–IN C

OUT B

OUT C

NOTES

1. NC = NO CONNECT.

2. EXPOSED PAD SHOULD BE CONNECTED TO V+.

05072-104

Figure 6. 16-Lead LFCSP (CP-16) (Not Drawn to Scale)

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2004–2011 Analog Devices, Inc. All rights reserved.

AD8641/AD8642/AD8643 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Pin Configurations ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics ............................................................. 3

REVISION HISTORY

9/11—Rev. D to Rev. E

Changes to Thermal Resistance Section........................................ 5

7/11—Rev. C to Rev. D

Changes to Figure 6.......................................................................... 1

11/10—Rev. B to Rev. C

Changes to Figure 6.......................................................................... 1

Added Thermal Resistance Section and Table 4 .......................... 5

Updated Outline Dimensions....................................................... 13

Changes to Ordering Guide.......................................................... 15

4/05—Rev. A to Rev. B

Added AD8643 ...................................................................Universal

Added 14-Lead SOIC.........................................................Universal

Added 16-Lead LFCSP.......................................................Universal

Updated Outline Dimensions....................................................... 13

Changes to Ordering Guide.......................................................... 14

Absolute Maximum Ratings ............................................................5

Thermal Resistance.......................................................................5

ESD Caution...................................................................................5

Typical Performance Characteristics..............................................6

Outline Dimensions....................................................................... 13

Ordering Guide .......................................................................... 15

3/05—Rev. 0 to Rev. A

Added AD8642 ...................................................................Universal

Changes to General Description .....................................................1

Added Figure 3 and Figure 4............................................................1

Changes to Specifications.................................................................3

Changes to Absolute Maximum Ratings........................................5

Changes to Figure 22.........................................................................8

Changes to Figure 23.........................................................................9

Changes to Figure 41...................................................................... 12

Updated Outline Dimensions....................................................... 13

Changes to Ordering Guide.......................................................... 14

10/04—Initial Version: Revision 0

Rev. E | Page 2 of 16

Data Sheet AD8641/AD8642/AD8643

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VS = 5.0 V, VCM = 2.5 V, TA = 25°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS 50 750 μV

AD8643 LFCSP only 1 mV
–40°C < TA < +85°C 1.5 mV
+85°C < TA < +125°C, VCM = 1.5 V 1.6 mV

Input Bias Current IB 0.25 1 pA

–40°C < TA < +125°C 180 pA

Input Offset Current IOS 0.5 pA
–40°C < TA < +125°C 60 pA

Input Voltage Range 0 3 V

Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.5 V 74 93 dB

Large Signal Voltage Gain AVO R

Offset Voltage Drift ∆VOS/∆T –40°C < TA < +125°C 2.5 μV/°C
OUTPUT CHARACTERISTICS

Output Voltage High VOH 4.95 V
I

Output Voltage Low VOL 0.05 V

I

Output Current I

±6 mA

OUT

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 5 V to 26 V 90 107 dB

Supply Current/Amplifier ISY 195 250 μA
–40°C < TA < +125°C 270 μA
DYNAMIC PERFORMANCE

Slew Rate SR 2 V/μs

Gain Bandwidth Product GBP AD8641, AD8642 3 MHz

AD8643 2.5 MHz

Phase Margin Ø

m

NOISE PERFORMANCE

Voltage Noise eN p-p f = 0.1 Hz to 10 Hz 4.0 μV p-p

Voltage Noise Density eN f = 1 kHz 28.5 nV/√Hz

Current Noise Density iN f = 1 kHz 0.5 fA/√Hz

= 10 kΩ, VO = 0.5 to 4.5 V 80 140 V/mV

L

= 1 mA, –40°C to +125°C 4.94 V

L

= 1 mA, –40°C to +125°C 0.01 0.05 V

L

50 Degrees

Rev. E | Page 3 of 16

AD8641/AD8642/AD8643 Data Sheet

VS= ±13 V, VCM = 0 V, TA =25°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS 70 750 μV
AD8643 LFCSP only 1 mV

–40° < TA < +125°C 1.5 mV

Input Bias Current IB 0.25 1 pA

–40°C < TA < +125°C 260 pA

Input Offset Current IOS 0.5 pA

–40°C < TA < +125°C 65 pA

Input Voltage Range –13 +10 V
Common-Mode Rejection Ratio CMRR VCM = −13 V to +10 V 90 107 dB
Large Signal Voltage Gain AVO R
Offset Voltage Drift ∆VOS/∆T –40°C < TA < +125°C 2.5 μV/°C

OUTPUT CHARACTERISTICS

Output Voltage High VOH +12.95 V

I

Output Voltage Low VOL –12.95 V

I

Output Current I

±12 mA

OUT

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = ±2.5 V to ±13 V 90 107 dB

Supply Current/Amplifier ISY 200 290 μA
–40°C < TA < +125°C 330 μA
DYNAMIC PERFORMANCE

Slew Rate SR 3 V/μs

Gain Bandwidth Product GBP 3.5 MHz

Phase Margin

Ø

m

NOISE PERFORMANCE

Voltage Noise eN p-p f = 0.1 Hz to 10 Hz 4.2 μV p-p

Voltage Noise Density eN f = 1 kHz 27.5 nV/√Hz

Current Noise Density iN f = 1 kHz 0.5 fA/√Hz

= 10 kΩ, VO = –11 V to +11 V 215 290 V/mV

L

= 1 mA, –40°C to +125°C +12.94 V

L

= 1 mA, –40°C to +125°C –12.94 V

L

60 Degrees

Rev. E | Page 4 of 16

Data Sheet AD8641/AD8642/AD8643

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings apply at 25°C, unless otherwise noted.

Table 3.

Parameter Rating

Supply Voltage 27.3 V
Input Voltage VS− to VS+
Differential Input Voltage ±Supply Voltage
Output Short-Circuit Duration Indefinite
Storage Temperature Range

KS-5, R-8, RM-8, R-14, CP-16 Packages −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range

KS-5, R-8, RM-8, R-14, CP-16 Packages −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. This
was measured using a standard 4-layer board. For the LFCSP
package, solder the exposed pad to a copper plane, which
should be connected to V+.

Table 4.

Package Type θJA θJC Unit

5-Lead SC70 (KS) 430 149 °C/W
8-Lead SOIC (R) 121 43 °C/W
8-Lead MSOP (RM) 142 45 °C/W
14-Lead SOIC (R) 110 36 °C/W
16-Lead LFCSP (CP) 81 16 °C/W

ESD CAUTION

Rev. E | Page 5 of 16

AD8641/AD8642/AD8643 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

20

18

16

14

12

10

8

6

NUMBER OF AMPLIFIERS

4

2

0

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

TCVOS (μV/°C)

Figure 10. Offset Voltage Drift

4.5
VSY = ±13V

4.0
T

= 25°C

A

3.5

3.0

2.5

2.0

1.5

INPUT BIAS (pA)

1.0

0.5

0

–0.5

–15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15

VCM (V)

Figure 11. Input Bias Current vs. V

CM

0.5

VSY = ±13V

0.4

T

= 25°C

A

0.3

0.2

0.1

0

–

0.1

INPUT BIAS (pA)

–

0.2

–

0.3

–

0.4

–

0.5

–15.0 –12.5 –10.0 –7.5 –5.0 –2.5

Figure 12. Input Bias Current vs. V

0 2.5 5.0 7.5 10.0 12.5 15.0

VCM (V)

CM

VSY = 5V

V

CM

8.0

8.5

= 1.5V

9.0

9.5

10.0

05072-005

05072-006

05072-007

FREQUENCY

NUMBER OF AMPLIFIERS

FREQUENCY

80

70

60

50

40

30

20

10

0

16

14

12

10

8

6

4

2

0

70

60

50

40

30

20

10

0

VSY =

±13V

–0.60

–0.55

–0.50

–0.45

0

0.5

1.0

VSY =±2.5V

–0.60

–0.55

–0.50

–0.45

0

0.05

–0.40

–0.35

–0.30

–0.25

–0.20

–0.15

–0.10

–0.05

VOS (mV)

0.10

Figure 7. Input Offset Voltage

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

OFFSET VOLTAGE (μV/°C)

Figure 8. Offset Voltage Drift

0

0.05

–0.40

–0.35

–0.30

–0.25

–0.20

–0.15

–0.10

–0.05

VOS (mV)

0.10

Figure 9. Input Offset Voltage

0.35

0.15

0.20

0.25

0.30

0.40

0.45

0.50

0.55

0.60

05072-002

VSY =

±13V

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

05072-003

0.15

0.20

0.25

0.30

0.40

0.45

0.50

0.55

0.35

0.60

05072-004

Rev. E | Page 6 of 16

Data Sheet AD8641/AD8642/AD8643

1000

VSY =

±13V

100

10

1

INPUT BIAS CURRENT (pA)

0.1
50 750 25 100 125 150

TEMPERATURE (°C)

Figure 13. Input Bias Current vs. Temperature

1.0

VSY =

+5V OR ±5V

–5 –4 –3 –2 –1 0 1 2 3 4 5

V

(V)

CM

Figure 14. Input Bias Current vs. V

CM

INPUT BIAS (pA)

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

1000

VSY =

±13V

0

–15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15

0

VCM (V)

(μV)
V

OS

–100

900
800
700
600
500
400
300
200
100

Figure 15. Input Offset Voltage vs. V

05072-008

05072-009

05072-010

CM

500

VSY =

5V

1.0 1.50 0.5 2.0 2.5
(V)

V

CM

Figure 16. Input Offset Voltage vs. V

CM

(μV)
V

OS

400

300

200

100

0

–100

–200

–300

–400

–500

10M

1M

VSY = ±13V

100k

OPEN-LOOP GAIN (V/V)

10k

0.1 101 100
LOAD RESISTANCE (kΩ)

VSY = ±2.5V

Figure 17. Open-Loop Gain vs. Load Resistance

1000

A
B

C

(V/mV)

VO

A

100

10

D

E

A. VSY = ±13V, VO = ±11V, RL = 10kΩ
B. V

= ±13V, VO = ±11V, RL = 2kΩ

SY

C. V

= +5V, VO = +0.5V/+4.5V, RL = 10kΩ

SY

D. V

= +5V, VO = +0.5V/+4.5V, RL = 2kΩ

SY

E. V

= +5V, VO = +0.5V/+4.5V, RL = 600Ω

SY

1

–50 –30 –10 10 30 50 70 90 110 130 150

TEMPERATURE (°C)

Figure 18. Open-Loop Gain vs. Temperature

05072-011

05072-012

05072-013

Rev. E | Page 7 of 16

AD8641/AD8642/AD8643 Data Sheet

600

VSY =

10kΩ

±13V

100kΩ

1kΩ

–5 0–15 –10 5 10 15

OUTPUT VOLTAGE (V)

OFFSET VOLTAGE (μV)

500
400
300
200
100

0
–100
–200
–300
–400
–500
–600

Figure 19. Input Error Voltage vs. Output Voltage for Resistive Loads

250
200
150
100

50

0

–50
–100
–150

INPUT VOLTAGE (μV)

–200
–250
–300
–350

0 50 100 150 200 250 300 350

OUTPUT VOLTAGE FROM SUPPLY RAIL (mV)

VSY =±5V

RL = 1kΩ
R

= 2kΩ

L

R

R

= 2kΩ

R

L

= 10kΩ

L

= 10kΩ

L

R

= 100kΩ

L

R

= 100kΩ

L

R

= 1kΩ

L

POS RAIL

NEG RAIL

Figure 20. Input Error Voltage vs. Output Voltage

Within 300 mV of Supply Rails

800

700

600

500

400

(μA)

SY

I

300

200

100

0

4 8 12 16 20 24 28

+25°C

+125°C

–55°C

V

(V)

SY

Figure 21. Quiescent Current vs. Supply Voltage at Different Temperatures

05072-014

05072-015

05072-016

10000

VSY =±13V

VSY– V

1000

100

10

SATURATION VOLTAGE (mV)

1

0.001 0.01 0.1 1 10 100
LOAD CURRENT (mA)

OH

–

VSY– V

OL

Figure 22. Output Saturation Voltage vs. Load Current

10000

VSY =5V

1000

100

10

SATURATION VOLTAGE (mV)

1

0.001 0.01 0.1 1 10 100
LOAD CURRENT (mA)

VSY–V

OH

V

OL

Figure 23. Output Saturation Voltage vs. Load Current

70

60

50

40

30

20

GAIN (dB)

10

0

–10

–20

–30 –135

10k 100k 1M 10M

GAIN

FREQUENCY (Hz )

V

=±13V

SY

R

= 2k

L

CL = 40pF

PHASE

Ω

Figure 24. Open-Loop Gain and Phase Margin vs. Frequency

315

270

225

180

135

90

45

0

–45

–90

05072-017

05072-018

PHASE (Degrees)

05072-019

Rev. E | Page 8 of 16

Data Sheet AD8641/AD8642/AD8643

70

60

50

40

30

20

GAIN (dB)

10

0

–10

–20

–30 –135

10k 100k 1M 10M

GAIN

FREQUENCY (Hz)

VSY = 5V
R

= 2k

L

CL = 40pF

PHASE

Ω

Figure 25. Open-Loop Gain and Phase Margin vs. Frequency

70

VSY =±13V

60

R

= 2k

Ω

L

CL = 40pF

50

40

G = +100

30

20

GAIN (dB)

G = +10

10

0

G = +1

–10

–20

–30

1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 26. Closed-Loop Gain vs. Frequency

70

VSY = 5V

60

R

= 2k

Ω

L

CL = 40pF

50

40

G = +100

30

20

GAIN (dB)

G = +10

10

0

G = +1

–10

–20

–30

1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 27. Closed-Loop Gain vs. Frequency

315

270

225

180

135

90

45

0

–45

–90

PHASE (Degrees)

05072-020

05072-021

05072-022

140

VSY =±13V

120

100

80

60

40

CMRR (dB)

20

0

–20

–40

–60

1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 28. CMRR vs. Frequency

140

VSY=5V

120

100

80

60

40

CMRR (dB)

20

0

–20

–40

–60

1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 29. CMRR vs. Frequency

140

=±13V

V

SY

120

100

80

60

40

PSRR (dB)

20

0

–20

–40

–60

1k 10k 100k 1M 10M

+PSRR

–PSRR

FREQUENCY (Hz)

Figure 30. PSRR vs. Frequency

05072-023

05072-024

05072-025

Rev. E | Page 9 of 16

AD8641/AD8642/AD8643 Data Sheet

140

VSY=5V

120

100

80

60

40

PSRR (dB)

20

0

–20

–40

–60

1k 10k 100k 1M 10M

+PSRR

–PSRR

FREQUENCY (Hz)

Figure 31. PSRR vs. Frequency

1000

VSY =±13V

G = +100

G = +1

(Ω)

Z

OUT

100

10

G = +10

1

0.1

05072-026

1.0

0.8

0.6

1

0.4

0.2

0

–0.2

INPUT BIAS (pA)

–0.4

2

–0.6

–0.8

–1.0

CH1 10.0V CH2 10.0V M400μs A CH1 1.00V

–5 –4 –3 –2 –1 0 1 2 3 4 5

T

T 0.00000s

V

(V)

CM

Figure 34. No Phase Reversal

15

VS = ±13V
GAIN = +5

10

5

0

–5

OUTPUT SWING (V)

–10

TS + (1%)

TS + (0.1%)

TS – (0.1%)

TS – (1%)

VSY =

V

IN

V

OUT

±

13V

05072-029

05072-009

0.01
1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 32. Output Impedance vs. Frequency

1000

VSY =5V

100

10

)

Ω

(

OUT

Z

1

0.1

0.01
1k 10k 100k 1M 10M 100M

G = +100

G = +10

G = +1

FREQUENCY (Hz)

Figure 33. Output Impedance vs. Frequency

05072-027

05072-028

–15

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

SETTLING TIME (μs)

Figure 35. Output Swing and Error vs. Settling Time

70

VS =±13V
R

= 10k

Ω

L

60

VIN = 100mV p-p
A

= +1

V

50

40

30

OVERSHOOT (%)

20

10

0

1 10010 1000

CAPACITANCE (pF)

OS–

Figure 36. Small Signal Overshoot vs. Load Capacitance

OS+

05072-030

05072-031

Rev. E | Page 10 of 16

Data Sheet AD8641/AD8642/AD8643

OVERSHOOT (%)

70

VS =±2.5V
R

L

60

VIN = 100mV p-p
A

V

50

40

30

20

= 10k
= +1

Ω

OS–

OS+

100

1k

VSY =

±13V

10

10

0

1 10010 1000

CAPACITANCE (pF)

Figure 37. Small Signal Overshoot vs. Load Capacitance

1.0

0.8

0.6

0.4

0.2

1

0

–0.2

INPUT BIAS (pA)

–0.4

–0.6

–0.8

–1.0

CH1 1.00V M1.00s A CH1 –20.0V

–5 –4 –3 –2 –1 0 1 2 3 4 5

V

(V)

CM

CH1 p-p = 4.26V

Figure 38. 0.1 Hz to 10 Hz Noise

1.0

0.8

0.6

0.4

0.2

1

0

–0.2

INPUT BIAS (pA)

–0.4

–0.6

–0.8

–1.0

CH1 1.00V M1.00s A CH1 –20.0V

–5 –4 –3 –2 –1 0 1 2 3 4 5

CH1 p-p = 4.06V

Figure 39. 0.1 Hz to 10 Hz Noise

VS = ±13V

G = +1M

VS = ±2.5V

G = +1M

05072-033

05072-034

05072-032

05072-009

5072-009

VOLTAGE NOISE DENSITY (nV/ Hz)

1

10 1k100 10k

FREQUENCY (Hz)

Figure 40. Voltage Noise Density

1k

VSY =

5V

100

10

VOLTAGE NOISE DENSITY (nV/ Hz)

1

10 1k100 10k

FREQUENCY (Hz)

Figure 41. Voltage Noise Density

0.004

V

= ±13V

0.001

0.0001

THD + NOISE (%)

0.00001

0.000001

SY

LOAD = 100kΩ
GAIN = +1

4V p-p INPUT

8V p-p INPUT

1V p-p INPUT

2V p-p INPUT

1k10012

FREQUENCY (Hz)

Figure 42. Total Harmonic Distortion + Noise vs. Frequency

05072-035

05072-036

0k

10k

05072-037

Rev. E | Page 11 of 16

AD8641/AD8642/AD8643 Data Sheet

–40
–50
–60
–70
–80
–90

–100

(dB)

–110
–120
–130
–140
–150
–160

20 100 1k 10k 100k

–
+

V

IN

VIN = 4.5V p-p

= 9V p-p

V

IN

2kΩ

20kΩ

–
+

2kΩ

FREQUENCY (Hz)

2kΩ

VIN = 18V p-p

05072-041

Figure 43. Channel Separation

Rev. E | Page 12 of 16

Data Sheet AD8641/AD8642/AD8643

OUTLINE DIMENSIONS

2.20

2.00

1.80

2.40

0.30

0.15

45

312

0.65 BSC

2.10

1.80

1.10

0.80

SEATING
PLANE

0.40

0.10

0.22

0.08

0.46

0.36

0.26

1.35

1.25

1.15

1.00

0.90

0.70

0.10 MAX

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-203-AA

072809-A

Figure 44. 5-Lead Thin Shrink Small Outline Transistor Package [SC70]

(KS-5)

Dimensions shown in millimeters

5.00(0.1968)

4.80(0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES)ARE ROUNDED-OFF MILLIMETER EQUIVALENTSFOR
REFERENCE ONLYAND ARE NOTAPPROPRIATE FOR USE IN DESIGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDSMS-012-AA

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

Figure 45. 8-Lead Standard Small Outline Package [SOIC_N]

(R-8)

Dimensions shown in millimeters and (inches)

Rev. E | Page 13 of 16

AD8641/AD8642/AD8643 Data Sheet

3.20

3.00

2.80

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

0.10

3.20

3.00

2.80

8

5

5.15

4.90

4

0.40

0.25

4.65

1.10 MAX

15° MAX

6°
0°

0.23

0.09

1

0.65 BSC

COMPLIANT TO JEDEC STANDARDS MO-187-AA

0.80

0.55

0.40

10-07-2009-B

Figure 46. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

8.75 (0.3445)

8.55 (0.3366)

4.00 (0.1575)

3.80 (0.1496)

14

1

8

7

6.20 (0.2441)

5.80 (0.2283)

0.25 (0.0098)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIMENSIONSARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-O FF MILLIMETER E QUIVALENTS FOR
REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

1.27 (0.0500)
BSC

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-012-AB

1.75 (0.0689)

1.35 (0.0531)

SEATING
PLANE

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0197)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

45°

060606-A

Figure 47. 14-Lead Standard Small Outline Package [SOIC_N]

(R-14)

Dimensions shown in millimeters and (inches)

0.50

PIN 1

INDICATOR

0.90

0.85

0.80

SEATING

PLANE

0.45

0.50

BSC

1.50 REF

0.60 MAX

BOTTOM VIEW

13

12

9
8

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

12° MAX

3.00

BSC SQ

TOP

VIEW

0.30

0.23

0.18

2.75

BSC SQ

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

*

COMPLIANT

EXCEPT FOR EXPOSED PAD DIMENSION.

TO

JEDEC STANDARDS MO-220-VEED-2

Figure 48. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

3 mm × 3 mm Body, Very Thin Quad (CP-16-3)

Dimensions shown in millimeters

EXPOSED

PAD

0.40

0.30

16

1

4

5

N

I

P

N

I

D

*

1.65

1.50 SQ

1.35

0.25 MIN

1

R

O

C

I

A

T

07-17-2008-A

Rev. E | Page 14 of 16

Data Sheet AD8641/AD8642/AD8643

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option Branding

AD8641AKSZ-R2 −40°C to +125°C 5-Lead SC70 KS-5 A07
AD8641AKSZ-REEL7 −40°C to +125°C 5-Lead SC70 KS-5 A07
AD8641AKSZ-REEL −40°C to +125°C 5-Lead SC70 KS-5 A07
AD8641ARZ −40°C to +125°C 8-lead SOIC_N R-8
AD8641ARZ-REEL7 −40°C to +125°C 8-lead SOIC_N R-8
AD8641ARZ-REEL −40°C to +125°C 8-lead SOIC_N R-8
AD8642ARMZ −40°C to +125°C 8-lead MSOP RM-8 A0A
AD8642ARMZ-REEL −40°C to +125°C 8-lead MSOP RM-8 A0A
AD8642ARZ −40°C to +125°C 8-lead SOIC_N R-8
AD8642ARZ-REEL7 −40°C to +125°C 8-lead SOIC_N R-8
AD8642ARZ-REEL −40°C to +125°C 8-lead SOIC_N R-8
AD8643ARZ −40°C to +125°C 14-lead SOIC_N R-14
AD8643ARZ-REEL7 −40°C to +125°C 14-lead SOIC_N R-14
AD8643ARZ-REEL −40°C to +125°C 14-lead SOIC_N R-14
AD8643ACPZ-R2 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 AUA
AD8643ACPZ-REEL7 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 AUA
AD8643ACPZ-REEL −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 AUA

1

Z = RoHS Compliant Part.

Rev. E | Page 15 of 16

AD8641/AD8642/AD8643 Data Sheet

NOTES

©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05072-0-9/11(E)

Rev. E | Page 16 of 16