Datasheet AD8632, AD8631 Datasheet (Analog Devices)

1.8 V, 5 MHz Rail-to-Rail

1

2

3

5

4

–IN A+IN A

V+

OUT A

AD8631

V–

OUT A

–IN A

+IN A

V–

V+

OUT B

–IN B

+IN B

AD8632

18

27

36

45

–IN A
+IN A

V–

OUT B
–IN B
+IN B

V+

1

4

5

8

AD8632

OUT A

a

Low Power Operational Amplifiers

FEATURES
Single Supply Operation: 1.8 V to 6 V
Space-Saving SOT-23, ␮SOIC Packaging
Wide Bandwidth: 5 MHz @ 5 V, 4 MHz @ 1.8 V
Low Offset Voltage: 4 mV Max, 0.8 mV typ
Rail-to-Rail Input and Output Swing
2 V/␮s Slew Rate @ 1.8 V
Only 225 ␮A Supply Current @ 1.8 V

APPLICATIONS

Portable Communications
Portable Phones
Sensor Interface
Active Filters
PCMCIA Cards
ASIC Input Drivers
Wearable Computers
Battery-Powered Devices
New Generation Phones
Personal Digital Assistants

GENERAL DESCRIPTION

The AD8631 brings precision and bandwidth to the SOT-23-5
package at single supply voltages as low as 1.8 V and low supply
current. The small package makes it possible to place the AD8631
next to sensors, reducing external noise pickup.

The AD8631 and AD8632 are rail-to-rail input and output bipolar
amplifiers with a gain bandwidth of 4 MHz and typical voltage
offset of 0.8 mV from a 1.8 V supply. The low supply current and
the low supply voltage makes these parts ideal for battery-powered
applications. The 3 V/µs slew rate makes the AD8631/AD8632 a
good match for driving ASIC inputs, such as voice codecs.

The AD8631/AD8632 is specified over the extended industrial
(–40ⴗC to +125ⴗC) temperature range. The AD8631 single is
available in 5-lead SOT-23 surface-mount packages. The dual
AD8632 is available in 8-lead SOIC and µSOIC packages.

AD8631/AD8632

PIN CONFIGURATIONS

5-Lead SOT-23

(RT Suffix)

8-Lead SOIC

(R Suffix)

8-Lead ␮SOIC

(RM Suffix)

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD8631/AD8632–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(VS = 5 V, V– = 0 V, VCM = 2.5 V, TA = 25ⴗC unless otherwise noted)

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V

OS

–40ⴗC ≤ T

Input Bias Current I

B

–40ⴗC ≤ T

Input Offset Current I

OS

–40ⴗC ≤ T

Input Voltage Range V

CM

Common-Mode Rejection Ratio CMRR 0 V ≤ V

–40ⴗC ≤ T

Large Signal Voltage Gain A

Offset Voltage Drift ∆V

VO

/∆T 3.5 µV/ⴗC

OS

RL = 10 kΩ, 0.5 V < V

= 100 kΩ, 0.5 V < V

R

L

R

= 100 kΩ, –40ⴗC ≤ TA ≤ +125ⴗC 100 V/mV

L

≤ +125ⴗC6mV

A

≤ +125ⴗC 500 nA

A

≤ +125ⴗC 550 nA

A

05V

≤ 5 V, 63 70 dB

CM

≤ +125ⴗC56 dB

A

< 4.5 V 25 V/mV

OUT

< 4.5 V 100 400 V/mV

OUT

0.8 4.0 mV

250 nA

±150 nA

Bias Current Drift ∆IB/∆T 400 pA/ⴗC

OUTPUT CHARACTERISTICS

Output Voltage Swing High V

Output Voltage Swing Low V

Short Circuit Current I

OH

OL

SC

IL = 100 µA
–40ⴗC ≤ T
I

= 1 mA 4.7 V

L

≤ +125ⴗC 4.965 V

A

IL = 100 µA
–40ⴗC ≤ T
I

= 1 mA 200 mV

L

≤ +125ⴗC35mV

A

Short to Ground, Instantaneous ±10 mA

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 2.2 V to 6 V, 75 90 dB

Supply Current/Amplifier I

SY

–40ⴗC ≤ T
V

OUT

≤ +125ⴗC72 dB

A

= 2.5 V 300 450 µA

–40ⴗC ≤ TA ≤ +125ⴗC 650 µA

DYNAMIC PERFORMANCE

Slew Rate SR 1 V < V

< 4 V, RL = 10 kΩ 3V/µs

OUT

Gain Bandwidth Product GBP 5 MHz
Settling Time T
Phase Margin φ

S

m

0.1% 860 ns
53 Degrees

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 0.8 µV p-p
Voltage Noise Density e
Current Noise Density i

Specifications subject to change without notice.

n

n

f = 1 kHz 23 nV/√Hz
f = 1 kHz 1.7 pA/√Hz

–2–

REV. 0

AD8631/AD8632

ELECTRICAL CHARACTERISTICS

(VS = 2.2 V, V– = 0 V, VCM = 1.1 V, TA = 25ⴗC unless otherwise noted)

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V

OS

–40ⴗC ≤ T

Input Bias Current I
Input Offset Current I
Input Voltage Range V

B

OS

CM

Common-Mode Rejection Ratio CMRR 0 V ≤ V

–40ⴗC ≤ T

Large Signal Voltage Gain A

VO

RL = 10 kΩ, 0.5 V < V

≤ +125ⴗC6mV

A

0 2.2 V

≤ 2.2 V, 54 70 dB

CM

≤ +125ⴗC47 dB

A

< 1.7 V 25 V/mV

OUT

0.8 4.0 mV

250 nA
±150 nA

RL = 100 kΩ 50 200 V/mV

OUTPUT CHARACTERISTICS

Output Voltage Swing High V

Output Voltage Swing Low V

OH

OL

IL = 100 µA 2.165 V
I

= 750 µA 1.9 V

L

IL = 100 µA35mV
IL = 750 µA 200 mV

POWER SUPPLY

Supply Current/Amplifier I

SY

V

= 1.1 V 250 350 µA

OUT

–40ⴗC ≤ TA ≤ +125ⴗC 500 µA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 10 kΩ 2.5 V/µs
Gain Bandwidth Product GBP 4.3 MHz
Phase Margin φ

m

50 Degrees

NOISE PERFORMANCE

Voltage Noise Density e
Current Noise Density i

Specifications subject to change without notice.

n

n

f = 1 kHz 23 nV/√Hz
f = 1 kHz 1.7 pA/√Hz

–3–REV. 0

AD8631/AD8632–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(VS = 1.8 V, V– = 0 V, VCM = 0.9 V, TA = 25ⴗC unless otherwise noted)

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V

OS

0ⴗC ≤ T

Input Bias Current I
Input Offset Current I
Input Voltage Range V

B

OS

CM

Common-Mode Rejection Ratio CMRR 0 V ≤ V

0ⴗC ≤ T

Large Signal Voltage Gain A

VO

RL = 10 kΩ, 0.5 V < V
RL = 100 kΩ, 0.5 V < V

≤ 125ⴗC6mV

A

0 1.8 V

≤ 1.8 V,

CM

≤ 125ⴗC4965dB

A

< 1.3 V 20 V/mV

OUT

< 1.3 V 40 200 V/mV

OUT

0.8 4.0 mV

250 nA
±150 nA

OUTPUT CHARACTERISTICS

Output Voltage Swing High V

Output Voltage Swing Low V

OH

OL

IL = 100 µA 1.765 V
I

= 750 µA 1.5 V

L

IL = 100 µA35mV
IL = 750 µA 200 mV

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 1.7 V to 2.2 V, 68 86 dB

Supply Current/Amplifier I

SY

0ⴗC ≤ T
V

≤ 125ⴗC65 dB

A

= 0.9 V 225 325 µA

OUT

0ⴗC ≤ TA ≤ 125ⴗC 450 µA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 10 kΩ 2V/µs
Gain Bandwidth Product GBP 4 MHz
Phase Margin φ

m

49 Degrees

NOISE PERFORMANCE

Voltage Noise Density e
Current Noise Density i

Specifications subject to change without notice.

n

n

f = 1 kHz 23 nV/√Hz
f = 1 kHz 1.7 pA/√Hz

–4–

REV. 0

AD8631/AD8632

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V

Input Voltage

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V

1

S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ±0.6 V

Internal Power Dissipation

SOT-23 (RT) . . . . . . . . . . . . See Thermal Resistance Chart

SOIC (R) . . . . . . . . . . . . . . . See Thermal Resistance Chart

µSOIC (RM) . . . . . . . . . . . . See Thermal Resistance Chart

Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite

Storage Temperature Range

R, RM, and RT Packages . . . . . . . . . . . . . –65ⴗC to +150ⴗC

Operating Temperature Range

AD8631, AD8632 . . . . . . . . . . . . . . . . . . –40ⴗC to +125ⴗC

Junction Temperature Range

R, RM, and RT Packages . . . . . . . . . . . . . –65ⴗC to +150ⴗC

Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300ⴗC

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

2

For supply voltages less than 6 V the input voltage is limited to the supply voltage.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option Brand

1

AD8631ART

–40ⴗC to +125ⴗC 5-Lead SOT-23 RT-5 AEA

AD8632AR –40ⴗC to +125ⴗC 8-Lead SOIC SO-8
AD8632ARM2–40ⴗC to +125ⴗC 8-Lead µSOIC RM-8 AGA

NOTES

1

Available in 3,000-piece reels only.

2

Available in 2,500-piece reels only.

Package Type ␪

1

JA

␪

JC

Unit

5-Lead SOT-23 (RT) 230 146 ⴗC/W
8-Lead SOIC (R) 158 43 ⴗC/W
8-Lead µSOIC (RM) 210 45 ⴗC/W

NOTE

1

θJA is specified for worst-case conditions, i.e., θ

in circuit board for SOT-23 and SOIC packages.

is specified for device soldered

JA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8631/AD8632 features proprietary ESD protection circuitry, permanent dam­age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

120

VS = 5V

= 2.5V

V

CM

= 25ⴗC

T

A

COUNT = 1,133 OP AMPS

90

60

QUANTITY OF AMPLIFIERS

30

0

–3 –2 –101234

–4

INPUT OFFSET VOLTAGE – mV

Figure 1. Input Offset Voltage Distribution

Figure 2. Supply Current per Amplifier vs. Supply Voltage

350

TA = 25ⴗC

325

300

275

250

SUPPLY CURRENT – ␮A

225

200

1

2

SUPPLY VOLTAGE – V

345

6

–5–REV. 0

AD8631/AD8632

g

– Typical Characteristics

500

VS = 5V

450

400

350

300

SUPPLY CURRENT – ␮A

250

200

ⴚ50

075

ⴚ25

25 50 100

TEMPERATURE – ⴗC

125

Figure 3. Supply Current per Amplifier vs. Temperature

150

VS = ⴞ2.5V

= 25ⴗC

T

A

100

50

0

INPUT BIAS CURRENT – nA

ⴚ100

ⴚ150

ⴚ50

ⴚ3

ⴚ2

ⴚ1

COMMON-MODE VOLTAGE – V

0

12

3

Figure 4. Input Bias Current vs. Common-Mode Voltage

40

30

20

10

0

ⴚ10

OPEN-LOOP GAIN – dB

ⴚ20

ⴚ30

ⴚ40

100k 100M1M

50

40

30

20

10

0

ⴚ10

CLOSED-LOOP GAIN – dB

ⴚ20

ⴚ30

ⴚ40

VS = 5V

= 25ⴗC

T

GAIN

10M

FREQUENCY – Hz

A

PHASE

Figure 6. Open-Loop Gain vs. Frequency

VS = ±2.5V

= 25ⴗC

T

A

10 100M1k

100 10k 100k 10M

FREQUENCY – Hz

1M

Figure 7. Closed-Loop Gain vs. Frequency

90

45

0

ⴚ45

ⴚ90

rees

PHASE SHIFT – De

140

TA = 25ⴗC

120

100

80

60

40

OUTPUT VOLTAGE – mV

20

0

10 10k100

SOURCE

1k

LOAD CURRENT – ␮A

Figure 5. Output Voltage to Supply Rail vs. Load Current

–6–

0

VS = ⴞ2.5V

= 25ⴗC

T

A

20

40

CMRR – dB

60

80

100

10 1k

100 10k 100k 10M

FREQUENCY – Hz

1M

Figure 8. CMRR vs. Frequency

REV. 0

0

FREQUENCY – Hz

10

100M1k

OUTPUT IMPEDANCE – ⍀

1M

0

60

40

100 10k 100k 10M

VS = 5V
T

A

= 25ⴗC

10

20

30

50

AV = +10

AV = +1

20

40

VS = ⴞ2.5V

= 25ⴗC

T

A

AD8631/AD8632

ⴚPSRR

60

PSRR – dB

80

100

120

10 1k

100 10k 100k 10M

FREQUENCY – Hz

ⴙPSRR

1M

Figure 9. PSRR vs. Frequency

60

VS = 5V

= 2.5V

V

CM

R

= 10k⍀

50

L

= 25ⴗC

T

A

= ⴞ50mV

V

IN

= +1

A

40

V

30

OVERSHOOT – %

20

10

0

10

CAPACITANCE – pF

ⴚOS

+OS

Figure 10. Overshoot vs. Capacitance Load

100

Figure 12. Output Impedance vs. Frequency

50

VS =5V
T

= 25ⴗC

40

30

20

10

VOLTAGE NOISE DENSITY – pA/ Hz

0

10 10k100

FREQUENCY – Hz

1k

A

Figure 13. Voltage Noise Density vs. Frequency

6

DISTORTION 3%

5

4

3

2

MAXIMUM OUTPUT SWING – V p-p

1

0

10k

100k

FREQUENCY – Hz

VS = 5V

= +1

A

V

= 10k⍀

R

L

= 25ⴗC

T

A

= 15pF

C

L

1M

Figure 11. Output Swing vs. Frequency

–7–REV. 0

5

4

3

2

1

CURRENT NOISE DENSITY – pA/ Hz

0

10 10k100

FREQUENCY – Hz

VS = 5V

= 25ⴗC

T

A

1k

Figure 14. Current Noise Density vs. Frequency

AD8631/AD8632

0

0

0

0

0

0

VOLTAGE – 200nV/DIV

0

0

0

TIME – 1s/DIV

Figure 15. 0.1 Hz to 10 Hz Noise

0

0

0

0

VS = ⴞ2.5V

= 1

A

V

= SINE WAVE

V

IN

= 25ⴗC

T

A

= ⴞ2.5V

V

S

TA = 25ⴗC

0

VS = ⴞ2.5V

= +1

A

V

= 25ⴗC

T

A

= 33pF

C

L

0

= 10k⍀

R

L

0

0

0

VOLTAGE – 20mV/DIV

0

0

0

TIME – 250ns/DIV

Figure 17. Small Signal Transient Response

0

VS = ⴞ2.5V

= +1

A

V

T

= 25ⴗC

A

= 100pF

C

L

0

= 10k⍀

R

L

0

0

0

VOLTAGE – 1V/DIV

0

0

0

TIME – 200␮s/DIV

Figure 16. No Phase Reversal

THEORY OF OPERATION

The AD863x is a rail-to-rail operational amplifier that can operate
at supply voltages as low as 1.8 V. This family is fabricated using
Analog Devices’ high-speed complementary bipolar process, also
called XFCB. The process trench isolates each transistor to mini­mize parasitic capacitance, thereby allowing high-speed perfor­mance. Figure 19 shows a simplified schematic of the AD863x
family.

The input stage consists of two parallel complementary differen­tial pair: one NPN pair (Q1 and Q2) and one PNP pair (Q3 and
Q4). The voltage drops across R7, R8, R9, and R10 are kept low
for rail-to-rail operation. The major gain stage of the op amp is a
double-folded cascode consisting of transistors Q5, Q6, Q8, and
Q9. The output stage, which also operates rail-to-rail, is driven by
Q14. The transistors Q13 and Q10 act as level-shifters to give
more headroom during 1.8 V operation.

As the voltage at the base of Q13 increases, Q18 starts to sink
current. When the voltage at the base of Q13 decreases I8 flows
through D16 and Q15 increasing the VBE of Q17, then Q20
sources current.

The output stage also furnishes gain, which depends on the load
resistance, since the output transistors are in common emitter

0

VOLTAGE – 500mV/DIV

0

0

0

TIME – 500ns/DIV

Figure 18. Large Signal Transient Response

configuration. The output swing when sinking or sourcing 100 µA
is 35 mV maximum from each rail.

The input bias current characteristics depend on the common­mode voltage (see Figure 4). As the input voltage reaches about
1 V below V

, the PNP pair (Q3 and Q4) turns off.

CC

The 1 kΩ input resistor R1 and R2, together with the diodes D7
and D8, protect the input pairs against avalanche damage.

The AD863x family exhibits no phase reversal as the input signal
exceeds the supply by more than 0.6 V. Excessive current can flow
through the input pins via the ESD diodes D1-D2 or D3-D4, in the
event their ~0.6 V thresholds are exceeded. Such fault currents must
be limited to 5 mA or less by the use of external series resistance(s).

LOW VOLTAGE OPERATION
Battery Voltage Discharge

The AD8631 operates at supply voltages as low as 1.8 V. This
amplifier is ideal for battery-powered applications since it can
operate at the end of discharge voltage of most popular batteries.
Table I lists the Nominal and End-of-Discharge Voltages of
several typical batteries.

–8–

REV. 0

AD8631/AD8632

NONINVERTING CONFIGURATION

AD8631

R

S

V

I

V

OUT

RF = R

S

UNITY GAIN BUFFER

V

OUT

R

F

R

I

RB = R

I

ⱍⱍ

R

F

V

I

V

OUT

RB = R

I

ⱍⱍ

R

F

V

I

R

F

R

I

AD8631

INVERTING CONFIGURATION

AD8631

V

CC

R7 R8

D1

ESD

ⴚIN

R1

D2 ESD

I1

Q2 Q4

Q1Q3

D7

R5 R6

D8

I2

ⴙIN

Q5

I3

Q10

C1

Q8

V

EE

D3

ESD

R4R3

R2

D4

ESD

R10R9

Q6

Q11

Q9

I4

Figure 19. Simplified Schematic

Table I. Typical Battery Life Voltage Range

Nominal End-of-Voltage

Battery Voltage (V) Discharge (V)

Lead-Acid 2 1.8
Lithium 2.6–3.6 1.7–2.4
NiMH 1.2 1
NiCd 1.2 1
Carbon-Zinc 1.5 1.1

RAIL-TO-RAIL INPUT AND OUTPUT

The AD8631 features an extraordinary rail-to-rail input and
output with supply voltages as low as 1.8 V. With the amplifier’s
supply set to 1.8 V, the input can be set to 1.8 V p-p, allowing the
output to swing to both rails without clipping. Figure 20 shows a
scope picture of both input and output taken at unity gain, with a
frequency of 1 kHz, at V

= 1.8 V and VIN = 1.8 V p-p.

S

V

CC

R14

C3

R12

Q19 Q20

C4

Q17

D16

R13

Q18

D9

V

OUT

D6

V

EE

Q7

I7

Q13

I5

I6

I8

Q14

C2

R11

Q15

The rail-to-rail feature of the AD8631 can be observed over the
supply voltage range, 1.8 V to 5 V. Traces are shown offset for
clarity.

INPUT BIAS CONSIDERATION

The input bias current (IB) is a non-ideal, real-life parameter that
affects all op amps. I
voltage. This offset voltage is created by I
the negative feedback resistor R

is 100 kΩ, the corresponding generated offset voltage is 25 mV

R

F

(V

= IB  RF).

OS

Obviously the lower the R
Using a compensation resistor, R

can generate a somewhat significant offset

B

. If IB is 250 nA (worst case), and

F

the lower the generated voltage offset.

F

, as shown in Figure 21, can

B

when flowing through

B

minimize this effect. With the input bias current minimized we
still need to be aware of the input offset current (I

) which will

OS

generate a slight offset error. Figure 21 shows three different
configurations to minimize I

-induced offset errors.

B

VS = 1.8V

= 1.8V p-p

V

IN

V

IN

V

OUT

Figure 20. Rail-to-Rail Input Output

TIME – 200␮s/Div

Figure 21. Input Bias Cancellation Circuits

–9–REV. 0

AD8631/AD8632

DRIVING CAPACITIVE LOADS
Capacitive Load vs. Gain

Most amplifiers have difficulty driving capacitance due to degra­dation of phase margin caused by additional phase lag from the
capacitive load. Higher capacitance at the output can increase the
amount of overshoot and ringing in the amplifier’s step response
and could even affect the stability of the device. The value of
capacitive load that an amplifier can drive before oscillation varies
with gain, supply voltage, input signal, temperature, among oth­ers. Unity gain is the most challenging configuration for driving
capacitive load. However, the AD8631 offers reasonably good
capacitive driving ability. Figure 22 shows the AD8631’s ability to
drive capacitive loads at different gains before instability occurs.
This graph is good for all V

1M

100k

10k

1k

CAPACITIVE LOAD – pF

100

10

.

SY

UNSTABLE

STABLE

468

GAIN – V/V

102

93571

Figure 22. Capacitive Load vs. Gain

In-the-Loop Compensation Technique for Driving
Capacitive Loads

When driving capacitance in low gain configuration, the in-the-loop
compensation technique is recommended to avoid oscillation as is
illustrated in Figure 23.

R

R

F

V

IN

G

C

F

90kHz INPUT SIGNAL
A

= 1

V

C = 600pF

VOLTAGE – 200mV/DIV

TIME – 2␮s/DIV

Figure 24. Driving Capacitive Loads without Compensation

By connecting a series R–C from the output of the device to
ground, known as the “snubber” network, this ringing and over­shoot can be significantly reduced. Figure 25 shows the network
setup, and Figure 26 shows the improvement of the output
response with the “snubber” network added.

5V

AD8631

V

IN

R

X

C

X

V

OUT

C

L

Figure 25. Snubber Network Compensation for Capacitive
Loads

90kHz INPUT SIGNAL
A

= 1

V

C = 600pF

R

RX =

[

RF + R

R

X

G

F

AD8631

RO R

G

WHERE RO = OPEN-LOOP OUTPUT RESISTANCE

R

F

CF =1 +

1

[

A

CL

CLR

V

OUT

C

L

O

Figure 23. In-the-Loop Compensation Technique for
Driving Capacitive Loads

Snubber Network Compensation for Driving Capacitive Loads

As load capacitance increases, the overshoot and settling time
will increase and the unity gain bandwidth of the device will
decrease. Figure 24 shows an example of the AD8631 in a non­inverting configuration driving a 10 kΩ resistor and a 600 pF
capacitor placed in parallel, with a square wave input set to a
frequency of 90 kHz and unity gain.

–10–

VOLTAGE – 200mV/DIV

TIME – 2␮s/DIV

Figure 26. Photo of a Square Wave with the Snubber
Network Compensation

The network operates in parallel with the load capacitor, CL,
and provides compensation for the added phase lag. The actual
values of the network resistor and capacitor have to be empirically
determined. Table II shows some values of snubber network for
large capacitance load.

REV. 0

AD8631/AD8632

Table II. Snubber Network Values for Large Capacitive Loads

C

LOAD

Rx Cx

600 pF 300 Ω 1 nF
1 nF 300 Ω 1 nF
10 nF 90 Ω 8

nF

TOTAL HARMONIC DISTORTION + NOISE

The AD863x family offers a low total harmonic distortion, which
makes this amplifier ideal for audio applications. Figure 27 shows
a graph of THD + N, which is ~0.02% @ 1 kHz, for a 1.8 V supply.
At unity gain in an inverting configuration the value of the Total
Harmonic Distortion + Noise stays consistently low over all volt­ages supply ranges.

10

INVERTING
A

= 1

V

1

0.1

THD + N – %

0.01

0.001
10 20k

VS = 1.8V

VS = 5V

100 1k 10k

FREQUENCY – Hz

Figure 27. THD + N vs. Frequency Graph

AD8632 Turn-On Time

The low voltage, low power AD8632 features an extraordinary turn
on time. This is about 500 ns for V

= 5 V, which is impressive

SY

considering the low supply current (300 µA typical per amplifier).
Figure 28 shows a scope picture of the AD8632 with both channels
configured as followers. Channel A has an input signal of 2.5 V and
channel B has the input signal at ground. The top waveform shows
the supply voltage and the bottom waveform reflects the response
of the amplifier at the output of Channel A.

0

VS = 5V

= 1

A

0

0

0V

0

0

VOLTAGE – 1V/DIV

0V

0

0

TIME – 200ns/DIV

V

V

= 2.5V STEP

IN

Figure 28. AD8632 Turn-On Time

A MICROPOWER REFERENCE VOLTAGE GENERATOR

Many single-supply circuits are configured with the circuit biased
to one-half of the supply voltage. In these cases, a false-ground
reference can be created by using a voltage divider buffered by an
amplifier. Figure 28 shows the schematic for such a circuit.

The two 1 MΩ resistors generate the reference voltages while
drawing only 0.9 µA of current from a 1.8 V supply. A capacitor
connected from the inverting terminal to the output of the op
amp provides compensation to allow a bypass capacitor to be
connected at the reference output. This bypass capacitor helps
establish an ac ground for the reference output.

1.8V TO 5V

10k⍀

0.022␮F

1M⍀

1M⍀

1␮F

AD8631

100⍀

1␮F

V

REF

0.9V TO 2.5V

Figure 29. A Micropower Reference Voltage Generator

MICROPHONE PREAMPLIFIER

The AD8631 is ideal to use as a microphone preamplifier.
Figure 30 shows this implementation.

R3

220k⍀

1.8V

AD8631

V

OUT

R3

A

=

V

R2

2.2k⍀

ELECTRET

MIC

1.8V

R1

C1

R2

0.1␮F

V

IN

22k⍀

V

REF

= 0.9V

Figure 30. A Microphone Preamplifier

R1 is used to bias an electret microphone and C1 blocks dc voltage
from the amplifier. The magnitude of the gain of the amplifier is
approximately R3/R2 when R2 ≥ 10  R1. V

should be equal to

REF

1/2  1.8 V for maximum voltage swing.

Direct Access Arrangement for Telephone Line Interface

Figure 31 illustrates a 1.8 V transmit/receive telephone line interface
for 600 Ω transmission systems. It allows full duplex transmission of
signals on a transformer-coupled 600 Ω line in a differential manner.
Amplifier A1 provides gain that can be adjusted to meet the modem
output drive requirements. Both A1 and A2 are configured to apply
the largest possible signal on a single supply to the transformer.
Amplifier A3 is configured as a difference amplifier for two reasons:
(1) It prevents the transmit signal from interfering with the receive
signal and (2) it extracts the receive signal from the transmission line
for amplification by A4. A4’s gain can be adjusted in the same
manner as A1’s to meet the modem’s input signal requirements.
Standard resistor values permit the use of SIP (Single In-line
Package) format resistor arrays. Couple this with the AD8631/

–11–REV. 0

AD8631/AD8632

AD8632’s 5-lead SOT-23, 8-lead µSOIC, and 8-lead SOIC
footprint and this circuit offers a compact solution.

P1

Tx GAIN

TO TELEPHONE

LINE

1:1

Z

O

600⍀

T1

MIDCOM
671-8005

A1, A2 = 1/2 AD8632
A3, A4 = 1/2 AD8632

6.2V

6.2V

R11

10k⍀

360⍀

R9

10k⍀

R12

10k⍀

ADJUST

R3

R5

10k⍀

R6

10k⍀

R10

10k⍀

2

A3

3

2k⍀

1

7

1

9.09k⍀

A1

A2

R13

10k⍀

R2

2

3

6

5

R14

14.3k⍀

6

5

R1

10k⍀

A4

C1

0.1␮F

+1.8V DC

10␮F

P2
Rx GAIN
ADJUST

2k⍀

7

C2

0.1␮F

TRANSMIT

TxA

R7
10k⍀

R8
10k⍀

RECEIVE

RxA

Figure 31. A Single-Supply Direct Access Arrangement
for Modems

SPICE Model

The SPICE model for the AD8631 amplifier is available and
can be downloaded from the Analog Devices’ web site at
http://www.analog.com. The macro-model accurately simulates
a number of AD8631 parameters, including offset voltage, input
common-mode range, and rail-to-rail output swing. The output
voltage versus output current characteristics of the macro-model
is identical to the actual AD8631 performance, which is a critical
feature with a rail-to-rail amplifier model. The model also accurately
simulates many ac effects, such as gain-bandwidth product, phase
margin, input voltage noise, CMRR and PSRR versus frequency,
and transient response. Its high degree of model accuracy makes the
AD8631 macro-model one of the most reliable and true-to-life
models available for any amplifier.

C3810–2.5–4/00 (rev. 0)

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.0098 (0.25)

0.0040 (0.10)

SEATING

PLANE

8-Lead Narrow Body SOIC

(SO-8)

0.1968 (5.00)

0.1890 (4.80)

85

0.0500
(1.27)

BSC

0.2440 (6.20)

41

0.2284 (5.80)

0.0688 (1.75)

0.0532 (1.35)

0.0192 (0.49)

0.0138 (0.35)

0.0098 (0.25)

0.0075 (0.19)

0.0669 (1.70)

0.0590 (1.50)

0.0512 (1.30)

0.0354 (0.90)

8ⴗ
0ⴗ

0.0059 (0.15)

0.0019 (0.05)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

0.0196 (0.50)

0.0099 (0.25)

0.0500 (1.27)

0.0160 (0.41)

ⴛ 45ⴗ

5-Lead SOT-23

(RT-5)

0.1181 (3.00)

0.1102 (2.80)

4 5

0.1181 (3.00)

0.1024 (2.60)

0.0374 (0.95) BSC

0.0571 (1.45)

0.0374 (0.95)

SEATING
PLANE

PIN 1

1 3

2

0.0748 (1.90)
BSC

0.0197 (0.50)

0.0138 (0.35)

0.122 (3.10)

0.114 (2.90)

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

10ⴗ

0ⴗ

0.122 (3.10)

0.114 (2.90)

85

PIN 1

0.0256 (0.65) BSC

0.120 (3.05)

0.112 (2.84)

0.018 (0.46)

0.008 (0.20)

0.0079 (0.20)

0.0031 (0.08)

0.0217 (0.55)

0.0138 (0.35)

8-Lead ␮SOIC

(RM-8)

0.199 (5.05)

0.187 (4.75)

41

0.043 (1.09)

0.037 (0.94)

0.011 (0.28)

0.003 (0.08)

0.120 (3.05)

0.112 (2.84)

33ⴗ
27ⴗ

0.028 (0.71)

0.016 (0.41)

PRINTED IN U.S.A.

–12–

REV. 0