16-Channel, 8-Bit
a
FEATURES
16 Independently Addressable Voltage Outputs
Full-Scale Set by External Reference
2 µs Settling Time
Double Buffered 8-Bit Parallel Input
High Speed Data Load Rate
Data Readback
Operates from Single +5 V
Optional ±6 V Supply Extends Output Range
APPLICATIONS
Phased Array Ultrasound & Sonar
Power Level Setting
Receiver Gain Setting
Automatic Test Equipment
LCD Clock Level Setting
GENERAL DESCRIPTION
The AD8600 contains 16 independent voltage output digital-toanalog converters that share a common external reference input
voltage. Each DAC has its own DAC register and input register
to allow double buffering. An 8-bit parallel data input, four address pins, a
digital interface.
The AD8600 is constructed in a monolithic CBCMOS process
which optimizes use of CMOS for logic and bipolar for speed
and precision. The digital-to-analog converter design uses voltage mode operation ideally suited to single supply operation.
The internal DAC voltage range is fixed at DACGND to V
The voltage buffers provide an output voltage range that approaches ground and extends to 1.0 V below V
reference voltage values and digital inputs will settle within
±1 LSB in 2 µs.
Data is preloaded into the input registers one at a time after the
internal address decoder selects the input register. In the write
mode (R/
the positive edge of the
be used to load the data. After changes have been submitted to
the input registers, the DAC registers are simultaneously updated by a common load
put voltages simultaneously appear on all 16 outputs.
CS select, a LD, EN, R/W, and RS provide the
.
REF
. Changes in
CC
W low) data is latched into the input register during
EN pulse. Pulses as short as 40 ns can
EN × LD strobe. The new analog out-
Multiplying DAC
AD8600*
FUNCTIONAL BLOCK DIAGRAM
V
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CS
EN
A3
A2
A1
A0
R/W
CONTROL
ADDRESS
REGISTERS
LOGIC
DECODE
16 x 8
INPUT
D
GND1
DD1
At system power up or during fault recovery the reset (RS) pin
forces all DAC registers into the zero state which places zero
volts at all DAC outputs.
The AD8600 is offered in the PLCC-44 package. The device is
designed and tested for operation over the extended industrial
temperature range of –40°C to +85°C.
R/
W•CS•ADDR•EN
DB7...DB0
RS
D
GND1
R/W•CS•ADDRESS
V
INPUT
REGISTER
DD1
Figure 1. Equivalent DAC Channel
V
LD
DD2VREFVCC
16 x 8
DAC
REGISTERS
AD8600
D
GND2
V
DD2
DAC
REGISTER
D
GND2
LD•EN
RS
8-BIT
DAC
DACGND
DACGND
16
V
REF
R-2R
DAC
O0
O1
O2
O3
O4
O5
O6
O7
O8
S
O9
O10
O11
O12
O13
O14
O15
V
EE
V
CC
O
X
V
EE
*Patent pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
AD8600–SPECIFICATIONS
(@ V
= V
SINGLE SUPPLY
DD1
= VCC = +5 V ± 5%, V
DD2
Parameter Symbol Condition Min Typ Max Units
STATIC PERFORMANCE
Resolution N 8 Bits
Relative Accuracy
2
Differential Nonlinearity
Full-Scale Voltage V
Full-Scale Tempco TCV
Zero Scale Error V
Reference Input Resistance R
ANALOG OUTPUT
Output Voltage Range
Output Current I
Capacitive Load C
1
2
2
INL –1 ±1/2 +1 LSB
DNL Guaranteed Monotonic –1 ±1/4 +1 LSB
FS
ZSE
V
ZSE
REF
OVR
OUT
L
Data = FF
Data = FF
FS
Data = 00H, RS = “0,” TA= +25°C +3.5 LSB
Data = 00H, RS = “0” +5 LSB
Data = AB
V
SS
= +2.5 V 0.000 2.500 V
REF
Data = 80
No Oscillation 50 pF
LOGIC INPUTS
Logic Input Low Voltage V
Logic Input High Voltage V
Logic Input Current I
Logic Input Capacitance
3
IL
IH
IL
C
IL
LOGIC OUTPUTS
Logic Out High Voltage V
Logic Out Low Voltage V
AC CHARACTERISTICS
3
Slew Rate SR For ∆V
Voltage Output Settling Time
Voltage Output Settling Time2t
OH
OL
2
t
S1
S2
IOH = –0.4 mA 3.5 V
IOL = 1.6 mA 0.4 V
REF
±1 LSB of Final Value, Full-Scale Data Change 2 µs
±1 LSB of Final Value, ∆V
POWER SUPPLIES
V
Positive Supply Current I
Logic Supply Currents I
Power Dissipation P
CC
DD1&2
DISS
= 5 V, VIL = 0 V, No Load 24 35 mA
IH
V
= 5 V, VIL = 0 V, No Load 0.1 mA
IH
V
= 5 V, VIL = 0 V, No Load 120 175 mW
IH
Power Supply Sensitivity PSS ∆VCC = ±5% 0.007 %/%
Logic Power Supply Range V
Positive Power Supply Range3V
NOTES
1
When V
2
Single supply operation does not include the final 2 LSBs near analog ground. If this performance is critical, use a negative supply (VEE) pin of at least –0.7 V to
–5.25 V. Note that for the INL measurement zero-scale voltage is extrapolated using codes 7
3
Guaranteed by design not subject to production test.
Specifications subject to change without notice.
= 2.500 V, 1 LSB = 9.76 mV.
REF
DDR
CCR
= 0 V, V
EE
H
H
H
H
= +2.500 V, –40°C ≤ TA ≤ +85°C, unless otherwise noted)
REF
2.480 2.490 2.500 V
±20 ppm/°C
1.2 2 kΩ
±2mA
0.8 V
2.4 V
10 µA
10 pF
or FS Code Change 4 7 V/µs
= 1 V, Data = FF
REF
H
2 µs
4.75 5.25 V
to 8010.
10
V
DD
7.0 V
–2–
REV. 0
AD8600
(@ V
= V
DUAL SUPPLY
DD1
= VCC = +5 V ± 5%, V
DD2
Parameter Symbol Condition Min Typ Max Units
STATIC PERFORMANCE
1
Resolution N 8 Bits
Total Unadjusted Error TUE All Other DACs Loaded with Data = 55
Relative Accuracy INL –1 ±1/2 +1 LSB
Differential Nonlinearity DNL Guaranteed Monotonic –1 ±1/4 +1 LSB
Full-Scale Voltage V
Full-Scale Voltage Error V
FS
FSE
Full-Scale Tempco TCV
Zero Scale Error V
Zero Scale Error V
Zero Scale Error V
ZSE
ZSE
ZSE
Zero Scale Tempco TCV
Reference Input Resistance R
Reference Input Capacitance2C
REF
REF
Data = FFH, V
Data = FFH, V
Data = FFH, V
FS
Data = 00H, RS = “0,” TA = +25°C–2±1+2 mV
Data = 00H, All Other DACs Data = 00
Data = 00H, All Other DACs Data = 55
Data = 00H, VCC = +5 V, VEE = –5 V ±10 µV/°C
ZS
Data = AB
Data = AB
ANALOG OUTPUT
V
Output Voltage Range OVR
Output Voltage Range
Output Current I
Capacitive Load
2
2
OVR
OUT
C
L
1
2
= +3.5 V 0.000 3.500 V
REF
V
= V
CC
Data = 80
No Oscillation 50 pF
LOGIC INPUTS
Logic Input Low Voltage V
Logic Input High Voltage V
Logic Input Current I
Logic Input Capacitance
2
IL
IH
IL
C
IL
LOGIC OUTPUTS
Logic Out High Voltage V
Logic Out Low Voltage V
AC CHARACTERISTICS
2
OH
OL
IOH = –0.4 mA 3.5 V
IOL = 1.6 mA 0.4 V
Reference In Bandwidth BW –3 dB Frequency, V
Slew Rate SR For ∆ V
Voltage Noise Density e
Digital Feedthrough FT Digital Inputs to DAC Outputs 10 nVs
Voltage Output Settling Time
Voltage Output Settling Time3t
N
3
t
S1
S2
f = 1 kHz, V
±1 LSB of Final Value, FS Data Change 1 2 µs
±1 LSB of Final Value, ∆V
POWER SUPPLIES
V
Positive Supply Current I
Negative Supply Current I
Logic Supply Currents I
Power Dissipation
4
CC
EE
DD1&2
P
DISS
= 5 V, VIL = 0 V, VEE = –5 V, No Load 22 35 mA
IH
V
= 5 V, VIL = 0 V, VEE = –5 V, No Load 22 35 mA
IH
V
= 5 V, VIL = 0 V, VEE = –5 V, No Load 0.1 mA
IH
V
= 5 V, VIL = 0 V, VEE = –5 V, No Load 225 350 mW
IH
Power Supply Sensitivity PSS ∆ VCC & ∆VEE = ±5% 0.007 %/%
Logic Power Supply Range V
Pos Power Supply Range
Neg Power Supply Range
NOTES
1
When V
2
Guaranteed by design not subject to production test.
3
Settling time test is performed using RL = 50 kΩ and CL = 35 pF.
4
Power Dissipation is calculated using 5 V × (IDD + |ISS| + I
Specifications subject to change without notice.
= +3.500 V, 1 LSB = 13.67 mV.
REF
2
2
V
V
DDR
CCR
EER
DD1
= –5 V ± 5%, V
EE
REF
REF
REF
H
H
= +7 V, V
DD2
H
= +3.5 V 3.473 3.486 3.500 V
= +3.5 V –1 +1 LSB
= +3.5 V ±20 ppm/°C
EE
= +3.500 V, –40°C ≤ TA ≤ +85°C, unless otherwise noted)
REF
H
H
H
–1 ±3/4 +1 LSB
–1 +1 LSB
±1/2 LSB
1.2 2 kΩ
= –0.7 V, V
= 5 V 0.000 5.000 V
REF
±2mA
240 pF
0.8 V
2.4 V
10 µA
10 pF
= 2.5 VDC + 0.1 V
or FS Code Change 4 7 V/µs
REF
REF
= 0 V 46 nV/√Hz
REF
= 1 V, Data = FF
REF
AC
500 kHz
H
12 µs
4.75 5.25 V
V
DD
7.0 V
–5.25 0.0 V
+ I
).
DD2
REV. 0
–3–
AD8600
(@ V
= V
= VCC = +5 V ± 5%, V
DD2
ELECTRICAL CHARACTERISTICS
DD1
unless otherwise noted)
Parameter Symbol Condition Min Typ Max Units
INTERFACE TIMING
Clock (EN) Frequency f
EN) High Pulse Width t
Clock (
EN) LowPulse Width t
Clock (
Data Setup Time t
Data Hold Time t
Address Setup Time t
Address Hold Time t
Valid Address to Data Valid t
Load Enable Setup Time t
Load Enable Hold Time t
Read/Write to Clock (
Read/Write to DataBus Hi-Z t
Read/Write to DataBus Active t
EN) to Read/Write t
Clock (
EN) to Chip Select t
Clock (
Chip Select to Clock (
Chip Select to Data Valid t
Chip Select to DataBus Hi-Z t
Reset Pulse Width t
NOTES
1
Guaranteed by design not subject to production test.
2
All logic input signals have maximum rise and fall times of 2 ns.
Specifications subject to change without notice.
1, 2
CLK
CH
CL
DS
DH
AS
AH
AD
LS
EN)t
EN)t
LH
RWC
RWZ
RWD
TWH
TCH
CSC
CSD
CSZ
RS
Data Loading 12.5 MHz
= –5 V, V
EE
= +3.500 V, –40°C ≤ TA ≤ +85°C,
REF
40 ns
40 ns
40 ns
10 ns
0ns
0ns
160 ns
0ns
0ns
30 ns
120 ns
120 ns
0ns
0ns
30 ns
120 ns
150 ns
25 ns
R/W
DATA
ADDR
EN
CS
t
RWZ
t
t
RWC
AS
t
DS
t
CSC
Figure 2. Write Timing
R/W
t
TWH
t
DH
t
AH
t
CH
t
CL
t
TCH
HIGH-Z
DATA
ADDR
EN
CS
HIGH -Z
t
t
RWD
CSD
t
AD
t
CSZ
Figure 3. Readback Timing
LD
t
LS
EN
RS
OUT
t
LH
t
RS
t
S1
t
S1
Figure 4. Write to DAC Register & Voltage Output Settling
Timing (CS= High, Prevents Input Register Changes)
–4–
REV. 0
AD8600
ABSOLUTE MAXIMUM RATINGS
(TA= +25°C unless otherwise noted)
V
(Digital Supply) to GND . . . . . . . . . . . . . .–0.3 V, +7 V
DD1
(DAC Buffer/Driver Supply) . . . . . . . . . . . . –0.3 V, +7 V
V
DD2
(Analog Supply) to GND . . . . . . . . . . . . . . . –0.3 V, +7 V
V
CC
(Analog Supply) to GND . . . . . . . . . . . . . . . +0.3 V, –7 V
V
EE
to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
V
REF
to V
V
DD2
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
V
OUT
Short Circuit Duration
V
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V
REF
to GND or Power Supplies
1
. . . . . . . . . . . . . . .
Digital Input/Output Voltage to GND . . . –0.3 V, V
Thermal Resistance–Theta Junction-to-Ambient (θ
+ 0.3 V
CC
CC
Continuous
+ 0.3 V
DD
)
JA
PLCC-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
– T
Package Power Dissipation . . . . . . . . . . . . . . . . (T
Maximum Junction Temperature T
max . . . . . . . . . . . 150°C
J
)/θ
J
A
JA
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
NOTE
1
No more than four outputs may be shorted to power or GND simultaneously.
PIN CONFIGURATION
CC
DD2
DGND2
V
V
43
25 28
26
A2
A0
A1
EE
V
O8
404142
O9
39
38
O10
O11
37
O12
36
35
O13
34
O14
33
O15
32
DGND1
31
LD
30
CS
29
EN
27
A3
R/W
O6
7
8
O5
9
O4
10
O3
O2
11
O1
12
13
O0
V
14
DD1
RS
15
DB0
16
DB1
17
NC = NO CONNECT
O7
DB2
EE
V
DB3
CC
V
DB4
REF
NC
DACGND
V
3
AD8600
TOP VIEW
(Not to Scale)
21 24
22182019
23
DB7
DB5
DB6
4412645
ORDERING GUIDE
Package Package
Model Temperature Description Option
AD8600AP –40°C to +85°C 44-Lead PLCC P-44A
AD8600Chips +25°C Die*
*For die specifications contact your local Analog Devices sales office.
The AD8600 contains 5782 transistors.
PIN DESCRIPTION
Pin No. Name Description
1 NC No Connection
2V
REF
Reference input voltage common
to all DACs.
3 DACGND DAC Analog Ground Return. Sets
analog zero-scale voltage.
4V
5V
CC
EE
Output Amplifier Positive Supply
Output Amplifier Negative Supply
6 O7 DAC Channel Output No. 7
7 O6 DAC Channel Output No. 6
8 O5 DAC Channel Output No. 5
9 O4 DAC Channel Output No. 4
10 O3 DAC Channel Output No. 3
11 O2 DAC Channel Output No. 2
12 O1 DAC Channel Output No. 1
13 O0 DAC Channel Output No. 0
14 V
15
DD1
RS Active Low Reset Input Pin
Digital Logic Power Supply
16 DB0 Data Bit Zero I/O (LSB)
17 DB1 Data Bit I/O
18 DB2 Data Bit I/O
19 DB3 Data Bit I/O
20 DB4 Data Bit I/O
21 DB5 Data Bit I/O
22 DB6 Data Bit I/O
23 DB7 Most Significant Data Bit I/O (MSB)
24 A0 Address Bit Zero (LSB)
25 A1 Address Bit
26 A2 Address Bit
27 A3 Most Significant Addr Bit (MSB)
28 R/
29
30
31
W Read/Write Select Control Input
EN Active Low Enable Clock Strobe
CS Chip Select Input
LD DAC Register Load Strobe
32 DGND1 Digital Ground Input No. 1
33 O15 DAC Channel Output No. 15
34 O14 DAC Channel Output No. 14
35 O13 DAC Channel Output No. 13
36 O12 DAC Channel Output No. 12
37 O11 DAC Channel Output No. 11
38 O10 DAC Channel Output No. 10
39 O9 DAC Channel Output No. 9
40 O8 DAC Channel Output No. 8
41 V
42 V
EE
CC
Output Amplifier Negative Supply
Output Amplifier Positive Supply
43 DGND2 Digital Ground Input No. 2
44 V
DD2
DAC Analog Supply Voltage
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8600 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
–5–
WARNING!
ESD SENSITIVE DEVICE
AD8600
TRANSFER EQUATIONS
Output Voltage
V
Oi= D ×
REF
256
where i is the DAC channel number and D is the decimal value
of the DAC register data.
Table I. Truth Table
EN R/W CS LD RS Operation
Write to DAC Register
– X H L H Update DAC Register
L X H – H Update DAC Register
+ X H L H Latches DAC Register
L X H + H Latches DAC Register
L L L L H DAC Register Transparent
Write to Input Register
L L L H H Load Data to Input Register at
Decoded Address
+ L L H H Latches Data in Input Register at
Decoded Address
L L + H H Latches Data in Input Register at
Decoded Address
Readback Input Registers
X H L H H Input Register Readback (Data
Access)
X H + H H Hi-Z Readback Disconnects from
Bus
X X H X X Hi-Z on Data Bus
Reset
X X X X L Clear All Registers to Zero,
= 0 V
V
OUT
X X H H + Latches All Registers to Zero
LX LH +
CS = Low; Input Register Ready
R/W, DAC Register Latched
for
to Zero
NOTES
1
+ symbol means positive edge of control input line.
2
– symbol means negative edge of control input line.
Decoded DAC Register
Oi= A
where A is the decimal value of the decoded address bits A3,
A2, A1, A0 (LSB).
Address,
vation of the active low
ent when
the decoded input register. When the load strobe
CS, R/W and data inputs should be stable prior to acti-
EN input. Input registers are transpar-
EN is low. When EN returns high, data is latched into
LD and EN
pins are active low, all input register data is transferred to the
DAC registers. The DAC registers are transparent while they
are enabled.
Table II. Address Decode Table
A3 A2 A1 A0 Addr DAC
(MSB) (LSB) Code Updated
(Binary) (Hex)
0000 0 O0
0001 1 O1
0010 2 O2
0011 3 O3
0100 4 O4
0101 5 O5
0110 6 O6
0111 7 O7
1000 8 O8
1001 9 O9
1010 A O10
1011 B O11
1100 C O12
1101 D O13
1110 E O14
1111 F O15
–6–
REV. 0
Typical Performances Characteristics–AD8600
125–25–50
8
–4
–2
0
4
1007550250
TEMPERATURE – °C
ZERO-SCALE – mV
VCC = +5V
V
EE
= –5V
V
REF
= 3.5V
+1/2
–1/2
+1/2
LINEARITY ERROR – LSB
–1/2
DACs 00–07 SUPERIMPOSED
0
VCC = +5V
V
EE
V
REF
T
A
0
DACs 08–015 SUPERIMPOSED
DIGITAL INPUT CODE – Decimal
= –5V
= +3.5V
= +25°C
Figure 5. Linearity Error vs.
Digital Code
15
VCC = +5V
V
= –5V
EE
10
RS = 0
5
0
– mA
OUT
–5
I
–10
–15
–4 –3 –2 0–1 1 2 3 4
V
– Volts
OUT
3.50
3.49
3.48
FULL-SCALE OUTPUT – Volts
3.47
2560 19212864
Figure 6. Full-Scale Voltage vs.
Temperature
4
3
2
1
OUTPUT AMPLITUDE – Volts
0
VCC = +5V
VEE = –5V
V
= 3.5V
REF
TEMPERATURE – °C
VCC = +5V
V
= –5V
EE
V
= 3.5V
REF
TIME – 250ns/DIV
125–25–50 1007550250
Figure 7. Zero-Scale Voltage vs.
Temperature
100
VCC = +5V
= –5V
V
80
60
40
20
NOISE VOLTAGE DENSITY – nV/√Hz
EE
V
= 0V
REF
= +25°C
T
A
0
10
100
FREQUENCY – Hz
10k1k
Figure 8. Output Current vs.
Voltage
–5
–10
GAIN – dB
–15
1k
VIN = 100mV p-p + 2.5V
CODE = FF
TA = +25°C
H
10k 10M1M100k
FREQUENCY – Hz
DC
GAIN
00
–45
PHASE
–90
Figure 11. Gain & Phase vs.
Frequency
Figure 9. Full-Scale Settling Time
0
–20
–40
–60
FEEDTHROUGH – dB
PHASE – Degrees
–80
–100
100
VIN = 2V p-p + 1V
RS = 0
T
= +25°C
A
1k 100k10k
FREQUENCY – Hz
Figure 12. AC Feedthrough vs.
Frequency
Figure 10. Voltage Noise Density vs.
Frequency
60
DC
50
40
PSRR – dB
30
20
∆VCC = 100mV p-p
T
= +25°C
A
CODE = 00
VEE = –5V
FREQUENCY – Hz
H
1k
10k10010 100k
Figure 13. PSRR vs. Frequency
REV. 0
–7–
AD8600
20
19
18
17
SUPPLY CURRENT – mA
16
15
VCC = +5V
= –5V
V
EE
V
= 3.5V
REF
TEMPERATURE – °C
χ + 3σ
χ
χ − 3σ
125–50–75 10025 50–25 0 75
Figure 14. Supply Current vs. Temperature Figure 15. Output Voltage Drift
Operation
The AD8600 is a 16-channel voltage output, 8-bit digital to
analog converter. The AD8600 operates from a single +5 V
supply, or for a wider output swing range, the part can operate
from dual supplies of ±5 V or ±6 V or a single supply of +7 V.
The DACs are based upon a unique R-2R ladder structure*
that removes the possibility of current injection from the reference to ground during code switching. Each of the 8-bit DACs
has an output amplifier to provide 16 low impedance outputs.
With a single external reference, 16 independent dc output levels can be programmed through a parallel digital interface. The
interface includes 4 bits of address (A0–A3), 8 bits of data
(DB0–DB7), a read/write select pin (R/
EN), a DAC register load strobe (LD), and a chip select
strobe (
CS). Additionally a reset pin (RS) is provided to asynchro-
pin (
W), an enable clock
nously reset all 16 DACs to 0 V output.
D/A Converter Section
The internal DAC is an 8-bit voltage mode device with an output that swings from DACGND to the external reference voltage, V
. The equivalent schematic of one of the DACs is
REF
shown in Figure 16. The DAC uses an R-2R ladder to ensure
accuracy and linearity over the full temperature range of the part.
The switches shown are actually N and P-channel MOSFETs to
allow maximum flexibility and range in the choice of reference
V
REF
DACGND
TO 15
DACs
R
R
V
R
R
R
R
R
R
R
R
2R
R
*R = 30kΩ
TYPICALLY
OUT
Figure 16. Equivalent Schematic of Analog Channel
voltage. The switches’ low ON resistance and matching is important in maintaining the accuracy of the R-2R ladder.
5
VCC = +5V
4
3
2
1
0
–1
–2
–3
CHANGE IN ZERO SCALE – mV
–4
–5
= –5V
V
EE
V
= 3.5V
REF
CODE = 00
T = HOURS OF OPERATION AT +125°C
H
χ + 3σ
χ
χ − 3σ
12002000 1000600 800400
Accelerated by Burn-In
Amplifier Section
The output of the DAC ladder is buffered by a rail-to-rail output amplifier. This amplifier is configured as a unity gain follower as shown in Figure 16. The input stage of the amplifier
contains a PNP differential pair to provide low offset drift and
noise. The output stage is shown in Figure 17. It employs
complementary bipolar transistors with their collectors connected to the output to provide rail-to-rail operation. The NPN
transistor enters into saturation as the output approaches the
negative rail. Thus, in single supply, the output low voltage is
limited by the saturation voltage of the transistor. For the transistors used in the AD8600, this is approximately 40 mV. The
AD8600 was not designed to swing to the positive rail in contrast to some of ADI’s other DACs (for example, the AD8582).
The output stage of the amplifier is actually capable of swinging
to the positive rail, but the input stage limits this swing to approximately 1.0 V below V
CC
.
V
CC
V
OUT
V
EE
Figure 17. Equivalent Analog Output Circuit
During normal operation, the output stage can typically source
and sink ±1 mA of current. However, the actual short circuit
current is much higher. In fact, each DAC is capable of sourcing 20 mA and sinking 8 mA during a short condition. The
absolute maximum ratings state that, at most, four DACs can
be shorted simultaneously. This restriction is due to current
densities in the metal traces. If the current density is too high,
voltage drops in the traces will cause a loss in linearity performance for the other DACs in the package. Thus to ensure longterm reliability, no more than four DACs should be shorted
simultaneously.
*Patent Pending.
–8–
REV. 0
Power Supply and Grounding Considerations
The low power consumption of the AD8600 is a direct result of
circuit design optimizing using a CBCMOS process. The overall power dissipation of 120 mW translates to a total supply current of only 24 mA for 16 DACs. Thus, each DAC consumes
only 1.5 mA. Because the digital interface is comprised entirely
of CMOS logic, the power dissipation is dependent upon the
logic input levels. As expected for CMOS, the lowest power
dissipation is achieved when the input level is either close to
ground or +5 V. Thus, to minimize the power consumption,
CMOS logic should be used to interface to the AD8600.
The AD8600 has multiple supply pins. V
the output amplifiers’ positive supply, and V
(Pins 4 and 42) is
CC
(Pins 5 and 41)
EE
the amplifiers’ negative supply. The digital input circuitry is
powered by V
2R ladder switches are powered by V
(Pin 14), and finally the DAC register and R-
DD1
(Pin 44). To minimize
DD2
noise feedthrough from the supplies, each supply pin should be
decoupled with a 0.1 µF ceramic capacitor close to the pin.
When applying power to the device, it is important for the digital supply, V
for V
to remain less than 0.3 V above V
REF
, to power on before the reference voltage and
DD2
during normal
DD2
operation. Otherwise, an inherent diode will energize, and it
could damage the AD8600.
In order to improve ESD resistance, the AD8600 has several
ESD protection diodes on its various pins. These diodes shunt
ESD energy to the power supplies and protect the sensitive active circuitry. During normal operation, all the ESD diodes are
reversed biased and do not affect the part. However, if overvoltages occur on the various inputs, these diodes will energize. If
the overvoltage is due to ESD, the electrical spike is typically
short enough so that the part is not damaged. However, if the
overvoltage is continuous and has sufficient current, the part
could be damaged. To protect the part, it is important not to
forward bias any of the ESD protection diodes during normal
operation or during power up. Figure 18 shows the location of
these diodes. For example, the digital inputs have diodes connected to V
and from DGND1. Thus, the voltage on any
CC
digital input should never exceed the analog supply or drop below ground, which is also indicated in the absolute maximum
ratings.
AD8600
V
V
CC
DD2
ALL DIGITAL INPUTS
(A0–A3, DB0–DB7)
W, CS, EN, LD, RS )
(R/
DGND1
V
REF
DACGND
Figure 18. ESD Protection Diode Locations
Attention should be paid to the ground pins of the AD8600 to
ensure that noise is not introduced to the output. The pin labeled DACGND (Pin 3) is actually the ground for the R-2R
ladder, and because of this, it is important to connect this pin to
a high quality analog ground. Ideally, the analog ground should
be an actual ground plane. This helps create a low impedance,
low noise ground to maintain accuracy in the analog circuitry.
The digital ground pins (DGND1 at Pin 32 and DGND2 at
Pin 43) provide the ground reference for the internal digital circuitry and latches. The first thought may be to connect both of
these pins to the system digital ground. However, this is not the
best choice because of the high noise typically found on a
system’s digital ground. This noise can feed through to the output through the DAC’s ground pins. Instead, DGND1 and
DGND2 should be connected to the analog ground plane. The
actual switching current in these pins is small and should not
degrade the analog ground.
5 V Output Swing
The output swing is limited to 1.0 V below the positive supply.
This gives a maximum output of +4.0 V on a +5 V supply. To
increase the output range, the analog supply, V
ladder supply, V
output of +5 V with a 5 V reference. V
, can be increased to +7 V. This allows an
DD2
DD1
+5 V to ensure that the input logic levels do not change.
Reference Input Considerations
The AD8600 is designed for one reference to drive all 16 DACs.
The reference pin (V
) is connected directly to the R-2R lad-
REF
ders of each DAC. With 16 DACs in parallel, the input impedance is typically 2 kΩ and a minimum of 1.2 kΩ. The input
resistance is code dependent. Thus, the chosen reference device
must be able to drive this load. Some examples of +2.5 V references that easily interface to the AD8600 are the REF43,
AD680, and AD780. The unique architecture ensures that the
reference does not have to supply “shoot through” current,
which is a condition in some voltage mode DACs where the reference is momentarily connected to ground through the CMOS
switches. By eliminating this possibility, all 16 DACs in the
AD8600 can easily be driven from a single reference.
, and the DAC
CC
should remain at
REV. 0
–9–
AD8600
Interface Timing and Control
The AD8600 employs a double buffered DAC structure with
each DAC channel having a unique input register and DAC register as shown in the diagram entitled “Equivalent DAC Channel” on the first page of the data sheet. This structure allows
maximum flexibility in loading the DACs. For example, each
DAC can be updated independently, or, if desired, all 16 input
registers can be loaded, followed by a single
LD strobe to update all 16 DACs simultaneously. An additional feature is the
ability to read back from the input register to verify the DAC’s
data.
A0
A1
N1
A2
R/W
EN
CS
R/W
CS
LD
EN
D7–D0
A3
N2
N3
N4
N5
N6
8
INPUT
REGISTER
READ BACK
88
DAC
REGISTER
R-2R
LADDER
Figure 19. Logic Interface Circuit for DAC Channel 0
The interface logic for a single DAC channel is shown in Figure
19. This figure specifically shows the logic for Channel 0; however, by changing the address input configuration to gate N1,
the other 15 channels are achieved. All of the logic for the
AD8600 is level sensitive and not edge triggered. For example,
if all the control inputs (
CS, R/W, EN, LD) are low, the input
and DAC registers are transparent and any change in the digital
inputs will immediately change the DAC’s R-2R ladder.
Table I details the different logic combinations and their effects.
Chip Select (
CS), Enable (EN) and R/W must be low to write
the input register. During this time that all three are low, any
data on DB7–DB0 changes the contents of the input register.
This data is not latched until either
EN or CS returns high.
The data setup and hold times shown in the timing diagrams
must be observed to ensure that the proper data is latched into
the input register.
To load multiple input registers in the fastest time possible,
W and CS should remain low, and the EN line be used
both R/
to “clock” in the data. As the write timing diagram shows, the
address should be updated at the same time as
EN returns high, valid data must be present for a time
Before
equal to the data setup time (t
the data Hold Time (t
DH
), and after EN returns high,
DS
) must be maintained. If these mini-
EN goes low.
mum times are violated, invalid data may be latched into the input register. This cycle can be repeated 16 times to load all of
the DACs. The fastest interface time is equal to the sum of the
low and high times (t
minimum of 80 ns. Because the
and tCH) for the EN input, which gives a
CL
EN input is used to clock in
the data, it is often referred to as the clock input, and the timing
specifications give a maximum clock frequency of 12.5 MHz,
which is just the reciprocal of 80 ns.
After all the input registers have been loaded, a single load
strobe will transfer the contents of the input registers to the
DAC registers.
address or data on the inputs could change, then
EN must also be low during this time. If the
CS should be
high during this time to ensure that new data is not loaded into
an input register. Alternatively, a single DAC can be updated
by first loading its input register and then transferring that to the
DAC register without loading the other 15 input registers.
The final interface option is to read data from the DAC’s input
registers, which is accomplished by setting R/
CS low. Read back allows the microprocessor to verify that
ing
W high and bring-
correct data has been loaded into the DACs. During this time
EN and LD should be high. After a delay equal to t
RWD
, the
data bus becomes active and the contents of the input register
are read back to the data pins, DB0–DB7. The address can be
changed to look at the contents of all the input registers. Note
that after an address change, the valid data is not available for a
time equal to t
. The delay time is due to the internal
AD
readback buffers needing to charge up the data bus (measured
with a 35 pF load). These buffers are low power and do not
have high current to charge the bus quickly. When
CS returns
high, the data pins assume a high impedance state and control
of the data lines or bus passes back to the microprocessor.
–10–
REV. 0
AD8600
DB0–DB7
A0–A3
LD
EN
R/
W
CS
DGND1, DGND2
DACGND
8
4
DIGITAL GROUND ANALOG GROUND
AD8600
MOTOROLA
68HC11
PC0–PC7
PB0–PB3
PB4
PB5
PB6
PB7
GND
Unipolar Output Operation
The AD8600 is configured to give unipolar operation. The fullscale output voltage is equivalent to the reference input voltage
minus 1 LSB. The output is dependent upon the digital code
and follows Table III. The actual numbers given for the analog
output are calculated assuming a +2.5 V reference.
Table III. Unipolar Code Table
DAC
Binary Input
MSB LSB Analog Output
1 1 1 1 1 1 1 1 +V
1 0 0 0 0 0 0 1 +V
1 0 0 0 0 0 0 0 +V
0 1 1 1 1 1 1 1 +V
0 0 0 0 0 0 0 1 +V
0 0 0 0 0 0 0 0 +V
(255/256) = +2.49 V
REF
(129/256) = +1.26 V
REF
(128/256) = +1.25 V
REF
(127/256) = +1.24 V
REF
(001/256) = +0.01 V
REF
(000/256) = +0.00 V
REF
Bipolar Output Operation
The AD8600 can be configured for bipolar operation with the
addition of an op amp for each output as shown in Figure 20.
The output will now have a swing of ± V
, as detailed in Table
REF
IV. This modification is only needed on those channels that require bipolar outputs. For channels which only require unipolar
output, no external amplifier is needed. The OP495 quad amplifier is chosen for the external amplifier because of its low
power, rail-to-rail output swing, and DC accuracy. Again, the
values calculated for the analog output are based upon an assumed +2.5 V reference.
V
REF
R1
10k
R1
10k
Table IV. Bipolar Code Table
DAC
Binary Input
MSB LSB Analog Output
1 1 1 1 1 1 1 1 +2 V
1 0 0 0 0 0 0 1 +2 V
1 0 0 0 0 0 0 0 +2 V
0 1 1 1 1 1 1 1 +2 V
0 0 0 0 0 0 0 1 +2 V
0 0 0 0 0 0 0 0 +2 V
(255/256) – V
REF
(129/256) – V
REF
(128/256) – V
REF
(127/256) – V
REF
(001/256) – V
REF
(000/256) – V
REF
= +2.49 V
REF
= +0.02 V
REF
= +0.00 V
REF
= –0.02 V
REF
= –2.48 V
REF
= –2.50 V
REF
Interfacing to the 68HC11 Microcontroller
The 68HC11 is a popular microcontroller from Motorola,
which is easily interfaced to the AD8600. The connections between the two components are shown in Figure 21. Port C of
the 68HC11 is used as a bidirectional input/output data port to
write to and read from the AD8600. Port B is used for addressing and control information. The bottom 4 LSBs of Port B are
the address, and the top 4 MSBs are the control lines (
LD, CS,
EN, and R/W). The microcode for the 68 HC11 is shown in
Figure 22. The comments in the program explain the function
of each step. Three routines are included in this listing: read
from the AD8600, write to the AD8600, and a continuous loop
that generates a saw-tooth waveform. This loop is used in the
application below.
REV. 0
+5V
V
REF
AD8600
OUT
1/4
OP495
ø
–5V
Figure 20. Circuit for Bipolar Output Operation
V
OUT
Figure 21. Interfacing the 68HC11 to the AD8600
–11–
AD8600
* This program contains subroutines to read and write
* to the AD8600 from the 68HC11. Additionally, a ramp
* program has been included, to continuously ramp the
* output giving a triangle wave output.
*
* The following connections need to be made:
* 68HC11 AD8600
* GND DGND1,2
* PC0-PC7 DB0–DB7 respectively, data port
* PB0-PB3 A0–A3 respectively, address port
* PB4 LD
* PB5 EN
* PB6 R/W
* PB7 CS
*
portc equ $1003 define port addresses
portb equ $1004
ddrc equ $1007
*
org $C000
read lds #$CFFF subroutine to read from AD8600
*
ldaa #$00 initialize port c to 00000000
staa ddrc configures PC0-PC7 as inputs.
*
ldx #$00 points to DAC address in 68HC11 memory
ldaa 0,x put the address in the accumulator
adda #$70 add the control bits to the address
* R/W, LD, EN are high, CS is low.
staa portb output control and address on port b.
*
inx points to memory location to store the data
ldaa portc read data from DAC
staa 0,x Store this data in memory at address “x”
*
ldy #$1000
bset portb,y $f0 Set CS, LD, EN high
jmp $e000 Return to BUFFALO
*
*
write lds #$cfff routine to write to AD8600
ldaa #$ff initialize port c to 11111111
staa ddrc configures PC0-PC7 as outputs.
*
ldx #$00 points to DAC address in 68HC11 mem
ldaa 0,x puts the address in the accumulator
adda #$30 set CS, R/W low and LD, EN high
staa portb output to portb for control and address
*
inx points to memory location to store the data
ldaa 0,x load the data into the accumulator
staa portc write the data to the DAC
*
ldy #$1000
bclr portb,y $30 Set LD, EN low to latch data
bset portb,y $b0 Bring LD, EN, CS high, write is complete
*
jmp $e000 Return to BUFFALO
*
*
ramp lds #$cfff routine to generate a triangle wave
ldaa #$ff configure port c as outputs
–12–
REV. 0
staa ddrc
*
ldx #$00 set x to point to the DAC address
ldaa 0,x load the address from 68HC11 mem
staa portb set the address on portb
* LD, CS, EN, R/W are all low for
* transparent DAC loading
ldab #$ff set accumulator b to 255
*
loop ldaa #$00 start the triangle wave at zero
staa portc write the data to the AD8600
*
load inca increase the data by one
staa portc send the new data to the AD8600
cba compare a to b
bne load we haven’t reached 255 yet
jmp loop we have reached 255, so start over
Figure 22. 68HC11 Microcode to Interface to the AD8600.
AD8600
Time Dependent Variable Gain Amplifier Using the AD600
The AD8600 is ideal for generating a control signal to set the
gain of the AD600, a wideband, low noise variable gain amplifier. The AD600 (and similar parts such as the AD602 and
AD603) is often used in ultrasound applications, which require
the gain to vary with time. When a burst of ultrasound is applied, the reflections from near objects are much stronger than
from far objects. To accurately resolve the far objects, the gain
must be greater than for the near objects. Additionally, the signals take longer to reach the ultrasound sensor when reflected
from a distant object. Thus, the gain must increase as the time
increases.
The AD600 requires a dc voltage to adjust its gain over a
40 dB range. Since it is a dual, the two variable gain amplifiers
can be cascaded to achieve 80 dB of gain. The AD8600 is used
to generate a ramped output to control the gain of the AD600.
The slope of the ramp should correspond to the time delay
of the ultrasound signal. Since ultrasound applications often
require multiple channels, the AD8600 is ideal for this
application.
The circuit to achieve a time dependent variable gain amp is
shown in Figure 23. The AD600’s gain is controlled by differential inputs, C1LO and C1HI, with a gain constant of
32 dB/V. Thus for 40 dB of gain, the differential control input
needs to be 1.25 V. In this application, the C1LO input is set at
the midscale voltage of 0.625 V, which is generated by a simple
voltage divider from the REF43. The AD8600’s output is divided in half, generating a 0 V to 1.25 V ramp, and then applied
to C1HI. This ramp sweeps the gain from 0 dB to 40 dB.
+5V
VCC, V
2
DD1
AD8600
V
REF
2
+2.5V
DIGITAL
CONTROL
+5V
46
REF43
, V
DD2
ULTRASOUND
O
ø
13
V
IN
(FROM
SENSOR)
R1
10k
10k
R2
A1LO
0V – 1.25V
C1
100pF
2
A1HI
3
4
GAT11C1LO
R3
30k
C1HI
16
+5V
AD600
–5V
0.625V
R4
10k
V
POS
13
V
OUT
14
A1OP
15
A1CM
12
Figure 23. Ultrasound Amplifier with Digitally Controlled
Variable Gain
REV. 0
–13–
AD8600
200ns/DIV200ns/DIV
V
OUT
50mV/DIV
The functionality of this circuit is shown in the scope photo in
Figure 24 The top trace is the control ramp, which goes from
0 V to 1.25 V. The bottom trace is the output of the AD600.
The input is actually a 12 mV p-p, 10 kHz sine wave. Thus, the
bottom trace shows the envelop of this waveform to illustrate
the increase in gain as time progresses. This ramp was generated under control of the 68HC11 using the “ramp” subroutine
as mentioned above. The slope of the ramp can easily be
lengthened by adding some delay in the loop, or the slope can
be increased by stepping by 2 or more LSBs instead of the current 1 LSB changes.
GAIN
CONTROL
1V/DIV
AD600
OUTPUT
0.2V/DIV
200µs/DIV
Glitch Impulse
A specification of interest in many DAC applications is the
glitch impulse. This is the amount of energy contained in any
overshoot when a DAC changes at its major carry transition, in
other words, when the DAC switches from code 01111111 to
code 10000000. This point is the most demanding because all
of the R-2R ladder switches are changing state. The AD8600’s
glitch impulse is shown in Figure 25. Calculating the value of
the glitch is accomplished by calculating the area of the pulse,
which for the AD8600 is: Glitch Impulse = (1/2) × (100 mV) ×
(200 ns) = 10 nV sec.
Figure 24. Time Dependent Gain of the AD600
Figure 25. Glitch Impulse
–14–
REV. 0
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead Plastic Lead Chip Carrier (PLCC) Package
(P-44A)
0.180 (4.57)
0.165 (4.19)
40
39
29
28
0.110 (2.79)
0.085 (2.16)
0.025 (0.63)
0.015 (0.38)
0.021 (0.53)
0.013 (0.33)
0.032 (0.81)
0.026 (0.66)
0.050
(1.27)
BSC
0.040 (1.01)
0.025 (0.64)
0.048 (1.21)
0.042 (1.07)
0.020
(0.50)
0.048 (1.21)
0.042 (1.07)
6
7
17
18
R
PIN 1
IDENTIFIER
TOP VIEW
0.656 (16.66)
0.650 (16.51)
0.695 (17.65)
0.685 (17.40)
0.056 (1.42)
0.042 (1.07)
SQ
SQ
0.63 (16.00)
0.59 (14.99)
AD8600
REV. 0
–15–
AD8600
C1921–18–7/94
–16–
PRINTED IN U.S.A.
REV. 0
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