Datasheet AD8572 Datasheet (ANALOG DEVICES)

Zero-Drift, Single-Supply, Rail-to-Rail

–

O

www.BDTIC.com/ADI

Input/Output Operational Amplifiers

FEATURES

Low offset voltage: 1 μV
Input offset drift: 0.005 μV/°C
Rail-to-rail input and output swing
5 V/2.7 V single-supply operation
High gain: 145 dB typical
CMRR: 140 dB typical
PSRR: 130 dB typical
Ultralow input bias current: 10 pA typical
Low supply current: 750 μA per op amp
Overload recovery time: 50 μs
No external capacitors required

APPLICATIONS

Temperature sensors
Pressure sensors
Precision current sensing
Strain gage amplifiers
Medical instrumentation
Thermocouple amplifiers

GENERAL DESCRIPTION

This family of amplifiers has ultralow offset, drift, and bias
current. The AD8571, AD8572, and AD8574 are single, dual,
and quad amplifiers, respectively, featuring rail-to-rail input
and output swings. All are guaranteed to operate from 2.7 V to
5 V single supply.

The AD857x family provides benefits previously found only in
expensive auto-zeroing or chopper-stabilized amplifiers. Using
Analog Devices, Inc., topology, these zero-drift amplifiers
combine low cost with high accuracy. (No external capacitors
are required.) Using a patented spread-spectrum, auto-zero
technique, the AD857x family eliminates the intermodulation
effects from interaction of the chopping function with the
signal frequency in ac applications.

With an offset voltage of only 1 µV and drift of 0.005 µV/°C, the
AD857x family is perfectly suited for applications where error
sources cannot be tolerated. Position and pressure sensors,
medical equipment, and strain gage amplifiers benefit greatly
from nearly zero drift over their operating temperature range.
Many more systems require the rail-to-rail input and output
swings provided by the AD857x family.

AD8571/AD8572/AD8574

PIN CONFIGURATIONS

1

NC

AD8571

2

–IN A

+IN A

TOP VIEW

3

(Not to Scale)

V–

4

NC = NO CONNECT

Figure 1. 8-Lead MSOP (RM Suffix)

1

NC

2

IN A

+IN A

AD8571

3

TOP VIEW

(Not to Scale)

V–

4

NC = NO CONNECT

Figure 2. 8-Lead SOIC (R Suffix)

1

OUT A V+

–IN A

+IN A

V–

AD8572

2

TOP VIEW

3

(Not to Scale)

4

Figure 3. 8-Lead TSSOP (RU Suffix)

1

OUT A V+

–IN A

+IN A

V–

AD8572

2

TOP VIEW

3

(Not to Scale)

4

Figure 4. 8-Lead SOIC (R Suffix)

OUT A

1

–IN A

2

+IN A

3

AD8574

V+

4

TOP VIEW

+IN B

–IN B

OUT B

(Not to Scale)

5

6

7

Figure 5. 14-Lead TSSOP (RU Suffix)

OUT A

1

–IN A

2

+IN A

3

AD8574

V+

4

TOP VIEW

UT B

(Not to S cale)

5

6

7

+IN B

–IN B

Figure 6. 14-Lead SOIC (R Suffix)

The AD857x family is specified for the extended industrial/
automotive temperature range (−40°C to +125°C). The AD8571
single amplifier is available in 8-lead MSOP and narrow SOIC
packages. The AD8572 dual amplifier is available in 8-lead narrow
SOIC and surface-mount TSSOP packages. The AD8574 quad
amplifier is available in 14-lead narrow SOIC and TSSOP packages.

8

7

6

5

8

7

6

5

8

7

6

5

8

7

6

5

14

13

12

11

10

9

8

14

13

12

11

10

9

8

NC

V+

OUT A

NC

NC

V+

OUT A

NC

OUT B

–IN B

+IN B

OUT B

–IN B

+IN B

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

1104-001

01104-004

01104-002

01104-005

01104-003

1104-006

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©1999–2008 Analog Devices, Inc. All rights reserved.

AD8571/AD8572/AD8574

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Pin Configurations ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

5 V Electrical Characteristics ...................................................... 3

2.7 V Electrical Characteristics ................................................... 4

Absolute Maximum Ratings ............................................................ 5

Thermal Characteristics .............................................................. 5

ESD Caution .................................................................................. 5

Typical Performance Characteristics ............................................. 6

Functional Description .................................................................. 14

Amplifier Architecture .............................................................. 14

Basic Auto-Zero Amplifier Theory .......................................... 14

Auto-Zero Phase ......................................................................... 15

Amplification Phase ................................................................... 15

High Gain, CMRR, and PSRR .................................................. 16

Maximizing Performance Through Proper Layout ............... 16

1/f Noise Characteristics ........................................................... 17

Random Auto-Zero Correction Eliminates Intermodulation

Distortion .................................................................................... 17

Broadband and External Resistor Noise Considerations .......... 18

Output Overdrive Recovery ...................................................... 18

Input Overvoltage Protection ................................................... 18

Output Phase Reversal ............................................................... 18

Capacitive Load Drive ............................................................... 19

Power-Up Behavior .................................................................... 19

Applications Information .............................................................. 20

5 V Precision Strain Gage Circuit ............................................ 20

3 V Instrumentation Amplifier ................................................ 20

High Accuracy Thermocouple Amplifier ............................... 21

Precision Current Meter ............................................................ 21

Precision Voltage Comparator .................................................. 21

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 23

REVISION HISTORY

6/08—Rev. C to Rev. D

Changes to Figure 19 and Figure 20 ............................................... 8

Changes to Figure 44 ...................................................................... 12

Changes to Figure 38 ...................................................................... 13

Moved Figure 50 and Figure 51 .................................................... 14

Changes to Figure 66, Precision Current Meter Section, Layout,

Figure 67, Equation 24, and Figure 68 ......................................... 21

5/07—Rev. B to Rev. C

Changes to Features .......................................................................... 1

Changes to Table 1 ............................................................................ 3

Changes to Table 2 ............................................................................ 4

Changes to Basic Auto-Zero Amplifier Theory Section ........... 14

Changes to Figure 50 ...................................................................... 15

Changes to Figure 55 ...................................................................... 16

Changes to Figure 66 ...................................................................... 21

Updated Outline Dimensions ....................................................... 22

9/06—Rev. A to Rev. B

Updated Format .................................................................. Universal

Changes to Table 1 ............................................................................. 3

Changes to Table 2 ............................................................................. 4

Changes to Figure 50 ...................................................................... 14

Changes to Figure 51 ...................................................................... 15

Changes to Figure 66 ...................................................................... 21

Deleted Figure 69 and SPICE Macro-Model Section ................ 17

Deleted SPICE Macro-Model for the AD857x Section ............. 18

Updated Outline Dimensions ....................................................... 22

Changes to Ordering Guide .......................................................... 23

7/03—Rev. 0 to Rev. A

Renumbered Figures .......................................................... Universal

Changes to Ordering Guide ............................................................. 4

Change to Figure 15. ...................................................................... 16

Updated Outline Dimensions ....................................................... 19

10/99—Revision 0: Initial Version

Rev. D | Page 2 of 24

AD8571/AD8572/AD8574

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SPECIFICATIONS

5 V ELECTRICAL CHARACTERISTICS

VS = 5 V, VCM = 2.5 V, VO = 2.5 V, TA = 25°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS 1 5 V

−40°C ≤ TA ≤ +125°C 10 V
Input Bias Current IB 10 50 pA

AD8571/AD8574 −40°C ≤ TA ≤ +125°C 1.0 1.5 nA
AD8572 −40°C ≤ TA ≤ +85°C 160 300 pA

−40°C ≤ TA ≤ +125°C 2.5 4 nA
Input Offset Current IOS 20 70 pA

AD8571/AD8574 −40°C ≤ TA ≤ +125°C 150 200 pA
AD8572 −40°C ≤ TA ≤ +85°C 30 150 pA

−40°C ≤ TA ≤ +125°C 150 400 pA
Input Voltage Range 0 5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 5 V 120 140 dB

−40°C ≤ TA ≤ +125°C 115 130 dB
Large Signal Voltage Gain

−40°C ≤ TA ≤ +125°C 120 135 dB
Offset Voltage Drift VOS/T −40°C ≤ TA ≤ +125°C 0.005 0.04 V/°C

OUTPUT CHARACTERISTICS

Output Voltage High VOH R

R

R

R

Output Voltage Low VOL R

R

R

Short-Circuit Limit ISC ±25 ±50 mA

−40°C to +125°C ±40 mA
Output Current IO ±30 mA

−40°C to +125°C ±15 mA

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 2.7 V to 5.5 V 120 130 dB

−40°C ≤ TA ≤ +125°C 115 130 dB
Supply Current per Amplifier ISY V

−40°C ≤ TA ≤ +125°C 1000 1075 A

DYNAMIC PERFORMANCE

Slew Rate SR RL = 10 kΩ 0.4 V/s
Overload Recovery Time 0.05 0.3 ms
Gain Bandwidth Product GBP 1.5 MHz

NOISE PERFORMANCE

Voltage Noise en p-p 0 Hz to 10 Hz 1.3 V p-p
0 Hz to 1 Hz 0.41 V p-p
Voltage Noise Density en f = 1 kHz 51 nV/√Hz
Current Noise Density in f = 10 Hz 2 fA/√Hz

1

Gain testing is dependent upon test bandwidth.

1

A

R

VO

= 10 kΩ, VO = 0.3 V to 4.7 V 125 145 dB

L

= 100 kΩ to GND 4.99 4.998 V

L

= 100 kΩ to GND @ −40°C to +125°C 4.99 4.997 V

L

= 10 kΩ to GND 4.95 4.98 V

L

= 10 kΩ to GND @ −40°C to +125°C 4.95 4.975 V

L

= 100 kΩ to V+ 1 10 mV

L

= 100 kΩ to V+ @ −40°C to +125°C 2 10 mV

R

L

= 10 kΩ to V+ 10 30 mV

L

= 10 kΩ to V+ @ −40°C to +125°C 15 30 mV

L

= 0 V 850 975 A

O

Rev. D | Page 3 of 24

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2.7 V ELECTRICAL CHARACTERISTICS

VS = 2.7 V, VCM = 1.35 V, VO = 1.35 V, TA = 25°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS 1 5 V

−40°C ≤ TA ≤ +125°C 10 V

Input Bias Current IB 10 50 pA

AD8571/AD8574 −40°C ≤ TA ≤ +125°C 1.0 1.5 nA
AD8572 −40°C ≤ TA ≤ +85°C 160 300 pA

−40°C ≤ TA ≤ +125°C 2.5 4 nA

Input Offset Current IOS 10 50 pA

AD8571/AD8574 −40°C ≤ TA ≤ +125°C 150 200 pA
AD8572 −40°C ≤ TA ≤ +85°C 30 150 pA

−40°C ≤ TA ≤ +125°C 150 400 pA

Input Voltage Range 0 2.7 V

Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.7 V 115 130 dB

−40°C ≤ TA ≤ +125°C 110 130 dB

Large Signal Voltage Gain

−40°C ≤ TA ≤ +125°C 105 130 dB

Offset Voltage Drift VOS/T −40°C ≤ TA ≤ +125°C 0.005 0.04 µV/°C
OUTPUT CHARACTERISTICS

Output Voltage High VOH R

R

R

R

Output Voltage Low VOL R

R

R

R

Short-Circuit Limit ISC ±10 ±15 mA

−40°C to +125°C ±10 mA

Output Current IO ±10 mA

−40°C to +125°C ±5 mA

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 2.7 V to 5.5 V 120 130 dB

−40°C ≤ TA ≤ +125°C 115 130 dB

Supply Current per Amplifier ISY V

−40°C ≤ TA ≤ +125°C 950 1000 A

DYNAMIC PERFORMANCE

Slew Rate SR RL = 10 kΩ 0.5 V/s

Overload Recovery Time 0.05 ms

Gain Bandwidth Product GBP 1 MHz
NOISE PERFORMANCE

Voltage Noise en p-p 0 Hz to 10 Hz 2.0 V p-p

Voltage Noise Density en f = 1 kHz 94 nV/√Hz

Current Noise Density in f = 10 Hz 2 fA/√Hz

1

Gain testing is dependent upon test bandwidth.

1

A

R

VO

= 10 kΩ, VO = 0.3 V to 2.4 V 110 140 dB

L

= 100 kΩ to GND 2.685 2.697 V

L

= 100 kΩ to GND @ −40°C to +125°C 2.685 2.696 V

L

= 10 kΩ to GND 2.67 2.68 V

L

= 10 kΩ to GND @ −40°C to +125°C 2.67 2.675 V

L

= 100 kΩ to V+ 1 10 mV

L

= 100 kΩ to V+ @ −40°C to +125°C 2 10 mV

L

= 10 kΩ to V+ 10 20 mV

L

= 10 kΩ to V+ @ −40°C to +125°C 15 20 mV

L

= 0 V 750 900 A

O

Rev. D | Page 4 of 24

AD8571/AD8572/AD8574

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ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage 6 V
Input Voltage GND to VS + 0.3 V
Differential Input Voltage
ESD (Human Body Model) 2000 V
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C

1

Differential input voltage is limited to ±5.0 V or the supply voltage,

whichever is less.

1

±5.0 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in a circuit board for SOIC and
TSSOP packages.

Table 4. Thermal Resistance

Package Type θJA θ

8-Lead SOIC (R) 158 43 °C/W
8-Lead MSOP (RM) 190 44 °C/W
8-Lead TSSOP (RU) 240 43 °C/W
14-Lead SOIC (R) 120 36 °C/W
14-Lead TSSOP (RU) 180 36 °C/W

Unit

JC

ESD CAUTION

Rev. D | Page 5 of 24

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TYPICAL PERFORMANCE CHARACTERISTICS

NUMBER OF AMPL IFIERS

180

160

140

120

100

80

60

40

20

0

–1.5–2.5 –0.5 0.5 1.5 2.5

OFFSET VO LTAGE (µV)

Figure 10. Input Offset Voltage Distribution

VS = 5V
V

= 2.5V

CM

T

= 25°C

A

1104-010

180

160

140

120

100

80

60

NUMBER OF AMPLIFIERS

40

20

0

–1.5–2.5 –0.5 0.5 1.5 2.5

OFFSET VOLTAGE (µV)

VS = 2.7V
V

= 1.35V

CM

T

= 25°C

A

01104-007

Figure 7. Input Offset Voltage Distribution

50

= 5V

V

S

T

= –40°C, +25° C, +85°C

40

A

30

20

10

0

–10

INPUT BIAS CURRENT (pA)

–20

–30

012 435

INPUT COMMO N-MODE VOL TAGE (V)

+85°C

+25°C

–40°C

01104-008

Figure 8. Input Bias Current vs. Input Common-Mode Voltage

1500

V

= 5V

S

T

= 125°C

A

1000

500

0

–500

–1000

INPUT BIAS CURRENT (pA)

–1500

12

10

8

6

4

NUMBER OF AMPLIFIERS

2

0

01234 65

INPUT OFFSET DRIFT (nV/°C)

Figure 11. Input Offset Voltage Drift Distribution

10k

VS = 5V
T

= 25°C

A

1k

100

10

OUTPUT VOLTAGE (mV)

1

SOURCE

VS = 5V
V

= 2.5V

CM

T

= –40°C TO +125°C

A

SINK

1104-011

–2000

012345

COMMON-MODE VOLTAGE (V)

Figure 9. Input Bias Current vs. Common-Mode Voltage

01104-009

0.1

0.0001 0.001 0.01 0. 1 100101

LOAD CURRENT (mA)

Figure 12. Output Voltage to Supply Rail vs. Load Current

Rev. D | Page 6 of 24

01104-012

AD8571/AD8572/AD8574

www.BDTIC.com/ADI

10k

= 2.7V

V

S

T

= 25°C

A

1k

800

700

600

T

A

= 25°C

100

10

OUTPUT VOL TAGE (mV)

1

0.1

0.0001 0.001 0.01 0. 1 1 10 100

SOURCE

LOAD CURRENT (mA)

SINK

Figure 13. Output Voltage to Supply Rail vs. Load Current

1000

VCM = 2.5V
V

= 5V

S

750

500

250

INPUT BIAS CURRENT (pA)

0

–75 –50 –25 0 25 50 75 100 125 150

TEMPERATURE ( °C)

Figure 14. Input Bias Current vs. Temperature

1.0

0.8

0.6

0.4

SUPPLY CURRENT (mA)

0.2

0

–75 –25–50 25 750 50 100 150125

TEMPERATURE (° C)

5V

2.7V

Figure 15. Supply Current vs. Temperature

500

400

300

200

100

SUPPLY CURRENT PER AMPLIFIER (µA)

0

01 2 34 5 6

01104-013

SUPPLY VOLTAGE (V)

01104-016

Figure 16. Supply Current per Amplifier vs. Supply Voltage

60

VS= 2.7V
C

= 0pF

50

L

R

=

∞

L

40

30

20

10

0

–10

OPEN-LOOP GAIN (dB)

–20

–30

–40

10k 100k 1M 10M 100M

01104-014

FREQUENCY (Hz)

0

45

90

135

180

225

270

PHASE SHIF T (Degrees)

01104-017

Figure 17. Open-Loop Gain and Phase Shift vs. Frequency

60

V

= 5V

S

C

= 0pF

50

L

R

=

∞

L

40

30

20

10

0

–10

OPEN-LOOP GAIN (dB)

–20

–30

–40

10k 100k 1M 10M 100M

01104-015

FREQUENCY (Hz)

0

45

90

135

180

225

270

PHASE SHIFT (Degrees)

01104-018

Figure 18. Open-Loop Gain and Phase Shift vs. Frequency

Rev. D | Page 7 of 24

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60

50

40

AV = 100

30

20

= 10

A

V

10

0

AV = 1

–10

CLOSED-LOOP GAIN (dB)

–20

–30

–40

100 10k1k 1M100k 10M

FREQUENCY (Hz)

Figure 19. Closed-Loop Gain vs. Frequency

V

S

C

L

R

L

= 2.7V

= 20pF
= 2kΩ

01104-019

300

VS= 5V

270

240

210

180

150

120

90

OUTPUT IMPEDANCE (Ω)

60

30

0

100 10 k1k 10M

FREQUENCY (Hz)

AV = 100

AV = 10

AV = 1

Figure 22. Output Impedance vs. Frequency

1M100k

01104-022

60

50

40

AV = 100

30

20

A

= 10

V

10

0

AV = 1

–10

CLOSED-LOOP GAIN (dB)

–20

–30

–40

100 10k1k 1M100k 10M

FREQUENCY (Hz)

Figure 20. Closed-Loop Gain vs. Frequency

300

VS= 2.7V

270

240

210

180

150

120

90

OUTPUT IM PEDANCE (Ω)

60

30

0

100 10k1k 10M

FREQUENCY (Hz)

AV = 100

AV = 10

AV = 1

Figure 21. Output Impedance vs. Frequency

V
C
R

1M100k

= 5V

S

= 20pF

L

= 2kΩ

L

VS = 2.7V
C

= 300pF

L

R

= 2kΩ

L

A

= 1

V

2µs 500mV

01104-020

1104-023

Figure 23. Large Signal Transient Response

VS = 5V
C

= 300pF

L

R

= 2kΩ

L

A

= 1

V

5µs 1V

1104-021

01104-024

Figure 24. Large Signal Transient Response

Rev. D | Page 8 of 24

AD8571/AD8572/AD8574

V

V

www.BDTIC.com/ADI

VS = ±1.35V
C

= 50pF

L

R

=

∞

L

AV = 1

5µs 50 mV

Figure 25. Small Signal Transient Response

VS = ±2.5V
C

= 50pF

L

R

=

∞

L

AV = 1

01104-025

45

VS = ±2.5V
R

= 2kΩ

L

40

T

= 25°C

A

35

30

25

20

15

10

SMALL SIGNAL OVERSHOOT (%)

5

0

10 100 1k 10k

CAPACITANCE (pF )

+OS

–OS

Figure 28. Small Signal Overshoot vs. Load Capacitance

V

OUT

0V

IN

VS = ±2.5V
V

= –200mV p-p

IN

(RET TO GND)

C

= 0pF

L

R

= 10kΩ

L

A

= –100

V

01104-028

5µs 50mV

Figure 26. Small Signal Transient Response

50

VS = ±1.35V

45

R

= 2kΩ

L

T

= 25°C

A

40

35

30

25

20

15

10

SMALL SIGNAL OVERSHOOT (%)

5

0

0

10 100 1k 10k

CAPACITANCE (pF)

+OS

–OS

Figure 27. Small Signal Overshoot vs. Load Capacitance

0V

1104-026

BOTTOM SCALE: 1V/DIV
TOP SCALE: 200mV/DIV

20µs 1V

1104-029

Figure 29. Positive Overvoltage Recovery

V

IN

0V

VS = ±2.5V
V

= 200mV p-p

IN

(RET TO GND)

C

= 0pF

L

R

= 10kΩ

L

A

= –100

V

0V

OUT

20µs

BOTTOM SCALE: 1V/DIV

01104-027

TOP SCALE : 200mV/DIV

1V

01104-030

Figure 30. Negative Overvoltage Recovery

Rev. D | Page 9 of 24

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140

120

100

PSRR (dB)

VS = ±1.35V

80

60

40

20

0

100 10k1k 1M100k 10M

–PSRR +PSRR

FREQUENCY (Hz)

Figure 34. PSRR vs. Frequency

140

VS = ±2.5V

120

100

80

+PSRR

01104-034

140

120

100

VS = ±2.5V
R

= 2kΩ

L

A

= –100

V

V

= 60mV p-p

IN

200µs

1V

01104-031

Figure 31. No Phase Reversal

VS = 2.7V

80

60

CMRR (dB)

40

20

0

100 10k1k 1M100k 10M

FREQUENCY (Hz)

Figure 32. CMRR vs. Frequency

140

120

100

CMRR (dB)

VS = 5V

80

60

40

20

0

100 10k1k 10M

FREQUENCY (Hz)

Figure 33. CMRR vs. Frequency

60

PSRR (dB)

40

20

0

100 10k1k 10M

01104-032

–PSRR

FREQUENCY (Hz)

1M100k

01104-035

Figure 35. PSRR vs. Frequency

3.0

2.5
VS = ±1.35V

R

= 2kΩ

L

A

= 1

V

THD + N < 1%

2.0
T

= 25°C

A

1.5

1.0

OUTPUT SWING (V p-p)

0.5

1M100k

01104-033

0

100 10k1k 100k 1M

FREQUENCY (Hz)

01104-036

Figure 36. Maximum Output Swing vs. Frequency

Rev. D | Page 10 of 24

AD8571/AD8572/AD8574

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5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

OUTPUT SWING (V p-p)

1.5

1.0

0.5

0

100 10k1k 100k 1M

FREQUENCY (Hz)

Figure 37. Maximum Output Swing vs. Frequency

VS = ±2.5V
R

= 2kΩ

L

A

= 1

V

THD + N < 1%
T

= 25°C

A

364

312

260

208

n (nV/ Hz)

e

156

104

52

0 0.5 1.0 1.5 2.0 2.5

01104-037

FREQUENCY (kHz)

VS = 2.7V
R

= 0Ω

S

1104-040

Figure 40. Voltage Noise Density from 0 Hz to 2.5 kHz

VS = ±1.35V
A

= 120,000

V

0

1sec

50mV

1104-038

Figure 38. 0.1 Hz to 10 Hz Noise

VS = ±2.5V
A

= 120,000

V

112

96

80

64

n (nV/ Hz)

e

48

32

16

0 5 10 15 20 25

FREQUENCY (kHz)

Figure 41. Voltage Noise Density from 0 Hz to 25 kHz

182

156

130

104

n (nV/ Hz)

e

78

VS = 5V
R

= 0Ω

S

VS = 2.7V
R

= 0Ω

S

01104-041

52

1sec

Figure 39. 0.1 Hz to 10 Hz Noise

50mV

01104-039

26

0 0.5 1.0 1.5 2.0 2.5

Figure 42. Voltage Noise Density from 0 Hz to 2.5 kHz

Rev. D | Page 11 of 24

FREQUENCY (kHz)

01104-042

AD8571/AD8572/AD8574

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150

112

96

80

64

n (nV/ Hz)

e

48

VS = 5V
R

= 0Ω

S

VS = 2.7V TO 5.5V

145

140

135

32

16

0 5 10 15 20 25

FREQUENCY (kHz)

Figure 43. Voltage Noise Density from 0 Hz to 25 kHz

210

180

150

120

n (nV/ Hz)

e

90

60

30

05

FREQUENCY (Hz)

VS = 5V
R

= 0Ω

S

Figure 44. Voltage Noise Density from 0 Hz to 10 Hz

POWER SUPPLY REJECTION (dB)

01104-043

OUTPUT SHO RT-CIRCUIT CURRENT (mA)

10

01104-044

130

125

–75 –50 –25 0 25 50 75 100 125 150

TEMPERATURE ( °C)

Figure 45. Power Supply Rejection vs. Temperature

50

VS = 2.7V

40

30

20

10

0

–10

–20

–30

–40

–50

–75 –50 –25 0 25 50 75 100 125 150

TEMPERATURE (° C)

I

SC–

I

SC+

Figure 46. Output Short-Circuit Current vs. Temperature

01104-045

01104-046

Rev. D | Page 12 of 24

AD8571/AD8572/AD8574

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100

VS = 5V

80

60

40

20

0

–20

–40

–60

–80

OUTPUT SHO RT-CIRCUIT CURRENT (mA)

–100

–75 –50 –25 0 25 50 75 100 125 150

TEMPERATURE ( °C)

I

I

Figure 47. Output Short-Circuit Current vs. Temperature

250

VS = 2.7V

225

200

175

150

125

100

75

OUTPUT VOLTAGE (mV)

50

25

0

–75 –50 –25 0 25 50 75 100 125 150

RL = 10kΩ

TEMPERATURE ( °C)

= 1kΩ

R

L

RL= 100kΩ

Figure 48. Output Voltage to Supply Rail vs. Temperature

SC–

SC+

01104-047

01104-048

250

VS = 5V

225

200

175

150

125

100

75

OUTPUT VOLTAGE (mV)

50

25

0

–75 –50 –25 0 25 50 75 100 125 150

= 10kΩ

R

L

TEMPERATURE ( °C)

RL = 1kΩ

R

L

Figure 49. Output Voltage to Supply Rail vs. Temperature

= 100kΩ

01104-049

Rev. D | Page 13 of 24

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FUNCTIONAL DESCRIPTION

The AD8571/AD8572/AD8574 are CMOS amplifiers that
achieve their high degree of precision through random frequency
auto-zero stabilization. The autocorrection topology allows the
AD857x to maintain its low offset voltage over a wide temperature
range, and the randomized auto-zero clock eliminates any inter­modulation distortion (IMD) errors at the amplifier output.

The AD857x can run from a single-supply voltage as low as 2.7 V.
The extremely low offset voltage of 1 µV and no IMD products
allow the amplifier to be easily configured for high gains without
risk of excessive output voltage errors, which makes the AD857x
an ideal amplifier for applications requiring both dc precision
and low distortion for ac signals. The extremely small temperature
drift of 5 nV/°C ensures a minimum of offset voltage error over
its −40°C to +125°C temperature range. These combined features
make the AD857x an excellent choice for a variety of sensitive
measurement and automotive applications.

AMPLIFIER ARCHITECTURE

Each AD857x op amp consists of two amplifiers: a main amplifier
and a secondary amplifier that is used to correct the offset voltage
of the main amplifier. Both consist of a rail-to-rail input stage,
allowing the input common-mode voltage range to reach both
supply rails. The input stage consists of an NMOS differential
pair operating concurrently with a parallel PMOS differential
pair. The outputs from the differential input stages are combined in
another gain stage whose output is used to drive a rail-to-rail
output stage.

The wide voltage swing of the amplifier is achieved by using two
output transistors in a common-source configuration. The output
voltage range is limited by the drain-to-source resistance of
these transistors. As the amplifier is required to source or sink
more output current, the voltage drop across these transistors
increases due to their on resistance (R
voltage does not swing as close to the rail under heavy output
current conditions as it does with light output current. This is a
characteristic of all rail-to-rail output amplifiers. Figure 12 and
Figure 13 show how close the output voltage can get to the rails
with a given output current. The output of the AD857x is short­circuit protected to approximately 50 mA of current.

The AD857x amplifiers have exceptional gain, yielding greater
than 120 dB of open-loop gain with a load of 2 k. Because
the output transistors are configured in a common-source
configuration, the gain of the output stage, and thus the open­loop gain of the amplifier, is dependent on the load resistance.
Open-loop gain decreases with smaller load resistances, which
is another characteristic of rail-to-rail output amplifiers.

). Simply put, the output

DS

BASIC AUTO-ZERO AMPLIFIER THEORY

Autocorrection amplifiers are not a new technology. Various IC
implementations have been available for more than 15 years,
and some improvements have been made over time. The
AD857x design offers a number of significant performance
improvements over older versions while attaining a very
substantial reduction in device cost. This section offers a
simplified explanation of how the AD857x is able to offer
extremely low offset voltages and high open-loop gains.

As noted in the Amplifier Architecture section, each AD857x
op amp contains two internal amplifiers. One is used as the
primary amplifier, and the other as an autocorrection, or nulling,
amplifier. Each amplifier has an associated input offset voltage
that can be modeled as a dc voltage source in series with the
noninverting input. In Figure 50 and Figure 51, these are labeled as
V

and V

OSA

denotes the primary amplifier. The open-loop gain for the +IN
and −IN inputs of each amplifier is given as A
also have a third voltage input with an associated open-loop
gain of B

V

IN+

V

IN–

V

IN+

V

IN–

There are two modes of operation determined by the action of
two sets of switches in the amplifier: an auto-zero phase and an
amplification phase.

, where A denotes the nulling amplifier and B

OSB

. Both amplifiers

X

.

X

OSB

+

A

B

ΦA

ΦB

V

OSA

1

V

OA

+

A

ΦB

A

–B

A

ΦA

2

V

NA

Figure 50. Auto-Zero Phase of the Amplifier

OSB

+

A

B

ΦA

ΦB

V

OSA

V

OA

+

A

ΦB

A

–B

A

ΦA

V

NA

Figure 51. Output Phase of the Amplifier

V

OUT

B

B

C

M2

V

NB

C

M1

1104-050

V

OUT

B

B

C

M2

V

NB

C

M1

01104-051

Rev. D | Page 14 of 24

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(

)

−

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=

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=

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AUTO-ZERO PHASE

In this phase, all ΦAX switches are closed, and all ΦB switches
are open. Here, the nulling amplifier is taken out of the gain
loop by shorting its two inputs together. Of course, there is a
degree of offset voltage, shown as V

, inherent in the nulling

OSA

amplifier, that maintains a potential difference between the +IN
and −IN inputs. The nulling amplifier feedback loop is closed
through ΦA
amplifier and on C

, and V

2

appears at the output of the nulling

OSA

, an internal capacitor in the AD857x.

M1

Mathematically, this can be expressed in the time domain as

V

[t] = AAV

OA

[t] − BAVOA[t] (1)

OSA

This can also be expressed as

tVA

[]

OA

tV

[]

OSAA

(2)

B

+=1

A

The previous equations show that the offset voltage of the nulling
amplifier times a gain factor appears at the output of the nulling
amplifier and thus on the C

capacitor.

M1

AMPLIFICATION PHASE

When the ΦB switches close and the ΦAX switches open for
the amplification phase, the offset voltage remains on CM1 and
essentially corrects any error from the nulling amplifier. The
voltage across C
between the two inputs to the primary amplifier is designated as

, or VIN = (V

V

IN

can then be expressed as

[t] = AA(VIN[t] − V

V

OA

Because ΦA
discharge, the voltage (V
the voltage at the output of the nulling amp (V

is closed. If the period of the autocorrection switching

ΦA

X

frequency is designated as T
phases every 0.5 × T

[]

and substituting Equation 4 and Equation 2 into Equation 3 yields

[] [] []

is designated as VNA. The potential difference

M1

− V

IN+

is now open and there is no place for CM1 to

X

AOA

). The output of the nulling amplifier

IN−

[t]) − BAVNA[t] (3)

OSA

) at the present time (t) is equal to

NA

) at the time when

OA

, the amplifier switches between

S

. Therefore, in the amplification phase

S

1

⎡
⎢

⎣

⎤

−=

(4)

TtVtV

SNANA

⎥

2

⎦

⎡
⎢

−+=

IN

tVAtVAtV

OSAA

⎣

1

+

B

A

−

1

⎤

TtVBA

SOSAAA

⎥

2

⎦

(5)

Rev. D | Page 15 of 24

For the sake of simplification, it can be assumed that the auto­correction frequency is much faster than any potential change
in V

or V

OSA

. This is a good assumption because changes in

OSB

offset voltage are a function of temperature variation or long­term wear time, both of which are much slower than the
auto-zero clock frequency of the AD857x, which effectively
makes the V

time invariant, and Equation 5 can be rewritten as

OS

[] []

tVAtV

IN

AOA

+

1

+=

B

1

+

VBAVBA

OSAAAOSAAA

A

(6)

or

⎛
⎜

[] []

tVAtV

+=

IN

AOA

⎜
⎝

1

Here, the auto-zeroing becomes apparent. Note that the V
term is reduced by a factor of 1 + B

⎞

V

OSA

⎟

(7)

⎟

B

+

A

⎠

, which shows how the

A

OS

nulling amplifier has greatly reduced its own offset voltage error
even before correcting the primary amplifier. Therefore, the
primary amplifier output voltage is the voltage at the output of the
AD857x amplifier. It is equal to

V

[t] = AB(VIN[t] + V

OUT

In the amplification phase, V

tV

]

OUT

[] []

BINB

OSB

) + BBVNB (8)

OSB

= VNB, so this can be rewritten as

OA

⎡

⎛
⎜

+++

⎢

B

⎢

⎣

tVABVAtVA

IN

A

⎜
⎝

⎤

(9)

⎞

V

OSA

⎟

⎥

⎟

+

B

1

⎥

A

⎠

⎦

Combining terms yield

]

tV

OUT

VBA

B

OSA

()

[]

BAAtV

BIN

A

A

++

B

1

+

B

+

A

(10)

VA

B

OSB

The AD857x architecture is optimized in such a way that
A

= AB, BA = BB, and BA >> 1. In addition, the gain product to

A

A

is much greater than AB. Therefore, Equation 10 can be

ABB

simplified to

[t] = VIN[t]AABA + AA(V

V

OUT

OSA

+ V

) (11)

OSB

Most obvious is the gain product of both the primary and nulling
amplifiers. This A
high open-loop gain. To understand how V

term is what gives the AD857x its extremely

ABA

and V

OSA

OSB

relate to
the overall effective input offset voltage of the complete amplifier,
set up the generic amplifier equation of

= k × (VIN + V

V

OUT

) (12)

OS, EFF

where:

k is the open-loop gain of an amplifier.
V

is its effective offset voltage.

OS, EFF

Putting Equation 12 into the form of Equation 11 gives

V

[t] = VIN[t]AABA + V

OUT

OS, EFFAABA

(13)

AD8571/AD8572/AD8574

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V

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Therefore,

VVV+

OSBOSA

≈

EFFOS

,

B

(14)

A

Thus, the offset voltages of both the primary and nulling
amplifiers are reduced by the gain factor B

, which takes a typical

A

input offset voltage from several millivolts down to an effective
input offset voltage of submicrovolts. This autocorrection scheme
makes the AD857x family of amplifiers extremely precise.

HIGH GAIN, CMRR, AND PSRR

Common-mode and power supply rejection are indications of the
amount of offset voltage an amplifier has as a result of a change in
its input common-mode or power supply voltages. As shown in
the Amplification Phase section, the autocorrection architecture
of the AD857x allows it to effectively minimize offset voltages.
The technique also corrects for offset errors caused by common­mode voltage swings and power supply variations, which results
in superb CMRR and PSRR figures in excess of 130 dB. Because
the autocorrection occurs continuously, these figures can be
maintained across the temperature range of the device (−40°C
to +125°C).

MAXIMIZING PERFORMANCE THROUGH PROPER LAYOUT

To achieve the maximum performance of the extremely high
input impedance and low offset voltage of the AD857x, care
should be taken in the circuit board layout. The PCB surface
must remain clean and free of moisture to avoid leakage currents
between adjacent traces. Surface coating of the circuit board
reduces surface moisture and provides a humidity barrier, reducing
parasitic resistance on the board. The use of guard rings around
the amplifier inputs further reduces leakage currents. Figure 52
shows how the guard ring should be configured, and Figure 53
shows the top view of how a surface-mount layout can be
arranged. The guard ring does not need to be a specific width,
but it should form a continuous loop around both inputs. By
setting the guard ring voltage equal to the voltage at the non­inverting input, parasitic capacitance is minimized as well. For
further reduction of leakage currents, components can be mounted
to the PCB using Teflon® standoff insulators.

V

V

IN

AD8572

V

IN

OUT

V

IN

AD8572

V

OUT

AD8572

Figure 52. Guard Ring Layout and Connections to

Reduce PCB Leakage Currents

V

OUT

+

R2 R1

V

IN2

GUARD
RING

V

REF

01104-053

IN1

GUARD
RING

R1 R2

V

REF

AD8572

V–

Figure 53. Top View of AD8572 SOIC Layout with Guard Rings

Other potential sources of offset error are thermoelectric
voltages on the circuit board. This voltage, also called Seebeck
voltage, occurs at the junction of two dissimilar metals and is
proportional to the junction temperature. The most common
metallic junctions on a circuit board are solder-to-board trace
and solder-to-component lead. Figure 54 shows a cross-section
view of the thermal voltage error sources. When the temperature
of the PCB at one end of the component (T
temperature at the other end (T

), the Seebeck voltages are not

A2

) differs from the

A1

equal, resulting in a thermal voltage error.

This thermocouple error can be reduced by using dummy
components to match the thermoelectric error source. Placing
the dummy component as close as possible to its partner ensures
that both Seebeck voltages are equal, thus canceling the thermo­couple error. Maintaining a constant ambient temperature on the
circuit board further reduces this error. The use of a ground
plane helps distribute heat throughout the board and also
reduces EMI noise pickup.

COMPONENT

LEAD

SOLDER

V

SC1

TS1

+

–

COPPER

TRACE

+

–

T

A1

SURFACE MOUNT

COMPO NENT

PC BOARD

IF TA1≠ TA2, THEN
V

TS1 +VSC1

V

SC2

+

–

V

TS2

+

–

T

A2

≠ V

TS2 +VSC2

01104-054

Figu re 54. Mismatch in Seebeck Voltages Causes a Thermoelectric Voltage Error

R

F

R1

V

V

IN

RS SHOULD BE PLACED IN CLOSE PROXIMIT Y AND
ALIGNMENT TO R1 TO BALANCE SEEBECK VOL TAGES

RS = R1

AD8571/AD8572/
AD8574

AV= 1 + (RF/R1)

OUT

01104-055

Figu re 55. Using Dummy Components to Cancel Thermoelectric Voltage Errors

01104-052

Rev. D | Page 16 of 24

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1/f NOISE CHARACTERISTICS

Another advantage of auto-zero amplifiers is their ability to
cancel flicker noise. Flicker noise, also known as 1/f noise, is
noise inherent in the physics of semiconductor devices and
increases 3 dB for every octave decrease in frequency. The 1/f
corner frequency of an amplifier is the frequency at which the
flicker noise is equal to the broadband noise of the amplifier.
At lower frequencies, flicker noise dominates, causing higher
degrees of error for sub-Hertz frequencies or dc precision
applications.

Because the AD857x amplifiers are self-correcting op amps,
they do not have increasing flicker noise at lower frequencies. In
essence, low frequency noise is treated as a slowly varying offset
error and is greatly reduced with autocorrection. The correction
becomes more effective as the noise frequency approaches dc,
offsetting the tendency of the noise to increase exponentially as
frequency decreases, which allows the AD857x to have lower
noise near dc than standard low noise amplifiers that are
susceptible to 1/f noise.

RANDOM AUTO-ZERO CORRECTION ELIMINATES INTERMODULATION DISTORTION

The AD857x can be used as a conventional op amp for gains up
to 1 MHz. The auto-zero correction frequency of the device
continuously varies, based on a pseudorandom generator with a
uniform distribution from 2 kHz to 4 kHz. The randomization
of the autocorrection clock creates a continuous randomization
of IMD products that show up as simple broadband noise at the
output of the amplifier. This broadband noise naturally combines
with the amplifier voltage noise in a root-squared-sum fashion,
resulting in an output free IMD. Figure 56 shows the spectral
output of an AD8572 with the amplifier configured for unity
gain and the input grounded. Figure 57 shows the spectral
output with the amplifier configured for a gain of 60 dB.

0

= 5V

V

–20

–40

A

S

= 0dB

V

0

= 5V

V

S

A

–20

–40

–60

OUTPUT SIGNAL

–80

–100

–120

012345678910

Figure 57. Spectral Analysis of AD857x Output with 60 dB Gain

FREQUENCY (kHz)

= 60dB

V

01104-057

Figure 58 shows the spectral output of an AD8572 configured in
a high gain (60 dB) with a 1 mV input signal applied. Note the
absence of any IMD products in the spectrum. The signal-to­noise ratio (SNR) of the output signal is better than 60 dB, or 0.1%.

0

VS = 5V
A

= 60dB

–20

–40

–60

OUTPUT SIGNAL

–80

–100

–120

012345678910

Figure 58. Spectral Analysis of AD8572 in High Gain with an Input Signal

FREQUENCY (kHz)

V

01104-058

–60

–80

–100

OUTPUT SI GNAL

–120

–140

–160

12345678910

Figure 56. Spectral Analysis of AD8572 Output in Unity Gain Configuration

FREQUENCY (kHz)

01104-056

Rev. D | Page 17 of 24

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BROADBAND AND EXTERNAL RESISTOR NOISE CONSIDERATIONS

The total broadband noise output from any amplifier is primarily a
function of three types of noise: input voltage noise from the
amplifier, input current noise from the amplifier, and Johnson
noise from the external resistors used around the amplifier.
Input voltage noise, or e

, is strictly a function of the amplifier

n

used. The Johnson noise from a resistor is a function of the
resistance and the temperature. Input current noise, or i

,

n

creates an equivalent voltage noise proportional to the resistors
used around the amplifier. These noise sources are not correlated
with each other and their combined noise sums in a root­squared-sum fashion. The full equation is given as

e

n, TOTAL

2

= [e

+ 4kTrs + (inrs)2]

n

1/2

(15)

where:

e

is the input voltage noise of the amplifier.

n

i

is the input current noise of the amplifier.

n

is the source resistance connected to the noninverting

r

s

terminal.
k is Boltzmann’s constant (1.38 × 10

−23

J/K).

T is the ambient temperature in Kelvin (K = 273.15 + °C).

The input voltage noise density, e
and the input noise, i

, is 2 fA/√Hz. The e

n

, of the AD857x is 51 nV/√Hz,

n

is dominated by

n, TOTAL

the input voltage noise provided that the source resistance is less
than 172 k. With source resistance greater than 172 k, the
overall noise of the system is dominated by the Johnson noise of
the resistor itself.

Because the input current noise of the AD857x is very small, i
does not become a dominant term unless r

> 4 G, which is an

s

n

impractical value of source resistance.

The total noise, e

, is expressed in volts-per-square-root

n, TOTAL

Hertz, and the equivalent rms noise over a certain bandwidth
can be found as

= e

e

n

× BW (16)

n, TOTAL

The output overdrive recovery for an autocorrection amplifier is
defined as the time it takes for the output to correct to its final
voltage from an overload state. It is measured by placing the
amplifier in a high gain configuration with an input signal that
forces the output voltage to the supply rail. The input voltage is
then stepped down to the linear region of the amplifier, usually
to halfway between the supplies. The time from the input signal
step-down to the output settling to within 100 µV of its final
value is the overdrive recovery time. Many autocorrection
amplifiers require a number of auto-zero clock cycles to recover
from output overdrive, and some can take several milliseconds
for the output to settle properly.

INPUT OVERVOLTAGE PROTECTION

Although the AD857x are rail-to-rail input amplifiers, care
should be taken to ensure that the potential difference between
the inputs does not exceed 5 V. Under normal operating conditions,
the amplifier corrects its output to ensure that the two inputs
are at the same voltage. However, if the device is configured as
a comparator, or is under some unusual operating condition, the
input voltages may be forced to different potentials, which could
cause excessive current to flow through the internal diodes in the
AD857x used to protect the input stage against overvoltage.

If either input exceeds either supply rail by more than 0.3 V,
large amounts of current begin to flow through the ESD
protection diodes in the amplifier. These diodes are connected
between the inputs and each supply rail to protect the input
transistors against an electrostatic discharge event and are
normally reverse-biased. However, if the input voltage exceeds
the supply voltage, these ESD diodes become forward-biased.
Without current-limiting, excessive amounts of current can
flow through these diodes, causing permanent damage to the
device. If inputs are subject to overvoltage, appropriate series
resistors should be inserted to limit the diode current to less
than 2 mA.

where BW is the bandwidth of interest in Hertz.

OUTPUT OVERDRIVE RECOVERY

The AD857x amplifiers have an excellent overdrive recovery
of only 200 µs from either supply rail. This characteristic is
particularly difficult for autocorrection amplifiers because the
nulling amplifier requires a substantial amount of time to error
correct the main amplifier back to a valid output. Figure 29 and
Figure 30 show the positive and negative overdrive recovery
times for the AD857x.

OUTPUT PHASE REVERSAL

Output phase reversal occurs in some amplifiers when the input
common-mode voltage range is exceeded. As common-mode
voltage moves outside the common-mode range, the outputs of
these amplifiers suddenly jump in the opposite direction to
the supply rail. This is the result of the differential input pair
shutting down, causing a radical shifting of internal voltages
that results in the erratic output behavior.

The AD857x amplifier has been carefully designed to prevent
any output phase reversal, provided that both inputs are
maintained within the supply voltages. If one or both inputs
exceed either supply voltage, a resistor should be placed in
series with the input to limit the current to less than 2 mA to
ensure that the output does not reverse its phase.

Rev. D | Page 18 of 24

AD8571/AD8572/AD8574

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CAPACITIVE LOAD DRIVE

The AD857x have excellent capacitive load driving capabilities
and can safely drive up to 10 nF from a single 5 V supply.
Although the device is stable, capacitive loading limits the
bandwidth of the amplifier. Capacitive loads also increase the
amount of overshoot and ringing at the output. The RC snubber
network shown in Figure 59 can be used to reduce the capacitive
load ringing and overshoot.

5V

–

V

IN

200mV p-p

Figure 59. Snubber Network Configuration for Driving Capacitive Loads

+

Although the snubber network does not recover the loss of
amplifier bandwidth from the load capacitance, it does allow
the amplifier to drive larger values of capacitance while
maintaining a minimum of overshoot and ringing. Figure 60
shows the output of an AD857x driving a 1 nF capacitor with
and without a snubber network.

AD8571/
AD8572/
AD8574

Rx
60Ω

Cx

0.47µF

C

L

4.7nF

V

OUT

01104-059

The optimum value for the resistor and capacitor is a function
of the load capacitance and is best determined empirically
because actual C

includes stray capacitances and can differ

L

substantially from the nominal capacitive load. Table 5 shows
some snubber network values that can be used as starting points.

Table 5. Snubber Network Values for Driving Capacitive Loads

CL (nF) Rx (Ω) Cx

1 200 1 nF

4.7 60 0.47 µF
10 20 10 µF

POWER-UP BEHAVIOR

At power-up, the AD857x settles to a valid output within 5 s.
Figure 61 shows an oscilloscope photo of the output of the
amplifier along with the power supply voltage. Figure 62 shows
the test circuit. With the amplifier configured for unity gain, the
device takes approximately 5 µs to settle to its final output
voltage, hundreds of microseconds faster than many other
autocorrection amplifiers.

10μs

WITH

NUBBER

WITHOUT

NUBBER

VS = 5V
C

= 4.7nF

L

Figure 60. Overshoot and Ringing Are Substantially Reduced Using

a Snubber Network

100mV

OUT

0V

V+

0V

5µs

BOTTOM TRACE = 2V/DI V
TOP TRACE = 1V/DIV

01104-060

Figure 61. AD857x Output Behavior at Power-Up

1V

01104-061

AD8571/
AD8572/
AD8574

VSY= 0V TO 5

V

OUT

1104-062

100kΩ

100kΩ

Figure 62. AD857x Test Circuit for Power-Up Time

Rev. D | Page 19 of 24

AD8571/AD8572/AD8574

(

)

+

A

www.BDTIC.com/ADI

APPLICATIONS INFORMATION

5 V PRECISION STRAIN GAGE CIRCUIT

The extremely low offset voltage of the AD8572 makes it an ideal
amplifier for any application requiring accuracy with high gains,
such as a weigh scale or strain gage. Figure 63 shows a configura­tion for a single-supply, precision strain gage measurement system.

The REF192 provides a 2.5 V precision reference voltage for A2.
The A2 amplifier boosts this voltage to provide a 4.0 V reference
for the top of the strain gage resistor bridge. Q1 provides the
current drive for the 350  bridge network. A1 is used to amplify
the output of the bridge with the full-scale output voltage equal to

2R1R +×2

(17)

B

where R

R

is the resistance of the load cell.

B

Using the values given in Figure 63, the output voltage linearly
varies from 0 V with no strain to 4 V under full strain.

Q1

2N2222

OR

EQUIVALENT

4.0V

350Ω

LOAD

CELL

NOTE:
USE 0.1% TOL ERANCE RESIST ORS.

1kΩ

AD8572-B

12kΩ

40mV

FULL-SCALE

Figure 63. 5 V Precision Strain Gage Amplifier

5V

A2

R1

17.4kΩ

R3

17.4kΩ

2.5V

20kΩ

R2

100Ω

A1

AD8572-A

R4

100Ω

6

2

REF192

4

V
0V TO 4V

OUT

3

01104-063

3 V INSTRUMENTATION AMPLIFIER

The high common-mode rejection, high open-loop gain,
and operation down to 3 V of the supply voltage make the
AD857x family an excellent op amp choice for discrete single­supply instrumentation amplifiers. The common-mode
rejection ratio of the AD857x is greater than 120 dB, but the
CMRR of the system is also a function of the external resistor
tolerances. The gain of the difference amplifier shown in Figure 64
is given as

⎞

⎛

OUT

⎛

⎛

=

1VV

⎜
⎝

⎞

4R

⎜

⎟

+

4R3R

⎝

⎠

⎞

1R

−

+

1 (18)

⎟

2R

⎠

2R

2V

⎟

⎜

1R

⎠

⎝

V2

V1

Figure 64. Using the AD857x as a Difference Amplifier

R1

R3

R4

R4

R2 R2

IF = , THEN V

R1 R1

R3

In an ideal difference amplifier, the ratio of the resistors is set
equal to

4R

2R

A

V

== (19)

3R

1R

Set the output voltage of the system to

V

= AV (V1 − V2) (20)

OUT

Due to finite component tolerance, the ratio between the four
resistors is not exactly equal, and any mismatch results in a
reduction of common-mode rejection from the system. Referring
to Figure 64, the exact common-mode rejection ratio can be
expressed as

= (21)

CMRR

2

In the 3-op amp instrumentation amplifier configuration shown
in Figure 65, the output difference amplifier is set to unity gain
with all four resistors equal in value. If the tolerance of the
resistors used in the circuit is given as δ, the worst-case CMRR
of the instrumentation amplifier is

MIN

2R
R

1

δ=2

D8574-A

R

R

AD8574-B

(V1 – V2)

G

CMRR (22)

V2

R

G

V1

V

= 1 +

OUT

Figure 65. Discrete Instrumentation Amplifier Configuration

Therefore, using 1% tolerance resistors results in a worst-case
system CMRR of 0.02, or 34 dB. To achieve high common­mode rejection, either high precision resistors or an additional
trimming resistor, as shown in Figure 65, should be used. The value
of this trimming resistor should be equal to the value of R
multiplied by its tolerance. For example, using 10 k resistors
with 1% tolerance would require a series trimming resistor
equal to 100 .

R2

V

AD8571/
AD8572/
AD8574

(V1 – V2)

=

OUT

R2R3R2R41R4R

+

R2R3R1R4

22

−

R

R

R

R

TRIM

OUT

R

AD8574-C

01104-064

V

OUT

01104-065

Rev. D | Page 20 of 24

AD8571/AD8572/AD8574

T

V

www.BDTIC.com/ADI

HIGH ACCURACY THERMOCOUPLE AMPLIFIER

Figure 66 shows a K-type thermocouple amplifier configuration
with cold-junction compensation. Even from a 5 V supply, the
AD8571 can provide enough accuracy to achieve a resolution of
better than 0.02°C from 0°C to 500°C. D1 is used as a tempera­ture measuring device to correct the cold-junction error from
the thermocouple and should be placed as close as possible to
the two terminating junctions. With the thermocouple measuring
tip immersed in a 0°C ice bath, R6 should be adjusted until the
output is at 0 V.

Using the values shown in Figure 66, the output voltage tracks
temperature at 10 mV/°C. For a wider range of temperature
measurement, R9 can be decreased to 62 kΩ. This creates a
5 mV/°C change at the output, allowing measurements of up
to 1000°C.

12V

0.1µF

K-TYPE

HERMOCOUPLE

40.7µV/°C

Figure 66. Precision K-Type Thermocouple Amplifier

REF02EZ

2

1N4148

D1

–

+–+

5.62kΩ

with Cold-Junction Compensation

4

10.7kΩ

2.74kΩ

R4

5V

6

R5

200Ω

R3

53.6Ω

40.2kΩ

R8

453Ω

R6

R1

R2

R9

124kΩ

5V

10µF

+

0.1µF

2

7

3

6

AD8571

4

0V TO 5V
(0°C TO 500°C)

PRECISION CURRENT METER

Because of its low input bias current and superb offset voltage at
single-supply voltages, the AD857x family is an excellent amplifier
for precision current monitoring. Its rail-to-rail input allows the
amplifier to be used as either a high-side or a low-side current
monitor. Using both amplifiers in the AD8572 provides a simple
method to monitor both current supply and return paths for
load or fault detection.

Figure 67 shows a high-side current monitor configuration.
Here, the input common-mode voltage of the amplifier is at or
near the positive supply voltage. The rail-to-rail input of the
amplifier provides a precise measurement, even with the input
common-mode voltage at the supply voltage. The CMOS input
structure does not draw any input bias current, ensuring a
minimum of measurement error.

01104-066

Using the components shown in Figure 67, the monitor output
transfer function is 2.49 V/A.

R

V+

MONITOR

OUTPUT

100Ω

M1

Si9433

SENSE

0.1Ω

R1

S

G

D

R2

2.49kΩ

3

+

AD8572

2

–

1/2

I

L

V+

0.1µF

8

4

LOAD

1

01104-067

Figure 67. High-Side Load Current Monitor

Figure 68 shows the low-side monitor equivalent. In this circuit,
the input common-mode voltage to the AD8572 is at or near
ground. Again, a 0.1  resistor provides a voltage drop propor­tional to the return current. The output voltage is given as

R

2

⎛

VOutputMonitor

⎜

+

⎝

SENSE

R

1

⎞

IR

(24)

××−=

⎟

L

⎠

For the component values shown in Figure 68, the monitor
output transfer function is V+ − 2.49 V/A.

+

R2

R1

100Ω

Q1

2.49kΩ

R

SENSE

0.1Ω

2

3

I

V+

L

1/2 AD8572

V+

LOAD

01104-068

MONITOR

OUTPUT

Figure 68. Low-Side Load Current Monitor

PRECISION VOLTAGE COMPARATOR

The AD857x can be operated open loop and used as a precision
comparator. The AD857x have less than 50 µV of offset voltage
when they run in this configuration. The slight increase of
offset voltage stems from the fact that the autocorrection
architecture operates with the lowest offset in a closed-loop
configuration, that is, one with negative feedback. With 50 mV
of overdrive, the device has a propagation delay of 15 µs on the
rising edge and 8 µs on the falling edge.

The 0.1  resistor creates a voltage drop to the noninverting
input of the AD857x. The output of the amplifier is corrected
until this voltage appears at the inverting input, which creates a
current through R1 that in turn flows through R2. The monitor
output is given by

Monitor Output = R2 × (R

/R1) × IL (23)

SENSE

Rev. D | Page 21 of 24

Care should be taken to ensure that the maximum differential
voltage of the device is not exceeded. For more information, see
the Input Overvoltage Protection section.

AD8571/AD8572/AD8574

Y

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

3.20

3.00

2.80

8

5

4

SEATING
PLANE

5.15

4.90

4.65

1.10 MAX

0.23

0.08

8°
0°

3.20

3.00

1

2.80

PIN 1

0.65 BSC

0.95

0.85

0.75

0.15

0.38

0.00

0.22

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 69. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

0.80

0.60

0.40

0.15

0.05

COPLANARIT

0.10

Figure 71. 8-Lead Thin Shrink Small Outline Package [TSSOP]

3.10

3.00

2.90

8

5

4.50

6.40 BSC

4.40

4.30

41

PIN 1

0.65 BSC

1.20
MAX

0.30
SEATING

0.19

PLANE

COMPLIANT TO JEDEC STANDARDS MO-153-AA

0.20

0.09

8°
0°

(RU-8)

Dimensions shown in millimeters

0.75

0.60

0.45

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARI TY

0.10

CONTROL LING DIMENSI ONS ARE IN MILL IMET ERS; INCH DI MENSIO NS
(IN PARENTHESES ) ARE ROUNDED- OFF MI LLI METER EQ UIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE I N DESIG N.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLI ANT TO JEDE C STANDARDS MS-012-A A

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

Figure 70. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

5.10

5.00

4.90

14

4.50

4.40

4.30

PIN 1

1.05

1.00

0.80

012407-A

0.65
BSC

0.15

0.05

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

0.30

0.19

8

6.40
BSC

71

1.20
MAX

SEATING
PLANE

0.20

0.09

COPLANARITY

0.10

8°
0°

0.75

0.60

0.45

Figure 72. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

Rev. D | Page 22 of 24

AD8571/AD8572/AD8574

www.BDTIC.com/ADI

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARIT Y

0.10

CONTROLL ING DIMENSIONS ARE IN MILLIMETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-O FF MIL LIMETE R EQUIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

8.75 (0.3445)

8.55 (0.3366)

BSC

8

7

6.20 (0.2441)

5.80 (0.2283)

1.75 (0.0689)

1.35 (0.0531)

SEATING
PLANE

0.25 (0.0098)

0.17 (0.0067)

14

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-012-AB

0.50 (0.0197)

0.25 (0.0098)

8°
0°

1.27 (0.0500)

0.40 (0.0157)

45°

060606-A

Figure 73. 14-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-14)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD8571AR −40°C to +125°C 8-Lead SOIC_N R-8
AD8571AR-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8571AR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
AD8571ARZ
AD8571ARZ-REEL
AD8571ARZ-REEL7
AD8571ARM-R2 −40°C to +125°C 8-Lead MSOP RM-8 AJA
AD8571ARM-REEL −40°C to +125°C 8-Lead MSOP RM-8 AJA
AD8571ARMZ-R2
AD8571ARMZ-REEL
AD8572AR −40°C to +125°C 8-Lead SOIC_N R-8
AD8572AR-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8572AR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
AD8572ARZ
AD8572ARZ-REEL
AD8572ARZ-REEL7
AD8572ARU −40°C to +125°C 8-Lead TSSOP RU-8
AD8572ARU-REEL −40°C to +125°C 8-Lead TSSOP RU-8
AD8572ARUZ1 −40°C to +125°C 8-Lead TSSOP RU-8
AD8572ARUZ-REEL1 −40°C to +125°C 8-Lead TSSOP RU-8
AD8574AR −40°C to +125°C 14-Lead SOIC_N R-14
AD8574AR-REEL −40°C to +125°C 14-Lead SOIC_N R-14
AD8574AR-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14
AD8574ARZ1 −40°C to +125°C 14-Lead SOIC_N R-14
AD8574ARZ-REEL1 −40°C to +125°C 14-Lead SOIC_N R-14
AD8574ARZ-REEL71 −40°C to +125°C 14-Lead SOIC_N R-14
AD8574ARU −40°C to +125°C 14-Lead TSSOP RU-14
AD8574ARU-REEL −40°C to +125°C 14-Lead TSSOP RU-14
AD8574ARUZ1 −40°C to +125°C 14-Lead TSSOP RU-14
AD8574ARUZ-REEL1 −40°C to +125°C 14-Lead TSSOP RU-14

1

Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked.

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead MSOP RM-8 AJA#

1

−40°C to +125°C 8-Lead MSOP RM-8 AJA#

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead SOIC_N R-8

Rev. D | Page 23 of 24

AD8571/AD8572/AD8574

www.BDTIC.com/ADI

NOTES

©1999–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01104-0-6/08(D)

Rev. D | Page 24 of 24