Datasheet AD8564 Datasheet (ANALOG DEVICES)

Quad 7 ns

www.BDTIC.com/ADI

FEATURES

5 V single-supply operation
7 ns propagation delay
Low power
Separate input and output sections
TTL/CMOS logic-compatible outputs
Wide output swing
TSSOP, SOIC, and PDIP packages

APPLICATIONS

High speed timing
Line receivers
Data communications
High speed V-to-F converters
Battery operated instrumentation
High speed sampling systems
Window comparators
PCMCIA cards
Upgrade for MAX901 designs

Single Supply Comparator

AD8564

PIN CONFIGURATIONS

–IN A
+IN A

GND

OUT A
OUT B

V

–ANA

+IN B
–IN B

116

AD8564

89

Figure 1. 16-Lead TSSOP

U-16)

(R

–IN A
+IN A

GND
OUT A
OUT B

V

–ANA

+IN B
–IN B

AD8564

Figure 2. 16-Lead Narrow Body SOIC

(R

-16)

1

–IN A

2

+IN A

GND

OUT A

V

–ANA

+IN B
–IN B

3

4

5

6

7
8

–

+

AD8564

–

+

Figure 3. 16-Lead PDIP

(N-16)

–IN D
+IN D
V

+ANA

OUT D
OUT C
V

+DIG

+IN C
–IN C

1103-003

–IN D
+IN D
V

+ANA

OUT D
OUT C

V

+DIG

+IN C
–IN C

01103-001

16

–IN D

15

+IN D

–

+

V

14

+ANA

13

OUT D

12

OUT COUT B
V

11

+DIG

–

+

+IN C

10

–IN C

9

01103-002

GENERAL DESCRIPTION

The AD8564 is a quad 7 ns comparator with separate input and
output supplies, thus enabling the input stage to be operated
from ±5 V dual supplies or a 5 V single supply while maintaining a
CMOS-/TTL-compatible output.

Fast 7 ns propagation delay makes the AD8564 a good choice
for

timing circuits and line receivers. Independent analog and
digital supplies provide excellent protection from supply pin
interaction. The AD8564 is pin compatible with the MAX901
and has lower supply currents.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

All four comparators have similar propagation delays. The

ropagation delay for rising and falling signals is similar, and

p
tracks over temperature and voltage. These characteristics make
the AD8564 a good choice for high speed timing and data
communications circuits. For a similar single comparator with
latch function, refer to the

The AD8564 is specified over the industrial temperature range

°C to +125°C). The quad AD8564 is available in the 16-lead

(−40
TSSOP, 16-lead narrow body SOIC, and 16-lead plastic DIP
packages.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©1999–2007 Analog Devices, Inc. All rights reserved.

AD8561 data sheet.

AD8564

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features.............................................................................................. 1

ESD Caution...................................................................................5

Applications....................................................................................... 1

Pin Configurations ........................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Specifications............................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

REVISION HISTORY

8/07—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Applications .................................................................. 1

Changes to General Description .................................................... 1

Changes to Specifications................................................................ 3

Changes to the Absolute Maximum Ratings Section .................. 5

Changes to the Applications Information Section....................... 9

Deleted Spice Model Section......................................................... 11

Updated Outline Dimensions....................................................... 12

Changes to Ordering Guide.......................................................... 13

Typical Performance Characteristics..............................................6

Applications Information.................................................................9

Optimizing High Speed Performance........................................9

Output Loading Considerations..................................................9

Input Stage and Bias Currents .....................................................9

Using Hysteresis ......................................................................... 10

Outline Dimensions....................................................................... 11

Ordering Guide .......................................................................... 12

6/99—Rev. 0 to Rev. A

Rev. B | Page 2 of 12

AD8564

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SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

V

= V

+ANA

= 5.0 V, V

+DIG

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS 2.3 7 mV

−40°C ≤ TA ≤ +125°C
Offset Voltage Drift ΔVOS/ΔT 4 μV/°C
Input Bias Current IB VCM = 0 V ±4 μA

−40°C ≤ TA ≤ +125°C
Input Offset Current IOS VCM = 0 V ±3 μA
Input Common-Mode Voltage Range VCM 0 2.75 V
Common-Mode Rejection Ratio CMRR 0 V ≤ VCM ≤ 3.0 V 65 85 dB
Large Signal Voltage Gain A
Input Capacitance CIN 3.0 pF

DIGITAL OUTPUTS

Logic 1 Voltage VOH IOH = −3.2 mA, ΔVIN > 250 mV 2.4 3.5 V
Logic 0 Voltage VOL IOL = 3.2 mA, VIN > 250 mV 0.3 0.4 V

DYNAMIC PERFORMANCE2

Propagation Delay tP 200 mV step with 100 mV overdrive 6.75 9.8 ns

−40°C ≤ TA ≤ +125°C1 13 ns
100 mV step with 5 mV overdrive 8 ns
Differential Propagation Delay (Rising Propagation Delay vs.

Falling Propagation Delay)
Rise Time 20% to 80% 3.8 ns
Fall Time 20% to 80% 1.5 ns

POWER SUPPLY

Power Supply Rejection Ratio PSRR 4.5 V ≤ V
Analog Supply Current I

−40°C ≤ TA ≤ +85°C

−40°C ≤ TA ≤ +125°C1 17 mA
Digital Supply Current I

−40°C ≤ TA ≤ +125°C1 8.0 mA
Analog Supply Current I

−40°C ≤ TA ≤ +85°C1 15.6 mA

−40°C ≤ TA ≤ +125°C1 17 mA

1

Full electrical specifications to −55°C, but these package types are guaranteed for operation from −40°C to +125°C only. Package reliability below −40°C is not guaranteed.

2

Guaranteed by design.

= 0 V, TA = 25°C, unless otherwise noted.

−ANA

1

1

R

VO

Δt

100 mV step with 20 mV overdrive 0.5 2.0 ns

P

10.5 14.0 mA

+ANA

VO = 0 V, RL = ∞ 6.0 7.0 mA

DIG

–7.0 +14.0 mA

−ANA

= 10 kΩ 3000 V/V

L

+ANA

and V

≤ 5.5 V 80 dB

+DIG

1

8 mV

±9 μA

15.6 mA

Rev. B | Page 3 of 12

AD8564

www.BDTIC.com/ADI

V

= V

+ANA

= 5.0 V, V

+DIG

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS 2.3 7 mV

−40°C ≤ TA ≤ +125°C
Offset Voltage Drift ΔVOS/ΔT 4 μV/°C
Input Bias Current IB VCM = 0 V ±4 μA

−40°C ≤ TA ≤ +125°C
Input Offset Current IOS VCM = 0 V ±3 μA
Input Common-Mode Voltage Range VCM −4.9 +3.5 V
Common-Mode Rejection Ratio CMRR 0 V ≤ VCM ≤ 3.0 V 65 85 dB
Large Signal Voltage Gain AVO RL = 10 kΩ 3000 V/V
Input Capacitance CIN 3.0 pF

DIGITAL OUTPUTS

Logic 1 Voltage VOH IOH = –3.2 mA, ΔVIN > +250 mV 2.6 3.6 V
Logic 0 Voltage VOL IOL = 3.2 mA, ΔVIN > 250 mV 0.2 0.3 V

DYNAMIC PERFORMANCE2

Propagation Delay tP 200 mV step with 100 mV overdrive 6.75 9.8 ns

−40°C ≤ TA ≤ +85°C1 8 13 ns
100 mV step with 5 mV overdrive 8 ns
Differential Propagation Delay (Rising Propagation Delay

vs. Falling Propagation Delay)
Rise Time 20% to 80% 3 ns
Fall Time 20% to 80% 3 ns

POWER SUPPLY

Power Supply Rejection Ratio PSRR 4.5 V ≤ V
Analog Supply Current I

−40°C ≤ TA ≤ +85°C1 15.6 mA

−40°C ≤ TA ≤ +125°C
Digital Supply Current I

−40°C ≤ TA ≤ +125°C1 5.6 mA
Analog Supply Current I

−40°C ≤ TA ≤ +85°C1 15.6 mA

−40°C ≤ TA ≤ +125°C1 17 mA

1

Full electrical specifications to −55°C, but these package types are guaranteed for operation from −40°C to +125°C only. Package reliability below −40°C is not guaranteed.

2

Guaranteed by design.

= −5 V, TA = 25°C, unless otherwise noted.

−ANA

Δt

+ANA

DIG

−ANA

1

1

100 mV step with 20 mV overdrive 0.5 2.0 ns

P

+ANA

and V

≤ 5.5 V 50 70 dB

+DIG

10 mV

±9 μA

10.8 14.0 mA

1

17 mA

VO = 0 V, RL = ∞ 3.6 4.4 mA

−8.2 +14.0 mA

Rev. B | Page 4 of 12

AD8564

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ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Total Analog Supply Voltage 14 V
Digital Supply Voltage 17 V
Analog Positive Supply to Digital Positive Supply −600 mV
Input Voltage1 ±7 V
Differential Input Voltage ±8 V
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −55°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature Range (Soldering, 10 sec) 300°C

1

The analog input voltage is equal to ±7 V or the analog supply voltage,

whichever is less.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages (SOIC
and TSSOP). θ

Table 4. Thermal Resistance

Package Type θJA θ

16-Lead PDIP (N) 90 47 °C/W
16-Lead Narrow Body SOIC (R) 113 37 °C/W
16-Lead TSSOP (RU) 180 37 °C/W

is specified for device in socket for PDIP.

JA

Unit

JC

ESD CAUTION

Rev. B | Page 5 of 12

AD8564

G
A

A

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TYPICAL PERFORMANCE CHARACTERISTICS

V

= V

+ANA

1.0

+DIG

= 5 V, V

= 0 V, TA = 25°C, unless otherwise noted.

–ANA

500

0.8

0.6

0.4

INPUT OFFSET VOLTAGE (mV)

0.2

0

–75 –50 –25 0 25 50 75 100 125 150

TEMPERATURE (°C)

Figure 4. Input Offset Voltage vs. Temperature

0

–1

–2

–3

INPUT BIAS CURRENT (µA)

–4

400

300

200

NUMBER OF AMP LIFIERS

100

0

–5 –4 –3 –2 –1 0 1 2 3 4

01103-004

INPUT OFFSET VOLTAGE (mV)

5

01103-007

Figure 7. Input Offset Voltage Distribution

10

8

Y (ns)

6

TION DEL

4

PROPA

2

t

PDHL

t

PDLH

STEPSIZE = 100mV
OVERDRIVE = 5 mV

–5

–75 –50 –25 0 25 50 75 100 125 150

TEMPERATURE (°C)

Figure 5. Input Bias Current vs. Temperature

0

V

= V

+ANA

V

–ANA

–1

–2

–3

INPUT BIAS CURRE NT (µA)

–4

–5

–7.5 –5.0 –2.5 0 2.5 5.0

= +5V

+DIG

= –5V

INPUT COMMON-MODE VOLTAGE (V)

Figure 6. Input Bias Current vs. Input Common-Mode Voltage

0

01103-005

–50 –25 0 25 50 75 100 125

Figure 8. Propagation Delay, t

5.0

4.4

3.8

3.2

OUTPUT HIGH VOLTAGE (mV)

2.6

2.0

01103-006

036912

Figure 9. Output High Voltage, V

TEMPERATURE (°C)

TA = +85°C

= +25°C

T

A

T

= –40°C

A

SOURCE CURRENT (mA)

vs. Temperature

PDHL/tPDLH

vs. Source Current

OH

01103-008

15

01103-009

Rev. B | Page 6 of 12

AD8564

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0.5

3.0

0.4

= +25°C

T

0.3

0.2

OUTPUT LOW VOLTAGE (V)

0.1

0

0 3 6 9 12 15

A

Figure 10. Output Low Voltage, V

5

4

3

2

SUPPLY CURRENT (mA)

+ANA

I

1

= –40°C

T

A

TA = +85°C

SINK CURRENT (mA)

OL

TA = +85°C

T

= +25°C

A

= –40°C

T

A

vs. Sink Current

2.5

2.0
T

= +25°C

1.5

1.0

SUPPLY CURRENT (mA)

+DIG

I

0.5

0

2 4 6 8 10 12

01103-010

Figure 13. I

5

4

3

2

SUPPLY CURRENT (mA)

+ANA

I

1

Supply Current/Comparator vs. V

+DIG

A

V

SUPPLY VOLTAGE (V)

+DIG

V

= ±5V

+ANA

V

+ANA

T

T

= +5V

= +85°C

A

= –40°C

A

Supply Voltage

+DIG

01103-013

0

2468101

Figure 11. I

Figure 12. I

+ANA

0

–1

–2

–3

SUPPLY CURRENT (mA)

–ANA

I

–4

–5

2 4 6 8 10 12

−ANA

V

SUPPLY VOLTAGE (V)

+ANA

Supply Current/Comparator vs. V

T

= –40°C

A

= +25°C

T

A

= +85°C

T

A

V

SUPPLY VOLTAGE (V)

–ANA

Supply Current/Comparator vs. V

Supply Voltage

+ANA

Supply Voltage

−ANA

2

01103-011

01103-012

0

–75 –50 –25 0 25 50 75 100 125 150

Figure 14. I

0

–1

–2

–3

SUPPLY CURRENT (mA)

–ANA

I

–4

–5

–75 –50 –25 0 25 50 75 100 125 150

Figure 15. I

+ANA

−ANA

TEMPERATURE (°C)

Supply Current/Comparator vs. Temperature

V

= +5V

+ANA

V

= ±5V

+ANA

TEMPERATURE (°C)

Supply Current/Comparator vs. Temperature

01103-014

01103-015

Rev. B | Page 7 of 12

AD8564

www.BDTIC.com/ADI

2.0

1.5

1.0

SUPPLY CURRENT (mA)

0.5

+DIG

I

0

–75 –50 –25 0 25 50 75 100 125 150

Figure 16. I

+DIG

TEMPERATURE (°C)

Supply Current/Comparator vs. Temperature

01103-016

Rev. B | Page 8 of 12

AD8564

www.BDTIC.com/ADI

APPLICATIONS INFORMATION

OPTIMIZING HIGH SPEED PERFORMANCE

As with any high speed comparator or amplifier, proper design
and layout techniques should be used to ensure optimal perform­ance from the AD8564. The performance limits of high speed
circuitry can easily be a result of stray capacitance, improper
ground impedance, or other layout issues.

Minimizing resistance from the source to the input is an important

nsideration in maximizing the high speed operation of the

co
AD8564. Source resistance, in combination with equivalent
input capacitance, may cause a lagged response at the input,
thus delaying the output. The input capacitance of the AD8564,
in combination with stray capacitance from an input pin to
ground, may result in several picofarads of equivalent capaci­tance. A combination of 3 kΩ source resistance and 5 pF of
input capacitance yields a time constant of 15 ns, which is slower
than the 5 ns capability of the AD8564. Source impedances
should be less than 1 kΩ for the best performance.

It is also important to provide bypass capacitors for the power
su

pply in a high speed application. A 1 μF electrolytic bypass
capacitor should be placed within 0.5 inches of each power
supply pin to ground. These capacitors reduce any potential
voltage ripples from the power supply. In addition, a 10 nF
ceramic capacitor should be placed as close as possible to the
power supply pins to ground. These capacitors act as a charge
reservoir for the device during high frequency switching.

OUTPUT LOADING CONSIDERATIONS

The AD8564 output can deliver up to 40 mA of output current
without any significant increase in propagation delay. The
output of the device should not be connected to more than 20
TTL input logic gates or drive a load resistance less than 100 Ω.

To ensure the best performance from the AD8564, it is important
to

minimize capacitive loading of the output of the device.
Capacitive loads greater than 50 pF cause ringing on the output
waveform and reduce the operating bandwidth of the comparator.
Propagation delay also increases with capacitive loads above 100 pF.

INPUT STAGE AND BIAS CURRENTS

The AD8564 uses a PNP differential input stage that enables the
input common-mode range to extend all the way from the
negative supply rail to within 2.2 V of the positive supply rail.
The input common-mode voltage can be found as the average
of the voltage at the two inputs of the device. To ensure the
fastest response time, care should be taken to not allow the
input common-mode voltage to exceed this voltage.

The input bias current for the AD8564 is 4 μA. As with any

NP differential input stage, this bias current goes to 0 on an

P
input that is high and doubles on an input that is low. Care should
be taken in choosing resistor values to be connected to the
inputs because large resistors could cause significant voltage
drops due to the input bias current.

A ground plane is recommended for proper high speed perform­an

ce. This can be created by using a continuous conductive plane
over the surface of the circuit board, only allowing breaks in the
plane for necessary current paths. The ground plane provides a
low inductance ground, eliminating any potential differences at
different ground points throughout the circuit board caused
from ground bounce. A proper ground plane also minimizes
the effects of stray capacitance on the circuit board.

The input capacitance for the AD8564 is typically 3 pF. This can
b

e measured by inserting a large source resistance to the input

and measuring the change in propagation delay.

Rev. B | Page 9 of 12

AD8564

V

(

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USING HYSTERESIS

Hysteresis can easily be added to a comparator through the
addition of positive feedback. Adding hysteresis to a comparator
offers an advantage in noisy environments where it is not desirable
for the output to toggle between states when the input signal is
near the switching threshold.

nfiguring the AD8564 with hysteresis.

co

SIGNAL

REF

Figure 17. Configuring the AD8564 with Hysteresis

The input signal is connected directly to the inverting input of
the comparator. The output is fed back to the noninverting
input through R2 and R1. The ratio of R1 to R1 + R2 and the
output swing establishes the width of the hysteresis window,
with V

setting the center of the window or the average

REF

switching voltage. The output switches high when the input

Figure 17 shows a method for

COMPARATOR

R1

R2

C

F

01103-017

voltage is greater than V
the input voltage is less than V

1

+

⎛
⎜

VV

1

REF

LO

where

V

+

The C

capacitor may also be added to introduce a pole into

F

⎜
⎝

is the positive supply voltage.

the feedback network. This has the effect of increasing the
amount of hysteresis at high frequencies. This can be useful
when comparing a relatively slow signal in a high frequency
noise environment.

At frequencies greater than

window approaches

At frequencies less than
in Equation 1.

and does not switch low again until

HI

, as given in Equation 2.

LO

R1

)

VVV

−−=

V

HI

R2R1

+

⎞

R1

⎟

(2)

⎟

+−=R2R1

⎠

f

P

= V+ – 1 V and VLO = 0 V.

f

, the threshold voltages remain as it is

P

(1)

V

REFREFHI

1

, the hysteresis

R2C

π=2

F

Rev. B | Page 10 of 12

AD8564

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.800 (20.32)

0.790 (20.07)

0.780 (19.81)

0.210 (5.33)

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

16

1

0.100 (2.54)
BSC

MAX

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

CONTRO LLING DIME N S IONS ARE IN INCHES ; MIL LIMETER DIM ENSIO NS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS F OR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIG URE D AS WHOLE OR HALF LEADS.

Figure 18. 16-Lead Plastic Dual In-Line Package [PDIP]

9

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

8

0.060 (1.52)

0.015
(0.38)

0.015 (0.38)

MIN

SEATING
PLANE

0.005 (0.13)
MIN

COMPLIANT TO JEDEC STANDARDS MS-001-AB

GAUGE

PLANE

MAX

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.430 (10.92)

(N-16)

Dim

ensions shown in inches and (millimeters)

MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

073106-B

10.00 (0.3937)

9.80 (0.3858)

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIME NSIONS ARE IN MIL LIMETERS ; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OF F MILLIMETER EQ UIVALENTS FOR
REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DE S IGN.

16

1

1.27 (0.0500)
BSC

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-012-AC

9

6.20 (0.2441)

5.80 (0.2283)

8

1.75 (0.0689)

1.35 (0.0531)

SEATING
PLANE

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0197)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

45°

060606-A

Figure 19. 16-Lead Standard Small Outline Package [SOIC_N]

Nar

row Body

(R-16)

Dimensions shown in millimeters and (inches)

Rev. B | Page 11 of 12

AD8564

www.BDTIC.com/ADI

4.50

4.40

4.30

PIN 1

0.15

0.05

0.65
BSC

Figure 20. 16-Lead Thin Shrink S

5.10

5.00

4.90

16

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40
BSC

0.20

0.09

mall Outline Package [TSSOP]

8°
0°

0.75

0.60

0.45

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8564AN −40°C to +125°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
AD8564ANZ
AD8564AR −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_N]
AD8564AR-REEL −40°C to +125°C 16-Lead Standar
AD8564AR-REEL7 −40°C to +125°C 16-Lead Standar
AD8564ARZ
AD8564ARZ-REEL
AD8564ARZ-REEL7
AD8564ARU-REEL −40°C to +125°C 16-Lead Thin Shr
AD8564ARUZ-REEL

1

Z = RoHS Compliant Part.

1

−40°C to +125°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
R-16

d Small Outline Package [SOIC_N] R-16
d Small Outline Package [SOIC_N] R-16

1

−40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_N] R-16

1

−40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_N] R-16

1

−40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_N] R-16

ink Small Outline Package [TSSOP] RU-16

1

−40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16

©1999–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01103-0-8/07(B)

Rev. B | Page 12 of 12