Datasheet AD8564 Datasheet (Analog Devices)

Quad 7 ns

–IN A
+IN A

GND
OUT A
OUT B

V

–ANA

+IN B

–IN B

–IN D

+IN D
V

+ANA

OUT D
OUT C
V

+DIG

+IN C
–IN C

AD8564

+IN A

GND

OUT A

+IN D
V

+ANA

OUT D

–IN D

1

89

16

AD8564

–IN A

V

+DIG

+IN C
–IN C

OUT C

V

–ANA

+IN B
–IN B

OUT B

a

FEATURES
+5 V Single-Supply Operation
7 ns Propagation Delay
Low Power
Separate Input and Output Sections
TTL and CMOS Logic Compatible Outputs
Wide Output Swing
TSSOP, SOIC and PDIP Packages

APPLICATIONS
High Speed Timing
Line Receivers
Data Communications
High Speed V-to-F Converters
Battery Operated Instrumentation
High Speed Sampling Systems
Window Comparators
Read Channel Detection
PCMCIA Cards
Upgrade for MAX901 Designs

Single Supply Comparator

PIN CONFIGURATIONS

16-Lead Narrow Body SO

(S Suffix)

R-16A

16-Lead TSSOP

(RU-Suffix)

RU-16

AD8564

16-Lead Epoxy DIP

(P Suffix)

N-16

–IN A

1

+IN A

GND

OUT A

V

–ANA

+IN B

–IN B

2

+–

3

4

5

6

+–

7

8

AD8564

–

+

+–

16

15

14

13

12

11

10

9

–IN D

+IN D

V

+ANA

OUT D

OUT COUT B

V

+DIG

+IN C

–IN C

GENERAL DESCRIPTION

The AD8564 is quad 7 ns comparator with separate input and
output supplies, thus enabling the input stage to be operated
from ±5 V dual supplies or a +5 V single supply while maintain­ing a CMOS/TTL-compatible output.

Fast 7 ns propagation delay makes the AD8564 a good choice
for timing circuits and line receivers. Independent analog and
digital supplies provide excellent protection from supply pin
interaction. The AD8564 is pin compatible with the MAX901,
and has lower supply currents.

All four comparators have similar propagation delays. The
propagation delay for rising and falling signals is similar, and
tracks over temperature and voltage. These characteristics
make the AD8564 a good choice for high speed timing and data
communications circuits. For a similar dual comparator with a
latch function, please see the AD8598 data sheet. For a similar
single comparator with latch function, please see the AD8561
data sheet.

The AD8564 is specified over the industrial (–40°C to +85°C)
temperature range. The quad AD8564 is available in the 16­lead plastic DIP, narrow SO-16 surface mount, and 16-lead
TSSOP packages.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD8564–SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

(@ V

+ANA

= V

= +5.0 V, V

+DIG

= 0 V, TA = +25ⴗC unless otherwise noted)

–ANA

Parameter Symbol Conditions Min Typ Max Units

INPUT CHARACTERISTICS

Offset Voltage V

OS

–40°C ≤ T

Offset Voltage Drift ∆V
Input Bias Current I

Input Offset Current I
Input Common-Mode Voltage Range V

/∆T4µV/°C

OS

B

I

B

OS

CM

VCM = 0 V ±4 µA
–40°C ≤ TA ≤ +85°C ±9 µA
VCM = 0 V ±3 µA

Common-Mode Rejection Ratio CMRR 0 V ≤ V
Large Signal Voltage Gain A
Input Capacitance C

VO

IN

RL = 10 kΩ 3000 V/V

≤ +85°C8mV

A

0 +2.75 V

≤ +3.0 V 65 85 dB

CM

2.3 7 mV

3.0 pF

DIGITAL OUTPUTS

Logic “1” Voltage V
Logic “0” Voltage V

OH

OL

IOH = –3.2 mA, ∆VIN > 250 mV 2.4 3.5 V
IOL = 3.2 mA, ∆VIN > 250 mV 0.3 0.4 V

DYNAMIC PERFORMANCE

Propagation Delay t

Propagation Delay t

P

P

200 mV Step with 100 mV Overdrive 6.75 9.8 ns
–40°C ≤ T

≤ +85°C

A

100 mV Step with 5 mV Overdrive

1

1

8ns

13 ns

Differential Propagation Delay

(Rising Propagation Delay vs.

Falling Propagation Delay) ∆t

P

100 mV Step with 20 mV Overdrive

1

0.5 2.0 ns

Rise Time 20% to 80% 3.8 ns

Fall Time 20% to 80% 1.5 ns

POWER SUPPLY

Power Supply Rejection Ratio PSRR +4.5 V ≤ V
Analog Supply Current I

+ANA

–40°C ≤ T

Digital Supply Current I

DIG

VO = 0 V, RL =
–40°C ≤ T

Analog Supply Current I

–ANA

and V

+ANA

≤ +85°C15.6mA

A

∞

≤ +85°C 8.0 mA

A

≤ +5.5 V 80 dB

+DIG

10.5 14.0 mA

6.0 7.0 mA

–7.0 14.0 mA

–40°C ≤ TA ≤ +85°C15.6mA

NOTES

1

Guaranteed by design.

Specifications subject to change without notice.

ELECTRICAL SPECIFICATIONS

(@ V

+ANA

= V

= +5.0 V, V

+DIG

= –5 V, TA = +25ⴗC unless otherwise noted)

–ANA

Parameter Symbol Conditions Min Typ Max Units

INPUT CHARACTERISTICS

Offset Voltage V

OS

–40°C ≤ T

Offset Voltage Drift ∆V
Input Bias Current I

Input Offset Current I
Input Common-Mode Voltage Range V

/∆T4µV/°C

OS

B

I

B

OS

CM

VCM = 0 V ±4 µA
–40°C ≤ TA ≤ +85°C ±9 µA
VCM = 0 V ±3 µA

Common-Mode Rejection Ratio CMRR 0 V ≤ V
Large Signal Voltage Gain A
Input Capacitance C

VO

IN

RL = 10 kΩ 3000 V/V

≤ +85°C8mV

A

–4.9 +3.5 V

≤ +3.0 V 65 85 dB

CM

2.3 7 mV

3.0 pF

DIGITAL OUTPUTS

Logic “1” Voltage V
Logic “0” Voltage V

OH

OL

IOH = –3.2 mA, ∆VIN > 250 mV 2.6 3.6 V
IOL = 3.2 mA, ∆VIN > 250 mV 0.2 0.3 V

–2–

REV. A

AD8564

WARNING!

ESD SENSITIVE DEVICE

Parameter Symbol Conditions Min Typ Max Units

DYNAMIC PERFORMANCE

Propagation Delay t

Propagation Delay t

P

P

Differential Propagation Delay

(Rising Propagation Delay vs.

Falling Propagation Delay) ∆t

P

Rise Time 20% to 80% 3 ns

Fall Time 20% to 80% 3 ns

POWER SUPPLY

Power Supply Rejection Ratio PSRR +4.5 V ≤ V
Analog Supply Current I

Digital Supply Current I

Analog Supply Current I

NOTES

1

Guaranteed by design.

Specifications subject to change without notice.

+ANA

DIG

–ANA

200 mV Step with 100 mV Overdrive 6.75 9.8 ns
–40°C ≤ T

≤ +85°C

A

100 mV Step with 5 mV Overdrive

100 mV Step with 20 mV Overdrive

+ANA

and V

1

1

1

≤ +5.5 V 50 70 dB

+DIG

813ns
8ns

0.5 2.0 ns

10.8 14.0 mA

–40°C ≤ T

≤ +85°C 15.6 mA

A

VO = 0 V, RL = ∞ 3.6 4.4 mA
–40°C ≤ T

≤ +85°C 5.6 mA

A

–8.2 14.0 mA

–40°C ≤ TA ≤ +85°C 15.6 mA

ABSOLUTE MAXIMUM RATINGS

Total Analog Supply Voltage . . . . . . . . . . . . . . . . . . . . . +14 V

Digital Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V

Analog Positive Supply–Digital Positive Supply . . . . . –600 mV

Input Voltage

1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ±8 V

Output Short-Circuit Duration to GND . . . . . . . . . Indefinite

Storage Temperature Range

N, R, RU Package . . . . . . . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Junction Temperature Range

N, R, RU Package . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering, 10 sec) . . . . . . . +300°C

ORDERING GUIDE

Temperature Package Package

Model Range Description Options

AD8564AN –40°C to +85°C 16-Lead Plastic DIP N-16
AD8564AR –40°C to +85°C 16-Lead Narrow Body SOIC R-16A
AD8564ARU –40°C to +85°C 16-Lead Thin Shrink Small Outline (TSSOP) RU-16

Package Type ␪

2

JA

␪

JC

Units

16-Lead Plastic DIP (N) 90 47 °C/W
16-Lead Narrow Body SO (R) 113 37 °C/W
16-Lead TSSOP (RU) 180 37 °C/W

NOTES

1

The analog input voltage is equal to ± 7 V or the analog supply voltage, whichever

is less.

2

θJA is specified for the worst case conditions, i.e., θ

for, P-DIP, and θ
TSSOP packages.

is specified for device soldered in circuit board for SOIC and

JA

is specified for device in socket

JA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8564 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–3–REV. A

AD8564

–Typical Performance Characteristics

(V

= V

+ ANA

= +5 V, V

+DIG

otherwise noted)

= 0 V, TA = +25ⴗC unless

– ANA

1.000

0.800

0.600

0.400

0.200

INPUT OFFSET VOLTAGE – mV

0.000

–75 –50 150

–25 0 25 75 100 12550

TEMPERATURE – ⴗC

Figure 1. Input Offset Voltage vs.
Temperature

500

400

300

200

NUMBER OF AMPLIFIERS

100

0.000

–1.000

–2.000

–3.000

–4.000

INPUT BIAS CURRENT – ␮A

–5.000

–75 –50 150

–25 0 25 75 100 12550

TEMPERATURE – ⴗC

Figure 2. Input Bias Current vs.
Temperature

PROPAGATION DELAY – ns

10

8

6

4

2

STEPSIZE = 100mV
OVERDRIVE = 5mV

t

PDHL

t

PDLH

0

–1

–2

–3

–4

INPUT BIAS CURRENT – ␮A

–5

–7.5 –55

INPUT COMMON-MODE VOLTAGE – V

V

= V
= –5V

+DIG

= +5V

+ANA

V

–ANA

–2.5 0 2.5

Figure 3. Input Bias Current vs. Input
Common-Mode Voltage

5.000

4.400

3.800

3.200

OUTPUT HIGH VOLTAGE – V

TA = –40ⴗC

2.600

TA = +85ⴗC

TA = +25ⴗC

0

–55–4 –3 –2 –101 2 34

INPUT OFFSET VOLTAGE – mV

Figure 4. Input Offset Voltage

0.500

0.400

0.300

0.200

0.100

OUTPUT LOW VOLTAGE – V

0.00
03 15

TA = –40ⴗC

69 12

SINK CURRENT – mA

TA = +25ⴗC

TA = +85ⴗC

Figure 7. Output Low Voltage, V
vs. Sink Current

OL

0

–50

–25 0 25 75 100 12550

TEMPERATURE – ⴗC

Figure 5. Propagation Delay, t

vs. Temperature

t

PDLH

5.000

4.000

TA = +85ⴗC

3.000

TA = +25ⴗC

2.000

, SUPPLY CURRENT – mA

1.000

+ANA

I

0.000
24 12

Figure 8. I

TA = –40ⴗC

6810

V

SUPPLY VOLTAGE – V

+

ANA

: Analog Supply Cur-

+ANA

PDHL

rent/Comparator vs. Supply Voltage

2.000
03 15

/

Figure 6. Output High Voltage, V

6912

SOURCE CURRENT – mA

OH

vs. Source Current

0.000

–1.000

–2.000

–3.000

, SUPPLY CURRENT – mA

–4.000

ANA

–

I

–5.000

24 12

Figure 9. I

TA = –40ⴗC

TA = +85ⴗC

6810

V

SUPPLY VOLTAGE – V

–

ANA

: Analog Supply Cur-

–ANA

TA = +25ⴗC

rent/Comparator vs. Supply Voltage

–4–

REV. A

AD8564

3.000

2.500

2.000

1.500

1.000

, SUPPLY CURRENT – mA

DIG
+

I

0.500

0.000
24 126810

Figure 10. I

TA = +25ⴗC

V+ SUPPLY VOLTAGE – V

: Digital Supply Cur-

+DIG

TA = +85ⴗC

TA = –40ⴗC

rent/Comparator vs. Supply Voltage

5.000

4.000

V

= ⴞ5V

+ANA

3.000

2.000

, SUPPLY CURRENT – mA

1.000

ANA
+

I

0

–75 –50 150

–25 0 25 75 100 12550

TEMPERATURE – ⴗC

Figure 11. I

+ANA

V

= +5V

+ANA

: Analog Supply Cur-

rent/Comparator vs. Temperature

2.000

1.500

1.000

0.000

–1.000

V

= +5V

–2.000

–3.000

, SUPPLY CURRENT – mA

–4.000

ANA

–

I

–5.000

–75 –50 150

Figure 12. I

+ANA

V

= ⴞ5V

+ANA

–25 0 25 75 100 12550

TEMPERATURE – ⴗC

: Analog Supply Cur-

–ANA

rent/Comparator vs. Temperature

, SUPPLY CURRENT – mA

0.500

DIG
+

I

0.000

–75 –50 150

–25 0 25 75 100 12550

TEMPERATURE – ⴗC

Figure 13. I

: Digital Supply Current/

+DIG

Comparator vs. Temperature

APPLICATIONS

OPTIMIZING HIGH SPEED PERFORMANCE

As with any high speed comparator or amplifier, proper design
and layout techniques should be used to ensure optimal perfor­mance from the AD8564. The performance limits of high speed
circuitry can easily be a result of stray capacitance, improper
ground impedance or other layout issues.

Minimizing resistance from source to the input is an important
consideration in maximizing the high speed operation of the
AD8564. Source resistance in combination with equivalent
input capacitance could cause a lagged response at the input,
thus delaying the output. The input capacitance of the AD8564
in combination with stray capacitance from an input pin to
ground could result in several picofarads of equivalent capaci­tance. A combination of 3 kΩ source resistance and 5 pF of
input capacitance yields a time constant of 15 ns, which is
slower than the 5 ns capability of the AD8564. Source imped­ances should be less than 1 kΩ for the best performance.

It is also important to provide bypass capacitors for the power
supply in a high speed application. A 1 µF electrolytic bypass
capacitor should be placed within 0.5 inches of each power
supply pin to ground. These capacitors will reduce any potential
voltage ripples from the power supply. In addition, a 10 nF
ceramic capacitor should be placed as close as possible from the

–5–REV. A

power supply pins to ground. These capacitors act as a charge
reservoir for the device during high frequency switching.

A ground plane is recommended for proper high speed perfor­mance. This can be created by using a continuous conductive
plane over the surface of the circuit board, only allowing breaks
in the plane for necessary current paths. The ground plane
provides a low inductance ground, eliminating any potential
differences at different ground points throughout the circuit
board caused from “ground bounce.” A proper ground plane
also minimizes the effects of stray capacitance on the circuit
board.

OUTPUT LOADING CONSIDERATIONS

The AD8564 output can deliver up to 40 mA of output current
without any significant increase in propagation delay. The out­put of the device should not be connected to more than twenty
(20) TTL input logic gates, or drive a load resistance less than
100 Ω.

To ensure the best performance from the AD8564 it is impor­tant to minimize capacitive loading of the output of the device.
Capacitive loads greater than 50 pF will cause ringing on the
output waveform and will reduce the operating bandwidth of
the comparator. Propagation delay will also increase with
capacitive loads above 100 pF.

AD8564

INPUT STAGE AND BIAS CURRENTS

The AD8564 uses a PNP differential input stage which enables
the input common-mode range to extend all the way from the
negative supply rail to within 2.2 V of the positive supply rail.
The input common-mode voltage can be found as the average of
the voltage at the two inputs of the device. To ensure the fastest
response time, care should be taken to not allow the input
common-mode voltage to exceed this voltage.

The input bias current for the AD8564 is 4 µA. As with any
PNP differential input stage, this bias current will go to zero on
an input that is high and will double on an input that is low.
Care should be taken in choosing resistor values to be connected
to the inputs as large resistors could cause significant voltage
drops due to the input bias current.

The input capacitance for the AD8564 is typically 3 pF. This is
measured by inserting a kΩ source resistance to the input and
measuring the change in propagation delay.

USING HYSTERESIS

Hysteresis can easily be added to a comparator through the
addition of positive feedback. Adding hysteresis to a comparator
offers an advantage in noisy environments where it is not desir­able for the output to toggle between states when the input
signal is near the switching threshold. Figure 14 shows a method
for configuring the AD8564 with hysteresis.

COMPARATOR

SIGNAL

The input signal is connected directly to the inverting input of
the comparator. The output is fed back to the noninverting
input through R2 and R1. The ratio of R1 to R1 + R2 estab­lishes the width of the hysteresis window with V

setting the

REF

center of the window, or the average switching voltage. The
output will switch high when the input voltage is greater than

and will not switch low again until the input voltage is less

V

HI

than V

Where V

The capacitor C

as given in Equation 1:

LO

VHI= V+–1–V

()

VLO=V

+



1–

REF



R1+ R2



is the positive supply voltage.

can also be added to introduce a pole into the

F

REF

R1

R1

R1+ R2






+V

REF

(1)

feedback network. This has the effect of increasing the amount
of hysteresis at high frequencies. This can be useful when com­paring a relatively slow signal in a high frequency noise environ-

1

ment. At frequencies greater than f

window approaches V
cies less than f

the threshold voltages remain as in Equation 1.

P

= V+ – 1 V and VLO = 0 V. At frequen-

HI

P

=

2π C

, the hysteresis

R2

F

V

REF

R1

R2

C

F

Figure 14. Configuring the AD8564 with Hysteresis

–6–

REV. A

Spice Model

* AD8564 SPICE Macro-Model Typical Values
* 8/98, Ver. 1.0
* TAM / ADSC
*
* Node assignments
* noninverting input
* | inverting input
* | | positive supply
* | | | negative supply
* ||||Output
* |||||
* |||||
* |||||
* |||||
.SUBCKT AD8564 1 2 99 50 45
*
* INPUT STAGE
*
*
Q1 435PIX
Q2 625PIX
IBIAS 99 5 800E-6
RC1 4 50 1k
RC2 6 50 1k
CL1 4 6 2.5E-12
CIN 1 2 3E-12
EOS 3 1 (4,6) 1E-3
*
* Reference Voltage
*
EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5
RDUM 98 0 100E3
GSY 99 50 POLY(1) (99,50) 8E-3 –2.6E-3
*
* Gain Stage Av=250 fp=100MHz
*
G1 98 20 (4.6) 0.25
R1 20 98 1E3
C1 20 98 16E-13
D1 20 21 DX
D2 22 20 DX
V1 99 21 DC 0.71
V2 22 50 DC 0.71
*
* Output Stage
*
Q3 99 41 46 NOX
Q4 47 42 50 NOX
RB1 43 41 200
RB2 40 42 200
CB1 99 41 10p
CB2 42 50 5p
RO1 46 45 2E3
RO2 47 45 500
EO1 98 43 POLY(1) (20,98) 0 1
EO2 40 98 POLY(1) (20,98) 0 1
*
* MODELS
*
.MODEL PIX PNP(BF=100,VAF=130,IS=1E-14)
.MODEL NOX NPN(BF=100,VAF=130,IS=1E-14)
.MODEL DX D(IS=1E-14,CJO=1E-15)

.ENDS AD8564

AD8564

REV. A

–7–

AD8564

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead Epoxy DIP

(N-16)

16-Lead Narrow Body SOIC

0.3937 (10.00)

0.3859 (9.80)

PLANE

0.0500
(1.27)

16 9

PIN 1

0.0192 (0.49)

0.0138 (0.35)

BSC

0.1574 (4.00)

0.1497 (3.80)

0.0098 (0.25)

0.0040 (0.10)

SEATING

16-Lead Thin Shrink Small Outline (TSSOP)

(RU-16)

(R-16A)

0.2440 (6.20)

81

0.2284 (5.80)

0.0688 (1.75)

0.0532 (1.35)

0.0099 (0.25)

0.0075 (0.19)

0.0196 (0.50)

0.0099 (0.25)

8ⴗ
0ⴗ

0.0500 (1.27)

0.0160 (0.41)

C3219a–2–6/99

ⴛ 45ⴗ

–8–

PRINTED IN U.S.A.

REV. A