Datasheet AD8557 Datasheet (ANALOG DEVICES)

Digitally Programmable

V

VOUT

www.BDTIC.com/ADI

FEATURES

Very low offset voltage: 12 μV maximum over temperature
Very low input offset voltage drift: 65 nV/°C maximum
High CMRR: 96 dB minimum
Digitally programmable gain and output offset voltage
Gain range from 28 to 1300
Single-wire serial interface
Stable with any capacitive load
SOIC_N and LFCSP_VQ packages

2.7 V to 5.5 V operation

APPLICATIONS

Automotive sensors
Pressure and position sensors
Precision current sensing
Thermocouple amplifiers
Industrial weigh scales
Strain gages

GENERAL DESCRIPTION

The AD8557 is a zero drift, sensor signal amplifier with digitally
programmable gain and output offset. Designed to easily and
accurately convert variable pressure sensor and strain bridge
outputs to a well-defined output voltage range, the AD8557
accurately amplifies many other differential or single-ended
sensor outputs. The AD8557 uses the Analog Devices, Inc.
patented low noise auto-zero and DigiTrim® technologies to
create an accurate and flexible signal processing solution in a
compact footprint.

Gain is digitally programmable in a wide range from 28 to 1300

hrough a serial data interface. Gain adjustment can be fully

t
simulated in circuit and then permanently programmed with
reliable polyfuse technology. Output offset voltage is also
digitally programmable and is ratiometric to the supply voltage.

In addition to extremely low input offset voltage and input

ffset voltage drift and very high dc and ac CMRR, the AD8557

o

Sensor Signal Amplifier

AD8557

FUNCTIONAL BLOCK DIAGRAM

DD

R6

VDD

A3

VSS

VCLAMP

A4

VSS

06013-001

VDD

VNEG

VPOS

A1

VSS

VDD

A2

VSS

P3

R4

R1

P1

R3

P2

R2

R5 R7

P4

VDD

DAC

VSS

Figure 1.

also includes a pull-up current source at the input pins and a
pull-down current source at the VCLAMP pin. Output
clamping set via an external reference voltage allows the
AD8557 to drive lower voltage ADCs safely and accurately.

When used in conjunction with an ADC referenced to the same

pply, the system accuracy becomes immune to normal supply

su
voltage variations. Output offset voltage can be adjusted with a
resolution of better than 0.4% of the difference between VDD
and VSS. A lockout trim after gain and offset adjustment
further ensures field reliability.

The AD8557 is fully specified from −40°C to +125°C.
O

perating from single-supply voltages of 2.7 V to 5.5 V, the
AD8557 is offered in an 8-lead SOIC_N, and a 4 mm × 4 mm,
16-lead LFCSP_VQ.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007–2008 Analog Devices, Inc. All rights reserved.

AD8557

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

REVISION HISTORY

1/08—Rev. 0 to Rev. A

Changes to Theory of Operation Section.................................... 14

Changes to Determining Optimal Gain and Offset
C

odes Section.................................................................................. 20

5/07—Revision 0: Initial Version

Typical Perf or m an c e Charac t e r istics ..............................................7

Theory of Operation ...................................................................... 14

Gain Values ................................................................................. 15

Open Wire Fault Detection....................................................... 16

Shorted Wire Fault Detection ................................................... 16

Floating VPOS, VNEG, or VCLAMP Fault Detection ......... 16

Device Programming................................................................. 16

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 21

Rev. A | Page 2 of 24

AD8557

www.BDTIC.com/ADI

SPECIFICATIONS

VDD = 5.0 V, VSS = 0.0 V, VCM = 2.5 V, VOUT = 2.5 V, gain = 28, TA = −40°C to +125°C, unless otherwise specified.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

INPUT STAGE

Input Offset Voltage VOS 2 12 V
Input Offset Voltage Drift TCV
Input Bias Current I
Input Offset Current I
Input Voltage Range 0.6 3.8 V
Common-Mode Rejection Ratio CMRR VCM = 0.9 V to 3.6 V, AV = 28 75 85 dB
V
Linearity VOUT = 0.2 V to 3.4 V 20 ppm
VOUT = 0.2 V to 4.8 V 1000 ppm
Differential Gain Accuracy Second stage gain = 10 to 70 1.6 %
Differential Gain Accuracy Second stage gain = 100 to 250 2.5 %
Differential Gain Temperature Coefficient Second stage gain = 10 to 250 15 40 ppm/°C

DAC

Accuracy Offset codes = 8 to 248 0.7 0.8 %
Ratiometricity Offset codes = 8 to 248 50 ppm
Output Offset Offset codes = 8 to 248 5 35 mV
Temperature Coefficient 20 80 ppm FS/°C

VCLAMP

Clamp Input Bias Current ICLAMP 1.25 V to 5.0 V 200 nA
Clamp Input Voltage Range 1.25 5.0 V

OUTPUT STAGE

Short-Circuit Current I
I
Output Voltage, Low V
Output Voltage, High V

POWER SUPPLY

Supply Current I

Power Supply Rejection Ratio PSRR VDD = 2.7 V to 5.5 V 105 125 dB

DYNAMIC PERFORMANCE

Gain Bandwidth Product GBP First gain stage, TA = 25°C 2 MHz
Second gain stage, TA = 25°C 8 MHz
Settling Time t

NOISE PERFORMANCE

Input Referred Noise f = 1 kHz, TA = 25°C 32 nV/√Hz
Low Frequency Noise en p-p f = 0.1 Hz to 10 Hz, TA = 25°C 0.5 µV p-p
Total Harmonic Distortion THD

DIGITAL INTERFACE

Input Current 2 µA
DIGIN Pulse Width to Load 0 tw
DIGIN Pulse Width to Load 1 tw
Time Between Pulses at DIGIN tw
DIGIN Low TA = 25°C 0.2 × VDD V
DIGIN High TA = 25°C 0.8 × VDD V
DIGOUT Logic 0 TA = 25°C 0.2 × VDD V
DIGOUT Logic 1 TA = 25°C 0.8 × VDD V

B

OS

SC

SC

OL

OH

SY

s

0

1

s

27 65 nV/°C

OS

10 18 25 nA
1 4 nA

= 0.9 V to 3.6 V, AV = 1300 96 112 dB

CM

Source −45 −25 mA
Sink 40 55 mA
RL = 10 kΩ to 5 V 30 mV
RL = 10 kΩ to 0 V 4.94 V

VPOS = VNEG = 2.5 V,
VDAC code = 128, VOUT = 2.5 V

To 0.1%, 4 V output step 8 µs

= 16.75 mV rms, f = 1 kHz,

V

IN

T

= 25°C

A

TA = 25°C 0.05 10 µs
TA = 25°C 50 µs
TA = 25°C 10 µs

1.8 mA

−100 dB

Rev. A | Page 3 of 24

AD8557

www.BDTIC.com/ADI

VDD = 2.7 V, VSS = 0.0 V, VCM = 1.35 V, VOUT = 1.35 V, gain = 28, TA = −40°C to +125°C, unless otherwise specified.

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

INPUT STAGE

Input Offset Voltage VOS 2 12 µV
Input Offset Voltage Drift TCV
Input Bias Current I
Input Offset Current I
Input Voltage Range 0.6 1.5 V
Common-Mode Rejection Ratio CMRR VCM = 0.9 V to 1.5 V, AV = 28 71 82 dB
V
Linearity VOUT = 0.2 V to 1.8 V 20 ppm
VOUT = 0.2 V to 2.5 V 1000 ppm
Differential Gain Accuracy Second stage gain = 10 to 250 1.6 %
Differential Gain Temperature Coefficient Second stage gain = 10 to 250 15 40 ppm/°C

DAC

Accuracy Offset codes = 8 to 248 0.7 0.8 %
Ratiometricity Offset codes = 8 to 248 50 ppm
Output Offset Offset codes = 8 to 248 5 35 mV
Temperature Coefficient 20 80 ppm FS/°C

VCLAMP

Input Bias Current ICLAMP 1.25 V to 2.7 V 200 nA
Input Voltage Range 1.25 2.7 V

OUTPUT STAGE

Short-Circuit Current I
Sink 15 25 mA
Output Voltage, Low V
Output Voltage, High V

POWER SUPPLY

Supply Current I

Power Supply Rejection Ratio PSRR VDD = 2.7 V to 5.5 V 105 125 dB

DYNAMIC PERFORMANCE

Gain Bandwidth Product GBP First gain stage, TA = 25°C 2 MHz
Second gain stage, TA = 25°C 8 MHz
Settling Time t

NOISE PERFORMANCE

Input Referred Noise f = 1 kHz 32 nV/√Hz
Low Frequency Noise en p-p f = 0.1 Hz to 10 Hz 0.5 µV p-p
Total Harmonic Distortion THD VIN = 16.75 mV rms, f = 1 kHz −100 dB

DIGITAL INTERFACE

Input Current 2 µA
DIGIN Pulse Width to Load 0 tw
DIGIN Pulse Width to Load 1 tw
Time Between Pulses at DIGIN tw
DIGIN Low TA = 25°C 0.2 × VDD V
DIGIN High TA = 25°C 0.8 × VDD V
DIGOUT Logic 0 TA = 25°C 0.2 × VDD V
DIGOUT Logic 1 TA = 25°C 0.8 × VDD V

B

OS

SC

OL

OH

SY

s

0

1

s

65 nV/°C

OS

10 18 25 nA
1 4 nA

= 0.9 V to 1.5 V, AV = 1300 96 112 dB

CM

Source −12 −7 mA

RL = 10 kΩ to 2.7 V 30 mV
RL = 10 kΩ to 0 V 2.64 V

VPOS = VNEG = 1.35 V,
VDAC code = 128, VOUT = 1.35 V

To 0.1%, 2 V output step,
T

= 25°C

A

TA = 25°C 0.05 10 µs
TA = 25°C 50 µs
TA = 25°C 10 µs

1.8 mA

8 µs

Rev. A | Page 4 of 24

AD8557

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage 6 V
Input Voltage VSS − 0.3 V to VDD + 0.3 V
Differential Input Voltage
Output Short-Circuit Duration to

VSS or VDD
ESD (Human Body Model) 2000 V
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature 300°C

1

Differential input voltage is limited to ±5.0 V or ± the supply voltage,

whichever is less.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

1

±6.0 V
Indefinite

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for LFCSP_VQ packages.

Table 4. Thermal Resistance

Package Type θ

8-Lead SOIC_N (R) 158 43 °C/W
16-Lead LFCSP_VQ (CP) 44 31.5 °C/W

JA

θ

JC

Unit

ESD CAUTION

Rev. A | Page 5 of 24

AD8557

www.BDTIC.com/ADI

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AVDD

DVDD

AVSS

DVSS

161514

13

12

VDD

DIGOUT

DIGIN

VNEG

1

AD8557

2

TOP VIEW

3

(Not to Scale)

4

VSS

8

VOUT

7

VCLAMP

6

VPOS

5

1

NC

DIGOUT

NC

DIGIN

06013-002

PIN 1
INDICATO R

2

AD8557

3

TOP VIEW

4

(Not to Scal e)

5

678

NC

NC

VNEG

NC = NO CONNECT

VOUT

11

NC

10

VCLAMP

9

NC

VPOS

6013-003

Figure 2. 8-Lead SOIC_N Pin Configuration

Figure 3. 16-Lead LFCSP_VQ Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

SOIC_N LFCSP_VQ

Mnemonic

Description

1 VDD Positive Supply Voltage.
2 2 DIGOUT In read mode, this pin functions as a digital output.
3 4 DIGIN
4 6 VNEG
5 8 VPOS
6 10 VCLAMP
7 12 VOUT
8 VSS
13, 14 DVSS, AVSS
15, 16 DVDD, AVDD

Digital Input.
Negative Amplifier Input (Inverting Input).
Positive Amplifier Input (Noninverting Input).
Set Clamp Voltage at Output.
Amplifier Output.
Negative Supply Voltage.
Negative Supply Voltage.
Positive Supply Voltage.

1, 3, 5, 7, 9, 11 NC Do Not Connect.

Rev. A | Page 6 of 24

AD8557

(

V

(

V

(

V

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

20

15

)

10

µ

5

0

–5

–10

INPUT OFFSET VOLTAGE

–15

–20

012345

+125°C

+25°C

–40°C

COMMON-MODE VOLTAGE (V)

VSY = 5V

Figure 4. Input Offset Voltage vs. Common-Mode Voltage, VSY = 5 V

06013-004

180

160

140

120

100

80

60

NUMBER OF AMPLIFIERS

40

20

0

–6–8–10 4 6 8 10

–2–402

INPUT OFFSET VOLTAGE (µV)

Figure 7. Input Offset Voltage Distribution, V

= 2.7 V

SY

06013-007

10

8

6

)

µ

4

2

0

–2

–4

INPUT OFFSET VOLTAGE

–6

–8

–10

0 0.5 1.0 1.5 2.0 2.5

+125°C

+25°C

–40°C

COMMON-MODE VOLTAGE (V)

VSY = 2.7V

Figure 5. Input Offset Voltage vs. Common-Mode Voltage, V

180

160

140

120

100

80

60

NUMBER OF AMPLI FIERS

40

20

0

–6–8–10 4 6 8 10

Figure 6. Input Offset Voltage Distribution, V

–2–402

INPUT OFFSET VOLTAGE (µV )

= 5 V

SY

= 2.7 V

SY

15

10

)

µ

5

0

–5

INPUT OFFSET VOLTAGE

–10

–15

06013-005

25 500–25–50

TEMPERATURE ( °C)

75 100 125 150 175

5V

2.7V

06013-008

Figure 8. Input Offset Voltage vs. Temperature

30

25

20

15

10

NUMBER OF AMPLIFIERS

5

0

06013-006

10 15 20 25 30 35 40 45 50 55 60 65

05

TCVOS (nV/°C)

Figure 9. T

at VSY = 5 V, −40°C ≤TA ≤ +125°C

CVOS

06013-009

Rev. A | Page 7 of 24

AD8557

(

A

www.BDTIC.com/ADI

35

0.5

30

25

20

15

10

NUMBER OF AMPLIFIERS

5

0

20

)

18

n

16

14

INPUT BIAS CURRENT

12

10 15 20 25 30 35 40 45 50 55 60 65

05

Figure 10. T

at VSY = 2.7 V, −40°C ≤ TA ≤ +125°C

CVOS

25 500–25–50

TEMPERATURE ( °C)

Figure 11. Input Bias Current at V

V

TCVOS (nV/°C)

75 100 125 150 175

POS, VNEG vs. Temperature,

= 5 V, 2.7 V

SY

–IB 5V

+I

B

5V

0.3

0.1

(nA)

OS

I

–0.1

–0.3

–0.5

–50 –25 0 25 50 75 100 125 150 175

06013-010

TEMPERATURE (° C)

06013-012

Figure 13. Input Offset Current vs. Temperature

3.0

2.5

2.0

1.5

1.0

DIGITAL INPUT CURRENT (µA)

0.5

0

05

06013-011

1234

DIGITAL INPUT VOLTAGE (V)

+25°C

–40°C

+125°C

VSY = 5V

06013-014

Figure 14. Digital Input Current vs. Digital Input Voltage (Pin 4)

100

10

1

INPUT BIAS CURRENT (nA)

0.1
05

1234

COMMON-MO DE VOLTAGE (V)

06013-013

Figure 12. Input Bias Current at VPOS, VNEG

s. Common-Mode Voltage, T

v

= 25°C

A

1000

+25°C

100

VCLAMP CURRENT (n A)

10

05

1234

VCLAMP VOLTAGE (V)

Figure 15. VCLAMP Current over Temperature at V

vs. VCLAMP Voltage

Rev. A | Page 8 of 24

+125°C

–40°C

VSY = 5V

= 5 V

SY

06013-015

AD8557

www.BDTIC.com/ADI

1000

+125°C

+25°C

120

100

80

HIGH GAIN +1300

100

–40°C

VCLAMP CURRENT (nA)

10

0.5 1.51.0 2.0 2.5

03

VCLAMP VOLTAGE (V)

Figure 16. VCLAMP Current over Temperature at V

VSY = 2.7V

= 2.7 V

SY

.0

06013-016

60

CMRR (dB)

40

20

0

0.1 1000

Figure 19. CMRR vs. Frequency, V

vs. VCLAMP Voltage

2.0

1.5

1.0

(mA)

SY

I

0.5

0

065

1234

V

(V)

SY

Figure 17. Supply Current (I

) vs. Supply Voltage

SY

06013-017

120

100

80

60

CMRR (dB)

40

20

0

0.1 1000

Figure 20. CMRR vs. Frequency, V

LOW GAIN +28

1 10 100

FREQUENCY (kHz)

SY

HIGH GAI N +1300

LOW GAIN +28

1 10 100

FREQUENCY (kHz)

= 2.7 V

SY

= 5 V

06013-019

06013-020

3.0

2.5

2.0

1.5

(mA)

SY

I

1.0

0.5

0
–50 175–25 0 25 50 75 100 125 150

Figure 18. Supply Current (I

ISY 5V

TEMPERATURE (° C)

ISY 2.7V

) vs. Temperature

SY

06013-018

Rev. A | Page 9 of 24

150

130

110

90

CMRR GAIN +1300

70

CMRR (dB)

50

30

10

–50 175

–25 0 25 50 75 100 125 150

Figure 21. CMRR vs. Temperature a

CMRR GAIN +28

CMRR GAIN +448

TEMPERATURE (°C)

t Different Gains, V

= 5 V

SY

06013-021

AD8557

www.BDTIC.com/ADI

140

120

100

CMRR (dB)

Figure 22. CMRR vs. Temperature a

CMRR GAIN +28

CMRR GAIN +448

80

60

40

20

0

–50 175

REF 502µV MARKER 20 000.0Hz

START .0 Hz STOP 1 000 000.0Hz

CMRR GAIN +1300

–25 0 25 50 75 100 125 150

TEMPERATURE (°C)

t Different Gains, V

5dB/DIV RANGE 12.5mV 1.89µV/√Hz

RBW 100Hz VBW 300Hz ST 900s

= 2.7 V

SY

6013-023

Figure 23. Input Voltage Noise Density vs. Frequency (0 Hz to 1000 kHz)

CHANNEL 1

16.6mV p-p

1

VOLTAG E NOISE, GAIN = 28 × 1000

CH1 10.0mV M 1.00s A CH1 –2.80mV

06013-022

Figure 25. Low Frequency Input Volt

70

60

HIGH GAIN +1300 62.28dB

50

40

30

LOW G AIN +28 28.9d B

20

GAIN (dB)

10

0

–10

–20

0.1 10k

1101001k

age Noise 0.1 Hz to 10 Hz, V

VSY = 5V

FREQUENCY (kHz)

Figure 26. Closed-Loop Gain vs. Frequency Measured at Output Pin, V

= 2.7 V

SY

06013-025

= 5 V

SY

06013-026

70

60

HIGH GAIN +1300 62.28dB

CHANNEL 1

15.2mV p-p

1

VOLTAG E NOISE, GAIN = 28 × 1000

CH1 10.0mV M 1.00s A CH1 –2.80mV

Figure 24. Low Frequency Input Voltage Noise, 0.1 Hz to 10 Hz, V

= 5 V

SY

06013-024

50

40

30

LOW G AIN +28 28.9d B

20

GAIN (dB)

10

0

–10

–20

0.1 10k

1101001k

FREQUENCY (kHz)

Figu re 27. Cl osed-Loop G ain vs. F requency Measured at Output Pin, V

Rev. A | Page 10 of 24

VSY = 2.7V

= 2.7 V

SY

06013-027

AD8557

www.BDTIC.com/ADI

10

1

SOURCE

0.1

OUTPUT VOLTAGE (V)

0.01

SINK

VSY = 5V

1

2

0.001

0.01 100

0.1 1 10

LOAD CURRENT (mA)

Figure 28. Output Voltage to Supply Rail vs. Load Current

100

ILIMSINK 5V

50

ILIMSINK 2.7V

0

(mA)

SC

I

–50

–100

–25 0 25 50 75 100 125 150

–50 175

ILIMS RC 2.7V

ILIMSRC 5V

TEMPERATURE (° C)

Figure 29. Output Short-Circuit vs. Temperature

CH1 2.0V CH2 1. 0V M 100µs

06013-028

T 23.80%

A CH1 800mV

06013-042

Figure 31. Power-On Response at 125°C

1

2

CH1 2.0V CH2 1. 0V M 100µs

06013-029

175

Figure 32. Power-On Response at −40°C

PSRR 2.7V TO 5.5V

T 23.80%

A CH1 800mV

06013-043

160

145

1

PSRR (dB)

130

115

2

100

–25 0 25 50 75 100 125 150

CH1 2.0V CH2 1. 0V M 100µs

T 23.80%

Figure 30. Power-On Response at 25°C

A CH1 800mV

06013-041

–50 175

Figure 33. PSRR vs. Temperature

Rev. A | Page 11 of 24

TEMPERATURE (° C)

06013-030

AD8557

www.BDTIC.com/ADI

140

120

100

80

60

PSRR (dB)

40

20

0

0.01 100

0.10.1 1 10

FREQUENCY (kHz)

GAIN = +1300

GAIN = +28

Figure 34. PSRR vs. Frequency

CHANNEL 3
+OVER

5.967%

CHANNEL 3
–OVER

6.878%

3

2

CH2 1.0V M 10.0µs

06013-031

T 23.20%

Figure 37. Large Signal Response, C

2

A CH2 0V

= 0 pF

L

06013-044

CH3 50.0mV M 10.0µs

T 24.20%

Figure 35. Small Signal Response, V

3

CH3 50.0mV M 10.0µs

T 24.20%

Figure 36. Small Signal Response, V

A CH3 12.0mV

= 5 V, CL = 100 pF

SY

CHANNEL 3
+OVER

98.13%

CHANNEL 3
–OVER

54.94%

A CH2 480µV

= 5 V, CL = 15 nF

SY

CH2 1.0V M 10.0µs

06013-032

T 23.20%

Figure 38. Large Signal Response, C

60

VSY = 5V
GAIN = +28

50

40

30

(dB)

20

OUT

Z

10

0

–10

–20

0.1 1000

06013-033

1 10 100

FREQUENCY (kHz)

Figure 39. Output Imped

ance vs. Frequency

A CH2 0V

= 5 nF

L

06013-045

06013-034

Rev. A | Page 12 of 24

AD8557

www.BDTIC.com/ADI

VSY = ±2.5V
GAIN = +28
T

= 25°C

A

1

2

CH1 50.0mV CH2 2. 00V M 1.00µ s A CH1 57.0mV

Figure 40. Positive Overload Recovery

1

VSY = ±2.5V
GAIN = +28
T

= 25°C

A

2

CH1 10.0mV CH2 2.00V M 10.0µs A CH1 –5.80mV

Figure 41. Negative Overload Recovery

VSY = ±2.5V
GAIN = +1300
T

= 25°C

A

1

2

06013-035

CH1 50.0mV CH2 2.00V M 1. 00µs

T 4.00µs

A CH1 –21.0mV

06013-038

Figure 43. Positive Overload Recovery (Gain = 1300)

10

5

2

1

0.5

0.2

THD + N (%)

0.1

0.05

0.02

0.01

06013-036

20 20k

100 200 50050 1k 2k 5k 10k

FREQUENCY (Hz)

06013-046

Figure 44. THD + N vs. Frequency

VSY = ±2.5V
GAIN = +1300
T

= 25°C

A

1

2

CH1 10.0mV CH2 2.00V M 10.0µ s

T 10.00%

A CH1 10.8mV

06013-037

Figure 42. Negative Overload Recovery (Gain = 1300)

Rev. A | Page 13 of 24

AD8557

(

−

=

V

VOUT

www.BDTIC.com/ADI

THEORY OF OPERATION

A1, A2, R1, R2, R3, P1, and P2 form the first gain stage of the
differential amplifier. A1 and A2 are auto-zeroed op amps that
minimize input offset errors. P1 and P2 are digital potentiome­ters, guaranteed to be monotonic. Programming P1 and P2
allows the first stage gain to be varied from 2.8 to 5.2 with 7-bit
resolution (see

justment resolution of 0.49%. Because R1, R2, R3, P1, and P2

ad

Tabl e 6 and Equation 1), giving a fine gain

each have a similar temperature coefficient, the first stage gain
temperature coefficient is lower than 100 ppm/°C.

Code

⎛

⎞

⎜

5.2

⎛

×≈

82

.GAIN1

⎜

2.8

⎝

⎟

271

⎝

⎠

⎞

(1)

⎟
⎠

A3, R4, R5, R6, R7, P3, and P4 form the second gain stage of the
dif

ferential amplifier. A3 is an auto-zeroed op amp that mini­mizes input offset errors and also includes an output buffer. P3
and P4 are digital potentiometers, which allow the second stage
gain to be varied from 10 to 250 in eight steps (see

R6, R7, P3, and P4 each have a similar temperature coefficient,

R5,

Tabl e 7). R4,

so the second stage gain temperature coefficient is lower than
100 ppm/°C. The output stage of A3 is supplied from a buffered
version of VCLAMP instead of VDD, allowing the positive
swing to be limited.

A4 implements a voltage buffer, which provides the positive
s

upply to the output stage of A3. Its function is to limit VOUT
to a maximum value, useful for driving analog-to-digital
converters (ADC) operating on supply voltages lower than
VDD. The input to A4, VCLAMP, has a very high input
resistance. It should be connected to a known voltage and not
be left floating. However, the high input impedance allows the
clamp voltage to be set using a high impedance source, such as a
potential divider. If the maximum value of VOUT does not
need to be limited, VCLAMP should be connected to VDD.

An 8-bit digital-to-analog converter (DAC) is used to generate a
va

riable offset for the amplifier output. This DAC is guaranteed

to be monotonic. To preserve the ratiometric nature of the input
signal, the DAC references are driven from VSS and VDD, and
the DAC output can swing from VSS (Code 0) to VDD (Code

255). The 8-bit resolution is equivalent to 0.39% of the difference
between VDD and VSS, for example, 19.5 mV with a 5 V supply.
The DAC output voltage (VDAC) is given approximately by

Code

+

5.0

256

⎞

()

⎟

VSSVSSVDD

(2)

⎠

VDAC is lower than

VDAC +−

⎛

≈

⎜
⎝

where the temperature coefficient of
200 ppm/°C.

The amplifier output voltage (VOUT) is given by

)

GAIN is the product of the first and second stage gains.

where

VDD

VNEG

VPOS

A1

VSS

VDD

A2

VSS

Figure 45. Functional Schematic

P3

R4

R1

P1

R3

P2

R2

R5 R7

P4

VDD

DAC

VSS

R6

VDD

A3

VSS

(3)

VDACVNEGVPOSGAINVOUT +

DD

VCLAMP

A4

VSS

06013-001

Rev. A | Page 14 of 24

AD8557

www.BDTIC.com/ADI

GAIN VALUES

Table 6. First Stage Gain vs. First Stage Gain Code

First Stage
Gain Code

0 2.800 32 3.273 64 3.825 96 4.471
1 2.814 33 3.289 65 3.844 97 4.493
2 2.827 34 3.305 66 3.863 98 4.515
3 2.841 35 3.321 67 3.881 99 4.537
4 2.855 36 3.337 68 3.900 100 4.559
5 2.869 37 3.353 69 3.919 101 4.581
6 2.883 38 3.370 70 3.939 102 4.603
7 2.897 39 3.386 71 3.958 103 4.626
8 2.911 40 3.403 72 3.977 104 4.649
9 2.926 41 3.419 73 3.997 105 4.671
10 2.940 42 3.436 74 4.016 106 4.694
11 2.954 43 3.453 75 4.036 107 4.717
12 2.969 44 3.470 76 4.055 108 4.740
13 2.983 45 3.487 77 4.075 109 4.763
14 2.998 46 3.504 78 4.095 110 4.786
15 3.012 47 3.521 79 4.115 111 4.810
16 3.027 48 3.538 80 4.135 112 4.833
17 3.042 49 3.555 81 4.156 113 4.857
18 3.057 50 3.573 82 4.176 114 4.881
19 3.072 51 3.590 83 4.196 115 4.905
20 3.087 52 3.608 84 4.217 116 4.929
21 3.102 53 3.625 85 4.237 117 4.953
22 3.117 54 3.643 86 4.258 118 4.977
23 3.132 55 3.661 87 4.279 119 5.001
24 3.147 56 3.679 88 4.300 120 5.026
25 3.163 57 3.697 89 4.321 121 5.050
26 3.178 58 3.715 90 4.342 122 5.075
27 3.194 59 3.733 91 4.363 123 5.100
28 3.209 60 3.751 92 4.384 124 5.125
29 3.225 61 3.770 93 4.406 125 5.150
30 3.241 62 3.788 94 4.427 126 5.175
31 3.257 63 3.806 95 4.449 127 5.200

First Stage Gain

First Stage
Gain Code

First Stage Gain

First Stage
Gain Code

First Stage Gain

First Stage
Gain Code

First Stage Gain

Table 7. Second Stage Gain and Gain Ranges vs. Second Stage Gain Code

Second Stage Gain Code Second Stage Gain Minimum Combined Gain Maximum Combined Gain

0 10 28.0 52.0
1 16 44.8 83.2
2 25 70.0 130.0
3 40 112.0 208.0
4 63 176.4 327.6
5 100 280.0 520.0
6 160 448.0 832.0
7 250 700.0 1300.0

Rev. A | Page 15 of 24

AD8557

V

V

V

www.BDTIC.com/ADI

OPEN WIRE FAULT DETECTION

The inputs to A1 and A2, VNEG and VPOS, each have a com­parator to detect whether VNEG or VPOS exceeds a threshold
voltage, nominally VDD − 2.0 V. If VNEG > (VDD − 2.0 V) or
VPOS > (VDD − 2.0 V), VOUT is clamped to VSS. The output
current limit circuit is disabled in this mode, but the maximum
sink current is approximately 10 mA when VDD = 5 V. The
inputs to A1 and A2, VNEG and VPOS, are also pulled up to
VDD by currents IP1 and IP2. These are both nominally 16 nA
and matched to within 3 nA. If the inputs to A1 or A2 are
accidentally left floating, as with an open wire fault, IP1 and IP2
pull them to VDD, which would cause VOUT to swing to VSS,
allowing this fault to be detected. It is not possible to disable IP1
and IP2, nor the clamping of VOUT to VSS, when VNEG or
VPOS approaches VDD.

SHORTED WIRE FAULT DETECTION

The AD8557 provides fault detection in the case where VPOS,
VNEG, or VCLAMP shorts to VDD and VSS. Figure 46 shows
th

e voltage regions at VPOS, VNEG, and VCLAMP that trigger
an error condition. When an error condition occurs, the VOUT
pin is shorted to VSS. Tab le 8 lists the voltage levels shown in
Figure 46.

POS

ERROR

NORMAL

ERROR

VDD

VINH

VINL
VSS

Figure 46. Voltage Regions at VPOS, VNEG, and VCLAMP

t

Table 8. Typical VINL, VINH, and VCLL Values
(VDD = 5 V)

Voltage Min (V) Max (V) VOUT Condition

VINH 3.9 4.2 Short to VSS fault detection
VINL 0.195 0.55 Short to VSS fault detection
VCLL 1.0 1.2 Short to VSS fault detection

NEG

ERROR

NORMAL

ERROR

hat Trigger a Fault Condition

t

WS

t

W0

VDD

VINH

VINL
VSS

t

W1

CLAMP

NORMAL

ERROR

VDD

VCLL

VSS

t

WS

t

WS

t

W0

06013-039

t

FLOATING VPOS, VNEG, OR VCLAMP FAULT DETECTION

A floating fault condition at the VPOS, VNEG, or VCLAMP
pins is detected by using a low current to pull a floating input
into an error voltage range, defined in the previous section. In
this way, the VOUT pin is shorted to VSS when a floating input
is detected. Tabl e 9 lists the currents used.

Table 9. Floating Fault Detection at VPOS, VNEG,
and VCLAMP

Pin Typical Current Goal of Current

VPOS 16 nA pull-up Pull VPOS above VINH
VNEG 16 nA pull-up Pull VNEG above VINH
VCLAMP 0.2 µA pull-down Pull VCLAMP below VCLL

DEVICE PROGRAMMING

Digital Interface

The digital interface allows the first stage gain, second stage
gain, and output offset to be adjusted and allows desired values
for these parameters to be permanently stored by selectively
blowing polysilicon fuses. To minimize pin count and board
space, a single-wire digital interface is used. The digital input
pin, DIGIN, has hysteresis to minimize the possibility of
inadvertent triggering with slow signals. It also has a pull-down
current sink to allow it to be left floating when programming is
not being performed. The pull-down ensures inactive status of
the digital input by forcing a dc low voltage on DIGIN.

A short pulse at DIGIN from low to high and back to low again,
s

uch as between 50 ns and 10 µs long, loads a 0 into a shift
register. A long pulse at DIGIN, such as 50 µs or longer, loads a
1 into the shift register. The time between pulses should be at
least 10 µs. Assuming VSS = 0 V, voltages at DIGIN between
VSS and 0.2 × VDD are recognized as a low, and voltages at
DIGIN between 0.8 × VDD and VDD are recognized as a high.
A timing diagram example,
en

tering Code 010011 into the shift register.

t

W1

W0

t

WS

Figure 47, shows the waveform for

t

WS

t

W1

WAVEFORM

CODE

01001 1

Figure 47. Timing Diagram for Code 010011

Rev. A | Page 16 of 24

06013-040

AD8557

www.BDTIC.com/ADI

Table 10. Timing Specifications

Timing Parameter Description Specification

tw0 Pulse width for loading 0 into shift register Between 50 ns and 10 µs
tw1 Pulse width for loading 1 into shift register ≥50 µs
tws Width between pulses ≥10 µs

Table 11. 38-Bit Serial Word Format

Field No. Bits Description

0 0 to 11 12-bit start of packet 1000 0000 0001
1 12 to 13 2-bit function
00: change sense current
01: simulate parameter value
10: program parameter value
11: read parameter value
2 14 to 15 2-bit parameter
00: second stage gain code
01: first stage gain code
10: output offset code
11: other functions
3 16 to 17 2-bit dummy 10
4 18 to 25 8-bit value
Parameter 00 (second stage gain code): 3 LSBs used
Parameter 01 (first stage gain code): 7 LSBs used
Parameter 10 (output offset code): all 8 bits used
Parameter 11 (other functions)
Bit 0 (LSB): master fuse
Bit 1: fuse for production test at Analog Devices
5 26 to 37 12-bit end of packet 0111 1111 1110

A 38-bit serial word is used, divided into 6 fields. Assuming

h bit can be loaded in 60 µs, the 38-bit serial word transfers

eac
in 2.3 ms. Tabl e 11 summarizes the word format.

Field 0 and Field 5 are the start-of-packet field and end-of-

acket field, respectively. Matching the start-of-packet field with

p
1000 0000 0001 and the end-of-packet field with 0111 1111
1110 ensures that the serial word is valid and enables decoding
of the other fields.

Field 3 breaks up the data and ensures that no data combination

n inadvertently trigger the start-of-packet and end-of-packet

ca
fields. Field 0 should be written first and Field 5 written last.

Within each field, the MSB must be written first and the LSB

itten last. The shift register features power-on reset to mini-

wr
mize the risk of inadvertent programming; power-on reset
occurs when VDD is between 0.7 V and 2.2 V.

Initial State

Initially, all the polysilicon fuses are intact. Each parameter has
the value 0 assigned (see Tabl e 1 2 ).

Table 12. Initial State Before Programming

Second Stage Gain Code = 0 Second Stage Gain = 10

First stage gain code = 0 First stage gain = 2.8
Output offset code = 0 Output offset = VSS
Master fuse = 0 Master fuse not blown

When power is applied to a device, parameter values are taken
either from internal registers, if the master fuse is not blown,
or from the polysilicon fuses, if the master fuse is blown.
Programmed values have no effect until the master fuse is
blown. The internal registers feature power-on reset, so the
unprogrammed devices enter a known state after power-up.
Power-on reset occurs when VDD is between 0.7 V and 2.2 V.

Rev. A | Page 17 of 24

AD8557

www.BDTIC.com/ADI

Simulation Mode

The simulation mode allows any parameter to be temporarily
changed. These changes are retained until the simulated value is
reprogrammed, the power is removed, or the master fuse is
blown. Parameters are simulated by setting Field 1 to 01,
selecting the desired parameter in Field 2, and selecting the
desired value for the parameter in Field 4. Note that a value of
11 for Field 2 is ignored during the simulation mode. Examples
of temporary settings follow:

• Setting the second stage gain code (Parameter 00) to 011

and the second stage gain to 50 produces:
1000 0000 0001 01 00 10 0000 0011 0111 1111 1110

• Setting the first stage gain code (Parameter 01) to 000 1011

and the first stage gain to 4.166 produces:
1000 0000 0001 01 01 10 0000 1011 0111 1111 1110

A first stage gain of 4.166 with a second stage gain of 50

ives a total gain of 208.3. This gain has a maximum

g
tolerance of 2.5%.

• Set the output offset code (Parameter 10) to 0100 0000

and the output offset to 1.260 V when VDD = 5 V and
VSS = 0 V. This output offset has a maximum tolerance
of 0.8%:
1000 0000 0001 01 10 10 0100 0000 0111 1111 1110

Programming Mode

Intact fuses give a bit value of 0. Bits with a desired value of 1
need to have the associated fuse blown. Because a relatively
large current is needed to blow a fuse, only one fuse can be
reliably blown at a time. Thus, a given parameter value may
need several 38-bit words to allow reliable programming.

A 5.75 V (±0.25 V) supply is required when blowing fuses to

mize the on resistance of the internal MOS switches that

mini
blow the fuse. The power supply voltage must not exceed the
absolute maximum rating and must be able to deliver 250 mA
of current.

At least 10 µF (tantalum type) of decoupling capacitance is

eded across the power pins of the device during program-

ne
ming. The capacitance can be on the programming apparatus as
long as it is within 2 inches of the device being programmed.
An additional 0.1 F (ceramic type) in parallel with the 10
recommended within ½ inch of the device being programmed.
A minimum period of 1 ms should be allowed for each fuse to
blow. There is no need to measure the supply current during
programming.

The best way to verify correct programming is to use the read

ode to read back the programmed values. Then, remeasure

m
the gain and offset to verify these values. Programmed fuses
have no effect on the gain and output offset until the master
fuse is blown. After blowing the master fuse, the gain and
output offset are determined solely by the blown fuses, and the
simulation mode is permanently deactivated.

μF is

Parameters are programmed by setting Field 1 to 10, selecting
t

he desired parameter in Field 2, and selecting a single bit with
the value 1 in Field 4.

As an example, suppose the user wants to permanently set the

econd stage gain to 50. Parameter 00 needs to have the value

s
0000 0011 assigned. Two bits have the value 1, so two fuses need
to be blown. Because only one fuse can be blown at a time, this
code can be used to blow one fuse:
1000 0000 0001 10 00 10 0000 0010 0111 1111 1110

The MOS switch that blows the fuse closes when the complete

acket is recognized, and opens when the start-of-packet,

p
dummy, or end-of-packet fields are no longer valid. After 1 ms,
this second code is entered to blow the second fuse:
1000 0000 0001 10 00 10 0000 0001 0111 1111 1110

To permanently set the first stage gain to a nominal value of

arameter 01 needs to have the value 000 1011 assigned.

4.151, P
Three fuses need to be blown, and the following codes are used,
with a 1 ms delay after each code:
1000 0000 0001 10 01 10 0000 1000 0111 1111 1110
1000 0000 0001 10 01 10 0000 0010 0111 1111 1110
1000 0000 0001 10 01 10 0000 0001 0111 1111 1110

To permanently set the output offset to a nominal value of

1.260 V w
to have the value 0100 0000 assigned. If one fuse needs to be
blown, use the following code:
1000 0000 0001 10 10 10 0100 0000 0111 1111 1110

Finally, to blow the master fuse to deactivate the simulation

ode and prevent further programming, use code:

m
1000 0000 0001 10 11 10 0000 0001 0111 1111 1110

There are a total of 20 programmable fuses. Because each fuse

equires 1 ms to blow, and each serial word can be loaded in

r

2.3 ms, the maximum time needed to program the fuses can be
as low as 66 ms.

hen VDD = 5 V and VSS = 0 V, Parameter 10 needs

Read Mode

The values stored by the polysilicon fuses can be sent to the
DIGOUT pin to verify correct programming. Normally, the
DIGOUT pin is only connected to the second gain stage output.
During read mode, however, the DIGOUT pin is also connected
to the output of a shift register to allow the polysilicon fuse
contents to be read. Because VOUT is a buffered version of
DIGOUT, VOUT also outputs a digital signal during read mode.

Read mode is entered by setting Field 1 to 11 and selecting the

ed parameter in Field 2. Field 4 is ignored. The parameter

desir
value, stored in the polysilicon fuses, is loaded into an internal
shift register, and the MSB of the shift register is connected to
the DIGOUT pin. Pulses at DIGIN shift out the shift register
contents to the DIGOUT pin, allowing the 8-bit parameter
value to be read after seven additional pulses; shifting occurs on
the falling edge of DIGIN. An eighth pulse at DIGIN disconnects
DIGOUT from the shift register and terminates the read mode.

Rev. A | Page 18 of 24

AD8557

www.BDTIC.com/ADI

If a parameter value is less than eight bits long, the MSBs of the
shift register are padded with 0s.

For example, to read the second stage gain, this code is used:
1000 0000 0001 11 00 10 0000 0000 0111 1111 1110

ecause the second stage gain parameter value is only three bits

B
long, the DIGOUT pin has a value of 0 when this code is
entered, and remains 0 during four additional pulses at DIGIN.
The fifth, sixth, and seventh pulses at DIGIN return the 3-bit
value at DIGOUT, the seventh pulse returns the LSB. An eighth
pulse at DIGIN terminates the read mode.

Sense Current

A sense current is sent across each polysilicon fuse to determine
whether it has been blown. When the voltage across the fuse is
less than approximately 1.5 V, the fuse is considered not blown,
and Logic 0 is output from the OTP cell. When the voltage
across the fuse is greater than approximately 1.5 V, the fuse is
considered blown, and Logic 1 is output.

When the AD8557 is manufactured, all fuses have a low

esistance. When a sense current is sent through the fuse, a

r
voltage less than 0.1 V is developed across the fuse. This is
much lower than 1.5 V, so Logic 0 is output from the OTP cell.
When a fuse is electrically blown, it should have a very high
resistance. When the sense current is applied to the blown fuse,
the voltage across the fuse should be larger than 1.5 V, so
Logic 1 is output from the OTP cell.

It is theoretically possible, though very unlikely, for a fuse to
b

e incompletely blown during programming, assuming the
required conditions are met. In this situation, the fuse could
have a medium resistance, neither low nor high, and a voltage of
approximately 1.5 V could be developed across the fuse. Thus,
the OTP cell could output Logic 0 or Logic 1, depending on
temperature, supply voltage, and other variables.

To detect this undesirable situation, the sense current can be

wered by a factor of 4 using a specific code. The voltage devel-

lo
oped across the fuse would then change from 1.5 V to 0.38 V,
and the output of the OTP would be a Logic 0 instead of the
expected Logic 1 from a blown fuse. Correctly blown fuses would
still output a Logic 1. In this way, incorrectly blown fuses can be
detected. Another specific code would return the sense current
to the normal (larger) value. The sense current cannot be
permanently programmed to the low value. When the AD8557
is powered up, the sense current defaults to the high value.

The low sense current code is
1000 0000 0001 00 00 10 XXXX

The normal (high) sense current code is
1000 0000 0001 00 00 10 XXXX

XXX1 0111 1111 1110

XXX0 0111 1111 1110

Programming Procedure

For reliable fuse programming, it is imperative to follow the
programming procedure requirements, especially the proper
supply voltage during programming:

When programming the AD8557, the temperature of the

1.
device must be between 10°C to 40°C.

Set VDD and VSS to the desired values in the application.

2.
Use simulation mode to test and determine the desired
codes for the second stage gain, first stage gain, and output
offset. The nominal values for these parameters are shown
in Tab l e 6 , Ta bl e 7, Equation 2, and Equation 3; use the
co

des corresponding to these values as a starting point.
However, because actual parameter values for given codes
vary from device to device, some fine tuning is necessary
for the best possible accuracy.

One way to choose these values is to set the output offset to
a

n approximate value, such as Code 128 for midsupply, to
allow the required gain to be determined. Then, set the
second stage gain so the minimum first stage gain (Code 0)
gives a lower gain than required, and the maximum first
stage gain (Code 127) gives a higher gain than required.
After choosing the second stage gain, the first stage gain
can be chosen to fine tune the total gain. Finally, the output
offset can be adjusted to give the desired value. After
determining the desired codes for second stage gain, first
stage gain, and output offset, the device is ready for
permanent programming.

Note that once a programming attempt has been made for
a

ny fuse, there should be no further attempt to blow that
fuse. If a fuse does not program to the expected state,
discard the unit. The expected incidence rate of attempted
but unblown fuses is very small when following the proper
programming procedure and conditions.

3.

Set VSS to 0 V and VDD to 5.75 V (±0.25 V). Power

supplies should be capable of supplying 250 mA at the
required voltage and properly bypassed as described in the
Programming Mode section. Use program mode to
p

ermanently enter the desired codes for the first stage gain,
second stage gain, and output offset. Blow the master fuse
to allow the AD8557 to read data from the fuses and to
prevent further programming.

4.

Set VDD and VSS to the desired values in the application.

Use read mode with low sense current followed by high
sense current to verify programmed codes.

5.

Measure gain and offset to verify correct functionality.

Rev. A | Page 19 of 24

AD8557

www.BDTIC.com/ADI

9.

Determining Optimal Gain and Offset Codes

First, determine the desired gain:

Determine the desired gain, G

1.

(using the measurements

A

obtained from the simulation).

Us e Tabl e 7 to determine G

2.
that (2.8 × 1.05) < (G

, the second stage gain, such

2

) < (5.2/1.05). This ensures the

A/G2

first and last codes for the first stage gain are not used,
thereby allowing enough first stage gain codes within each
second stage gain range to adjust for the 3% accuracy.

Next, set the second stage gain:

Use the simulation mode to set the second stage gain to G

1.

Set the output offset to allow the AD8557 gain to be

2.
measured, for example, use Code 128 to set it to midsupply.

Us e Tabl e 6 or Equation 1 to set the first stage gain code

3.

, so the first stage gain is nominally GA/G2.

C

G1

Measure the resulting gain (G

4.
3% of G

Calculate the first stage gain error (in relative terms)

5.
E

Calculate the error (in the number of the first stage gain

6.
codes) C

Set the first stage gain code to C

7.

Measure the gain (G

8.

.

A

= GB/GBA − 1.

G1

EG1

= EG1/0.00489.

). GC should be closer to GA than to GB. B

C

). GB

B should be within

B

B

− C

G1

EG1

.

Calculate the error (in relative terms) E

Calculate the error (in the number of the first stage gain

10.
codes) C

Set the first stage gain code to C

11.

= EG2/0.00489.

EG2

G1

resulting gain should be within one code of G

Finally, determine the desired output offset:

Determine the desired output offset O

1.
measurements obtained from the simulation).

Use Equation 2 to set the output offset code C

2.
the output offset is nominally O

.

2

Measure the output offset (O

3.
3% of O

Calculate the error (in relative terms) E

4.

Calculate the error (in the number of the output offset

5.
codes) C

Set the output offset code to C

6.

Measure the output offset (O

7.
than to O

8.

Calculate the error (in relative terms) E

9.

Calculate the error (in the number of the output offset

codes) C

Set the output offset code to C

10.

.

A

= EO1/0.00392.

EO1

. B

B

= EO2/0.00392.

EO2

.

A

). OB

B

− C

O1

). OC should be closer to OA

C

− C

O1

resulting offset should be within one code of O

= GC/GA − 1.

G2

− C

− C

EG1

(using the

A

B should be within

B

O1

.

EO1

O2

− C

EO1

. The

EG2

.

A

such that

O1

= OB/OBA − 1.

= OC/OA − 1.

. The

EO2

.

A

Rev. A | Page 20 of 24

AD8557

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLL ING DIMENSI ONS ARE IN MILLIME TERS; INCH DIM ENSIONS
(IN PARENTHESES) ARE ROUNDED-OF F MILLIMETER E QUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESI GN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-A A

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

Figure 48. 8-Lead Standard Small Outline Package [SOIC_N]

Nar

row Body

(R-8)

Dimensions shown in millimeters and (inches)

PIN 1

INDICATOR

1.00

0.85

0.80

4.00

12° MAX

SEATING
PLANE

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

COMPLIANT TO JEDEC STANDARDS MO-220-VGG C

0.35

0.30

0.25

3.75

BSC SQ

0.20 REF

0.60 MAX

0.65 BSC

0.05 MAX

0.02 NOM

COPLANARIT Y

0.50

0.40

0.30

0.08

Figure 49. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4

mm × 4 mm Body, Very Thin Quad

(CP-16-10)

Dimensions shown in millimeters

0.60 MAX

13

12

EXPOSED

(BOTTOM VIEW)

9

8

PAD

16

5

1.95 BSC

PIN 1
INDICATOR

1

2.50

2.35 SQ

2.20

4

0.25 MIN

010606-0

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8557ACPZ-R2
AD8557ACPZ-REEL
AD8557ACPZ-REEL7
AD8557ARZ
AD8557ARZ-REEL
AD8557ARZ-REEL7
AD8557AR-EVAL Evaluation Board

1

Z = RoHS Compliant Part.

1

1

1

1

1

−40°C to +125°C 16-Lead LFCSP_VQ CP-16-10

−40°C to +125°C 16-Lead LFCSP_VQ CP-16-10

1

−40°C to +125°C 16-Lead LFCSP_VQ CP-16-10

−40°C to +125°C 8-Lead SOIC_N R-8

−40°C to +125°C 8-Lead SOIC_N R-8

−40°C to +125°C 8-Lead SOIC_N R-8

Rev. A | Page 21 of 24

AD8557

www.BDTIC.com/ADI

NOTES

Rev. A | Page 22 of 24

AD8557

www.BDTIC.com/ADI

NOTES

Rev. A | Page 23 of 24

AD8557

www.BDTIC.com/ADI

NOTES

©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06013-0-1/08(A)

Rev. A | Page 24 of 24