+5 Volt, Serial Input,
PDIP-14
SO-14
a
FEATURES
Complete Dual 12-Bit DAC
No External Components
+5 V Single-Supply Operation 610%
4.095 V Full Scale (1 mV/LSB)
Buffered Voltage Outputs
Low Power: 5 mW/DAC
Space Saving 1.5 mm Height SO-14 Package
APPLICATIONS
Digitally Controlled Calibration
Servo Controls
Process Control Equipment
Computer Peripherals
Portable Instrumentation
Cellular Base Stations Voltage Adjustment
GENERAL DESCRIPTION
The AD8522 is a complete dual 12-bit, single-supply, voltage
output DAC in a 14-pin DIP, or SO-14 surface mount package.
Fabricated in a CBCMOS process, features include a serial digital interface, onboard reference, and buffered voltage output.
Ideal for +5 V-only systems, this monolithic device offers low
cost and ease of use, and requires no external components to
realize the full performance of the device.
The serial digital interface allows interfacing directly to numerous microcontroller ports, with a simple high speed, three-wire
data, clock, and load strobe format. The 16-bit serial word contains the 12-bit data word and DAC select address, which is decoded internally or can be decoded externally using
LDA, LDB
Dual 12-Bit DAC
AD8522
FUNCTIONAL BLOCK DIAGRAM
V
DD
CS
CLK
SDI
(DATA)
SDO
LDA
LDB
CLK
LATCH
SHIFT
REGISTER
CONTROL
LOGIC
DGND
DAC A
REGISTER
D
12
D
DAC B
REGISTER
12
12
MSB
DAC A
BANDGAP
REFERENCE
DAC B
AD8522
RS
inputs. A serial data output allows the user to easily daisy-chain
multiple devices in conjunction with a chip select input. A reset
RS input sets the outputs to zero scale or midscale, as determined by the input MSB.
The output 4.095 V full scale is laser trimmed to maintain accuracy over the operating temperature range of the device, and
gives the user an easy-to-use one-millivolt-per-bit resolution. A
2.5 V reference output is also available externally for other data
acquisition circuitry, and for ratiometric applications. The output buffers are capable of driving ± 5 mA.
The AD8522 is available in the 14-pin plastic DIP and low profile 1.5 mm SOIC-14 packages.
AGND
REF
BUF
REF
BUF
OP
AMP
A
OP
AMP
B
V
V
V
OUTA
REF
OUTB
0.6
0.4
0.2
–0.2
–0.4
–0.6
LINEARITY ERROR – LSB
–0.8
–1.0
VDD = +4.5V
= –55°C, +25°C, +85°C, +125°C
T
A
0
+85°C
+125°C
DIGITAL INPUT CODE – Decimal
+25°C
–55°C
40960 30721024 2048
Figure 1. Linearity Error vs. Digital Code & Temperature
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PACKAGE TYPES AVAILABLE
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
AD8522–SPECIFICA TIONS
(@ VDD = +5.0 V 6 10%, RL = No Load, –408C ≤ TA ≤ +858C, both DACs tested, unless
ELECTRICAL CHARACTERISTICS
Parameter Symbol Condition Min Typ Max Units
STATIC PERFORMANCE
Resolution
Relative Accuracy INL -1.5 ±0.5 +1.5 LSB
Differential Nonlinearity DNL Monotonic -1 ±0.5 +1 LSB
Zero-Scale Error V
Full-Scale Voltage
Full-Scale Tempco
MATCHING PERFORMANCE
Linearity Matching Error ∆VFSA/B ±1 LSB
ANALOG OUTPUT
Output Current I
Load Regulation at Half-Scale LD
Capacitive Load
REFERENCE OUTPUT
Output Voltage V
Output Source Current
Line Rejection LN
Load Regulation LD
LOGIC INPUTS & OUTPUTS
Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance
Logic Output Voltage Low V
Logic Output Voltage High V
TIMING SPECIFICATIONS
Clock Width High t
Clock Width Low t
Load Pulse Width t
Data Setup t
Data Hold t
Clear Pulse Width t
Load Setup t
Load Hold t
Select t
Deselect t
Clock to SDO Propagation Delay t
AC CHARACTERISTICS
Voltage Output Settling Time6t
Crosstalk C
DAC Glitch Q Half-Scale Transition 13 nV s
Digital Feedthrough D
SUPPLY CHARACTERISTICS
Positive Supply Current I
Power Dissipation
Power Supply Sensitivity PSS ∆VDD = ±5% 0.002 0.004 %/%
NOTES
1
1 LSB = 1 mV for 0 V to +4.095 V output range.
2
Includes internal voltage reference error.
3
These parameters are guaranteed by design and not subject to production testing.
4
Very little sink current is available at the V
5
All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region.
7
Power Dissipation is calculated IDD × 5 V.
Specifications subject to change without notice.
1
2
2, 3
3
4
3
3, 5
3, 5
7
N 12 Bits
ZSE
V
FS
TCV
OUT
C
L
REF
I
REF
IL
IH
IL
C
IL
OL
OH
CH
CL
LDW
DS
DH
CLRW
LD1
LD2
CSS
CSH
PD
S
T
FT
DD
P
DISS
pin. Use external buffer if setting up a virtual ground.
REF
otherwise noted)
FS
REG
REJ
REG
Data = 000
Data = FFF
H
H
4.079 4.095 4.111 Volts
+0.5 +3 mV
±15 ppm/°C
Data = 800H, ∆V
RL = 402 Ω to ∞, Data = 800
≤ 3 LSB ±5mA
OUT
H
1 3 LSB
No Oscillation 500 pF
2.484 2.500 2.516 V
∆V
< 18 mV 5 mA
REF
0.025 0.08 %/V
I
= 0 to 5 mA, Data = 800
REF
H
0.025 0.1 %/mA
0.8 V
2.4 V
10 µA
10 pF
IOL = 1.6 mA 0.4 V
IOH = 400 µA 3.5 V
35 ns
35 ns
25 ns
10 ns
20 ns
20 ns
10 ns
10 ns
30 ns
30 ns
20 45 80 ns
To ±1 LSB of Final Value 16 µs
Signal Measured at DAC Output,
While Changing Opposite
LDA/B 38 dB
Signal Measured at DAC Output,
While Changing Data Without LDA/B 2 nV s
VDD = 5.5 V, VIH = 2.4 V or VIL = 0.8 V 3 5 mA
= 5 V, VIL = 0 V 1 2 mA
V
DD
VDD = 5 V, VIH = 2.4 V or VIL = 0.8 V 15 25 mW
= 5 V, VIL = 0 V 5 10 mW
V
DD
–2–
REV. A
AD8522
NC
CL
tDSt
DB11 DB10
DH
t
LD2
DB4 DB3 DB2 DB1 DB0
t
LDW
Figure 2. Timing Diagram
t
CSH
t
LD2
t
t
PD
t
t
S
±1 LSB
ERROR BAND
CLRW
t
S
LDW
SDI
CLK
SDO
CLK
V
CS
LD
SDI
LD
RS
OUT
Sf/Hd
t
LD1
t
CH
FS
ZS
t
AB
CSS
t
SERIAL INPUT REGISTER DATA FORMAT
Last First
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 NC A B Sf/Hd
Table I. Truth Table
Data Word Ext Pins
Sf/Hd BALDA LDB DAC Register
Hardware Load:
LXX↓↓Loads DACA + DACB with Data from SR
LXX↓H Loads DACA with Data from SR
L XXH↓Loads DACB with Data from SR
L X X H H No Load
Software Decode Load:
H L L X X No Load
HHL↓↓Loads DACB with Data from SR, See Note 1 Below
H H L H H No Load
HLH↓↓Loads DACA with Data from SR, See Note 1 Below
H L H H H No Load
HHH↓↓Loads DACA + DACB with Data from SR, See 1 Note Below
H H H H H No Load
NOTES
1
In software mode LDA and LDB perform the same function. They can be tied together or the unused pin should be tied high.
2
External Pins LDA and LDB should always be high when shifting Data into the shift register.
3
↓ symbol denotes negative transition.
1.6mA
REV. A
SDO
200µA
1.6 VOLT
Figure 3. AC Timing SDO Pin Load Circuit
–3–
AD8522
PIN DESCRIPTION
Pin Function
SDI Serial Data Input, input data loads directly into the shift register.
CLK Clock input, positive edge clocks data into shift register.
CS Chip Select, active low input. Prevents shift register loading when high. Does not affect LDA and LDB operation.
LDA/B Load DAC register strobes, active low. Transfers shift register data to DAC register. See truth table for operation.
Software decode feature only requires one
other pin tied high.
SDO Serial Data Output. Output of shift register, always active.
RS Resets DAC registers to condition determined by MSB pin. Active low input.
MSB Digital input: High presets DAC registers to half scale (800
strobed to active low.
V
DD
Positive +5 V power supply input. Tolerance ±10%.
AGND Analog Ground Input.
DGND Digital Ground Input.
V
REF
V
OUT A/B
Reference Voltage Output, 2.5 V nominal.
DAC A/B voltage outputs, 4.095 V full scale, ±5 mA output.
LD strobe. Tie LDA and LDB together or use one of them with the
); Low clears all registers to zero (000H), when RS is
H
PIN CONFIGURATION
14-Pin Plastic DIP 14-Lead SO-14
V
OUTA
AGND
DGND
CLK
SDI
SDO
CS
1
2
3
AD8522
(Not To Scale)
4
5
6
7
14
V
OUTB
13
V
REF
12
V
DD
11
MSB
10
RS
9
LDA
8
LDB
1
Table II. Truth Tables
DAC Register Preset
RS MSB Register Activity
0 0 Asynchronously Resets DAC Registers to Zero
Scale
0 1 Asynchronously Presets DAC Registers to
Half Scale (800
)
H
1 X None
Shift Register
CS CLK Shift Register
ABSOLUTE MAXIMUM RATINGS*
VDD to DGND & AGND . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
Logic Inputs and Output to DGND . . . . .–0.3 V, V
V
to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
OUT
V
to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
REF
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
I
Short Circuit to GND or VDD . . . . . . . . . . . . . . . . 50 mA
OUT
Package Power Dissipation . . . . . . . . . . . . . . .(T
Thermal Resistance, θ
JA
+ 0.3 V
DD
max–TA)/θ
J
DD
JA
14-Pin Plastic DIP Package (N-14) . . . . . . . . . . . . . 83°C/W
14-Lead SOIC Package (SO-14) . . . . . . . . . . . . . . 120°C/W
Maximum Junction Temperature (T
max) . . . . . . . . . . 150°C
J
Operating Temperature Range . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD8522AN –40°C to +85°C 14-Pin P-DIP N-14
AD8522AR –40°C to +85°C 14-Lead SOIC SO-14
1 X No Effect
The AD8522 contains 1482 transistors.
0 ↑ Shifts Register One Bit, SDO Outputs Data
from 16 Clocks Earlier
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8522 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. A
AD8522
OPERATION
The AD8522 is a complete ready-to-use dual 12-bit digital-toanalog converter. Only one +5 V power supply is necessary for
operation. It contains two voltage-switched, 12-bit, lasertrimmed digital-to-analog converters, a curvature-corrected
bandgap reference, rail-to-rail output op amps, input registers,
and DAC registers. The serial data interface consists of a serial
data input (SDI), clock (CLK), and two load strobe pins (
LDA,
LDB) with an active low CS strobe. In addition, an asynchro-
nous
RS pin will set all DAC register bits to zero causing the
V
to become zero volts, or to midscale for trimming applica-
OUT
tions when the MSB pin is programmed to Logic 1. This function is useful for power on reset or system failure recovery to a
known state.
D/A CONVERTER SECTION
The internal DAC is a 12-bit voltage-mode device with an output that swings from AGND potential to the 2.5 V internal
bandgap voltage. It uses a laser-trimmed R-2R ladder which is
switched by N channel MOSFETs. The output voltage of the
DAC has a constant resistance independent of digital input
code. The DAC output is internally connected to the rail-to-rail
output op amp.
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power consumption precision amplifier. This low power amplifier contains
a differential PNP pair input stage that provides low offset voltage and low noise, as well as the ability to amplify the zero-scale
DAC output voltages. The rail-to-rail amplifier is configured in
a gain of 1.638 (= 4.095 V/2.5 V) in order to set the 4.095 V
full-scale output (1 mV/LSB). See Figure 4 for an equivalent
circuit schematic of the analog section.
R
R
2R
RAIL-TO-RAIL
OUTPUT
AMPLIFIER
R2
R1
A
= 4.096/2.5
V
= 1.638V/V
V
OUT
BANDGAP
REFERENCE
V
2.5V
REF
VOLTAGE SWITCHED 12-BIT
R-2R D/A CONVERTER
BUFFER
SPDT
N CH FET
SWITCHES
2R
2R
2R
2R
Figure 4. Equivalent AD8522 Schematic of Analog Portion
The op amp has a 16 µs typical settling time to 0.01%. There
are slight differences in settling time for negative slewing signals
versus positive. See the oscilloscope photos in the “Typical Performance Characteristics” section of this data sheet.
OUTPUT SECTION
The rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply. Figure 5 shows an equivalent output schematic of
the rail-to-rail amplifier with its N channel pull-down FETs that
will pull an output load directly to GND. The output sourcing
current is provided by a P channel pull-up device that can supply GND terminated loads, especially important at the –10%
supply tolerance value of 4.5 V.
V
DD
P-CH
V
OUT
N-CH
AGND
Figure 5. Equivalent Analog Output Circuit
Figures 6 and 7 in the typical performance characteristics section provide information on output swing performance near
ground and full scale as a function of load. In addition to resistive load driving capability the amplifier has also been carefully
designed and characterized for up to 500 pF capacitive load
driving capability.
REFERENCE SECTION
The internal 2.5 V curvature-corrected bandgap voltage reference is laser trimmed for both initial accuracy and low temperature coefficient. The voltage generated by the reference is
available at the V
pin. Since V
REF
is not intended to drive
REF
heavy external loads, it must be buffered. The equivalent emitter follower output circuit of the V
Bypassing the V
pin will improve noise performance; how-
REF
pin is shown in Figure 4.
REF
ever, bypassing is not required for proper operation. Figure 10
shows broad band noise performance.
POWER SUPPLY
The very low power consumption of the AD8522 is a direct
result of a circuit design optimizing use of a CBCMOS process.
By using the low power characteristics of the CMOS for the
logic, and the low noise, tight matching of the complementary
bipolar transistors good analog accuracy is achieved.
For power consumption sensitive applications it is important to
note that the internal power consumption of the AD8522 is
strongly dependent on the actual in
the SDI, CLK,
CS, MSB, LDA, LDB and RS pins. Since these in-
put voltage levels present on
puts are standard CMOS logic structures, they contribute static
power dissipation dependent on the actual driving logic VOH and
VOL voltage levels. Consequently for optimum dissipation use of
CMOS logic versus TTL provides minimal dissipation in the static
state. A V
= 0 V on the logic input pins provides the lowest
INL
standby dissipation of 1 mA with a +5 V power supply.
As with any analog system, it is recommended that the AD8522
power supply be bypassed on the same PC card that contains
the chip. Figure 12 shows the power supply rejection versus frequency performance. This should be taken into account when
using higher frequency switched-mode power supplies with
ripple frequencies of 100 kHz and higher.
One advantage of the rail-to-rail output amplifiers used in the
AD8522 is the wide range of usable supply voltage. The part is
fully specified and tested over temperature for operation from
+4.5 V to +5.5 V. If reduced linearity and source current capability near full scale can be tolerated, operation of the AD8522
REV. A
–5–
AD8522
9
8
7
6
5
4
3
2
1
0
01 3452
VDD = +4.5V
VDD = +5V
TA = +25°C
SUPPLY CURRENT I
DD
– mA
LOGIC INPUT VOLTAGE VINH – Volts
is possible down to +4.3 V. The minimum operating supply
voltage versus load current plot, in Figure 7, provides information for operation below V
= +4.5 V.
DD
TIMING AND CONTROL
The AD8522 has a 16-bit serial input register that accepts
clocked in data when the CS pin is active low. The DAC registers are updated by the Load Enable (
LDA and LDB) pins.
The AD8522 offers two modes of data loading. The first mode,
hardware-load, directs the data currently clocked into the serial
shift register into either the DAC A or the DAC B register or
both depending on the external active low strobing of the
or
LDB pin. Serial data register bit Sf/Hd must be low for this
LDA
mode to be in effect.
The second mode of operation is software-load which is de-
signed to minimize the number of control lines connected to
the AD8522. In this mode of operation the
LDA and LDB pins
act as one control input taking the present contents of the serial
Typical Performance Characteristics
5
4
3
2
1
OUTPUT VOLTAGE – Volts
0
10 100 100k10k1k
RL TIED TO +5V
DATA = 000
LOAD RESISTANCE – Ω
VDD = +5V
T
= +25°C
A
RL TIED TO AGND
DATA = FFF
H
VINH = +5V
L = 0V
V
IN
H
5.2
5.0
4.8
PROPER OPERATION
4.6
MIN – Volts
DD
V
4.4
4.2
4.0
0.01
∆VFS ≤ 1 LSB
DATA = FFF
TA = +25°C
WHEN V
VOLTAGE IS ABOVE
OUTPUT LOAD CURRENT – mA
H
SUPPLY
DD
CURVE
0.1 100101.0
input register and transferring the 12 bits of data into the decoded address determined by the address bits A and B in the serial input register.
Unipolar Output Operation
This is the basic mode of operation for the AD8522. The
AD8522 has been designed to drive loads as low as 820 Ω in
parallel with 500 pF. The code table for this operation is shown
in Table III.
Table III. Unipolar Code Table
Hexadecimal Decimal Analog
Number in Number in Output
DAC Register DAC Register Voltage (V)
FFF 4095 +4.095
801 2049 +2.049
800 2048 +2.048
7FF 2047 +2.047
000 0 0
100
VDD = +5V
DATA = 000
VIH = 5.0V
10
V
1
0.1
OUTPUT PULL-DOWN VOLTAGE – mV
0.01
1 10 1000100
H
= 0.0V
IL
+85°C
–55°C
+25°C
OUTPUT SINK CURRENT – µA
Figure 6. Output Swing vs. Load
80
60
40
20
0
–20
–40
OUTPUT CURRENT – mA
–60
–80
POSITIVE
CURRENT
LIMIT
123
OUTPUT VOLTAGE – Volts
Figure 9. I
OUT
DATA = 800
NEGATIVE
CURRENT
LIMIT
vs. V
OUT
Figure 7. Minimum Supply Voltage
vs. Load Current
NBW = 1MHz
100
90
H
200µV/DIV
10
0%
100µs/DIV
TA = +25°C
Figure 10. Broadband Noise
Figure 8. Pull-Down Voltage vs. Output Sink Current Capability
Figure 11. Supply Current vs. Logic
Input Voltage
–6–
REV. A
AD8522
5V
0V
4V
0V
–SR +SR
OUTPUT INPUT
TIME – 20µs/DIV
100
90
10
0%
V
OUT
RS
TA = +25°C
V
DD
= +5V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.0
SUPPLY CURRENT – mA
–55 –35 –15 5 25 65 12545 85 105
TEMPERATURE – °C
VDD = +5.5V
VIN = +2.4V
NO LOAD
VDD = +5V
VDD = +4.5V
140
120
100
80
60
40
20
POWER SUPPLY REJECTION – dB
0
10 100 1k 10k 100k 1M
VDD = +5V ± 200mV
TA = +25°C
DATA = FFF
#299, DAC A
V
H = +5V
IN
L = 0V
V
IN
FREQUENCY – Hz
AC
H
Figure 12. Power Supply Rejection
vs. Frequency
40
35
30
25
20
FREQUENCY
15
10
5
0
TOTAL UNADJUSTED ERROR – mV
TUE = ∑ (INL+ZS+FS)
SSZ = 300 UNITS
V
= +4.5V
DD
T
= +25°C
A
543210–1–2–3–4–5
2048
LD
V
OUT
100mV/
DIV
5V
100
90
10
0%
100mV 500ns
TIME – 500ns/DIV
Figure 13. Midscale Transition
Performance
4.11
4.105
4.1
4.095
4.09
4.085
FULL SCALE VOLTAGE – Volts
4.08
4.075
AVG
–55 –35 –15 5 25 45 65 85 105 125
VDD = +4.5V
NO LOAD
SSZ = 300 UNITS
AVG +1
AVG –1
TEMPERATURE – °C
TO 2047
10
TA = +25°C
VDD = +5V
σ
σ
10
Figure 14. Large Signal Settling Time
1.6
1.4
1.2
1.0
0.8
0.6
0.4
ZERO-SCALE VOLTAGE – mV
0.2
0.0
–55 –35 –15 5 25 45 65 85 105 125
VDD = +4.5V
NO LOAD
SSZ = 300 UNITS
TEMPERATURE – °C
AVG +1
AVG
AVG –1
σ
σ
Figure 15. Total Unadjusted Error
Histogram
100
10
1.0
OUTPUT NOISE DENSITY – µV/√Hz
0.1
10 100 100k10k1k
Figure 18. Output Voltage Noise
Density vs. Frequency
REV. A
VDD = +5V
DATA = FFF
TA = +25°C
FREQUENCY – Hz
Figure 16. Full-Scale Voltage vs.
Temperature
4.096
4.095
H
4.094
4.093
4.092
4.091
4.090
4.089
4.088
4.087
4.086
4.085
FULL-SCALE OUTPUT VOLTAGE – Volts
4.084
0 100 200 300 400 500 600
HOURS OF OPERATION AT +150°C
AVG +1σ
AVG
AVG –1σ
VDD = +4.5V
SSZ = 135 UNITS
DATA = FFF
H
Figure 19. Long Term Drift Accelerated by Burn-In
Figure 17. Zero-Scale Voltage vs.
Temperature
Figure 20. Supply Current vs.
Temperature
–7–
AD8522
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.795 (20.19)
0.725 (18.42)
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.130
(3.30)
MIN
PIN 1
0.280 (7.11)
0.240 (6.10)
7
8
14
1
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
100
V
DD
90
0V
V
REF
10
0%
0V
2V
1V
TIME – 1µs/DIV
TA = +25°C
NO LOAD
= +5V
V
DD
1µs
CLK
V
OUT
20mV/
DIV
2.504
V
= +4.5V
AVG +1
AVG
AVG –1
σ
σ
5V
0V
2.502
2.500
– Volts
2.498
REF
V
DD
SSZ = 300 UNITS
2.496
TIME – 5µs/DIV
2.494
2.492
–55 –35 –15 5 25 65 12545 85 105
TEMPERATURE – °C
C1942–18–94
Figure 21. Reference Startup vs.
Time
0
–0.01
–0.02
–0.03
–0.04
AVG –3
LOAD REGULATION – %/mA
–0.05
REF
V
–0.06
–55 –35 –15 5 25 65 12545 85 105
TEMPERATURE – °C
Figure 24. Reference Load Regulation
vs. Temperature
V
= +4.5V
DD
SSZ = 300 UNITS
∆ I
= 5mA
L
AVG +3
AVG
σ
Figure 22. Digital Feedthrough vs.
Time
0.05
0.04
σ
0.03
0.02
LINE REGULATION – %/Volts
0.01
REF
V
0
–55 –35 –15 5 25 65 12545 85 105
Figure 25. Reference Line Regulation vs.
Temperature
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Figure 23. Reference Voltage vs.
Temperature
∆ V
= +4.5V TO +5.5V
DD
SSZ = 300 UNITS
AVG +3
σ
AVG
AVG –3
σ
TEMPERATURE – °C
14-Lead Epoxy DIP (N-14)14-Lead Narrow Body SOIC (SO-14)
PIN 1
0.0098 (0.25)
0.0040 (0.10)
14
1
0.3444 (8.75)
0.3367 (8.55)
0.0192 (0.49)
0.0500
(1.27)
0.0138 (0.35)
BSC
8
7
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0075 (0.19)
0.0196 (0.50)
0.0099 (0.25)
8
°
0
°
x 45
0.0500 (1.27)
0.0160 (0.41)
°
PRINTED IN U.S.A.
–8–
REV. A
Loading...