Datasheet AD8505, AD8506, AD8508 Datasheet (ANALOG DEVICES)

Page 1
20 μA Maximum, Rail-to-Rail I/O,
Zero Input Crossover Distortion Amplifiers

FEATURES

PSRR: 100 dB minimum CMRR: 105 dB typical Very low supply current: 20 μA per amplifier maximum
1.8 V to 5 V single supply or ±0.9 V to ±2.5 V dual supply Rail-to-rail input/output Low noise: 45 nV/√Hz at 1 kHz
2.5 mV offset voltage maximum Very low input bias current: 1 pA typical

APPLICATIONS

Pressure and position sensors Remote security Bio sensors IR thermometers Battery-powered consumer equipment Hazard detectors

GENERAL DESCRIPTION

The AD8505/AD8506/AD8508 are single, dual, and quad micro­power amplifiers featuring rail-to-rail input/output swings while operating from a single 1.8 V to 5 V power supply or from dual ±0.9 V to ±2.5 V power supplies. Using a new circuit technology, these amplifiers offer zero input crossover distortion (excellent PSRR and CMRR performance) and low bias current while operating with a supply current of less than 20 µA per amplifier. This amplifier family offers the lowest noise in its power class.
This combination of features makes the AD8505/AD8506/AD8508 amplifiers ideal choices for battery-powered applications because they minimize errors due to power supply voltage variations over the lifetime of the battery and maintain high CMRR even for a rail­to-rail input op amp. Remote battery-powered sensors, handheld instrumentation, consumer equipment, hazard detection (for example, smoke, fire, and gas), and patient monitors can benefit from the features of the AD8505/AD8506/AD8508 amplifiers.
The AD8505/AD8506/AD8508 are specified for both the industrial temperature range of −40°C to +85°C and the extended industrial temperature range of −40°C to +125°C. The AD8505 single ampli­fier is available in a tiny 5-lead SOT-23 and a 6-ball WLCSP packages. The AD8506 dual amplifier is available in 8-lead MSOP and 8-ball WLCSP packages. The AD8508 quad amplifier is available in 14-lead TSSOP and 14-ball WLCSP packages. The AD8505/AD8506/AD8508 are members of a growing series of zero crossover distortion op amps offered by Analog Devices, Inc., including the ADA4505-1/ADA4505-2/ADA4505-4, that operate from a single 1.8 V to 5 V supply or from dual ±0.9 V to ±2.5 V power supplies.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
AD8505/AD8506/AD8508

PIN CONFIGURATIONS

BALL A1 INDICATOR
OUT V+
A1 A2
V–
NC
B1 B2
+IN –IN
1
OUT
+IN
V–
AD8505
2
TOP VIEW
(Not to Scale)
3
V+
5
–IN
4
06900-051
Figure 1. 5-Lead SOT-23 (RJ-5) Figure 2. 6-Ball WLCSP (CB-6-7)
OUT A
–IN A
+IN A
V–
1
AD8506
2
TOP VIEW
3
(Not to Scale)
4
8
7
6
5
V+
OUT B
–IN B
+IN B
06900-002
Figure 3. 8-Lead MSOP (RM-8) Figure 4. 8-Ball WLCSP (CB-8-2)
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
1
2
3
AD8508
TOP VIEW
4
(Not to Scale)
5
6
7
14
13
12
11
10
9
8
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
06900-045
Figure 5. 14-Lead TSSOP (RU-14) Figure 6. 14-Ball WLCSP (CB-14-1)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
C1 C2
AD8505
TOP VIEW
(BALL SIDE DOW N)
Not to Scale
NC = NO CONNECT
BALL A1 CORNER
OUT B V+ OUT A
A1 A2 A3
–IN B –IN A
B1 B3
+IN B V– +IN A
C1 C2 C3
AD8506
TOP VIEW
(BALL SI DE DOW N)
Not to Scale
BALL A1 CORNER
OUTD OUTA –INA
A1
A2
–IND V– +INA
B1
B2
+IND +INB
C1
+INC V+ –INB
D1
D2
–INC OUTC
E1
E2
AD8508
TOP VIEW
(BALL SI DE DOWN)
Not to Scale
06900-100
06900-001
A3
B3
C3
D3
OUTB
E3
06900-104
Page 2
AD8505/AD8506/AD8508

TABLE OF CONTENTS

Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—1.8 V Operation ............................ 3
Electrical Characteristics—5 V Operation................................ 4
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5

REVISION HISTORY

5/10—Rev. D to Rev. E
Added AD8505, 6-Ball WLCSP Package ......................... Universal
Changes to Large-Signal Voltage Gain Parameter (Table 1) ....... 4
Changes to Large-Signal Voltage Gain Parameter (Table 2) ....... 5
Changes to Table 4 ............................................................................ 6
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 21
10/09—Rev. C to Rev. D
Added AD8505, 5-Lead SOT-23 Package ....................... Universal
Changes to General Description, Added Figure 1 ....................... 1
Moved Electrical Characteristics—1.8 V Operation Section,
Changes to Supply Current per Amplifier Parameter, Table 1 ..... 3
Moved Electrical Characteristics—5 V Operation Section,
Changes to Supply Current per Amplifier Parameter, Table 2 ..... 4
Changes to Thermal Resistance Section and Table 4 ................... 5
Changes to Figure 20 and Figure 23 ............................................... 8
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 17
3/09—Rev. B to Rev. C
Added AD8508, 14-Ball WLCSP Package ....................... Universal
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 18
10/08—Rev. A to Rev. B
Added WLCSP Package ..................................................... Universal
Added Figure 2; Renumbered Sequentially .................................. 1
Added Input Resistance Parameter ................................................ 3
Changes to Input Capacitance Differential Mode Parameter Symbol and Input Capacitance Common Mode Parameter
Symbol ................................................................................................ 3
Added Input Resistance Parameter ................................................ 4
Changes to Input Capacitance Differential Mode Parameter Symbol and Input Capacitance Common Mode Parameter
Symbol ................................................................................................ 4
Rev. E | Page 2 of 20
ESD Caution...................................................................................5
Typical Performance Characteristics ..............................................6
Theory of Operation ...................................................................... 13
Applications Information .............................................................. 15
Pulse Oximeter Current Source ............................................... 15
Four-Pole, Low-Pass Butterworth Filter for Glucose
Monitor ........................................................................................ 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 20
Changes to Table 4 ............................................................................. 5
Changes to Figure 46 ...................................................................... 16
Updated Outline Dimensions ....................................................... 17
Added Figure 49 ............................................................................. 17
Changes to Ordering Guide .......................................................... 18
7/08—Rev. 0 to Rev. A
Added AD8508 ................................................................... Universal
Added TSSOP Package ...................................................... Universal
Changes to Features Section and General Description Section .. 1
Added Figure 2; Renumbered Sequentially ................................... 1
Changed Electrical Characteristics Heading to Electrical
Characteristics—5 V Operation ...................................................... 3
Changes to Table 1 ............................................................................. 3
Added Electrical Characteristics—1.8 V Operation Heading ..... 4
Changes to Table 2 ............................................................................. 4
Changes to Table 3, Thermal Resistance Section, and Table 4 .... 5
Added T
Characteristics Section ..................................................................... 6
Changes to Figure 3, Figure 4, Figure 6, and Figure 7 .................. 6
Added Figure 11 and Figure 14 ....................................................... 7
Changes to Figure 17 Through Figure 20....................................... 8
Changes to Figure 21 Through Figure 26....................................... 9
Changes to Figure 27, Figure 28, Figure 30, and Figure 31....... 10
Changes to Figure 34, Figure 37, and Figure 38 ......................... 11
Added Figure 39 and Figure 40 .................................................... 12
Added Theory of Operation Section, Figure 41, and
Figure 42 .......................................................................................... 13
Added Figure 43 and Figure 44 .................................................... 14
Added Applications Information Section and Figure 45 .......... 15
Added Figure 46 ............................................................................. 16
Updated Outline Dimensions ....................................................... 17
Added Figure 48 ............................................................................. 17
Changes to Ordering Guide .......................................................... 17
11/07—Revision 0: Initial Version
= 25°C Condition to Typical Performance
A
Page 3
AD8505/AD8506/AD8508

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—1.8 V OPERATION

VSY = 1.8 V, VCM = VSY/2, TA = 25°C, RL = 100 k to GND, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 0 V VCM ≤ 1.8 V 0.5 2.5 mV
−40°C TA ≤ +125°C 3.5 mV Input Bias Current IB 1 10 pA
−40°C TA ≤ +85°C 100 pA
−40°C TA ≤ +125°C 600 pA Input Offset Current IOS 0.5 5 pA
−40°C TA ≤ +85°C 50 pA
−40°C TA ≤ +125°C 100 pA Input Voltage Range −40°C ≤ TA ≤ +125°C 0 1.8 V Common-Mode Rejection Ratio CMRR 0 V ≤ VCM ≤ 1.8 V 85 100 dB
−40°C TA ≤ +85°C 85 dB
−40°C TA ≤ +125°C 80 dB Large-Signal Voltage Gain AVO
0.05 V ≤ V R
L
OUT
= 100 kΩ to VCM
≤ 1.75 V,
95 115 dB
−40°C TA ≤ +125°C 95 dB Offset Voltage Drift
ΔV
OS
/ΔT
−40°C ≤ T
≤ +125°C 2.5 μV/°C
A
Input Resistance RIN 220 GΩ Input Capacitance, Differential Mode C Input Capacitance, Common Mode C
3 pF
INDM
4.2 pF
INCM
OUTPUT CHARACTERISTICS
Output Voltage High VOH R
= 100 kΩ to GND 1.78 1.79 V
L
−40°C TA ≤ +125°C 1.78 V R
= 10 kΩ to GND 1.65 1.75 V
L
−40°C TA ≤ +125°C 1.65 V Output Voltage Low VOL R
= 100 kΩ to VSY 2 5 mV
L
−40°C TA ≤ +125°C 5 mV R
= 10 kΩ to VSY 12 25 mV
L
−40°C TA ≤ +125°C 25 mV Short-Circuit Limit ISC V
= VSY or GND ±4.5 mA
OUT
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = 1.8 V to 5 V 100 110 dB
−40°C TA ≤ +85°C 100 dB
−40°C TA ≤ +125°C 95 dB Supply Current per Amplifier ISY
AD8506/AD8508 V
= VSY/2 16.5 20 μA
OUT
−40°C TA ≤ +125°C 25 μA AD8505 V
= VSY/2 16.5 24 μA
OUT
−40°C TA ≤ +125°C 27.5 μA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 100 kΩ, CL = 10 pF, G = 1 13 mV/μs Gain Bandwidth Product GBP RL = 1 MΩ, CL = 20 pF, G = 1 95 kHz Phase Margin Φ
M
RL = 1 MΩ, CL = 20 pF, G = 1 60 Degrees
NOISE PERFORMANCE
Voltage Noise en p-p f = 0.1 Hz to 10 Hz 2.8 μV p-p Voltage Noise Density en f = 1 kHz 45 nV/√Hz Current Noise Density in f = 1 kHz 15 fA/√Hz
Rev. E | Page 3 of 20
Page 4
AD8505/AD8506/AD8508

ELECTRICAL CHARACTERISTICS—5 V OPERATION

VSY = 5 V, VCM = VSY/2, TA = 25°C, RL = 100 k to GND, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 0 V VCM ≤ 5 V 0.5 2.5 mV
−40°C TA ≤ +125°C 3.5 mV Input Bias Current IB 1 10 pA
−40°C TA ≤ +85°C 100 pA
−40°C TA ≤ +125°C 600 pA Input Offset Current IOS 0.5 5 pA
−40°C TA ≤ +85°C 50 pA
−40°C TA ≤ +125°C 130 pA Input Voltage Range −40°C ≤ TA ≤ +125°C 0 5 V Common-Mode Rejection Ratio CMRR 0 V ≤ VCM ≤ 5 V 90 105 dB
−40°C TA ≤ +85°C 90 dB
−40°C TA ≤ +125°C 85 dB Large-Signal Voltage Gain AVO
0.05 V ≤ V R
= 100 kΩ to VCM
L
≤ 4.95 V,
OUT
−40°C TA ≤ +125°C 100 dB Offset Voltage Drift
ΔV
OS
/ΔT
−40°C ≤ T
≤ +125°C 2 μV/°C
A
Input Resistance RIN 220 GΩ Input Capacitance, Differential Mode C Input Capacitance, Common Mode C
3 pF
INDM
4.2 pF
INCM
OUTPUT CHARACTERISTICS
Output Voltage High VOH R
= 100 kΩ to GND 4.98 4.99 V
L
−40°C TA ≤ +125°C 4.98 V R
= 10 kΩ to GND 4.9 4.95 V
L
−40°C TA ≤ +125°C 4.9 V Output Voltage Low VOL R
= 100 kΩ to VSY 2 5 mV
L
−40°C TA ≤ +125°C 5 mV R
= 10 kΩ to VSY 10 25 mV
L
−40°C TA ≤ +125°C 30 mV Short-Circuit Limit ISC V
= VSY or GND ±45 mA
OUT
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = 1.8 V to 5 V 100 110 dB
−40°C TA ≤ +85°C 100 dB
−40°C TA ≤ +125°C 95 dB Supply Current per Amplifier ISY
AD8506/AD8508 V
= VSY/2 15 20 μA
OUT
−40°C TA ≤ +125°C 25 μA AD8505 −40°C TA ≤ +125°C 25.5 μA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 100 kΩ, CL = 10 pF, G = 1 13 mV/μs Gain Bandwidth Product GBP RL = 1 MΩ, CL = 20 pF, G = 1 95 kHz Phase Margin ΦM R
= 1 MΩ, CL = 20 pF, G = 1 60 Degrees
L
NOISE PERFORMANCE
Voltage Noise en p-p f = 0.1 Hz to 10 Hz 2.8 μV p-p Voltage Noise Density en f = 1 kHz 45 nV/√Hz Current Noise Density in f = 1 kHz 15 fA/√Hz
105 120 dB
Rev. E | Page 4 of 20
Page 5
AD8505/AD8506/AD8508

ABSOLUTE MAXIMUM RATINGS

Table 3.
Parameter Rating
Supply Voltage 5.5 V Input Voltage ±VSY ± 0.1 V Input Current1 ±10 mA Differential Input Voltage2 ±VSY Output Short-Circuit Duration to GND Indefinite Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +125°C Junction Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C
1
Input pins have clamp diodes to the supply pins. The input current should
be limited to 10 mA or less whenever the input signal exceeds the power supply rail by 0.5 V.
2
The differential input voltage is limited to 5 V or the supply voltage, whichever
is less.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages with its exposed paddle soldered to a pad, if applicable. Table 4 shows simulated thermal values for a 4-layer (2S2P) JEDEC standard thermal test board, unless otherwise specified.
Table 4.
Package Type θJA θJC Unit
5-Lead SOT-23 (RJ-5) 190 92 °C/W 6-Ball WLCSP (CB-6-7) 105 N/A °C/W 8-Lead MSOP (RM-8) 142 45 °C/W 8-Ball WLCSP (CB-8-2) 82 N/A °C/W 14-Lead TSSOP (RU-14) 112 35 °C/W 14-Ball WLCSP (CB-14-1) 64 N/A °C/W

ESD CAUTION

Rev. E | Page 5 of 20
Page 6
AD8505/AD8506/AD8508

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, unless otherwise noted.
250
200
VSY = 1.8V
= VSY/2
V
CM
250
200
VSY = 5V V
= VSY/2
CM
150
100
NUMBER OF AMPLIFIERS
50
0
–4 –1–3 0–2 1 2 3 4
VOS (mV)
Figure 7. Input Offset Voltage Distribution
16
14
12
10
8
6
NUMBER OF AMPLIFIERS
4
2
0
012345678910111213
TCVOS (µV/°C)
VSY = 1.8V –40°C T
A
Figure 8. Input Offset Voltage Drift Distribution
2000
1500
+125°C
VSY = 1.8V
150
100
NUMBER OF AMPLIFIERS
50
0
–4 –1–3 0–2 1 2 3 4
06900-003
VOS (mV)
06900-006
Figure 10. Input Offset Voltage Distribution
12
10
8
6
4
NUMBER OF AMPLIFIERS
2
0
012345678910111213
06900-004
TCVOS (µV/°C)
VSY = 5V –40°C T
+125°C
A
06900-007
Figure 11. Input Offset Voltage Drift Distribution
2000
1500
VSY = 5V
1000
500
(µV)
0
OS
V
–500
–1000
–1500
–2000
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
VCM (V)
Figure 9. Input Offset Voltage vs. Input Common-Mode Voltage
06900-005
Rev. E | Page 6 of 20
1000
500
(µV)
0
OS
V
–500
–1000
–1500
–2000
012345
VCM (V)
Figure 12. Input Offset Voltage vs. Input Common-Mode Voltage
06900-008
Page 7
AD8505/AD8506/AD8508
TA = 25°C, unless otherwise noted.
–115
VSY = 1.8V
–120
VSY = 5V
–120
–125
(µV)
OS
V
–130
–135
–140
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
VCM (V)
Figure 13. Input Offset Voltage vs. Input Common-Mode Voltage
600
550
500
450
400
(pA)
B
I
350
300
VSY = 1.8V
–125
–130
(µV)
–135
OS
V
–140
–145
–150
06900-037
054321
VCM (V)
06900-038
Figure 16. Input Offset Voltage vs. Input Common-Mode Voltage
600
550
500
450
400
(pA)
B
I
350
300
VSY = 5V
250
200
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
VCM (V)
06900-009
Figure 14. Input Bias Current vs. Input Common-Mode Voltage at 125°C
1000
VSY = 1.8V
= VSY/2
V
CM
100
10
(pA)
B
I
1
0.1
0.01 25 35 45 55 65 75 85 95 105 115 125
TEMPERATURE ( °C)
06900-018
Figure 15. Input Bias Current vs. Temperature
250
200
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VCM (V)
Figure 17. Input Bias Current vs. Input Common-Mode Voltage at 125°C
1000
VSY = 5V V
= VSY/2
CM
100
10
(pA)
B
I
1
0.1
0.01 25 35 45 55 65 75 85 95 105 115 125
TEMPERATURE ( °C)
06900-019
Figure 18. Input Bias Current vs. Temperature
06900-012
Rev. E | Page 7 of 20
Page 8
AD8505/AD8506/AD8508
TA = 25°C, unless otherwise noted.
10k
VSY = 1.8V
10k
VSY = 5V
1k
100
V
VDD – V
10
1
OUTPUT VOLTAGE TO SUPPLY RAIL (mV)
0.1
0.001 10
0.01 0.1 1
OH
LOAD CURRENT (mA)
OL
Figure 19. Output Voltage to Supply Rail vs. Load Current
14
VSY = 1.8V
12
VDD – VOH @ RL = 10k
10
8
@ RL = 10k
V
6
4
– VOH @ RL = 100k
V
DD
2
OUTPUT VOLT AGE TO SUPPLY RAIL (mV)
0
–40 –25 –10 5 20 35 50 65 80 95 110 125
@ RL = 100k
V
OL
TEMPERATURE (° C)
OL
Figure 20. Output Voltage to Supply Rail vs. Temperature
90
VCM = VSY/2
80
70
60
50
40
30
20
TOTAL SUPPLY CURRENT (µ A)
10
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)
Figure 21. Total Supply Current vs. Supply Voltage
AD8508 AD8506 AD8505
1k
VDD – V
100
10
1
0.1
OUTPUT VOLTAGE TO SUPPLY RAIL (mV)
0.01
6900-010
0.001 10 100
0.01 0.1 1 LOAD CURRENT (mA)
OH
V
OL
6900-013
Figure 22. Output Voltage to Supply Rail vs. Load Current
14
VSY = 5V
12
VDD – VOH @ RL = 10k
10
8
@ RL = 10k
V
6
4
– VOH @ RL = 100k
V
DD
2
OUTPUT VOLT AGE TO SUPPLY RAIL (mV)
0
06900-011
–40 –25 –10 5 20 35 50 65 80 95 110 125
V
OL
@ RL = 100k
OL
TEMPERATURE (° C)
06900-014
Figure 23. Output Voltage to Supply Rail vs. Temperature
90
VCM = VSY/2
80
70
60
AD8508, 1.8V AD8508, 5V
50
AD8506, 1.8V AD8606, 5V AD8505, 1.8V
40
AD8505, 5V
30
20
TOTAL SUPPLY CURRENT (µ A)
10
0
06900-052
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
06900-053
Figure 24. Total Supply Current vs. Temperature
Rev. E | Page 8 of 20
Page 9
AD8505/AD8506/AD8508
TA = 25°C, unless otherwise noted.
120
100
80
60
40
20
0
–20
OPEN-LOOP GAIN (dB)
–100
–120
–40
–60
–80
GAIN, CL = 0pF PHASE, C
L
GAIN, C
= 50pF
L
PHASE, C
L
GAIN, C
= 100pF
L
PHASE, C
L
100 1k 10k 100k 1M
PHASE
GAIN
= 0pF
= 50pF
= 100pF
FREQUENCY (Hz)
VSY = 1.8V
Figure 25. Open-Loop Gain and Phase vs. Frequency
120
100
80
60
40
20
0
–20
–40
–60
–80
–100
–120
PHASE (Degrees)
06900-022
120
100
80
60
40
20
0
OPEN-LOOP GAIN (dB)
–100
–20
–40
–60
–80
GAIN, CL = 0pF PHASE, C
L
GAIN, C
= 50pF
L
PHASE, C
L
GAIN, C
= 100pF
L
PHASE, C
L
100 1k 10k 100k 1M
PHASE
GAIN
= 0pF
= 50pF
= 100pF
FREQUENCY (Hz)
VSY = 5V
Figure 28. Open-Loop Gain and Phase vs. Frequency
120
100
80
60
40
20
0
–20
–40
–60
–80
–100
PHASE (Degrees)
06900-025
50
G= –100
40
30
G= –10
20
10
G= –1
0
–10
–20
CLOSED-LOOP GAIN (dB)
–30
–40
–50
100 1M
1k 10k 100k
FREQUENCY ( Hz)
VSY = 1.8V
Figure 26. Closed-Loop Gain vs. Frequency
10k
1k
G = 100
100
(Ω)
OUT
Z
10
G = 10
G = 1
VSY = 1.8V
50
G= –100
40
30
G= –10
20
10
G= –1
0
–10
–20
CLOSED-LOOP GAIN (dB)
–30
–40
–50
6900-017
100 1M
1k 10k 100k
FREQUENCY (Hz)
VSY = 5V
6900-020
Figure 29. Closed-Loop Gain vs. Frequency
10k
1k
G = 100
100
(Ω)
10
OUT
Z
1
G = 10
G = 1
VSY = 5V
1
0.1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 27. Z
vs. Frequency
OUT
06900-028
Rev. E | Page 9 of 20
0.1
0.01 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 30. Z
vs. Frequency
OUT
06900-031
Page 10
AD8505/AD8506/AD8508
TA = 25°C, unless otherwise noted.
100
VSY = 1.8V
100
VSY = 5V
90
80
70
CMRR (dB)
60
50
40
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 31. CMRR vs. Frequency
100
90
80
70
60
50
PSRR (dB)
40
30
20
10
0
10 100 1k 10k 100k 1M
PSRR–
FREQUENCY (Hz)
VSY = 1.8V
PSRR+
Figure 32. PSRR vs. Frequency
80
VSY = 1.8V R
= 100k
L
70
90
80
70
CMRR (dB)
60
50
40
10 100 1k 10k 100k 1M
06900-029
FREQUENCY (Hz)
06900-032
Figure 34. CMRR vs. Frequency
100
90
80
70
60
50
PSRR (dB)
40
30
20
10
0
10 100 1k 10k 100k 1M
06900-023
FREQUENCY (Hz)
PSRR–
VSY = 5V
PSRR+
06900-026
Figure 35. PSRR vs. Frequency
80
VSY = 5V R
= 100k
L
70
60
50
40
30
OVERSHOOT (%)
–OVERSHOOT
20
10
0
10 600100
+OVERSHOOT
LOAD CAPACITANCE ( pF)
Figure 33. Small-Signal Overshoot vs. Load Capacitance
06900-027
Rev. E | Page 10 of 20
60
50
40
30
OVERSHOOT (%)
–OVERSHOOT
20
10
0
10 600100
+OVERSHOOT
LOAD CAPACITANCE ( pF)
Figure 36. Small-Signal Overshoot vs. Load Capacitance
06900-030
Page 11
AD8505/AD8506/AD8508
TA = 25°C, unless otherwise noted.
VOLTAGE (500mV/DIV)
TIME ( 100µs/DIV)
Figure 37. Large-Signal Transient Response
VOLTAGE (5mV/DIV)
VSY = 1.8V R
= 100k
L
C
= 200pF
L
G = 1
VSY = 1.8V R
= 100k
L
C
= 200pF
L
G = 1
VSY = 5V
= 100k
R
L
C
= 200pF
L
G = 1
VOLTAGE (1V/DIV)
06900-033
TIME ( 100µs/DIV)
06900-035
Figure 40. Large-Signal Transient Response
VSY = 5V R
= 100k
L
= 200pF
C
L
G = 1
VOLTAGE (5mV/DIV)
TIME ( 100µs/DIV)
Figure 38. Small-Signal Transient Response
INPUT VOLTAGE NOISE (0.5µV/DIV)
TIME (4s/ DIV)
Figure 39. Input Voltage Noise 0.1 Hz to 10 Hz
VSY = 1.8V AND 5V
2.78µV p- p
06900-036
Figure 41. Small-Signal Transient Response
1k
Hz)
100
10
VOLTAGE NOISE DENSI TY (nV/
06900-034
1
1 10 100 1k 10k
Figure 42. Voltage Noise Density vs. Frequency
TIME ( 100µs/DIV)
FREQUENCY (Hz)
06900-046
VSY = 1.8V AND 5V
06900-047
Rev. E | Page 11 of 20
Page 12
AD8505/AD8506/AD8508
TA = 25°C, unless otherwise noted.
–50
–60
40
100k
10k
VSY = 1.8V V
= 1.5V p-p
IN
–50
–60
40
100k
10k
VSY = 5V V
= 4V p-p
IN
–70
–80
–90
–100
CHANNEL SEPARATIO N (dB)
–110
–120
100 1k 10k 100k
FREQUENCY (Hz)
Figure 43. Channel Separation vs. Frequency
06900-049
–70
–80
–90
–100
CHANNEL SEPARATIO N (dB)
–110
–120
100 1k 10k 100k
FREQUENCY (Hz)
Figure 44. Channel Separation vs. Frequency
06900-048
Rev. E | Page 12 of 20
Page 13
AD8505/AD8506/AD8508
V

THEORY OF OPERATION

The AD8505/AD8506/AD8508 are unity-gain, stable, CMOS, rail­to-rail input/output operational amplifiers designed to optimize performance in current consumption, PSRR, CMRR, and zero crossover distortion, all embedded in a small package. The typical offset voltage is 500 µV, with a low peak-to-peak voltage noise of 2.8 µV from 0.1 Hz to 10 Hz and a voltage noise density of 45 nV/√Hz at 1 kHz.
The AD8505/AD8506/AD8508 amplifiers are designed to solve two key problems in low voltage battery-powered applications: the battery voltage decrease over time and the rail-to-rail input stage distortion.
In battery-powered applications, the supply voltage available to the IC is the voltage of the battery. Unfortunately, the voltage of a battery decreases as it discharges itself through the load. This voltage drop over the lifetime of the battery causes an error in the output of the op amps. Some applications requiring precision measurements during the entire lifetime of the battery use voltage regulators to power up the op amps as a solution. If a design uses standard battery cells, the op amps experience a supply voltage change from roughly 3.2 V to 1.8 V during the lifetime of the battery. This means that for a PSRR of 70 dB minimum in a typical op amp, the input-referred offset error is approximately 440 µV. If the same application uses the AD8505/AD8506/ AD8508 amplifiers with a 100 dB minimum PSRR, the error is only 14 µV. It is possible to calibrate out this error or to use an external voltage regulator to power the op amp, but these solutions can increase system cost and complexity. The AD8505/AD8506/ AD8508 amplifiers solve the impasse with no additional cost or error-nullifying circuitry.
The second problem with battery-powered applications is the distortion caused by the standard rail-to-rail input stage. Using a CMOS non-rail-to-rail input stage (that is, a single differential pair) limits the input voltage to approximately one V source voltage) away from one of the supply lines. Because V
(gate-
GS
GS
for normal operation is commonly over 1 V, a single differential pair input stage op amp greatly restricts the allowable input voltage range when using a low supply voltage. This limitation restricts the number of applications where the non-rail-to-rail input op amp was originally intended to be used. To solve this problem, a dual differential pair input stage is usually implemented (see Figure 45); however, this technique has its own drawbacks.
One differential pair amplifies the input signal when the common­mode voltage is on the high end, whereas the other pair amplifies the input signal when the common-mode voltage is on the low end. This method also requires control circuitry to operate the two differential pairs appropriately. Unfortunately, this topology leads to a very noticeable and undesirable problem: if the signal level moves through the range where one input stage turns off and the other one turns on, noticeable distortion occurs (see Figure 46).
V
IN+
Q3 Q1
I
B
V
SS
Figure 45. A Typical Dual Differential Pair Input Stage Op Amp
(Dual PMOS Q1 and Q2 Transistors Form the Lower End of the Input Voltage
Range, Whereas Dual NMOS Q3 and Q4 Compose the Upper End)
300
VSY = 5V
250
= 25°C
T
A
200
150
100
50
0
(µV)
OS
–50
V
–100
–150
–200
–250
–300
0
Figure 46. Typical Input Offset Voltage vs. Common-Mode Voltage
Response in a Dual Differential Pair Input Stage Op Amp (Powered by 5 V
Supply; Results of Approximately 100 Units per Graph Are Displayed)
Q2
1.5 3. 5 5.0
1.00.5 2.5 4.54.03.02.0
This distortion forces the designer to devise impractical ways to avoid the crossover distortion areas, therefore narrowing the common-mode dynamic range of the operational amplifier. The AD8505/AD8506/AD8508 amplifiers solve this crossover dis­tortion problem by using an on-chip charge pump to power the input differential pair. The charge pump creates a supply voltage higher than the voltage of the battery, allowing the input stage to handle a wide range of input signal voltages without using a second differential pair. With this solution, the input voltage can vary from one supply extreme to the other with no distortion, thereby restoring the full common-mode dynamic range of the op amp.
DD
Q4
VCM (V)
V
BIAS
V
IN–
I
B
06900-039
06900-040
Rev. E | Page 13 of 20
Page 14
AD8505/AD8506/AD8508
V
V
V
V
The charge pump has been carefully designed so that switching noise components at any frequency, both within and beyond the amplifier bandwidth, are much lower than the thermal noise floor. Therefore, the spurious-free dynamic range (SFDR) is limited only by the input signal and the thermal or flicker noise. There is no intermodulation between the input signal and the switching noise.
Figure 47 displays a typical front-end section of an operational amplifier with an on-chip charge pump.
= POSITIVE PUMPED VOLTAGE =
V
BIAS
+IN
PP
PP
Q2
Q1
–IN
V
DD
V
SS
Figure 47. Typical Front-End Section of an Op Amp
with Embedded Charge Pump
+ 1.8
DD
CASCODE
STAGE
AND
RAIL-TO- RAIL
OUTPUT
STAGE
OUT
06900-041
Figure 48, the input offset voltage vs. input common-mode voltage response, shows the typical response of 12 devices. Figure 48 is expanded to make it easier to compare with Figure 46, the typical input offset voltage vs. common-mode voltage response in a dual differential pair input stage op amp.
300
250
VSY = 5V, TA = 25°C
200
150
100
50
0
(µV)
OS
–50
V
–100
–150
–200
–250
–300
0
1.5 3. 5 5.01.00.5 2.5 4.54.03. 02.0 VCM (V)
06900-042
Figure 48. Input Offset Voltage vs. Input Common-Mode Voltage Response
(Powered by a 5 V Supply; Results of 12 Units Are Displayed)
This solution improves the CMRR performance tremendously. For instance, if the input varies from rail to rail on a 2.5 V supply rail, using a part with a CMRR of 70 dB minimum, an input-referred error of 790 µV is introduced. Another part with a CMRR of 52 dB minimum generates a 6.3 mV error. The AD8505/AD8506/AD8508 CMRR of 90 dB minimum causes only a 79 µV error. As with the PSRR error, there are complex ways to minimize this error, but the AD8505/AD8506/AD8508 amplifiers solve this problem without incurring unnecessary circuitry complexity or increased cost.
Rev. E | Page 14 of 20
Page 15
AD8505/AD8506/AD8508
V

APPLICATIONS INFORMATION

PULSE OXIMETER CURRENT SOURCE

A pulse oximeter is a noninvasive medical device used for con­tinuously measuring the percentage of hemoglobin (Hb) saturated with oxygen and the pulse rate of a patient. Hemoglobin that is carrying oxygen (oxyhemoglobin) absorbs light in the infrared (IR) region of the spectrum; hemoglobin that is not carrying oxygen (deoxyhemoglobin) absorbs visible red (R) light. In pulse oximetry, a clip containing two LEDs (sometimes more, depending on the complexity of the measurement algorithm) and the light sensor (photodiode) is placed on the finger or earlobe of the patient. One LED emits red light (600 nm to 700 nm) and the other emits light in the near IR (800 nm to 900 nm) region. The clip is connected by a cable to a processor unit. The LEDs are rapidly and sequentially excited by two current sources (one for each LED), whose dc levels depend on the LED being driven, based on manufacturer requirements, and the detector is synchro­nized to capture the light from each LED as it is transmitted through the tissue.
An example design of a dc current source driving the red and infrared LEDs is shown in Figure 49. These dc current sources allow 62.5 mA and 101 mA to flow through the red and infrared LEDs, respectively. First, to prolong battery life, the LEDs are driven only when needed. One-third of the ADG733 SPDT analog switch is used to disconnect or connect the 1.25 V voltage reference from or to each current circuit. When driving the LEDs, the ADR1581 1.25 V voltage reference is buffered by half of the AD8506; the presence of this voltage on the noninverting input forces the output of the op amp (due to the negative feedback) to maintain a level that causes its inverting input to track the noninverting pin. Therefore, the 1.25 V appears in parallel with the 20 Ω R1 or 12.4  R5 current source resistor, creating the flow of 62.5 mA or 101 mA current through the red or infrared LED as the output of the op amp turns on the Q1 or Q2 N-MOSFET IRLMS2002.
The maximum total quiescent currents for the AD8506 (that is, half of the AD8506), ADR1581, and ADG733 are 25 µA, 70 µA, and 1 µA, respectively, resulting in a total of 96 µA current con­sumption (480 µW power consumption) per circuit, which is good for a system powered by a battery. If the accuracy and temperature
drift of the total design need to be improved, then a more accurate and low temperature coefficient drift voltage reference and current source resistor should be utilized. C3 and C4 are used to improve stabilization of U1; R3 and R7 are used to provide some current limit into the U1 inverting pin; and R2 and R6 are used to slow down the rise time of the N-MOSFET when it turns on. These elements may not be needed, or some bench adjustments may be required.
+5
CONNECT TO RED LED
+5V
C1
62.5mA
R2
22
Q1 IRLMS2002
R3
1k
R1 20
0.1% 1/4W MIN
CONNECT TO I NFRARED LED
101mA
R6
22
Q2 IRLMS2002
R7
1k
R5
12.4
0.1% 1/2W MIN
0.1µF
V
OUT1
7
C3
22pF
RED CURRENT
SOURCE
U1 1/2
AD8506
V
OUT2
1
C4
22pF
INFRARED CURRENT
SOURCE
8
V+
V–
4
+5V
V+
V–
AD8506
8
4
1/2
U1
Figure 49. Pulse Oximeter Red and Infrared Current Sources Using the
AD8506 as a Buffer to the Voltage Reference Device
C2
0.1µF
U2 ADG733
16
V
DD
S1A
D1
14
5
6
3
2
S1B
S2A
D2
15
S2B
S3A
4
D3
S3B
A2
A1
8
A0
GND
EN
V
SS
7
+5V
12
R4
53.6k
13
2
1
5
3
9 10
11
6
= 1.25V
V
REF
U3 ADR1581
I_BIT2 I_BIT1 I_BIT0 I_ENA
06900-043
Rev. E | Page 15 of 20
Page 16
AD8505/AD8506/AD8508

FOUR-POLE, LOW-PASS BUTTERWORTH FILTER FOR GLUCOSE MONITOR

There are several methods of glucose monitoring: spectroscopic absorption of infrared light in the 2 µm to 2.5 µm range, reflec­tance spectrophotometry, and the amperometric type using electrochemical strips with glucose oxidase enzymes. The amperometric type generally uses three electrodes: a reference electrode, a control electrode, and a working electrode. Although this is a well established and widely used technique, signal-to-noise ratio and repeatability can be improved using the AD8505/ AD8506/AD8508 amplifiers with their low peak-to-peak voltage noise of 2.8 µV from 0.1 Hz to 10 Hz and voltage noise density of 45 nV/√Hz at 1 kHz.
Another consideration is operation from a 3.3 V battery. Glucose signal currents are usually less than 3 µA full scale; therefore,
C1
1000pF
R1
5M
the I-to-V converter requires low input bias current. The AD8505/AD8506/AD8508 are excellent choices because these amplifiers provide 1 pA typical and 10 pA maximum of input bias current at ambient temperature.
A low-pass filter with a cutoff frequency of 80 Hz to 100 Hz is desirable in a glucose meter device to remove extraneous noise; this can be a simple two-pole or four-pole Butterworth filter. Low power op amps with bandwidths of 50 kHz to 500 kHz should be adequate. The AD8505/AD8506/AD8508 amplifiers with their 95 kHz GBP and 15 µA typical current consumption meet these requirements. A circuit design of a four-pole Butterworth filter (preceded by a one-pole, low-pass filter) is shown in Figure 50. With a 3.3 V battery, the total power consumption of this design is 297 µW typical at ambient temperature.
CONTROL
WORKING
REFERENCE
+3.3V
8
3
V+
V–
2
4
AD8506
DUPLICATE O F CIRCUIT ABO VE
R2
22.6k
1
U1 1/2
R3
22.6k
0.047µF
C2
0.1µF
C3
+3.3V
5
6
V+
V–
8
4
U1 1/2
AD8506
7
R4
22.6k
Figure 50. A Four-Pole Butterworth Filter That Can Be Used in a Glucose Meter
R5
22.6k
0.047µF
C4
0.1µF
V+
V–
8
4
U2
1/2
AD8506
1
V
OUT
06900-044
+3.3V
3
C5
2
Rev. E | Page 16 of 20
Page 17
AD8505/AD8506/AD8508
0
0

OUTLINE DIMENSIONS

3.00
2.90
2.80
.15 MAX .05 MIN
1.30
1.15
0.90
1.70
1.60
1.50
5
123
4
1.90
BSC
0.50 MAX
0.35 MIN
COMPLIANT TO JEDEC ST ANDARDS MO-178-AA
0.95 BSC
1.45 MAX
0.95 MIN
3.00
2.80
2.60
SEATING PLANE
0.20 MAX
0.08 MIN
10°
0.55
0.20
BSC
0.45
0.35
121608-A
Figure 51. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
0.645
0.600
0.555
SEATING PLANE
0.287
0.267
0.247
0.05 NOM COPLANARITY
0.80 BSC
0.40
BSC
0.40 BSC
12
BOTTOM VIEW
(BALL SIDE UP)
A
B
C
081709-A
BALL A1
IDENTIFIER
0.945
0.905
0.865
TOP VIEW
(BALL SIDE DOWN)
1.425
1.385
1.345
0.415
0.400
0.385
0.230
0.200
0.170
Figure 52. 6-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-6-7)
Dimensions shown in millimeters
Rev. E | Page 17 of 20
Page 18
AD8505/AD8506/AD8508
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.95
0.85
0.75
0.15
0.05
COPLANARITY
0.10
3.20
3.00
2.80
8
5
5.15
4.90
4
0.40
0.25
4.65
1.10 MAX
15° MAX
6° 0°
0.23
0.09
1
0.65 BSC
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.55
0.40
100709-B
Figure 53. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
0.650
1.460
1.420 SQ
1.380
0.595
0.540
SEATING PLANE
123
BALL 1
IDENTIFIER
TOP VIEW
0.380
0.355
0.330
COPLANARITY
0.075
0.50 BALL PI TCH
0.270
0.240
0.210
0.340
0.320
0.300
BOTTOM VIEW
(BALL SI DE UP)
A
B
C
011008-B
Figure 54. 8-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-8-2)
Dimensions shown in millimeters
Rev. E | Page 18 of 20
Page 19
AD8505/AD8506/AD8508
5.10
5.00
4.90
14
4.50
4.40
4.30
1
8
6.40 BSC
7
PIN 1
0.65 BSC
1.05
1.00
0.80
0.15
0.05
COPLANARITY
0.10
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
1.20 MAX
SEATING PLANE
0.20
0.09
8° 0°
0.60
0.45
061908-A
0.75
Figure 55. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
BALL 1
IDENTIFIER
1.50
1.46
1.42
3.00
2.96
2.92
0.650
0.595
0.540
SEATING PLANE
0.340
0.320
0.300
2.00 BSC
BSC
0.50 BSC
0.50 BSC
0.50 BSC
0.25
0.25 BSC
0.25 BSC
0.25
3
2
BSC
1
A
B
C
D
TOP VIEW
(BALL SIDE DOW N)
0.50
0.380
0.355
0.330
0.10 MAX COPLANARITY
0.270
0.240
0.210
BSC
Figure 56. 14-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-14-1)
Dimensions shown in millimeters
Rev. E | Page 19 of 20
1.00
BSC
BOTTOM VIEW (BALL SIDE UP)
E
061208-A
Page 20
AD8505/AD8506/AD8508

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option Branding
AD8505ARJZ-R2 −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A2E AD8505ARJZ-R7 −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A2E AD8505ARJZ-RL −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A2E AD8505ACBZ-R7 −40°C to +125°C 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-7 A2H AD8505ACBZ-RL −40°C to +125°C 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-7 A2H AD8506ACBZ-REEL −40°C to +125°C 8-Ball Wafer Level Chip Scale Package [WLCSP] CB-8-2 A1X AD8506ACBZ-REEL7 −40°C to +125°C 8-Ball Wafer Level Chip Scale Package [WLCSP] CB-8-2 A1X AD8506ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A1X AD8506ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A1X AD8506ARMZ-REEL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A1X AD8508ARUZ −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 AD8508ARUZ-REEL −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 AD8508ACBZ-REEL −40°C to +125°C 14-Ball Wafer Level Chip Scale Package [WLCSP] CB-14-1 A27 AD8508ACBZ-REEL7 −40°C to +125°C 14-Ball Wafer Level Chip Scale Package [WLCSP] CB-14-1 A27
1
Z = RoHS Compliant Part.
©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06900-0-5/10(E)
Rev. E | Page 20 of 20
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