Datasheet AD8469 Datasheet (ANALOG DEVICES)

Fast, Rail-to-Rail, Low Power, 2.5 V to 5.5 V,

Single-Supply TTL/CMOS Comparator

AD8469

Rev. 0

rights of third parties that may result from its use. Specifications subject to change without notice. No

Trademarks and registered trademarks are the prop erty of their respective owner s.

Fax: [phone] ©2012 Analog Devices, Inc. All rights reserved.

VP NONINVERT ING

INPUT

V

N

INVERTI NG

INPUT

S

DN

INPUT

Q OUTPUT

Q OUTPUT

HYS INPUT

10490-001

AD8469

TTL/CMOS

Data Sheet

FEATURES

Qualified for automotive applications
Fully specified rail-to-rail at V
Input common-mode voltage: V
Low glitch TTL-/CMOS-compatible output stage
40 ns propagation delay
Low power: 1.4 mW at 2.5 V
Shutdown pin
Programmable hysteresis
Power supply rejection better than −50 dB

−40°C to +125°C operation

APPLICATIONS

High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current/voltage controlled oscillators

= 2.5 V to 5.5 V

CC

− 0.2 V to VCC + 0.2 V

EE

GENERAL DESCRIPTION

The AD8469 is a fast comparator fabricated on XFCB2, an
Analog Devices, Inc., proprietary process. This comparator is
exceptionally versatile and easy to use. Features include an input
range from V

EE

CMOS-compatible output drivers, adjustable hysteresis control,
and a shutdown input. The device offers a 40 ns propagation
delay driving a 15 pF load with 10 mV overdrive on 500 µA
typical supply current.

A flexible power supply scheme allows the device to operate
from a single +2.5 V positive supply with a −0.2 V to +2.7 V
input signal range up to a +5.5 V positive supply with a −0.2 V
to +5.7 V input signal range.

The TTL-/CMOS-compatible output stage is designed to drive
up to 15 pF with full rated timing specifications and to degrade
in a graceful and linear fashion as additional capacitance is added.
The input stage of the comparator offers robust protection against
large input overdrive, and the outputs do not phase reverse when
the valid input signal range is exceeded.

The AD8469 is available in an 8-lead MSOP package and features
a shutdown pin and hysteresis control. It is fully specified over
an operating temperature range of −40°C to +125°C.

FUNCTIONAL BLOCK DIAGRAM

− 0.2 V to VCC + 0.2 V, low noise, TTL- and

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

license is granted by implication or ot herwise under any patent or patent rights of Analog D evices.

Figure 1.

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Tel: [phone] www.analog.com

AD8469 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics ............................................................. 3

Absolute Maximum Ratings ............................................................ 4

Thermal Resistance ...................................................................... 4

ESD Caution .................................................................................. 4

Pin Configuration and Function Descriptions ............................. 5

Typical Performance Characteristics ............................................. 6

REVISION HISTORY

1/12—Revision 0: Initial Version

Applications Information .................................................................8

Power/Ground Layout and Bypassing ........................................8

TTL-/CMOS-Compatible Output Stage ....................................8

Optimizing Performance ..............................................................8

Comparator Propagation Delay Dispersion ................................8

Comparator Hysteresis .................................................................9

Crossover Bias Point .....................................................................9

Minimum Input Slew Rate Requirement ................................ 10

Typical Applications Circuits ........................................................ 11

Outline Dimensions ....................................................................... 12

Ordering Guide .......................................................................... 12

Automotive Products ................................................................. 12

Rev. 0 | Page 2 of 12

Data Sheet AD8469

Input Voltage High

VIH

Comparator is operating

2.0 VCC

V

Propagation Delay Skew

Positive Supply Current

I

VCC = 2.5 V

550

650

μA

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VCC = 2.5 V, TA = −40°C to +125°C, typical values at TA = 25°C, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

DC INPUT CHARACTERISTICS

Voltage Range VP, VN VCC = 2.5 V to 5.5 V −0.2 VCC + 0.2 V
Common-Mode Range VCM VCC = 2.5 V to 5.5 V −0.2 VCC + 0.2 V
Differential Voltage VCC = 2.5 V to 5.5 V VCC V
Offset Voltage VOS −5.0 ±3 +5.0 mV
Bias Current IP, IN −0.4 +0.4 µA
Offset Current −1.0 +1.0 µA
Capacitance CP, CN 1 pF
Differential Mode Resistance −0.5 V to VCC + 0.5 V 200 7000 kΩ
Common-Mode Resistance −0.5 V to VCC + 0.5 V 100 4000 kΩ
Active Gain AV 80 dB
Common-Mode Rejection Ratio CMRR VCM = −0.2 V to +2.7 V, VCC = 2.5 V 50 dB
VCM = −0.2 V to +2.7 V, VCC = 5.5 V 50 dB
Hysteresis R

HYSTERESIS MODE AND TIMING

Hysteresis Mode Bias Voltage Current = 1 μA 1.145 1.25 1.35 V
Minimum Resistor Value Hysteresis = 120 mV 30 120 kΩ

SHUTDOWN PIN CHARACTERISTICS1

= ∞ 0.1 mV

HYS

Input Voltage Low VIL Shutdown guaranteed −0.2 +0.4 V
Input Current High IIH VIH = VCC −6 +6 µA
Sleep Time tSD lCC < 100 µA 300 ns
Wake-Up Time tH VP = 10 mV, output valid 150 ns

DC OUTPUT CHARACTERISTICS VCC = 2.5 V

Output Voltage High VOH IOH = 0.8 mA VCC − 0.4 V
Output Voltage Low VOL IOL = 0.8 mA 0.4 V

AC PERFORMANCE2

Rise Time/Fall Time tR/tF 10% to 90%, VCC = 2.5 V 25 to 50 ns
10% to 90%, VCC = 5.5 V 45 to 75 ns
Propagation Delay tPD VOD = 10 mV, VCC = 2.5 V 30 to 50 ns
VOD = 50 mV, VCC = 5.5 V 35 to 60 ns

Rising-to-Falling Transition VCC = 2.5 V 4.5 ns

VCC = 5.5 V 8 ns

Q to Q

V

= 2.5 V 3 ns

CC

VCC = 5.5 V 4 ns
Overdrive Dispersion 10 mV < VOD < 125 mV 12 ns
Common-Mode Dispersion −0.2 V < VCM < VCC + 0.2 V 1.5 ns

POWER SUPPLY

Supply Voltage Range VCC 2.5 5.5 V

VCC

VCC = 5.5 V 800 1100 μA

Power Dissipation PD VCC = 2.5 V 1.4 1.7 mW
VCC = 5.5 V 4.5 7 mW
Power Supply Rejection Ratio PSRR VCC = 2.5 V to 5.5 V −50 dB
Shutdown Current ISD VCC = 2.5 V to 5.5 V 150 260 μA

1

The output is high impedance when the device is in shutdown mode. Note that this feature must be used with care because the enable/disable time is much longer

than with a true tristate output.

2

VIN = 100 mV square input at 1 MHz, VCM = 0 V, CL = 15 pF, VCC = 2.5 V, unless otherwise noted.

Rev. 0 | Page 3 of 12

AD8469 Data Sheet

VCC to Ground

−0.5 V to +6.0 V

Shutdown Pin, SDN

±50 mA

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltages, VCC and VEE

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Differential Supply Voltage −6.0 V to +6.0 V

Analog Inputs, VP and VN

Input Voltage −0.5 V to VCC + 0.5 V
Differential Input Voltage ±(VCC + 0.5 V)
Maximum Input/Output Current ±50 mA

Applied Voltage (SDN to Ground) −0.5 V to VCC + 0.5 V
Maximum Input/Output Current ±50 mA

Hysteresis Control Pin, HYS

Applied Voltage (HYS to Ground) −0.5 V to VCC + 0.5 V

Maximum Input/Output Current ±50 mA
Output Current, Q and Q
Operating Temperature

Ambient Temperature Range −40°C to +125°C

Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Table 3.

Package Type θ

8-Lead MSOP (RM-8) 130 °C/W

1

Measurement in still air.

1

Unit

JA

ESD CAUTION

Rev. 0 | Page 4 of 12

Data Sheet AD8469

AD8469

TOP VIEW

(Not to S cale)

V

CC

1

Q

8

V

P

2

Q

7

V

N

3

V

EE

6

S

DN

4

HYS

5

10490-002

6

VEE

Negative Supply Voltage.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 VCC Positive Supply Voltage.
2 VP Noninverting Analog Input.
3 VN Inverting Analog Input.
4 SDN Shutdown. Drive this pin low to shut down the device.
5 HYS Hysteresis Control. Bias this pin with a resistor or current source for hysteresis.

7 Q

8

Q Inverting Output. In compare mode, Q is at logic low if the analog voltage at the noninverting input (VP) is

Noninverting Output. In compare mode, Q is at logic high if the analog voltage at the noninverting input (V
is greater than the analog voltage at the inverting input (V

).

N

greater than the analog voltage at the inverting input (VN).

)

P

Rev. 0 | Page 5 of 12

AD8469 Data Sheet

76543210–1

HYS PIN VOLTAGE (V)

400

300

200

100

0

–100

–200

–300

–400

HYS PIN CURRENT (µA)

V

CC

= 2.5V V

CC

= 5.5V

10490-003

3.53.02.52.01.51.00.50–0.5–1.0

5
4

3

2

1

0
–1

–2

–3

–4
–5

+125°C

–40°C

+25°C

COMMON-MODE VOLTAGE (V)

BIAS CURRENT (µ A)

10490-004

VCC = 2.5V

150100500

OVERDRIVE (mV)

60

55

50

45

40

35

30

25

20

PROPAGATION DELAY (ns)

V

CC

= 5.5V

FALL DELAY

V

CC

= 2.5V

RISE DELAY

V

CC

= 5.5V

RISE DELAY

V

CC

= 2.5V

FALL DELAY

10490-005

16

0
150
140
130
120
110
100

90
80
70
60
50
40
30
20
10

0

HYSTERESIS (mV)

13001200110010009008007006005004003002001000

HYS RESISTOR (kΩ)

VCC = 5.5V

V

CC

= 2.5V

10490-006

4.0–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

1.5

1.0

0.5

0

–0.5

–1.0

LOAD CURRENT (mA)

SINK

SOURCE

OUTPUT VOLTAGE (V)

10490-007

0.5 1.0 1.5 2.0 2.5 3.0

38.0

37.8

37.6

37.4

37.2

37.0

36.8

36.6

36.4

36.2

36.0

PROPAGATION DELAY (ns)

COMMON-MODE VOLTAGE (V)

RISE DELAY

FALL DELAY

10490-008

VCC = 2.5V

TYPICAL PERFORMANCE CHARACTERISTICS

VCC = 2.5 V, TA = 25°C, unless otherwise noted.

Figure 3. HYS Pin Current vs. Voltage, VCC = 2.5 V and 5.5 V

Figure 4. Input Bias Current vs. Input Common-Mode Voltage, VCC = 2.5 V

Figure 6. Hysteresis vs. HYS Resistor, VCC = 2.5 V and 5.5 V

Figure 7. Load Current vs. Output Voltage

Figure 5. Propagation Delay vs. Input Overdrive, VCC = 2.5 V and 5.5 V

Figure 8. Propagation Delay vs. Input Common-Mode Voltage, VCC = 2.5 V

Rev. 0 | Page 6 of 12

Data Sheet AD8469

Q

Q

10ns/DIV0.5V/DIV

10490-009

Q

Q

10ns/DIV1V/DIV

10490-010

Figure 9. 1 MHz Output Voltage Waveform, VCC = 2.5 V

Figure 10. 1 MHz Output Voltage Waveform, VCC = 5.5 V

Rev. 0 | Page 7 of 12

AD8469 Data Sheet

APPLICATIONS INFORMATION

POWER/GROUND LAYOUT AND BYPASSING

The AD8469 comparator is a high speed device. Despite the
low noise output stage, it is essential to use proper high speed
design techniques to achieve the specified performance. Because
comparators are uncompensated amplifiers, feedback in any
phase relationship is likely to cause oscillations or undesired
hysteresis. Of critical importance is the use of low impedance
supply planes, particularly the output supply plane (V

CC

) and
the ground plane. Separate supply planes are recommended
as part of a multilayer board. Providing the lowest inductance
return path for switching currents ensures the best possible
performance in the target application.

It is also important to adequately bypass the input and output
supplies. Place a 0.1 μF bypass capacitor as close as possible to
each supply pin. The capacitors should be connected to the
ground plane with redundant vias placed to provide a physically
short return path for output currents flowing back from ground
to the V

pin. Use high frequency bypass capacitors for mini-

CC

mum inductance and effective series resistance (ESR). Parasitic
layout inductance should also be strictly controlled to maximize
the effectiveness of the bypass at high frequencies.

TTL-/CMOS-COMPATIBLE OUTPUT STAGE

To achieve the specified propagation delay performance, keep
the capacitive load at or below the specified maximum value.
The outputs of the AD8469 are designed to directly drive one
Schottky TTL or three low power Schottky TTL loads (or
equivalent). For large fan outputs, buses, or transmission lines,
use an appropriate buffer to maintain the excellent speed and
stability of the comparator.

With the rated 15 pF load capacitance applied, more than half
of the total device propagation delay is output stage slew time.
For this reason, the total propagation delay decreases as V
decreases, and instability in the power supply may appear as
excess delay dispersion.

Delay is measured to the 50% point of the supply that is in use;
therefore, the fastest times are observed with the V

CC

2.5 V, and larger delay values are observed when driving loads
that switch at other levels.

Overdrive and input slew rate dispersions are not significantly
affected by output loading and V

variations.

CC

A simplified schematic diagram of the TTL-/CMOS-compatible
output stage is shown in Figure 11. Because of its inherent sym­metry and generally good behavior, this output stage is readily
adaptable for driving various filters and other unusual loads.

CC

supply at

A1

+IN

A

V

–IN

A2

GAIN STAGE

Figure 11. Simplified Schematic Diagram of

OUTPUT STAGE

TTL-/CMOS-Compatible Output Stage

OPTIMIZING PERFORMANCE

As with any high speed comparator, proper design and layout
techniques are essential to obtain the specified performance. Stray
capacitance, inductance, common power and ground impedances,
or other layout issues can severely limit performance and often
cause oscillation. Source impedance should be minimized as
much as possible. High source impedance, in combination with
the parasitic input capacitance of the comparator, causes an unde­sirable degradation in bandwidth at the input, therefore degrading
the overall response. Higher impedances encourage undesired
coupling.

COMPARATOR PROPAGATION DELAY DISPERSION

The AD8469 comparator is designed to reduce propagation delay
dispersion over a wide input overdrive range of 10 mV to V
Propagation delay dispersion is the variation in propagation delay
that results from a change in the degree of overdrive or slew rate—
that is, how far or how fast the input signal exceeds the switching
threshold (see Figure 12 and Figure 13).

The propagation delay dispersion specification becomes important
in high speed, time critical applications, such as data communica­tion, automatic test and measurement, and instrumentation. It is
also important in event driven applications, such as pulse spectros­copy, nuclear instrumentation, and medical imaging. Dispersion is
the variation in propagation delay as the input overdrive conditions
are changed (see Figure 12).

The propagation delay dispersion of the AD8469 is typically <12 ns
as the overdrive varies from 10 mV to 125 mV. This specification
applies to both positive and negative signals because the device has
very closely matched delays for both positive-going and negative­going inputs, and very low output skews. Note that for repeatable
dispersion measurements the actual device offset is added to the
overdrive.

V

LOGIC

Q1

Q2

OUTPUT

10490-011

− 1 V.

CC

Rev. 0 | Page 8 of 12

Data Sheet AD8469

Q/Q OUTPUT

INPUT VOLTAGE

500mV OVERDRIV E

10mV OVERDRIV E

DISPERSION

V

N

± V

OS

10490-012

Q/Q OUTPUT

INPUT VOLTAGE

10V/ns

1V/ns

DISPERSION

V

N

± V

OS

10490-013

OUTPUT

INPUT

0.0V

V

OL

V

OH

+V

H

2

–V

H

2

10490-014

160
150
140
130
120
110
100

90
80
70
60
50
40
30
20
10

0

HYSTERESIS (mV)

13001200110010009008007006005004003002001000

HYS RESISTOR (kΩ)

10490-019

VCC = 5.5V

V

CC

= 2.5V

The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. One limitation of this approach is that the amount of
hysteresis varies with the output logic level, resulting in hysteresis
that is not symmetric about the threshold. The external feedback
network can also introduce significant parasitics that reduce high
speed performance and can even induce oscillation in some cases.

The AD8469 comparator offers a programmable hysteresis

Figure 12. Propagation Delay—Overdrive Dispersion

feature that significantly improves accuracy and stability. By
connecting an external pull-down resistor or current source
from the HYS pin to ground, the user can vary the amount of
hysteresis in a predictable, stable manner. Leaving the HYS pin
disconnected or driving it high removes the hysteresis. The
maximum hysteresis that can be applied using the HYS pin is
approximately 160 mV. Figure 15 illustrates the amount of
hysteresis applied as a function of the external resistor value.

Figure 13. Propagation Delay—Slew Rate Dispersion

COMPARATOR HYSTERESIS

The addition of hysteresis to a comparator is often desirable in
noisy environments or when the differential input amplitudes
are relatively small or slow moving. The transfer function for a
comparator with hysteresis is shown in Figure 14.

Figure 14. Comparator Hysteresis Transfer Function

As the input voltage approaches the threshold (0.0 V in Figure 14)
from below the threshold region in a positive direction, the com­parator switches from low to high when the input crosses +V
The new switching threshold becomes −V
remains in the high state until the threshold, −V
from below the threshold region in a negative direction. In this
way, noise or feedback output signals centered on the 0.0 V input
cannot cause the comparator to switch states unless they exceed
the region bounded by ±V

/2.

H

/2. The comparator

H

/2, is crossed

H

/2.

H

Rev. 0 | Page 9 of 12

Figure 15. Hysteresis vs. HYS Resistor

The HYS pin appears as a 1.25 V bias voltage seen through a
series resistance of 7 kΩ ± 20% throughout the hysteresis control
range. The advantages of applying hysteresis in this manner are
improved accuracy, improved stability, reduced component
count, and maximum versatility. An external bypass capacitor is
not recommended on the HYS pin because it impairs the latch
function and often degrades the jitter performance of the device.

When the HYS pin is driven low, hysteresis may become large,
but in this device, the effect is not reliable or intended as a latch
function.

CROSSOVER BIAS POINT

Rail-to-rail inputs in both op amps and comparators have a dual
front-end design. Certain devices are active near the V
others are active near the V

rail. At some predetermined point

EE

in the common-mode range, a crossover occurs. At the crossover
point (normally V

/2), the direction of the bias current is reversed

CC

and there are changes in measured offset voltages and currents.

The AD8469 elaborates slightly on this scheme. The crossover
points are at approximately 0.8 V and 1.6 V.

rail, and

CC

AD8469 Data Sheet

MINIMUM INPUT SLEW RATE REQUIREMENT

With the rated load capacitance and normal good PCB design
(see the Power/Ground Layout and Bypassing section), the

AD8469 comparator should be stable at any input slew rate with

no hysteresis. Broadband noise from the input stage is observed
in place of the excessive chatter that is seen with most other high
speed comparators.

With additional capacitive loading or poor bypassing, oscillation
may be encountered. These oscillations are due to the high gain
bandwidth of the comparator in combination with feedback
through parasitics in the package and PCB. In many applications,
chatter is not harmful.

Rev. 0 | Page 10 of 12

Data Sheet AD8469

HYS

AD8469

5V

82pF

10kΩ

150kΩ

10kΩ

150kΩ

CONTROL

VOLTAGE

0V TO 2.5V

10490-016

OUTPUT

AD8469

OUTPUT

+

–

5V

0.1µF

10k

Ω

10kΩ

INPUT

V

REF

0.02µF

HYS

10490-017

CMOS
PWM
OUTPUT

AD8469

2.5V

V

REF

INPUT

1.25V

INPUT

1.25V ± 50mV

HYS

ADCMP601

82pF

10kΩ

10kΩ

100kΩ

10kΩ

10490-018

TYPICAL APPLICATIONS CIRCUITS

Figure 16. Voltage Controlled Oscillator

Figure 17. Duty Cycle to Differential Voltage Converter

Figure 18. Oscillator and Pulse-Width Modulator

Rev. 0 | Page 11 of 12

AD8469 Data Sheet

COMPLIANT TO JEDEC STANDARDS MO-187-AA

6°
0°

0.80

0.55

0.40

4

8

1

5

0.65 BSC

0.40

0.25

1.10 MAX

3.20

3.00

2.80

COPLANARITY

0.10

0.23

0.09

3.20

3.00

2.80

5.15

4.90

4.65

PIN 1

IDENTIFIER

15° MAX

0.95

0.85

0.75

0.15

0.05

10-07-2009-B

©2012 Analog Devices, Inc. All rights reserved. Trademarks and

OUTLINE DIMENSIONS

Figure 19. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

ORDERING GUIDE

1, 2

Model

Temperature Range Package Description Package Option Branding

AD8469WBRMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 Y4F
AD8469WBRMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 Y4F

1

Z = RoHS Compliant Part.

2

W = Qualified for Automotive Applications.

AUTOMOTIVE PRODUCTS

The AD8469W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.

registered trademarks are the property of their respective owners.
D10490-0-1/12(0)

Rev. 0 | Page 12 of 12