Datasheet AD8465 Datasheet (ANALOG DEVICES)

Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,

V

V

Data Sheet

FEATURES

Fully specified rail to rail at V
Input common-mode voltage from −0.2 V to V
Low glitch LVDS-compatible output stage
Propagation delay: 1.6 ns
Power dissipation: 37 mW at 2.5 V
Shutdown pin
Single-pin control for programmable hysteresis and latch
Power supply rejection > 60 dB

−40°C to +125°C operation

APPLICATIONS

High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
Automotive

= 2.5 V to 5.5 V

CCI

+ 0.2 V

CCI

Single-Supply LVDS Comparator

AD8465

FUNCTIONAL BLOCK DIAGRAM

NONINVERTI NG

P

INVERTING

V

N

INPUT

INPUT

AD8465

V

CCI

Figure 1.

CCO

LVDS

LE/HYS INPUT

INPUT

S

DN

Q OUTPUT

Q OUTPUT

07958-001

GENERAL DESCRIPTION

The AD8465 is a very fast comparator fabricated on the Analog
Devices, Inc., proprietary XFCB2 process. This comparator is
exceptionally versatile and easy to use. Features include an
input range from V
compatible output drivers, and TTL/CMOS latch inputs with
adjustable hysteresis and/or shutdown inputs.

The device offers 1.6 ns propagation delay with 1 ps rms
random jitter (RJ). Overdrive and slew rate dispersion are
typically less than 50 ps.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

− 0.5 V to V

EE

+ 0.2 V, low noise, LVDS-

CCI

A flexible power supply scheme allows the devices to operate
with a single 2.5 V positive supply and a −0.5 V to +2.7 V input
signal range up to a 5.5 V positive supply with a −0.5 V to +5.7 V
input signal range. Split input/output supplies, with no sequencing
restrictions, support a wide input signal range with greatly
reduced power consumption.

The LVDS-compatible output stage is designed to drive any
standard LVDS input. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded. High
speed latch and programmable hysteresis features are also provided
in a unique single-pin control option.

The AD8465 is available in a 12-lead LFCSP.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009–2011 Analog Devices, Inc. All rights reserved.

AD8465 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics ............................................................. 3

Timing Information......................................................................... 5

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

REVISION HISTORY

11/11—Rev. 0 to Rev. A

Changed V

Table 1 ................................................................................................ 3

4/09—Revision 0: Initial Version

= 0.4 V to VIL = 0.8 V in Conditions of IIL,

IL

Application Information................................................................ 10

Power/Ground Layout and Bypassing..................................... 10

LVDS-Compatible Output Stage.............................................. 10

Using/Disabling the Latch Feature........................................... 10

Optimizing Performance........................................................... 10

Comparator Propagation Delay Dispersion ........................... 11

Comparator Hysteresis .............................................................. 11

Crossover Bias Points................................................................. 12

Minimum Input Slew Rate Requirement ................................ 12

Typical Application Circuits ......................................................... 13

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. A | Page 2 of 16

Data Sheet AD8465

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

V

= V

CCI

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

DC INPUT CHARACTERISTICS

Voltage Range VP, VN V
Common-Mode Range V
Differential Voltage V
Offset Voltage VOS −5.0 +5.0 mV
Bias Current IP, IN −5.0 ±2 +5.0 μA
Offset Current −2.0 +2.0 μA
Capacitance CP, CN 1 pF
Resistance, Differential Mode −0.1 V to V
Resistance, Common Mode −0.5 V to V
Active Gain AV 62 dB
Common-Mode Rejection Ratio CMRR

V
Hysteresis R

LATCH ENABLE PIN CHARACTERISTICS

VIH Hysteresis is shut off 2.0 V
VIL Latch mode guaranteed −0.2 +0.4 +0.8 V
IIH V
IIL V

HYSTERESIS MODE AND TIMING

Hysteresis Mode Bias Voltage Current sink −1 μA 1.145 1.25 1.40 V
Minimum Resistor Value Hysteresis = 120 mV 30 110 kΩ
Hysteresis Current Hysteresis = 120 mV −25 −8 μA
Latch Setup Time tS V
Latch Hold Time tH V
Latch-to-Output Delay t
Latch Minimum Pulse Width tPL V

SHUTDOWN PIN CHARACTERISTICS

VIH Comparator is operating 2.0 V
VIL Shutdown guaranteed −0.2 +0.4 +0.6 V
IIH V
IIL V
Sleep Time tSD 10% output swing 1.4 ns
Wake-Up Time tH V

DC OUTPUT CHARACTERISTICS V

Differential Output Voltage Level VOD R
ΔVOD R
Common-Mode Voltage V
Peak-to-Peak Common-Mode Output V

= 2.5 V, TA = −40°C to +125°C, typical at TA = 25 °C, unless otherwise noted.

CCO

= 2.5 V to 5.5 V −0.5 V

CCI

= 2.5 V to 5.5 V −0.2 V

CCI

= 2.5 V to 5.5 V V

CCI

200 750 7500 kΩ

CCI

+ 0.5 V 100 370 4000 kΩ

CCI

= 2.5 V, V

V

CCI

V

= −0.2 V to +2.7 V

CM

= 2.5 V, V

CCI

= ∞ <0.1 mV

HYS

= V

IH

= 0.8 V −0.1 +0.1 mA

IL

= 50 mV −2 ns

OD

= 50 mV 2.7 ns

OD

, t

VOD = 50 mV 20 ns

PLOH

PLOL

= 50 mV 24 ns

OD

= V

IH

= 0 V −0.1 mA

IL

= 50 mV, output valid 25 ns

OD

= 2.5 V to 5.0 V

CCO

LOAD

LOAD

R

OCI

OC (p-p)

LOAD

R

LOAD

CCO

CCO

+ 0.2 V −6 +6 μA

CCO

−6 +6 μA

CCO

= 100 Ω 245 350 445 mV
= 100 Ω 50 mV
= 100 Ω 1.125 1.375 V
= 100 Ω 50 mV

+ 0.2 V

CCI

+ 0.2 V

CCI

V

CCI

= 2.5 V,

50 dB

= 5.0 V 50 dB

V

CCO

V

CCO

Rev. A | Page 3 of 16

AD8465 Data Sheet

Parameter Symbol Conditions Min Typ Max Unit

AC PERFORMANCE1

Rise Time/Fall Time tR, tF 10% to 90% 600 ps
Propagation Delay tPD

V
Propagation Delay Skew—Rising to Falling Transition t
Propagation Delay Skew—Q to Q

V

PINSKEW

V

= V

V

CCI

= 50 mV

V

OD

= V

CCI

= V

CCI

= V

CCI

= 2.5 V to 5.0 V,

CCO

= 2.5 V, VOD = 10 mV 3.0 ns

CCO

= 2.5 V to 5.0 V 70 ps

CCO

= 2.5 V to 5.0 V 70 ps

CCO

Overdrive Dispersion 10 mV < VOD < 125 mV 1.6 ns
Common-Mode Dispersion VCM = −0.2 V to V

+ 0.2 V 250 ps

CCI

Input Bandwidth 500 MHz
Minimum Pulse Width PW

MIN

= V

V

CCI

= 90% of PWIN

PW

OUT

= 2.5 V to 5.0 V,

CCO

POWER SUPPLY

Input Supply Voltage Range V
Output Supply Voltage Range V
Positive Supply Differential V
V
Input Section Supply Current I
Output Section Supply Current I
Power Dissipation PD V
V
Power Supply Rejection Ratio PSRR V
Shutdown Mode I
Shutdown Mode I

1

VIN = 100 mV square input at 50 MHz, VOD = 50 mV, VCM = 1.25 V, V

V

CCI

V

CCO

2.5 5.5 V

CCI

2.5 5.0 V

CCO

− V

Operating −3 +3 V

CCI

CCO

− V

Nonoperating −5.0 +5.0 V

CCI

CCO

V

VCCI

V

VCCO

= V

= 2.5 V, unless otherwise noted.

CCI

CCO

= 2.5 V to 5.5 V 1.6 3.0 mA

CCI

= 2.5 V to 5.0 V 15 23 mA

CCO

= V

CCI

CCI

CCI

CCI

CCI

= 2.5 V 37 55 mW

CCO

= V

= 5.0 V 95 120 mW

CCO

= V

= 2.5 V to 5.0 V −50 −60 dB

CCO

= V

= 2.5 V to 5.0 V 0.92 1.1 mA

CCO

= V

= 2.5 V to 5.0 V −30 +30 μA

CCO

1.6 ns

1.3 ns

Rev. A | Page 4 of 16

Data Sheet AD8465

TIMING INFORMATION

Figure 2 illustrates the AD8465 latch timing relationships. Tabl e 2 provides definitions of the terms shown in Figure 2.

1.1V

LATCH ENABLE

DIFFERENTIAL

INPUT VOLTAGE

Q OUTPUT

Q OUTPUT

t

S

t

H

V

IN

V

OD

t

PDL

t

PDH

t

t

R

t

PL

± V

V

N

OS

t

PLOH

50%

F

50%

t

PLOL

7958-002

Figure 2. System Timing Diagram

Table 2. Timing Descriptions

Symbol Timing Description

t

Input-to-Output High Delay

PDH

Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.

t

Input-to-Output Low Delay

PDL

Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.

t

Latch Enable-to-Output High Delay

PLOH

Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.

t

Latch Enable-to-Output Low Delay

PLOL

Propagation delay measured from the 50% point of the latch enable signal high-to-low
transition to the 50% point of an output high-to-low transition.

tH Minimum Hold Time

Minimum time after the negative transition of the latch enable signal that the input

signal must remain unchanged to be acquired and held at the outputs.
tPL Minimum Latch Enable Pulse Width Minimum time that the latch enable signal must be high to acquire an input signal change.
tS Minimum Setup Time

Minimum time before the negative transition of the latch enable signal occurs that an

input signal change must be present to be acquired and held at the outputs.
tR Output Rise Time

Amount of time required to transition from a low-to-high output as measured at the

20% and 80% points.
tF Output Fall Time

Amount of time required to transition from a high-to-low output as measured at the

20% and 80% points.
VOD Voltage Overdrive Difference between the input voltages, VP and VN.

Rev. A | Page 5 of 16

AD8465 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltages

Input Supply Voltage (V
Output Supply Voltage (V
Positive Supply Differential (V

to GND) −0.5 V to +6.0 V

CCI

to GND) −0.5 V to +6.0 V

CCO

− V

CCI

) −6.0 V to +6.0 V

CCO

Input Voltages

Input Voltage −0.5 V to V
Differential Input Voltage ±(V

CCI

CCI

+ 0.5 V)

+ 0.5 V

Maximum Input/Output Current ±50 mA

Shutdown Control Pin

Applied Voltage (SDN to GND) −0.5 V to V

+ 0.5 V

CCO

Maximum Input/Output Current ±50 mA

Latch/Hysteresis Control Pin

Applied Voltage (LE/HYS to GND) −0.5 V to V

+ 0.5 V

CCO

Maximum Input/Output Current ±50 mA
Output Current ±50 mA
Temperature

Operating Temperature Range, Ambient −40°C to +125°C

Operating Temperature, Junction 150°C

Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θ

1

Unit

JA

12-Lead LFCSP_VQ (CP-12-3) 62 °C/W

1

Measurement in still air.

ESD CAUTION

Rev. A | Page 6 of 16

Data Sheet AD8465

E

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

E

12 Q

11 V

10 Q

PIN 1

1

2

3

INDICATOR

AD8465

TOP VIEW

(Not to Scale)

4

5

P

V

V

V

CCO

V

CCI

V

EE

NOTES

1. FOR BEST THERMAL PERFORMANCE,
EXPOSED PAD MUST BE SOLDERED
TO THE PCB.

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 V
2 V

Output Section Supply.

CCO

Input Section Supply.

CCI

3, 5, 9, 11 VEE Negative Supply Voltages.
4 VP Noninverting Analog Input.
6 VN Inverting Analog Input.
7 SDN Shutdown. Drive this pin low to shut down the device.
8 LE/HYS Latch/Hysteresis Control. Bias with resistor or current for hysteresis; drive low to latch.
10

Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than

Q

the analog voltage at the inverting input, VN, if the comparator is in compare mode.

12 Q

Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, V
than the analog voltage at the inverting input, V

Heat Sink Paddle VEE

The metallic back surface of the package is electrically connected to V
because Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be
soldered to the application board if improved thermal and/or mechanical stability is desired.

9 V

EE

8 LE/HYS

7 S

DN

6

N

EE

V

07958-003

, is greater

, if the comparator is in compare mode.

N

. It can be left floating

EE

P

Rev. A | Page 7 of 16

AD8465 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

V

= V

CCI

= 2.5 V, TA = 25°C, unless otherwise noted.

CCO

800

600

400

200

0

–200

CURRENT (µA)

–400

–600

–800

–101 2345 6 7

LE/HYS PIN (V)

VCC = 5.5VVCC = 2.5V

Figure 4. LE/HYS Pin Current vs. Voltage

200

150

100

VCC = 5.5VVCC = 2.5V

50

0

CURRENT (µA)

–50

–100

–150

–1 0 1 2 3 4 5 6 7

Figure 5. S

SDN PIN (V)

Pin Current vs. Voltage

DN

1.60

1.50

1.40

1.30

1.20

OUTPUT (V)

1.10

1.00

0.90

2.4 3.4 4.4 5.4

2.9 3.9 4.9 5.9

07958-004

Figure 7. LVDS Output Level vs. V

850

800

750

700

650

600

RISE/ FALL (ps)

550

500

450

400

2.40 2.80 3.20 3.60 4.00 4.40 4.80 5.20 5. 60 6. 00

07958-005

Figure 8. LVDS Output Rise/Fall Time vs. V

OUTPUT HIG H

OUTPUT V

CM

OUTPUT LOW

V

(V)

CCO

+125°C

+25°C

–40°C

V

(V)

CCO

CCO

07958-007

7958-008

CCO

10

8

6

4

2

0

(µA)

B

I

–2

–4

–6

–8

–10

–1.0 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

AT VCC = 2.5V (V)

V

CM

+125°C

+25°C

–40°C

Figure 6. Input Bias Current vs. Input Common-Mode Voltage

07958-006

Rev. A | Page 8 of 16

250

200

150

100

HYSTERESIS (mV)

50

0

50 100 150 200 250 300 350 400 450 500

VCC = 2.5V

VCC = 5.5V

HYSTERESIS RESISTOR (kΩ)

Figure 9. Hysteresis vs. Hysteresis Resistor

07958-009

Data Sheet AD8465

350

300

250

200

150

HYSTERESIS (mV)

100

50

0

LE/HYS PI N CURRENT (µA)

+125°C

+25°C

–40°C

–18–16–14–12–10–8–6–4–20

07958-010

Figure 10. Hysteresis vs. LE/HYS Pin Current

3.5

0.44

0.43

0.42

0.41

0.40

0.39

OUTPUT SWING (V)

0.38

0.37

0.36

2.4 3.4 4.4 5.4
V

(V)

CCO

Figure 13. LVDS Output Swing vs. V

CCO

07958-013

3.0

2.5

2.0

PROPAGATI ON DELAY (n s)

1.5

1.0
0 1020304050607080 90100

PROPAGATION

DELAY

OVERDRIVE (mV)

Figure 11. Propagation Delay vs. Input Overdrive

1.6

PROPAGATI ON
DELAY RISE n s

1.5

PROPAGATI ON

DELAY FALL ns

1.4

PROPAGATI ON DELAY (n s)

1.425V

07958-011

925.0mV 1.000ns/DIV

Figure 14. 50 MHz Output Voltage Waveform at V

1.543V

Q

Q

07958-014

= 2.5 V

CCO

Q

1.3
–0.6 –0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0

VCM AT VCC = 2.5V (V)

Figure 12. Propagation Delay vs. Input Common-Mode Voltage

07958-012

Rev. A | Page 9 of 16

Q

1.043V 1.000ns/DI V

Figure 15. 50 MHz Output Voltage Waveform at V

CCO

= 5.5 V

07958-015

AD8465 Data Sheet

APPLICATION INFORMATION

POWER/GROUND LAYOUT AND BYPASSING

The AD8465 comparator is a very high speed device. Despite
the low noise output stage, it is essential to use proper high
speed design techniques to achieve the specified performance.
Because the comparator is an uncompensated amplifier, feedback
in any phase relationship is likely to cause oscillations or undesired
hysteresis. The use of low impedance supply planes is of critical
importance particularly with the output supply plane (V
and the ground plane (GND). Individual supply planes are
recommended as part of a multilayer board. Providing the
lowest inductance return path for switching currents ensures
the best possible performance in the target application.

It is also important to adequately bypass the input and output
supplies. Place multiple high quality 0.01 μF bypass capacitors
as close as possible to each of the V

CCI

and V

supply pins and

CCO

connect the capacitors to the GND plane with redundant vias.
Place at least one capacitor to provide a physically short return
path for output currents flowing back from ground to the V
pin and the V

pin. Carefully select high frequency bypass

CCO

capacitors for minimum inductance and ESR. Parasitic layout
inductance should also be strictly controlled to maximize the
effectiveness of the bypass at high frequencies.

The input and output supplies have been connected separately
(V

≠ V

CCI

); be sure to bypass each of these supplies separately

CCO

to the GND plane. Do not connect a bypass capacitor between
these supplies. It is recommended that the GND plane separate
the V

CCI

and V

planes when the circuit board layout is designed

CCO

to minimize coupling between the two supplies to take advan­tage of the additional bypass capacitance from each respective
supply to the ground plane. This enhances the performance when
split input/output supplies are used. If the input and output supplies
are connected together for single-supply operation (V
coupling between the two supplies is unavoidable; however,
careful board placement can help keep output return currents
away from the inputs.

CCI

CCO

= V

)

CCI

CCO

),

LVDS-COMPATIBLE OUTPUT STAGE

Specified propagation delay dispersion performance is only
achieved by keeping parasitic capacitive loads at or below the
specified minimums. The outputs of the AD8465 are designed
to directly drive any standard LVDS-compatible input.

USING/DISABLING THE LATCH FEATURE

The latch input is designed for maximum versatility. It can
safely be left floating or it can be driven low by any standard
TTL/CMOS device as a high speed latch. In addition, the pin
can be operated as a hysteresis control pin with a bias voltage
of 1.25 V nominal and an input resistance of approximately
70 kΩ. This allows the comparator hysteresis to be easily
controlled by either a resistor or an inexpensive CMOS DAC.
Driving this pin high or floating the pin disables all hysteresis.

Hysteresis control and latch mode can be used together if an
open drain, an open collector, or a three-state driver is connected
in parallel to the hysteresis control resistor or current source.

Due to the programmable hysteresis feature, the logic threshold
of the latch pin is approximately 1.1 V, regardless of V

CCO

.

OPTIMIZING PERFORMANCE

As with any high speed comparator, proper design and layout
techniques are essential for obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground imped­ances, or other layout issues can severely limit performance and
often cause oscillation. Large discontinuities along input and
output transmission lines can also limit the specified pulse width
dispersion performance. Minimize the source impedance as
much as is practicable. High source impedance, in combina­tion with the parasitic input capacitance of the comparator,
causes an undesirable degradation in bandwidth at the input,
thus degrading the overall response. Thermal noise from large
resistances can easily cause extra jitter with slowly slewing input
signals. Higher impedances encourage undesired coupling.

Rev. A | Page 10 of 16

Data Sheet AD8465

COMPARATOR PROPAGATION DELAY DISPERSION

The AD8465 comparator is designed to reduce propagation
delay dispersion over a wide input overdrive range of 5 mV
to V

− 1 V. Propagation delay dispersion is the variation in

CCI

propagation delay that results from a change in the degree of
overdrive or slew rate (how far or how fast the input signal is
driven past the switching threshold).

Propagation delay dispersion is a specification that becomes
important in high speed, time-critical applications, such as data
communications, automatic test and measurement, and instru­mentation. It is also important in event-driven applications, such
as pulse spectroscopy, nuclear instrumentation, and medical
imaging. Dispersion is defined as the variation in propagation
delay as the input overdrive conditions are changed (see Figure 16
and Figure 17).

The AD8465 dispersion is typically <1.6 ns as the overdrive
varies from 10 mV to 125 mV. This specification applies to
both positive and negative signals because the AD8465 has
substantially equal delays for positive-going and negative­going inputs and very low output skews.

500mV OVERDRIVE

COMPARATOR HYSTERESIS

The addition of hysteresis to a comparator is often desirable in
a noisy environment, or when the differential input amplitudes
are relatively small or slow moving. The transfer function for a
comparator with hysteresis is shown in Figure 18. As the input
voltage approaches the threshold (0 V, in this example) from
below the threshold region in a positive direction, the comparator
switches from low to high when the input crosses +V
new switching threshold becomes −V
in the high state until the −V

/2. The comparator remains

H

/2 threshold is crossed from below

H

the threshold region in a negative direction. In this manner, noise
or feedback output signals centered on 0 V input cannot cause
the comparator to switch states unless it exceeds the region
bounded by ±V

H

/2.

OUTPUT

V

V

OH

OL

/2. The

H

INPUT VOLTAGE

10mV OVERDRIVE

± V

V

N

–V

2

OS

Figure 18. Comparator Hysteresis Transfer Function

0V

H

INPUT

+V

H

2

07958-018

The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to

DISPERSION

Q/Q OUTPUT

07958-016

Figure 16. Propagation Delay—Overdrive Dispersion

INPUT VOLTAGE

Q/Q OUTPUT

Figure 17. Propagation Delay—Slew Rate Dispersion

1V/ns

10V/ns

V

± V

N

DISPERSION

OS

07958-017

the input. One limitation of this approach is that the amount
of hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that reduce high-speed performance and induce
oscillation in some cases.

Rev. A | Page 11 of 16

AD8465 Data Sheet

The AD8465 comparator offers a programmable hysteresis
feature that significantly improves accuracy and stability.
Connecting an external pull-down resistor or a current source
from the LE/HYS pin to GND varies the amount of hysteresis
in a predictable and stable manner. Leaving the LE/HYS pin
disconnected or driving it high removes hysteresis. The maxi­mum hysteresis that can be applied using this pin is approximately
160 mV. Figure 19 illustrates the amount of hysteresis applied as
a function of external resistor value. Figure 10 illustrates hysteresis
as a function of current.

The hysteresis control pin appears as a 1.25 V bias voltage
seen through a series resistance of 70 kΩ ± 20% throughout the
hysteresis control range. The advantages of applying hysteresis
in this manner are improved accuracy, improved stability, reduced
component count, and maximum versatility. An external bypass
capacitor is not recommended on the LE/HYS pin because it
would likely degrade the jitter performance of the device and
impair the latch function. As described in the Using/Disabling
the Latch Feature section, hysteresis control need not compro­mise the latch function.

250

CROSSOVER BIAS POINTS

Rail-to-rail inputs of this type, in both op amps and comparators,
have a dual front-end design. Certain devices are active near the
V

rail and others are active near the VEE rail. At some predeter-

CCI

mined point in the common-mode range, a crossover occurs.
At this point, normally V

/2, the direction of the bias current

CCI

reverses and there are changes in measured offset voltages and
currents.

MINIMUM INPUT SLEW RATE REQUIREMENT

With the rated load capacitance and normal good PCB design
practice, as discussed in the Optimizing Performance section,
these comparators should be stable at any input slew rate with
no hysteresis. Broadband noise from the input stage is observed
in place of the violent chattering seen with most other high
speed comparators. With additional capacitive loading or
poor bypassing, oscillation is observed. This oscillation is
due to the high gain bandwidth of the comparator in combina­tion with feedback parasitics in the package and PCB. In many
applications, chattering is not harmful.

200

150

100

HYSTERESIS (mV)

50

0

50 100 150 200 250 300 350 400 450 500

VCC = 2.5V

VCC = 5.5V

HYSTERESIS RESISTOR (kΩ)

Figure 19. Hysteresis vs. R

Control Resistor

HYS

07958-019

Rev. A | Page 12 of 16

Data Sheet AD8465

V

V

V

V

V

V

V

V

TYPICAL APPLICATION CIRCUITS

2.5V TO 5

0.1µF

2.5

INPUT

DIGITAL

INPUT

2kΩ

2kΩ

AD8465

0.1µF

Figure 20. Self-Biased, 50% Slicer

2.5V TO 3. 3

100ΩLVDS LVDS

AD8465

Figure 21. LVDS to Repeater

2.5V TO 5

AD8465

74VHC

1G07

150kΩ

LE/HYS

CMOS
OUTPUT

LVDS

AD8465

INPUT

1.25V

07958-020

±50m

INPUT

1.25V
REF

10kΩ

10kΩ

PWM
OUTPUT

ADCMP601

10kΩ

07958-021

82pF

LE/HYS

100kΩ

7958-024

Figure 24. Oscillator and Pulse-Width Modulator

2.5V TO 5

AD8465

DIGITAL

INPUT

74AHC

1G07

LE/HYS

CONTROL

VOLTAGE

0V TO 2.5V

150kΩ

Figure 22. Hysteresis Adjustment with Latch

2.5

10kΩ

82pF

AD8465

LE/HYS

CONTROL
VOLTAGE

0V TO 2.5

150kΩ

10kΩ

150kΩ

LVDS
OUTPUT

7958-022

7958-023

HYSTERESIS

CURRENT

10kΩ

Figure 25. Hysteresis Adjustment with Latch

7958-025

Figure 23. Voltage-Controlled Oscillator

Rev. A | Page 13 of 16

AD8465 Data Sheet

OUTLINE DIMENSIONS

PIN 1

INDICATOR

3.15

3.00 SQ

2.85

TOP

VIEW

2.95

2.75 SQ

2.55

0.60 MAX

0.50

0.40

0.30

0.60 MAX

9

7

10

EXPOSED

(BOTTOM

6

PAD

VIEW)

0.50
BSC

PIN 1

12

4

INDICATOR

*

1

3

1.65

1.50 SQ

1.35

0.25 MIN

1.00

0.85

0.80

SEATING

PLANE

12° MAX

0.80 MAX

0.65 TYP

0.30

0.23

0.18

*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1

EXCEPT FO R EXPOSED PAD DI MENSION.

0.05 MAX

0.02 NOM

0.20 REF

COPLANARITY

0.08

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DES CRIPTIONS
SECTION OF THIS DATA SHEET.

010809-B

Figure 26. 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

3 mm × 3 mm Body, Very Thin Quad

(CP-12-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option Branding

AD8465WBCPZ-WP −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-12-3 Y24
AD8465WBCPZ-R7 −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-12-3 Y24

1

Z = RoHS Compliant Part.

Rev. A | Page 14 of 16

Data Sheet AD8465

NOTES

Rev. A | Page 15 of 16

AD8465 Data Sheet

NOTES

©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07958-0-11/11(A)

Rev. A | Page 16 of 16