Page 1
Wideband, High Output Current,
a
FEATURES
AC PERFORMANCE
Gain Bandwidth Product: 80 MHz (Gain = 2)
Fast Settling: 100 ns to 0.01% for a 10 V Step
Slew Rate: 375 V/s
Stable at Gains of 2 or Greater
Full Power Bandwidth: 6.0 MHz for 20 V p-p
DC PERFORMANCE
Input Offset Voltage: 1 mV max
Input Offset Drift: 14 V/ⴗC
Input Voltage Noise: 9 nV/√Hz typ
Open-Loop Gain: 90 V/mV into a 500 ⍀ Load
Output Current: 100 mA min
Quiescent Supply Current: 14 mA max
APPLICATIONS
Line Drivers
DAC and ADC Buffers
Video and Pulse Amplifiers
Available in Plastic DIP, Hermetic Metal Can,
Hermetic Cerdip, SOIC and LCC Packages and in
Chip Form
MIL-STD-883B Parts Available
Available in Tape and Reel in Accordance with
EIA-481A Standard
PRODUCT DESCRIPTION
The AD842 is a member of the Analog Devices family of wide
bandwidth operational amplifiers. This device is fabricated using
Analog Devices’ junction isolated complementary bipolar (CB)
process. This process permits a combination of dc precision and
wideband ac performance previously unobtainable in a monolithic op amp. In addition to its 80 MHz gain bandwidth, the
AD842 offers extremely fast settling characteristics, typically
settling to within 0.01% of final value in less than 100 ns for a
10 volt step.
The AD842 also offers a low quiescent current of 13 mA, a high
output current drive capability (100 mA minimum), a low input
voltage noise of 9 nV√Hz and a low input offset voltage (1 mV
maximum).
The 375 V/µs slew rate of the AD842, along with its 80 MHz
gain bandwidth, ensures excellent performance in video and
pulse amplifier applications. This amplifier is ideally suited for
use in high frequency signal conditioning circuits and wide
bandwidth active filters. The extremely rapid settling time of
the AD842 makes this amplifier the preferred choice for data
acquisition applications which require 12-bit accuracy. The
*Covered by U.S. Patent Nos. 4,969,823 and 5,141,898.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Fast Settling Op Amp
AD842*
CONNECTION DIAGRAMS
Plastic DIP (N) Package
and
Cerdip (Q) Package
NC
NC
BALANCE
–INPUT
+INPUT
NC
1
AD842
2
3
4
+
5
6
V–
7
TOP VIEW
NC = NO CONNECT
14
NC
13
BALANCE
12
NC
11
V+
10
OUTPUT
9
NC
8
NC
TO-8 (H) Package
NC
BALANCE
BALANCE
NC
V+
AD842
–INPUT
+INPUT
NC
NOTE: CAN BE TIED TO V+
NC = NO CONNECT
+
NC
TOP VIEW
OUTPUT
V–
NC
AD842 is also appropriate for other applications such as high
speed DAC and ADC buffer amplifiers and other wide bandwidth circuitry.
APPLICATION HIGHLIGHTS
1. The high slew rate and fast settling time of the AD842 make
it ideal for DAC and ADC buffers amplifiers, lines drivers
and all types of video instrumentation circuitry.
2. The AD842 is a precision amplifier. It offers accuracy to
0.01% or better and wide bandwidth; performance previously
available only in hybrids.
3. Laser-wafer trimming reduces the input offset voltage of
1 mV max, thus eliminating the need for external offset
nulling in many applications.
4. Full differential inputs provide outstanding performance in
all standard high frequency op amp applications where the
circuit gain will be 2 or greater.
5. The AD842 is an enhanced replacement for the HA2542.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
LCC (E) Package
BALANCE
NC
BALANCE
NC
3212019
NC
4
–IN
5
NC
6
+IN
NC
+
7
AD842
8
9
101112
S
NC
NCNCNC
–V
NC = NO CONNECT
SOIC (R-16) Package
1
NC
–INPUT
+INPUT
–V
NC
NC
S
NC
2
AD842
3
4
5
+
6
7
8
TOP VIEW
NC = NO CONNECT
BALANCE
NC
13
NC
18
17
+V
16
NC
OUTPUT
15
14
NC
16
NC
15
BALANCE
14
+V
13
NC
12
OUTPUT
11
NC
10
NC
9
NC
S
S
Page 2
AD842–SPECIFICATIONS
Model AD842J/JR
(@ +25ⴗC and ⴞ15 V dc, unless otherwise noted)
1
AD842K AD842S
2
Conditions Min Typ Max Min Typ Max Min Typ Max Units
INPUT OFFSET VOLTAGE
3
T
MIN–TMAX
0.5 1.5 0.3 1.0 0.5 1.5 mV
2.5/3 1.5 3.5 mV
Offset Drift 14 14 14 µV/°C
INPUT BIAS CURRENT 4.2 8 3.5 5 4.2 8 µA
T
MIN–TMAX
10 612µA
Input Offset Current 0.1 0.4 0.05 0.2 0.1 0.4 µA
T
MIN–TMAX
0.5 0.3 0.6 µA
INPUT CHARACTERISTICS Differential Mode
Input Resistance 100 100 100 kΩ
Input Capacitance 2.0 2.0 2.0 pF
INPUT VOLTAGE RANGE
Common Mode ⴞ10 ⴞ10 ⴞ10 V
Common-Mode Rejection V
= ±10 V 86 115 90 115 86 115 dB
CM
T
MIN–TMAX
80 86 80 dB
INPUT VOLTAGE NOISE f = 1 kHz 9 9 9 nV/√Hz
Wideband Noise 10 Hz to 10 MHz 28 28 28 µV rms
OPEN-LOOP GAIN V
= ±10 V
O
R
≥ 500 Ω 40/30 90 50 90 40 90 V/mV
LOAD
T
MIN–TMAX
20/15 25 20 V/mV
OUTPUT CHARACTERISTICS
Voltage R
Current V
≥ 500 Ω ⴞ10 ⴞ10 ⴞ10 V
LOAD
= ±10 V 100 100 100 mA
OUT
Open Loop 5 5 5 Ω
FREQUENCY RESPONSE
Gain Bandwidth Product V
Full Power Bandwidth
Rise Time
Overshoot
Slew Rate
5
5
5
Settling Time
4
5
= 90 mV 80 80 80 MHz
OUT
VO = 20 V p-p
R
≥ 500 Ω 4.7 6 4.7 6 4.7 6 MHz
LOAD
A
= –2 10 10 10 ns
VCL
A
= –2 20 20 20 %
VCL
A
= –2 300 375 300 375 300 375 V/µs
VCL
10 V Step
to 0.1% 80 80 80 ns
to 0.01% 100 100 100 ns
Differential Gain f = 4.4 MHz 0.015 0.015 0.015 %
Differential Phase f = 4.4 MHz 0.035 0.035 0.035 Degree
POWER SUPPLY
Rated Performance ±15 ± 15 ±15 V
Operating Range ⴞ5 ⴞ18 ⴞ5 ⴞ18 ⴞ5 ⴞ18 V
Quiescent Current 13/14 14/16 13 14 13 14 mA
Power Supply Rejection Ratio V
TEMPERATURE RANGE
Rated Performance
6
T
MIN–TMAX
= ±5 V to ±18 V 86 100 90 105 86 100 dB
S
T
MIN–TMAX
80 86 80 dB
0 +75 0 +75 –55 +125 °C
16/19.5 16 19 mA
PACKAGE OPTIONS
Plastic (N-14) AD842JN AD842KN
Cerdip (Q-14) AD842JQ AD842KQ AD842SQ, AD842SQ/883B
SOIC (R-16) AD842JR-16
Tape and Reel AD842JR-16-REEL
AD842JR-16-REEL7
TO-8 (H-12A) AD842JH AD842KH AD842SH
LCC (E-20A) AD842SE/883B
Chips AD842JCHIPS AD842SCHIPS
NOTES
1
AD842JR specifications differ from those of the AD842JN, JQ and JH due to the thermal characteristics of the SOIC package.
2
Standard Military Drawing available 5962-8964201xx
2A – (SE/883B); XA – (SH/883B); CA – (SQ/883B).
3
Input offset voltage specifications are guaranteed after 5 minutes at TA = +25°C.
4
Full power bandwidth = slew rate/2 π V
5
Refer to Figures 22 and 23.
6
“S” grade T
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units.
Specifications subject to change without notice.
specifications are tested with automatic test equipment at TA = –55°C and TA = +125°C.
MIN–TMAX
PEAK
.
–2–
REV. E
Page 3
AD842
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation
2
1
Plastic (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Cerdip (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W
TO-8 (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
LCC (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ±6 V
Storage Temperature Range
Q, H, E . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
N, R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Maximum internal power dissipation is specified so that TJ does not exceed
+150°C at an ambient temperature of +25°C.
Thermal Characteristics:
S
Plastic Package 30°C/W 100°C/W
Cerdip Package 30°C/W 110°C/W 38°C/W
TO-8 Package 30°C/W 100°C/W 27°C/W
16-Lead SOIC Package 30°C/W 100°C/W
20-Lead LCC Package 35°C/W 150°C/W
Recommended Heat Sink: Aavid Engineering© #602B
θ
JC
θ
JA
θ
SA
–3–REV. E
Page 4
AD842
–Typical Characteristics
(at +25ⴗC and VS = ⴞ15 V, unless otherwise noted)
20
15
V
IN
10
5
INPUT COMMON-MODE RANGE – Volts
0
05 20
SUPPLY VOLTAGE – ⴞVolts
10 15
Figure 1. Input Common-Mode
Range vs. Supply Voltage
18
16
14
12
QUIESCENT CURRENT – mA
20
15
10
5
OUTPUT VOLTAGE SWING – Volts
0
05 20
SUPPLY VOLTAGE – ⴞ Volts
ⴞ V
OUT
10 15
Figure 2. Output Voltage Swing
vs. Supply Voltage
–5
–4
–3
INPUT BIAS CURRENT – A
30
25
20
15
10
5
OUTPUT VOLTAGE SWING – Volts p-p
0
10 100 10k
ⴞ 15V SUPPLIES
1k
LOAD RESISTANCE – ⍀
Figure 3. Output Voltage Swing
vs. Load Resistance
100
10
1
0.1
OUTPUT IMPEDANCE – ⍀
10
05 20
SUPPLY VOLTAGE – ⴞ Volts
10 15
Figure 4. Quiescent Current vs.
Supply Voltage
18
17
16
15
14
13
12
QUIESCENT CURRENT – mA
11
10
–60 –40 140
–20 0 20 40 60 80 100 120
TEMPERATURE – ⴗC
Figure 7. Quiescent Current vs.
Temperature
–2
–60 –40 140
–20 0 20 40 60 80 100 120
TEMPERATURE – ⴗC
Figure 5. Input Bias Current vs.
Temperature
300
275
250
225
200
175
–OUTPUT CURRENT
150
125
SHORT CIRCUIT CURRENT LIMIT – mA
100
–60 –40 140
+ OUTPUT CURRENT
–20020 40 60 80 100 120
AMBIENT TEMPERATURE – ⴗC
Figure 8. Short-Circuit Current
Limit vs. Temperature
0.01
10k 100k 100M
1M 10M
FREQUENCY – Hz
Figure 6. Output Impedance vs.
Frequency
85
80
75
70
GAIN BANDWIDTH – MHz
65
–60 –40 140
–20020 40 60 80 100 120
TEMPERATURE – ⴗC
Figure 9. Gain Bandwidth Product
vs. Temperature
–4–
REV. E
Page 5
AD842
120
100
80
60
40
OPEN-LOOP GAIN – dB
20
0
100 1k 100M
500⍀ LOAD
10k 100k 1M 10M
FREQUENCY – Hz
Figure 10. Open-Loop Gain and
Phase Margin vs. Frequency
120
100
80
CMR – dB
60
40
20
1k 10k 100M100k 1M 10M
FREQUENCY – Hz
VS = ⴞ 15V
V
= 1V p-p
CM
+ 25ⴗC
Figure 13. Common-Mode
Rejection vs. Frequency
100
80
60
40
20
0
110
105
100
500⍀ LOAD
95
OPEN-LOOP GAIN – dB
PHASE MARGIN – Degrees
90
05 20
SUPPLY VOLTAGE – ⴞV
10 15
Figure 11. Open-Loop Gain vs.
Supply Voltage
30
25
20
15
10
OUTPUT VOLTAGE – Volts p-p
5
0
1M 10M 100M
FREQUENCY – Hz
Figure 14. Large Signal Frequency
Response
RL = 1kV
+25ⴗC
V
= ⴞ15V
S
120
100
80
60
40
20
POWER SUPPLY REJECTION – dB
0
100 1k 100M
+ SUPPLY
– SUPPLY
10k 100k 1M 10M
FREQUENCY – Hz
Figure 12. Power Supply Rejection
vs. Frequency
10
8
V
ⴞ
6
4
2
0.1%
0
–2
–4
–6
OUTPUT SWING FROM 0 TO
–8
–10
30 40 110
0.01%
0.1%
0.01%
50 60 70 80 90 100
SETTLING TIME – ns
Figure 15. Output Swing and
Error vs. Settling Time
–80
–90
–100
–110
–120
HARMONIC DISTORTION – dB
–130
–140
100 1k 100k10k
3RD HARMONIC
FREQUENCY – Hz
2ND HARMONIC
3V RMS
R
= 1k⍀
L
Figure 16. Harmonic Distortion vs.
Frequency
50
40
30
20
INPUT VOLTAGE – nV Hz
10
0
10 100 10M
1k 10k 100k 1M
FREQUENCY – Hz
Figure 17. Input Voltage vs.
Frequency
550
500
450
400
350
SLEW RATE – Vs
300
250
–60 –40 140
–20020 40 60 80 100 120
TEMPERATURE – ⴗC
Figure 18. Slew Rate vs.
Temperature
–5–REV. E
Page 6
AD842
HP3314A
FUNCTION
GENERATOR
OR
EQUIVALENT
RIN =
499⍀
49.9⍀
332⍀
R
= 1k⍀
F
+V
–
AD842
+
–V
0.1F
S
2.2F
V
OUT
0.1F
2.2F
S
499⍀
Figure 19a. Inverting Amplifier
Configuration (DIP Pinout)
RF = 205⍀
0.1F
+V
S
2.2F
–
100⍀
49.9⍀
AD842
+
–V
0.1F
2.2F
S
IN
V
OUT
499⍀
HP3314A
FUNCTION
GENERATOR
OR
EQUIVALENT
R1 = 205⍀
V
Figure 20a. Noninverting Amplifier
Configuration (DIP Pinout)
Figure 19b. Inverter Large Signal
Pulse Response
Figure 20b. Noninverting Large
Signal Pulse Response
Figure 19c. Inverter Small Signal
Pulse Response
Figure 20c. Noninverting Small
Signal Pulse Response
–6–
REV. E
Page 7
OFFSET NULLING
The input offset voltage of the AD842 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 21 can be used.
AD842 SETTLING TIME
Figures 22 and 24 show the settling performance of the AD842
in the test circuit shown in Figure 23.
Settling time is defined as:
The interval of time from the application of an ideal step
function input until the closed-loop amplifier output has
entered and remains within a specified error band.
This definition encompasses the major components which comprise settling time. They include (1) propagation delay through
the amplifier; (2) slewing time to approach the final output value;
(3) the time of recovery from the overload associated with slewing and (4) linear settling to within the specified error band.
Expressed in these terms, the measurement of settling time is
obviously a challenge and needs to be done accurately to assure
the user that the amplifier is worth consideration for the
application.
+V
0.1F
S
10k ⍀
2.2F
0.1F
2.2F
–V
S
OUTPUT
R
L
INPUT
–
AD842
+
Figure 21. Offset Nulling (DIP Pinout)
AD842
ERROR
AMP
(ⴛ15)
HP6263
DDD5109
FLAT-TOP
PULSE
GENERATOR
499⍀ 1k⍀
499⍀ 1k⍀
50⍀
499⍀
+15V
AD842
–15V
0.1F
2.2F
0.1F
2.2F
Figure 23. Settling Time Test Circuit
Figure 23 shows how measurement of the AD842’s 0.01% settling in 100 ns was accomplished by amplifying the error signal
from a false summing junction with a very high-speed proprietary hybrid error amplifier specially designed to enable testing
of small settling errors. The device under test was driving a
300 Ω load. The input to the error amp is clamped in order to
avoid possible problems associated with the overdrive recovery
of the oscilloscope input amplifier. The error amp gains the
error from the false summing junction by 15, and it contains a
gain vernier to fine trim the gain.
Figure 24 shows the “long term” stability of the settling characteristics of the AD842 output after a 10 V step. There is no
evidence of settling tails after the initial transient recovery time.
The use of a junction isolated process, together with careful
layout, avoids these problems by minimizing the effects of transistor isolation capacitance discharge and thermally induced
shifts in circuit operating points. These problems do not occur
even under high output current conditions.
499⍀
TEK
7A13
TEK
7A16
TEK
7603
OSCILLOSCOPE
FET PROBE
TEK P6201
Figure 22. 0.01% Settling Time
–7–REV. E
Page 8
AD842
GROUNDING AND BYPASSING
In designing practical circuits with the AD842, the user must
remember that whenever high frequencies are involved, some
Figure 24. AD842 Settling Demonstrating No Settling
Tails
special precautions are in order. Circuits must be built with
short interconnect leads. Large ground planes should be used
whenever possible to provide a low resistance, low inductance
circuit path, as well as minimizing the effects of high frequency
coupling. Sockets should be avoided because the increased
interlead capacitance can degrade bandwidth.
Feedback resistors should be of low enough value to assure that
the time constant formed with the circuit capacitances will not
limit the amplifier performance. Resistor values of less than
5 kΩ are recommended. If a larger resistor must be used, a small
(<10 pF) feedback capacitor connected in parallel with the feedback resistor, R
, may be used to compensate for these stray
F
capacitances and optimize the dynamic performance of the
amplifier in the particular application.
Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. A 2.2 µF capacitor in parallel with
a 0.1 µF ceramic disk capacitor is recommended.
CAPACITIVE LOAD DRIVING ABILITY
Like all wideband amplifiers, the AD842 is sensitive to capacitive loading. The AD842 is designed to drive capacitive loads of
up to 20 pF without degradation of its rated performance. Capacitive loads of greater than 20 pF will decrease the dynamic
performance of the part although instability should not occur
unless the load exceeds 100 pF.
2.2F
+V
S
0.1F
V
IN
TERMINATION
RESISTOR FOR
INPUT SIGNAL
+
AD842
–
–V
0.1F
2.2F
S
USING A HEAT SINK
The AD842 draws less quiescent power than most precision
high speed amplifiers and is specified for operation without a
heat sink. However, when driving low impedance loads, the current to the load can be 10 times the quiescent current. This will
create a noticeable temperature rise. Improved performance can
be achieved by using a small heat sink such as the Aavid Engineering #602B.
TERMINATED LINE DRIVER
The AD842 is optimized for high speed line driver applications.
Figure 25 shows the AD842 driving a doubly terminated cable
in a gain-of-2 follower configuration. The AD842 maintains a
typical slew rate of 375 V/µs, which means it can drive a ±10 V,
6.0 MHz signal or a ±3 V, 19.9 MHz signal.
The termination resistor, R
, (when equal to the characteristic
T
impedance of the cable) minimizes reflections from the far end
of the cable. A back-termination resistor (R
, also equal to the
BT
characteristic impedance of the cable) may be placed between
the AD842 output and the cable in order to damp any stray
signals caused by a mismatch between R
and the cable’s char-
T
acteristic impedance. This will result in a “cleaner” signal. With
this circuit, the voltage on the line equals V
of V
is dropped across RBT.
OUT
because one half
IN
The AD842 has ±100 mA minimum output current and, therefore, can drive ±5 V into a 50 Ω cable.
The feedback resistors, R1 and R2, must be chosen carefully.
Large value resistors are desirable in order to limit the amount
of current drawn from the amplifier output. But large resistors
can cause amplifier instability because the parallel resistance
R1储R2 combines with the input capacitance (typically 2–5 pF) to
create an additional pole. Also, the voltage noise of the AD842
is equivalent to a 5 kΩ resistor, so large resistors can significantly increase the system noise. Resistor values of 1 kΩ or 2 kΩ
are recommended.
If termination is not used, cables appear as capacitive loads and
can be decoupled from the AD842 by a resistor in series with
the output.
50⍀ OR 75⍀
R
R1
CABLE
ST
R
T
RT = RST = CABLE CHARACTERISTIC
IMPEDANCE
R2
Figure 25. Line Driver Configuration
–8–
REV. E
Page 9
OVERDRIVE RECOVERY
50⍀
AD842
+V
S
0.1F
2.2F
–V
S
0.1F
2.2F
+
–
1k⍀
OUTPUT
HP3314A
PULSE GENERATOR
OR EQUIVALENT
1s, ⴞ1V SQUARE
WAVE INPUT
Figure 26 shows the overdrive recovery capability of the AD842.
Typical recovery time is 80 ns from negative overdrive and
400 ns from positive overdrive.
Figure 26. Overdrive Recovery
AD842
Figure 27. Overdrive Recovery Test Circuit
–9–REV. E
Page 10
AD842
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
PIN 1
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.93)
16 9
PIN 1
0.050 (1.27)
14-Lead Plastic Package
(N-14)
0.795 (20.19)
0.725 (18.42)
14
17
0.100 (2.54)
0.022 (0.558)
0.014 (0.356)
8
BSC
0.070 (1.77)
0.045 (1.15)
16-Lead SOIC Package
(R-16)
0.4133 (10.50)
0.3977 (10.00)
0.2992 (7.60)
0.2914 (7.40)
81
0.1043 (2.65)
BSC
0.0926 (2.35)
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.130
(3.30)
MIN
SEATING
PLANE
0.4193 (10.65)
0.3937 (10.00)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.0291 (0.74)
0.0098 (0.25)
0.195 (4.95)
0.115 (2.93)
ⴛ 45ⴗ
14-Lead Cerdip Package
(Q-14)
0.005 (0.13) MIN 0.098 (2.49) MAX
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
14
1
PIN 1
0.785 (19.94) MAX
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
8
0.310 (7.87)
0.220 (5.59)
7
0.060 (1.52)
0.015 (0.38)
0.070 (1.78)
0.030 (0.76)
0.150
(3.81)
MIN
SEATING
PLANE
0.320 (8.13)
0.290 (7.37)
15°
0°
0.015 (0.38)
0.008 (0.20)
20-Terminal Leadless Ceramic Chip Carrier Package
(E-20A)
0.200 (5.08)
BSC
R TYP
0.075
(1.91)
REF
0.055 (1.40)
0.045 (1.14)
REF
19
18
14
13
20
1
BOTTOM
VIEW
0.150 (3.81)
0.100 (2.54) BSC
3
4
0.050 (1.27)
8
BSC
9
45° TYP
BSC
0.015 (0.38)
MIN
0.028 (0.71)
0.022 (0.56)
0.358 (9.09)
0.342 (8.69)
SQ
0.100 (2.54)
0.064 (1.63)
0.358
(9.09)
MAX
SQ
0.088 (2.24)
0.054 (1.37)
0.095 (2.41)
0.075 (1.90)
0.011 (0.28)
0.007 (0.18)
0.075 (1.91)
C1195c–0–3/00 (rev. E)
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
0.181 (4.60)
0.148 (3.76)
0.615 (15.62)
0.592 (15.04)
0.040 (1.02) MAX
0.045 (1.14)
0.000 (0.00)
8ⴗ
0ⴗ
0.555 (14.10)
0.545 (13.84)
0.0500 (1.27)
0.0157 (0.40)
12-Lead Metal Can Package
(TO-8 Style)
REFERENCE PLANE
0.375 (9.53)
MIN
0.050 (1.27) MAX
0.400
(10.16)
BSC
0.019 (0.48)
0.016 (0.41)
0.021 (0.53)
0.016 (0.41)
BASE & SEATING PLANE
0.200 (5.08)
BSC
6
5
4
0.037 (0.94)
0.026 (0.66)
879
10
11
12
12 3
0.100 (2.54)
BSC
0.036 (0.91)
0.026 (0.66)
0.200
(5.08)
BSC
PRINTED IN U.S.A.
–10–
REV. E
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