Page 1
1-/2-/4-Channel
RDAC1
SHDN
8
8-BIT
LATCH
CK
RS
RDAC2
SHDN
8
8-BIT
LATCH
CK
RS
RDAC3
SHDN
8
8-BIT
LATCH
CK
RS
RDAC4
SHDN
8
8-BIT
LATCH
CK
RS
SHDN
DAC
SELECT
A1, A0
1
2
3
4
10-BIT
SERIAL
LATCH
CK Q RS
D
RS
SDO
A1
W1
B1
AGND1
A2
W2
B2
AGND2
A3
W3
B3
AGND3
A4
W4
B4
AGND4
AD8403
V
DD
DGND
SDI
CLK
CS
8
2
a
Digital Potentiometers
AD8400/AD8402/AD8403
FEATURES
256 Position
Replaces 1, 2 or 4 Potentiometers
1 kV, 10 kV, 50 kV, 100 kV
Power Shut Down—Less than 5 mA
3-Wire SPI Compatible Serial Data Input
10 MHz Update Data Loading Rate
+2.7 V to +5.5 V Single-Supply Operation
Midscale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Programmable Filters, Delays, Time Constants
Volume Control, Panning
Line Impedance Matching
Power Supply Adjustment
GENERAL DESCRIPTION
The AD8400/AD8402/AD8403 provide a single, dual or quad
channel, 256 position digitally controlled variable resistor (VR)
device. These devices perform the same electronic adjustment
function as a potentiometer or variable resistor. The AD8400
contains a single variable resistor in the compact SO-8 package.
The AD8402 contains two independent variable resistors in
space saving SO-14 surface mount package. The AD8403 contains four independent variable resistors in 24-lead PDIP, SOIC
and TSSOP packages. Each part contains a fixed resistor with a
wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the controlling serial input
register. The resistance between the wiper and either endpoint
of the fixed resistor varies linearly with respect to the digital
code transferred into the VR latch. Each variable resistor offers
a completely programmable value of resistance, between the A
terminal and the wiper or the B terminal and the wiper. The
fixed A to B terminal resistance of 1 kΩ, 10 kΩ, 50 kΩ or 100 kΩ
has a ±1% channel-to-channel matching tolerance with a nominal
temperature coefficient of 500 ppm/°C. A unique switching circuit minimizes the high glitch inherent in traditional switched
resistor designs avoiding any make-before-break or break-beforemake operation.
Each VR has its own VR latch that holds its programmed
The reset (
loading 80
tor to an end-to-end open circuit condition on the A terminal
and shorts the wiper to the B terminal, achieving a microwatt
power shutdown state. When
the previous latch settings put the wiper in the same resistance
setting prior to shutdown. The digital interface is still active in
shutdown so that code changes can be made which will produce
new wiper positions when the device is taken out of shutdown.
The AD8400 is available in both the SO-8 surface mount and
the 8-lead plastic DIP package.
The AD8402 is available in both surface mount (SO-14) and
the 14-lead plastic DIP package, while the AD8403 is available
in a narrow body 24-lead plastic DIP and the 24-lead surface
mount package. The AD8402/AD8403 are also offered in the
1.1 mm thin TSSOP-14/TSSOP-24 package for PCMCIA applications. All parts are guaranteed to operate over the extended
industrial temperature range of –40°C to +85°C.
resistance value. These VR latches are updated from an SPI
compatible serial-to-parallel shift register that is loaded from a
standard 3-wire serial-input digital interface. Ten data bits make
up the data word clocked into the serial input register. The data
word is decoded where the first two bits determine the address
of the VR latch to be loaded, the last eight bits are data. A serial
data output pin at the opposite end of the serial register allows
simple daisy-chaining in multiple VR applications without additional external decoding logic.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1997
FUNCTIONAL BLOCK DIAGRAM
RS) pin forces the wiper to the midscale position by
into the VR latch. The SHDN pin forces the resis-
H
SHDN is returned to logic high,
Page 2
AD8400/AD8402/AD8403–SPECIFICATIONS
10 kV VERSION
ELECTRICAL CHARACTERISTICS
(VDD = +3 V 6 10% or + 5 V 6 10%, VA = +VDD, VB = 0 V, –408C ≤ TA ≤ +858C unless
otherwise noted)
Parameter Symbol Conditions Min Typ1Max Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL
Resistor Nonlinearity
Nominal Resistance
Resistance Tempco ∆R
Wiper Resistance R
Nominal Resistance Match ∆R/R
2
2
3
R-DNL RWB, VA = NC –1 ±1/4 +1 LSB
R-INL RWB, VA = NC –2 ±1/2 +2 LSB
RT
/∆TV
AB
W
O
= +25°C, Model: AD840XYY10 8 10 12 kΩ
A
= VDD, Wiper = No Connect 500 ppm/°C
AB
IW = 1 V/R 50 100 Ω
CH 1 to 2, 3, or 4, VAB = VDD, TA = +25°C 0.2 1 %
DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
Resolution N 8 Bits
Integral Nonlinearity
Differential Nonlinearity
Voltage Divider Tempco ∆V
Full-Scale Error V
Zero-Scale Error V
RESISTOR TERMINALS
Voltage Range
Capacitance
Capacitance
6
6
Shutdown Current
Shutdown Wiper Resistance R
4
4
5
Ax, Bx C
Wx C
7
INL –2 ±1/2 +2 LSB
DNL V
DNL V
DNL V
/∆T Code = 80
W
WFSE
WZSE
V
A, B, W
A, B
W
I
A_SD
W_SD
= +5 V –1 ±1/4 +1 LSB
DD
= +3 V TA = +25°C–1±1/4 +1 LSB
DD
= +3 V TA = –40°C, +85°C –1.5 ±1/2 +1.5 LSB
DD
Code = FF
Code = 00
f = 1 MHz, Measured to GND, Code = 80
f = 1 MHz, Measured to GND, Code = 80
H
H
H
H
H
–4 –2.8 0 LSB
0 +1.3 +2 LSB
0V
15 ppm/°C
V
DD
75 pF
120 pF
VA = VDD, VB = 0 V, SHDN = 0 0.01 5 µA
VA = VDD, VB = 0 V, SHDN = 0, V
= +5 V 100 200 Ω
DD
DIGITAL INPUTS & OUTPUTS
Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
Input Capacitance
6
IH
IL
IH
IL
OH
OL
IL
C
IL
VDD = +5 V 2.4 V
VDD = +5 V 0.8 V
VDD = +3 V 2.1 V
VDD = +3 V 0.6 V
RL = 1 kΩ to V
DD
VDD–0.1 V
IOL = 1.6 mA, VDD = +5 V 0.4 V
VIN = 0 V or +5 V, VDD = +5 V ±1 µA
5pF
POWER SUPPLIES
Power Supply Range V
Supply Current (CMOS) I
Supply Current (TTL)
Power Dissipation (CMOS)
8
9
Power Supply Sensitivity PSS V
Range 2.7 5.5 V
I
P
DD
DD
DD
DISS
VIH = VDD or VIL = 0 V 0.01 5 µA
VIH = 2.4 V or 0.8 V, VDD = +5.5 V 0.9 4 mA
VIH = VDD or VIL = 0 V, VDD = +5.5 V 27.5 µW
= +5 V ± 10% 0.0002 0.001 %/%
DD
PSS VDD = +3 V ± 10% 0.006 0.03 %/%
DYNAMIC CHARACTERISTICS
6, 10
Bandwidth –3 dB BW_10K R = 10 kΩ 600 kHz
Total Harmonic Distortion THD
V
Settling Time t
W
Resistor Noise Voltage e
Crosstalk
NOTES FOR 10 kΩ VERSION
1
Typicals represent average readings at +25°C and VDD = +5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 30 test circuit.
IW = 50 µA for VDD = +3 V and IW = 400 µA for VDD = +5 V for the 10 kΩ versions.
3
V
AB
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL Specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
8
Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I
9
P
DISS
10
All Dynamic Characteristics use VDD = +5 V.
11
Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
Specifications subject to change without notice.
11
= VDD, Wiper (VW) = No Connect.
is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
S
C
W
NWB
T
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.003 %
VA = VDD, VB = 0 V, ±1% Error Band 2 µs
RWB = 5 kΩ, f = 1 kHz, RS = 0 9 nV/√Hz
VA = VDD, VB = 0 V –65 dB
versus logic voltage.
DD
–2–
REV. B
Page 3
SPECIFICATIONS
50 kV & 100 kV VERSION
ELECTRICAL CHARACTERISTICS
(VDD = +3 V 6 10% or + 5 V 6 10%, VA = +VDD, VB = 0 V, –408C ≤ TA ≤ +858C unless
otherwise noted)
AD8400/AD8402/AD8403
Parameter Symbol Conditions Min Typ1Max Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL
Resistor Nonlinearity
Nominal Resistance
Resistance Tempco ∆R
Wiper Resistance R
Nominal Resistance Match ∆R/R
2
2
3
R-DNL RWB, VA = NC –1 ±1/4 +1 LSB
R-INL RWB, VA = NC –2 ±1/2 +2 LSB
RT
RT
/∆TV
AB
W
O
= +25°C, Model: AD840XYY50 35 50 65 kΩ
A
= +25°C, Model: AD840XYY100 70 100 130 kΩ
A
= VDD, Wiper = No Connect 500 ppm/°C
AB
IW = 1 V/R 53 100 Ω
CH 1 to 2, 3, or 4, VAB = VDD, TA = +25°C 0.2 1 %
DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
Resolution N 8 Bits
Integral Nonlinearity
Differential Nonlinearity
Voltage Divider Tempco ∆V
Full-Scale Error V
Zero-Scale Error V
RESISTOR TERMINALS
Voltage Range
Capacitance
Capacitance
6
6
Shutdown Current
Shutdown Wiper Resistance R
4
4
5
Ax, Bx C
Wx C
7
INL –4 ±1 +4 LSB
DNL V
DNL V
DNL V
/∆T Code = 80
W
WFSE
WZSE
V
A, B, W
A, B
W
I
A_SD
W_SD
= +5 V –1 ±1/4 +1 LSB
DD
= +3 V TA = +25°C–1±1/4 +1 LSB
DD
= +3 V TA = –40°C, +85°C –1.5 ±1/2 +1.5 LSB
DD
Code = FF
Code = 00
f = 1 MHz, Measured to GND, Code = 80
f = 1 MHz, Measured to GND, Code = 80
H
H
H
H
H
–1 –0.25 0 LSB
0 +0.1 +1 LSB
0V
15 ppm/°C
V
DD
15 pF
80 pF
VA = VDD, VB = 0 V, SHDN = 0 0.01 5 µA
VA = VDD, VB = 0 V, SHDN = 0, V
= +5 V 100 200 Ω
DD
DIGITAL INPUTS & OUTPUTS
Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
Input Capacitance
6
IH
IL
IH
IL
OH
OL
IL
C
IL
VDD = +5 V 2.4 V
VDD = +5 V 0.8 V
VDD = +3 V 2.1 V
VDD = +3 V 0.6 V
RL = 1 kΩ to V
DD
VDD–0.1 V
IOL = 1.6 mA, VDD = +5 V 0.4 V
VIN = 0 V or +5 V, VDD = +5 V ±1 µA
5pF
POWER SUPPLIES
Power Supply Range V
Supply Current (CMOS) I
Supply Current (TTL)
Power Dissipation (CMOS)
8
9
Power Supply Sensitivity PSS V
Range 2.7 5.5 V
I
P
DD
DD
DD
DISS
VIH = VDD or VIL = 0 V 0.01 5 µA
VIH = 2.4 V or 0.8 V, VDD = +5.5 V 0.9 4 mA
VIH = VDD or VIL = 0 V, VDD = +5.5 V 27.5 µW
= +5 V ± 10% 0.0002 0.001 %/%
DD
PSS VDD = +3 V ± 10% 0.006 0.03 %/%
DYNAMIC CHARACTERISTICS
6, 10
Bandwidth –3 dB BW_50K R = 50 kΩ 125 kHz
BW_100K R = 100 kΩ 71 kHz
Total Harmonic Distortion THD
Settling Time tS_50K VA = VDD, VB = 0 V, ±1% Error Band 9 µs
V
W
Resistor Noise Voltage e
Crosstalk
NOTES FOR 50 kΩ and 100 kΩ VERSIONS
1
Typicals represent average readings at +25°C and VDD = +5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 30 test circuit.
IW = VDD/R for VDD = +3 V or +5 V for the 50 kΩ and 100 kΩ versions.
3
V
AB
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL Specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
8
Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I
9
P
DISS
10
All Dynamic Characteristics use VDD = +5 V.
11
Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
Specifications subject to change without notice.
11
= VDD, Wiper (VW) = No Connect.
is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
W
t
_100K VA = VDD, VB = 0 V, ±1% Error Band 18 µs
S
_50K RWB = 25 kΩ, f = 1 kHz, RS = 0 20 nV/√Hz
NWB
_100K RWB = 50 kΩ, f = 1 kHz, RS = 0 29 nV/√Hz
e
NWB
C
T
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.003 %
VA = VDD, VB = 0 V –65 dB
versus logic voltage.
DD
REV. B
–3–
Page 4
AD8400/AD8402/AD8403–SPECIFICATIONS
1 kV VERSION
ELECTRICAL CHARACTERISTICS
(VDD = +3 V 6 10% or + 5 V 6 10%, VA = +VDD, VB = 0 V, –408C ≤ TA ≤ +858C unless
otherwise noted)
Parameter Symbol Conditions Min Typ1Max Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL
Resistor Nonlinearity
Nominal Resistance
Resistance Tempco ∆R
Wiper Resistance R
Nominal Resistance Match ∆R/R
2
2
3
R-DNL RWB, VA = NC –5 –1 +3 LSB
R-INL RWB, VA = NC –4 ±1.5 +4 LSB
RT
/∆TV
AB
W
O
= +25°C, Model: AD840XYY1 0.8 1.2 1.5 kΩ
A
= VDD, Wiper = No Connect 700 ppm/°C
AB
IW = 1 V/R
AB
53 100 Ω
CH 1 to 2, VAB = VDD, TA = +25°C 0.75 2 %
DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
Resolution N 8 Bits
Integral Nonlinearity
Differential Nonlinearity
Voltage Divider Temperature Coefficent ∆V
Full-Scale Error V
Zero-Scale Error V
RESISTOR TERMINALS
Voltage Range
Capacitance
Capacitance
6
6
Shutdown Supply Current
Shutdown Wiper Resistance R
4
4
5
Ax, Bx C
Wx C
7
INL –6 ±2 +6 LSB
DNL V
DNL V
/∆T Code = 80
W
WFSE
WZSE
V
A, B, W
A, B
W
I
DD_SD
W_SD
= +5 V –4 –1.5 +2 LSB
DD
= +3 V, TA = +25°C –5 –2 +5 LSB
DD
Code = FF
Code = 00
f = 1 MHz, Measured to GND, Code = 80
f = 1 MHz, Measured to GND, Code = 80
H
H
H
H
H
–20 –12 0 LSB
0 6 10 LSB
0V
25 ppm/°C
V
DD
75 pF
120 pF
VA = VDD, VB = 0 V, SHDN = 0 0.01 5 µA
VA = VDD, VB = 0 V, SHDN = 0, V
= +5 V 50 100 Ω
DD
DIGITAL INPUTS & OUTPUTS
Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
Input Capacitance
6
IH
IL
IH
IL
OH
OL
IL
C
IL
VDD = +5 V 2.4 V
VDD = +5 V 0.8 V
VDD = +3 V 2.1 V
VDD = +3 V 0.6 V
RL = 1 kΩ to V
DD
VDD–0.1 V
IOL = 1.6 mA, VDD = +5 V 0.4 V
VIN = 0 V or +5 V, VDD = +5 V ±1 µA
5pF
POWER SUPPLIES
Power Supply Range V
Supply Current (CMOS) I
Supply Current (TTL)
Power Dissipation (CMOS)
8
9
Power Supply Sensitivity PSS ∆V
Range 2.7 5.5 V
I
P
DD
DD
DD
DISS
VIH = VDD or VIL = 0 V 0.01 5 µA
VIH = 2.4 V or 0.8 V, VDD = +5.5 V 0.9 4 mA
VIH = VDD or VIL = 0 V, VDD = +5.5 V 27.5 µW
= +5 V ± 10% 0.0035 0.008 %/%
DD
PSS ∆VDD = +3 V ± 10% 0.05 0.13 %/%
DYNAMIC CHARACTERISTICS
6, 10
Bandwidth –3 dB BW_1K R = 1 kΩ 5,000 kHz
Total Harmonic Distortion THD
V
Settling Time t
W
Resistor Noise Voltage e
Crosstalk
NOTES FOR 1 kΩ VERSION
1
Typicals represent average readings at +25°C and VDD = +5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. See Figure 30 test circuit.
IW = 500 µA for VDD = +3 V and IW = 4 mA for VDD = +5 V for 1 kΩ version.
3
V
AB
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL Specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
8
Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I
9
P
DISS
10
All Dynamic Characteristics use VDD = +5 V.
11
Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
Specifications subject to change without notice.
11
= VDD, Wiper (VW) = No Connect.
is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
S
C
W
NWB
T
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.015 %
VA = VDD, VB = 0 V, ±1% Error Band 0.5 µs
RWB = 500 Ω, f = 1 kHz, RS = 0 3 nV/√Hz
VA = VDD, VB = 0 V –65 dB
versus logic voltage.
DD
–4–
REV. B
Page 5
AD8400/AD8402/AD8403–SPECIFICATIONS
WARNING!
ESD SENSITIVE DEVICE
±1%
±1% ERROR BAND
RS
1
0
V
DD
VDD/2
V
OUT
t
RS
t
S
All VERSIONS
(VDD = +3 V 6 10% or + 5 V 6 10%, VA = +VDD, VB = 0 V, –408C ≤ TA ≤ +858C unless
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ1Max Units
SWITCHING CHARACTERISTICS
Input Clock Pulse Width tCH, t
Data Setup Time t
Data Hold Time t
CLK to SDO Propagation Delay
CS Setup Time t
CS High Pulse Width t
Reset Pulse Width t
CLK Fall to
CS Rise Hold Time t
CS Rise to Clock Rise Setup t
NOTES
1
Typicals represent average readings at +25°C and VDD = +5 V.
2
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
3
See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using VDD = +3 V or +5 V. To avoid false clocking a minimum input logic slew rate of 1 V/µs should be maintained.
4
Propagation Delay depends on value of VDD, RL and CL–see applications text.
Specifications subject to change without notice.
1
SDI
CLK
V
CS
OUT
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
V
DD
0V
Figure 1a. Timing Diagram
1
SDI
(DATA IN)
(DATA OUT)
SDO
V
CLK
CS
OUT
0
1
A'x OR D'x A'x OR D'x
0
t
PD_MIN
t
1
0
1
0
V
DD
0V
CH
t
CSS
Figure 1b. Detail Timing Diagram
2, 3
4
DAC REGISTER LOAD
Ax OR DxAx OR Dx
t
DS
t
DH
t
CL
t
CSH
otherwise noted)
CL
DS
DH
t
PD
CSS
CSW
RS
CSH
CS1
t
PD_MAX
t
CS1
t
CSW
t
S
±1 % ERROR BAND
Clock Level High or Low 10 ns
5ns
5ns
RL = 1 kΩ to +5 V, CL ≤ 20 pF 1 25 ns
10 ns
10 ns
50 ns
0ns
10 ns
Figure 1c. Reset Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
V
, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
A
AX–BX, AX–WX, BX–W
. . . . . . . . . . . . . . . . . . . . . . ±20 mA
X
Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (T
max) . . . . . . . . . +150°C
J
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . . . (T
Thermal Resistance (θ
)
JA
max–T
J
P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +83°C/W
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +63°C/W
SOIC (SO-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . +70°C/W
±1 %
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . +120°C/W
TSSOP-14 (RU-14) . . . . . . . . . . . . . . . . . . . . . . +180°C/W
TSSOP-24 (RU-24) . . . . . . . . . . . . . . . . . . . . . . +143°C/W
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
DD
)/θ
A
JA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8400/AD8402/AD8403 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
–5–
REV. B
Page 6
AD8400/AD8402/AD8403
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
AD8400
B1
CLK
V
DD
W1
A1
GND
CS
SDI
14
13
12
11
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AGND
V
DD
W1
A1
B1
B2
A2
W2
AD8402
SDI
CLK
RSDGND
SHDN
CS
13
16
15
14
24
23
22
21
20
19
18
17
TOP VIEW
(Not to Scale)
12
11
10
9
8
1
2
3
4
7
6
5
AD8403
AGND2
AGND1
W1
A1
B1
B2
A2
W2
W3
A3
B3
AGND4
B4
A4
W4
DGND
SHDN
RS
V
DD
AGND3
CS
SDI
CLK
SDO
ORDERING GUIDE
#CHs/ Temperature Package Package
Model kV Range Description Option*
AD8400AN10 X1/10 -40°C to +85°C PDIP-8 N-8
AD8400AR10 X1/10 -40°C to +85°C SO-8 SO-8
AD8402AN10 X2/10 -40°C to +85°C PDIP-14 N-14
AD8402AR10 X2/10 -40°C to +85°C SO-14 SO-14
AD8402ARU10 X2/10 -40°C to +85°C TSSOP-14 RU-14
AD8403AN10 X4/10 -40°C to +85°C PDIP-24 N-24
AD8403AR10 X4/10 -40°C to +85°C SOIC-24 SOL-24
AD8403ARU10 X4/10 -40°C to +85°C TSSOP-24 RU-24
AD8400AN50 X1/50 -40°C to +85°C PDIP-8 N-8
AD8400AR50 X1/50 -40°C to +85°C SO-8 SO-8
AD8402AN50 X2/50 -40°C to +85°C PDIP-14 N-14
AD8402AR50 X2/50 -40°C to +85°C SO-14 SO-14
AD8403AN50 X4/50 -40°C to +85°C PDIP-24 N-24
AD8403AR50 X4/50 -40°C to +85°C SOIC-24 SOL-24
AD8400AN100 X1/100 -40°C to +85°C PDIP-8 N-8
AD8400AR100 X1/100 -40°C to +85°C SO-8 SO-8
AD8402AN100 X2/100 -40°C to +85°C PDIP-14 N-14
AD8402AR100 X2/100 -40°C to +85°C SO-14 SO-14
AD8402ARU100 X2/100 -40°C to +85°C TSSOP-14 RU-14
AD8403AN100 X4/100 -40°C to +85°C PDIP-24 N-24
AD8403AR100 X4/100 -40°C to +85°C SOIC-24 SOL-24
AD8403ARU100 X4/100 -40°C to +85°C TSSOP-24 RU-24
AD8400AN1 X1/1 -40°C to +85°C PDIP-8 N-8
AD8400AR1 X1/1 -40°C to +85°C SO-8 SO-8
AD8402AN1 X2/1 -40°C to +85°C PDIP-14 N-14
AD8402AR1 X2/1 -40°C to +85°C SO-14 SO-14
AD8403AN1 X4/1 -40°C to +85°C PDIP-24 N-24
AD8403AR1 X4/1 -40°C to +85°C SOIC-24 SOL-24
AD8403ARU1 X4/1 -40°C to +85°C TSSOP-24 RU-24
*N = Plastic DIP; SO = Small Outline; RU = Thin Shrink SO.
The AD8400, AD8402 and the AD8403 contain 720 transistors.
Table I. Serial Data Word Format
ADDR DATA
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB MSB LSB
9
2
8
2
7
2
0
2
PIN CONFIGURATIONS
–6–
REV. B
Page 7
AD8400/AD8402/AD8403
AD8400 PIN DESCRIPTIONS
Pin Name Description
1 B1 Terminal B RDAC
2 GND Ground
3
CS Chip Select Input, Active Low. When CS
returns high data in the serial input register is
loaded into the DAC register.
4 SDI Serial Data Input
5 CLK Serial Clock Input, positive edge triggered
6V
DD
Positive power supply, specified for operation
at both +3 V and +5 V.
7 W1 Wiper RDAC, addr = 00
2
8 A1 Terminal A RDAC
AD8402 PIN DESCRIPTIONS
Pin Name Description
1 AGND Analog Ground*
2 B2 Terminal B RDAC #2
3 A2 Terminal A RDAC #2
4 W2 Wiper RDAC #2, Addr = 01
2
5 DGND Digital Ground*
SHDN Terminal A open circuit. Shutdown controls
6
Variable Resistors #1 and #2
7
CS Chip Select Input, Active Low. When CS
returns high data in the serial input register is
decoded based on the address bits and loaded
into the target DAC register.
8 SDI Serial Data Input
9 CLK Serial Clock Input, positive edge triggered
10
RS Active low reset to midscale; sets RDAC
11 V
DD
registers to 80
Positive power supply, specified for operation
H
at both +3 V and +5 V
12 W1 Wiper RDAC #1, addr = 00
2
13 A1 Terminal A RDAC #1
14 B1 Terminal B RDAC #1
*All AGNDs must be connected to DGND.
AD8403 PIN DESCRIPTIONS
Pin Name Description
1 AGND2 Analog Ground #2*
2 B2 Terminal B RDAC #2
3 A2 Terminal A RDAC #2
4 W2 Wiper RDAC #2, addr = 01
2
5 AGND4 Analog Ground #4*
6 B4 Terminal B RDAC #4
7 A4 Terminal A RDAC #4
8 W4 Wiper RDAC #4, addr = 11
2
9 DGND Digital Ground*
10
SHDN Active Low Input. Terminal A open circuit.
Shutdown controls variable resistors #1
through #4
11
CS Chip Select Input, Active Low. When CS
returns high data in the serial input register
is decoded based on the address bits and
loaded into the target DAC register.
12 SDI Serial Data Input
13 SDO Serial Data Output, Open Drain transistor
requires pull-up resistor
14 CLK Serial Clock Input, positive edge triggered
15
16 V
RS Active low reset to midscale; sets RDAC
DD
registers to 80
Positive power supply, specified for
H
operation at both +3 V and +5 V
17 AGND3 Analog Ground #3*
18 W3 Wiper RDAC #3, addr = 10
2
19 A3 Terminal A RDAC #3
20 B3 Terminal B RDAC #3
21 AGND1 Analog Ground #1*
22 W1 Wiper RDAC #1, addr = 00
2
23 A1 Terminal A RDAC #1
24 B1 Terminal B RDAC #1
*All AGNDs must be connected to DGND.
REV. B
–7–
Page 8
AD8400/AD8402/AD8403–Typical Performance Characteristics
CODE – DECIMAL
POTENTIOMETER MODE TEMPCO – ppm/C°
70
60
–10
0 32 160
64 96 128
30
20
10
0
50
40
192 224 256
VDD = +5V
TA = –40°C/+85°C
V
A
= 2.00V
V
B
= 0V
10
8
6
4
RESISTANCE – kΩ
2
0
0 32 256
VDD = +3V OR +5V
R
WB
64 96 128 160 192 224
CODE – Decimal
R
WA
Figure 2. Wiper to End Terminal
Resistance vs. Code
1
0.5
0
R-INL ERROR – LSB
–0.5
TA = –40°C
VDD = +5V
TA = +85°C
TA = +25°C
5
80
H
FF
4
3
2
VOLTAGE – V
WB
V
1
0
07
H
40
H
20
H
CODE = 10
H
TA = +25°C
05
H
V
= +5V
DD
145
23 6
IWA CURRENT – mA
Figure 3. Resistance Linearity vs.
Conduction Current
60
SS = 1205 UNITS
VDD = 4.5V
TA = +25°C
48
36
24
FREQUENCY
12
60
SS = 184 UNITS
VDD = 4.5V
TA = +25°C
48
36
24
FREQUENCY
12
0
40.0 42.5 65.045.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5
Figure 4. 100 kΩ Wiper-ContactResistance Histogram
10
8
6
4
2
NOMINAL RESISTANCE – Ω
WIPER RESISTANCE – Ω
RAB (END-TO-END)
RWB (WIPER-TO-END)
CODE = 80
H
–1
0 32 256
Figure 5. Resistance Step Position
Nonlinearity Error vs. Code
1
0.5
0
–0.5
INL NONLINEARITY ERROR – LSB
–1
0 32 25664 96 128 160 192 224
Figure 8. Potentiometer Divider
Nonlinearity Error vs. Code
64 96 128 160 192 224
DIGITAL INPUT CODE – Decimal
VDD = +5V
TA = +25°C
TA = –40°C
TA = +85°C
DIGITAL INPUT CODE – Decimal
0
40.0 42.5 65.045.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5
WIPER RESISTANCE – Ω
Figure 6. 10 kΩ Wiper-ContactResistance Histogram
60
SS = 184 UNITS
VDD = 4.5V
TA = +25°C
48
36
24
FREQUENCY
12
0
35 37 5539 41 43 45 47 49 51 53
WIPER RESISTANCE – Ω
Figure 9. 50 kΩ Wiper-ContactResistance Histogram
–8–
0
–75 –50 125
–25 0 25 50 75 100
TEMPERATURE – °C
Figure 7. Nominal Resistance vs.
Temperature
Figure 10.DVWB/DT Potentiometer
Mode Tempco
REV. B
Page 9
AD8400/AD8402/AD8403
FREQUENCY – Hz
6
0
–54
GAIN – dB
10 1M100 1k 10k 100k
–6
–12
–48
–18
–24
–30
–36
–42
CODE = FF
80
40
20
10
08
04
02
01
TA = +25°C
SEE TEST FIGURE 33
FREQUENCY – Hz
GAIN – dB
0
–6
–48
1k 10k 1M
–30
–36
–42
–12
–24
–18
–54
100k
6
CODE = FF
H
80
H
40
H
20
H
10
H
08
H
04
H
02
H
01
H
FREQUENCY – Hz
GAIN – dB
0
–6
–48
1k 10k 1M
–30
–36
–42
–12
–24
–18
–54
100k
CODE = FF
H
6
80
H
40
H
20
H
10
H
08
H
04
H
02
H
01
H
700
600
500
400
300
200
100
0
RHEOSTAT MODE TEMPCO – ppm/C°
–100
0 32 16064 96 128
VDD = +5V
TA = –40°C/+85°C
= NO CONNECT
V
A
R
MEASURED
WB
CODE – DECIMAL
192 224 256
Figure 11.DRWB/DT Rheostat Mode
Tempco
0.75
CODE = 80
H
VDD = +5V
0.5
SS = 158 UNITS
0.25
0
RESISTANCE – %
–0.25
WB
∆R
–0.5
AVG + 2 SIGMA
AVG
AVG – 2 SIGMA
R
W
(20mV/DIV)
CS
(5V/DIV)
TIME 500ns/DIV
Figure 12. One Position Step Change
at Half-Scale (Code 7F
OUTPUT
INPUT
to 80H)
H
Figure 13. Gain vs. Frequency for
R = 10 k
Ω
–0.75
0 600
100 300 400
HOURS OF OPERATION AT 150°C
Figure 14. Long-Term Drift
Accelerated by Burn-In
10
FILTER = 22kHz
VDD = +5V
T
= +25°C
A
1
0.1
SEE TEST CIRCUIT FIGURE 32
THD + NOISE – %
0.01
SEE TEST CIRCUIT FIGURE 31
0.001
10 100k
Figure 17. Total Harmonic Distortion
Plus Noise vs. Frequency
REV. B
100 1k 10k
200 500
FREQUENCY – Hz
TIME = 5µs/DIV
Figure 15. Large Signal Settling
Time
V
OUT
(50mV/DIV)
TIME 200ns/DIV
Figure 18. Digital Feedthrough
vs. Time
–9–
Figure 16. 50 kΩ Gain vs. Frequency vs. Code
Figure 19. 100 kΩ Gain vs. Frequency vs. Code
Page 10
AD8400/AD8402/AD8403
V
DD
R
ON
– Ω
160
0
140
80
60
40
20
120
100
01 6
2345
TA = +25°C
VDD = +2.7V
VDD = +5.5V
SEE TEST CIRCUIT
FIGURE 36
TEMPERATURE – °C
I
DD
– SUPPLY CURRENT –µA
1
0.1
0.001
–55 –35 125
–15 5 25 45 65 85 105
0.01
LOGIC INPUT
VOLTAGE = 0, V
DD
V
DD
= +5.5V
V
DD
= +3.3V
SEE TEST CIRCUIT 33
CODE = 80
VDD = +5V
T
R = 50kΩ
NORMALIZED GAIN FLATNESS – 0.1dB/DIV
10 10k 1M
R = 100kΩ
FREQUENCY – Hz
= +25°C
A
H
R = 10kΩ
100k100 1k
Figure 20. Normalized Gain Flatness vs. Frequency
12
f
6
0
–6
f
= 71kHz, R = 100kΩ
–3dB
–12
–18
GAIN – dB
–24
VIN = 100mV rms
–30
VDD = +5V
–36
= 1MΩ
R
L
–42
1k 10k 1M
= 700kHz, R = 10kΩ
–3dB
f
= 125kHz, R = 50kΩ
–3dB
FREQUENCY – Hz
100k
10
TA = +25°C
1
VDD = +5V
0.1
– SUPPLY CURRENT – mA
DD
I
0.01
05
VDD = +3V
1234
INPUT LOGIC VOLTAGE – Volts
Figure 21. Supply Current vs. Logic
Input Voltage
1200
A – VDD = 5.5V
CODE = 55
1000
B – VDD = 3.3V
CODE = 55
800
C – VDD = 5.5V
CODE = FF
600
D – VDD = 3.3V
CODE = FF
400
– SUPPLY CURRENT – µA
DD
I
200
0
1k 1M 10M10k 100k
H
H
H
H
FREQUENCY – Hz
TA = +25°C
A
B
C
D
80
60
40
PSRR – dB
20
0
100 1M
Figure 22. Power Supply Rejection
vs. Frequency
VDD = +5V DC ± 1V p-p AC
TA = +25°C
CODE = 80
H
CL = 10pF
V
= 4V, VB = 0V
A
SEE TEST CIRCUIT
FIGURE 32
1k 10k 100k
FREQUENCY – Hz
Figure 23. –3 dB Bandwidths
0
–10
–20
GAIN – dB
0
–45
–90
PHASE – Degrees
100k 2M
Figure 26. 1 kΩ Gain and Phase
vs. Frequency
400k 4M 6M
200k 1M
FREQUENCY – Hz
VDD = +5V
= +25°C
T
A
WIPER SET AT
HALF-SCALE 80
Figure 24. Supply Current vs.
Clock Frequency
100
VDD = +5V
10
SHUTDOWN CURRENT – nA
A
H
10M
I
1
–15 5 25 45 65 85 105 125
–55 –35
TEMPERATURE – °C
Figure 27. Shutdown Current vs.
Temperature
–10–
Figure 25. AD8403 Incremental
Wiper ON Resistance vs. V
DD
Figure 28. Supply Current vs.
Temperature
REV. B
Page 11
Parametric Test Circuits–AD8400/AD8402/AD8403
DUT
A
V+
W
B
V+ = V
DD
1LSB = V+/256
V
MS
Figure 29. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)
NO CONNECT
DUT
A
B
W
I
W
V
MS
Figure 30. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
DUT
AB
+5V
OFFSET
GND
V
~
IN
2.5V DC
W
OP279
V
OUT
Figure 33. Inverting Programmable Gain Test Circuit
+5V
V
OUT
OFFSET
GND
V
IN
W
~
AB
2.5V
OP279
DUT
Figure 34. Noninverting Programmable Gain Test Circuit
I
MS
DUT
V+
A
B
IW = 1V/R
V
W
W
NOMINAL
V
MS
V+ ≈ V
DD
VW2 – [VW1 + IW (RAWII RBW)]
RW = ––––––––––––––––––––––––––
WHERE V
AND V
W2
W1
= V
= V
MS
I
W
WHEN IW = 0
MS
WHEN IW = 1/R
Figure 31. Wiper Resistance Test Circuit
V
A
A
V
DD
V+
~
W
B
V
MS
± 10%
V+ = V
DD
PSRR (dB) = 20LOG ( –––––
PSS (%/%) = –––––––
∆VMS%
∆V
DD
∆V
MS
∆V
DD
%
)
Figure 32. Power Supply Sensitivity Test Circuit (PSS,
PSRR)
+15V
W
OP42
–15V
V
OUT
OFFSET
GND
A
V
~
IN
DUT
B
2.5V
Figure 35. Gain vs. Frequency Test Circuit
0.1V
R
DUT
W
B
SW
CODE = ØØ
I
SW
0 toV
=
I
SW
H
→
0.1V
DD
Figure 36. Incremental ON Resistance Test Circuit
REV. B
–11–
Page 12
AD8400/AD8402/AD8403
OPERATION
The AD8400/AD8402/AD8403 provide a single, dual and quad
channel, 256 position digitally controlled variable resistor (VR)
device. Changing the programmed VR settings is accomplished
by clocking in a 10-bit serial data word into the SDI (Serial
Data Input) pin. The format of this data word is two address
bits, MSB first, followed by eight data bits, MSB first. Table I
provides the serial register data word format. The AD8400/
AD8402/AD8403 has the following address assignments for the
ADDR decode, which determines the location of VR latch receiving the serial register data in Bits B7 through B0:
VR# = A1 × 2 + A0 + 1 Equation 1
The single-channel AD8400 requires A1 = A0 = 0. The dualchannel AD8402 requires A1 = 0. VR settings can be changed
one at a time in random sequence. The serial clock running at
10 MHz makes it possible to load all 4 VRs in under 4 µs (10 ×
4 × 100 ns) for the AD8403. The exact timing requirements are
shown in Figures 1a, 1b and 1c.
The AD8402/AD8403 resets to midscale by asserting the
RS
pin, simplifying initial conditions at power up. Both parts have a
power shutdown
SHDN pin that places the VR in a zero power
consumption state where terminals Ax are open circuited and
the wiper Wx is connected to Bx resulting in only leakage currents being consumed in the VR structure. In shutdown mode
the VR latch settings are maintained so that returning to operational mode from power shutdown, the VR settings return to
their previous resistance values. The digital interface is still active in shutdown, except that SDO is deactivated. Code changes
in the registers can be made that will produce new wiper positions when the device is taken out of shutdown.
Ax
Wx
Bx
/256
SHDN
D7
D6
D5
D4
D3
D2
D1
D0
RDAC
LATCH
DECODER
R
S
R
S
R
S
&
R
S
R
= R
S
NOMINAL
Figure 37. AD8402/AD8403 Equivalent VR (RDAC) Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the VR (RDAC) between terminals A
and B are available with values of 1 kΩ, 10 kΩ, 50 kΩ and 100 kΩ.
The final digits of the part number determine the nominal resistance value, e.g., 10 kΩ = 10; 100 kΩ = 100. The nominal resistance (R
) of the VR has 256 contact points accessed by the
AB
wiper terminal, plus the B terminal contact. The 8-bit data word
in the RDAC latch is decoded to select one of the 256 possible
settings. The wiper’s first connection starts at the B terminal for
data 00
. This B terminal connection has a wiper contact resis-
H
tance of 50 Ω. The second connection (10 kΩ part) is the first
tap point located at 89 Ω [= R
= 39 Ω + 50 Ω] for data 01
tap point representing 78 + 50 = 128 Ω for data 02
(nominal resistance)/256 + R
BA
. The third connection is the next
H
. Each LSB
H
W
data value increase moves the wiper up the resistor ladder until
the last tap point is reached at 10011 Ω. The wiper does not directly connect to the B terminal. See Figure 37 for a simplified
diagram of the equivalent RDAC circuit.
The AD8400 contains one RDAC, the AD8402 contains two
independent RDACs and the AD8403 contains four independent
RDACs. The general transfer equation that determines the digitally programmed output resistance between Wx and Bx is:
R
(Dx) = (Dx)/256 × R
WB
BA
+ R
W
Equation 2
where Dx is the data contained in the 8-bit RDAC# latch, and
R
is the nominal end-to-end resistance.
BA
For example, when V
= 0 V and A terminal is open circuit, the
B
following output resistance values will be set for the following
RDAC latch codes (applies to 10 kΩ potentiometers):
DR
WB
(Dec) (Ω) Output State
255 10011 Full Scale
128 5050 Midscale (
RS = 0 Condition)
1 89 1 LSB
0 50 Zero-Scale (Wiper Contact Resistance)
Note in the zero-scale condition a finite wiper resistance of 50 Ω
is present. Care should be taken to limit the current flow between W and B in this state to a maximum value of 5 mA to
avoid degradation or possible destruction of the internal switch
contact.
Like the mechanical potentiometer the RDAC replaces, it is totally symmetrical. The resistance between the wiper W and terminal A also produces a digitally controlled resistance R
WA
.
When these terminals are used the B terminal should be tied to
the wiper. Setting the resistance value for R
starts at a maxi-
WA
mum value of resistance and decreases as the data loaded in the
RDAC latch is increased in value. The general transfer equation
for this operation is:
R
(Dx) = (256–Dx)/256 × R
WA
BA
+ R
W
Equation 3
–12–
REV. B
Page 13
AD8400/AD8402/AD8403
R
DAC
LAT
#1
GND
A1
W1
B1
V
DD
AD8400
CS
CLK
8
D7
D0
EN
ADDR
DEC
A1
A0
SDI
DI
SER
REG
D0
D7
10-BIT
R
DAC
LAT
#1
R
AGND
RS
A1
W1
B1
V
DD
AD8403
CS
CLK
SDO
8
D7
D0
R
DAC
LAT
#4
R
A4
W4
B4
D7
D0
EN
ADDR
DEC
A1
A0
D7
SDI
DO
DI
SER
REG
D0
SHDN
DGND
where Dx is the data contained in the 8-bit RDAC# latch, and
R
is the nominal end-to-end resistance. For example, when
BA
V
= 0 V and B terminal is open circuit, the following output
A
resistance values will be set for the following RDAC latch codes
(applies to 10 kΩ potentiometers):
DR
WA
(Dec) (Ω) Output State
255 89 Full Scale
128 5050 Midscale (
RS = 0 Condition)
1 10011 1 LSB
0 10050 Zero Scale
The typical distribution of R
from channel-to-channel matches
BA
within ±1%. However, device-to-device matching is process lot
dependent having a ±20% variation. The change in R
BA
temperature has a positive 500 ppm/°C temperature coefficient.
The wiper-to-end-terminal resistance temperature coefficient
has the best performance over the 10% to 100% of adjustment
range where the internal wiper contact switches do not contribute
any significant temperature related errors. The graph in Figure
11 shows the performance of R
tempco vs. code, using the
WB
trimmer with codes below 32 results in the larger temperature
coefficients plotted.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example, connecting A terminal to +5 V and B terminal to
ground produces an output voltage at the wiper starting at zero
volts up to 1 LSB less than +5 V. Each LSB of voltage is equal
to the voltage applied across terminal AB divided by the 256
position resolution of the potentiometer divider. The general
equation defining the output voltage with respect to ground for
any given input voltage applied to terminals AB is:
V
(Dx) = Dx/256 × V
W
AB
+ V
B
Equation 4
Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resistors,
not the absolute value; therefore, the temperature drift improves
to 15 ppm/°C.
At the lower wiper position settings, the potentiometer divider
temperature coefficient increases due to the contributions of the
CMOS switch wiper resistance becoming an appreciable portion
of the total resistance from terminal B to the wiper. See Figure 10
for a plot of potentiometer tempco performance versus code
setting.
DIGITAL INTERFACING
The AD8400/AD8402/AD8403 contains a standard SPI compatible three-wire serial input control interface. The three inputs
are clock (CLK),
edge sensitive CLK input requires clean transitions to avoid
clocking incorrect data into the serial input register. For best results use logic transitions faster than 1 V/µs. Standard logic
families work well. If mechanical switches are used for product
evaluation, they should be debounced by a flip-flop or other
REV. B
CS and serial data input (SDI). The positive-
with
suitable means. The Figure 38 block diagrams show more detail
of the internal digital circuitry. When
CS is taken active low, the
clock loads data into the 10-bit serial register on each positive
clock edge (see Table II).
a.
V
DD
A1
W1
B1
A4
W4
B4
CLK
SDI
SHDN
CS
EN
ADDR
DEC
A1
A0
D7
10-BIT
SER
REG
DI
D0
8
DGND
RS
AD8402
D7
R
DAC
LAT
#1
D0
R
D7
R
DAC
LAT
#2
D0
R
AGND
b.
c.
Figure 38. Block Diagrams
–13–
Page 14
AD8400/AD8402/AD8403
ADDR
DECODE
RDAC 1
RDAC 2
RDAC 4
SERIAL
REGISTER
AD8403
SDI
CLK
CS
SERIAL
REGISTER
SDI
CK
RS
DQ
SHDN
CS
CLK
RS
SDO
1kΩ
DIGITAL
PINS
LOGIC
C
W
120pF
A
B
C
A
C
B
W
C
A
= 90.4pF · ( ) + 30pF
DW
256
RDAC
10kΩ
C
B
= 90.4pF · (1 – ) + 30pF
DW
256
Table II. Input Logic Control Truth Table
CLK CS RS SHDN Register Activity
L L H H No SR effect, enables SDO pin.
P L H H Shift One bit in from the SDI pin.
The tenth previously entered bit is
shifted out of the SDO pin.
X P H H Load SR data into RDAC latch
based on A1, A0 decode (Table III).
X H H H No Operation.
X X L H Sets all RDAC latches to midscale,
wiper centered, and SDO latch
cleared.
X H P H Latches all RDAC latches to 80
X H H L Open circuits all resistor
A–terminals, connects W to B,
turns off SDO output transistor.
NOTE: P = positive edge, X = don’t care, SR = shift register.
The serial data-output (SDO) pin contains an open drain nchannel FET. This output requires a pull-up resistor in order to
transfer data to the next package’s SDI pin. The pull-up resistor
termination voltage may be larger than the V
than max V
e.g., the AD8403 could operate at V
of +8 V) of the AD8403 SDO output device,
DD
= 3.3 V and the pull-up
DD
supply (but less
DD
for interface to the next device could be set at +5 V. This allows
for daisy chaining several RDACs from a single processor serial
data line. The clock period needs to be increased when using a
pull-up resistor to the SDI pin of the following device in the
series. Capacitive loading at the daisy chain node SDO–SDI
between devices must be accounted for to successfully transfer
data. When daisy chaining is used, the
CS should be kept low
until all the bits of every package are clocked into their respective serial registers insuring that the address bits and data bits
are in the proper decoding location. This would require 20 bits
of address and data complying to the word format provided in
Table I if two AD8403 four-channel RDACs are daisy chained.
Note, only the AD8403 has a SDO pin. During shutdown
SHDN the SDO output pin is forced to the off (logic high state)
to disable power dissipation in the pull up resistor. See Figure 40
for equivalent SDO output circuit schematic.
The data setup and data hold times in the specification table determine the data valid time requirements. The last 10 bits of the
data word entered into the serial register are held when
turns high. At the same time
CS goes high it gates the address
decoder, which enables one of the two (AD8402) or four
(AD8403) positive edge triggered RDAC latches. See Figure 39
detail and Table III Address Decode Table.
H
CS re-
.
Figure 39. Equivalent Input Control Logic
The target RDAC latch is loaded with the last eight bits of the
serial data word completing one DAC update. In the case of the
AD8403 four separate 10-bit data words must be clocked in to
change all four VR settings.
Figure 40. Detail SDO Output Schematic of the AD8403
All digital pins are protected with a series input resistor and parallel Zener ESD structure shown in Figure 41a. This structure
applies to digital pins
CS, SDI, SDO, RS, SHDN, CLK. The
digital input ESD protection allows for mixed power supply
applications where +5 V CMOS logic can be used to drive an
AD8400/AD8402 or AD8403 operating from a +3 V power supply. The analog pins A, B, W are protected with a 20 Ω series
resistor and parallel Zener, see Figure 41b.
Figure 41a. Equivalent ESD Protection Circuits
A, B, W
20Ω
Figure 41b. Equivalent ESD Protection Circuit (Analog
Pins)
A1 A0 Latch Decoded
0 0 RDAC#1
0 1 RDAC#2
1 0 RDAC#3 AD8403 Only
1 1 RDAC#4 AD8403 Only
Table III. Address Decode Table
Figure 42. RDAC Circuit Simulation Model for RDAC =
Ω
10 k
–14–
REV. B
Page 15
AD8400/AD8402/AD8403
The ac characteristics of the RDACs are dominated by the internal parasitic capacitances and the external capacitive loads. The
–3 dB bandwidth of the AD8403AN10 (10 kΩ resistor) measures 600 kHz at half scale as a potentiometer divider. Figure 23
provides the large signal BODE plot characteristics of the three
available resistor versions 10 kΩ, 50 kΩ, and 100 kΩ. The gain
flatness versus frequency graph, Figure 26, predicts filter applications performance. A parasitic simulation model has been developed, and is shown in Figure 42. Listing I provides a macro
model net list for the 10 kΩ RDAC:
Listing I. Macro Model Net List for RDAC
.PARAM DW=255, RDAC=10E3
*
.SUBCKT DPOT (A,W,)
*
CA A 0 {DW/256*90.4E-12+30E-12}
RAW A W {(1-DW/256)*RDAC+50}
CW W 0 120E-12
RBW W B {DW/256*RDAC+50}
CB B 0 {(1-DW/256)*90.4E-12+30E-12}
*
.ENDS DPOT
The total harmonic distortion plus noise (THD+N) is measured
at 0.003% in an inverting op amp circuit using an offset ground
and a rail-to-rail OP279 amplifier, Figure 33. Thermal noise is
primarily Johnson noise, typically 9 nV/√
Hz for the 10 kΩ ver-
sion at f = 1 kHz. For the 100 kΩ device, thermal noise becomes
29 nV/√
Hz. Channel-to-channel crosstalk measures less than
–65 dB at f = 100 kHz. To achieve this isolation, the extra ground
pins provided on the package to segregate the individual RDACs
must be connected to circuit ground. AGND and DGND pins
should be at the same voltage potential. Any unused potentiometers in a package should be connected to ground. Power supply rejection is typically –35 dB at 10 kHz (care is needed to
minimize power supply ripple in high accuracy applications).
APPLICATIONS
The digital potentiometer (RDAC) allows many of the applications of trimming potentiometers to be replaced by a solid-state
solution offering compact size, freedom from vibration, shock
and open contact problems encountered in hostile environments. A major advantage of the digital potentiometer is its
programmability. Any settings can be saved for later recall in
system memory.
The two major configurations of the RDAC include the
potentiometer divider (basic 3-terminal application) and the
rheostat (2-terminal configuration) connections shown in
Figures 29 and 30.
Certain boundary conditions must be satisfied for proper
AD8400/AD8402/AD8403 operation. First, all analog signals
must remain within the 0 to V
range used to operate the
DD
single-supply AD8400/AD8402/AD8403 products. For standard
potentiometer divider applications, the wiper output can be
used directly. For low resistance loads, buffer the wiper with a
suitable rail-to-rail op amp such as the OP291 or the OP279.
Second, for ac signals and bipolar dc adjustment applications, a
virtual ground will generally be needed. Whatever method is
used to create the virtual ground, the result must provide the
necessary sink and source current for all connected loads, including adequate bypass capacitance. Figure 33 shows one
channel of the AD8402 connected in an inverting programmable gain amplifier circuit. The virtual ground is set at +2.5 V
which allows the circuit output to span a ± 2.5 volt range with
respect to virtual ground. The rail-to-rail amplifier capability is
necessary for the widest output swing. As the wiper is adjusted
from its midscale reset position (80
(code FF
), the voltage gain of the circuit is increased in suc-
H
) toward the A terminal
H
cessfully larger increments. Alternatively, as the wiper is adjusted toward the B terminal (code 00
), the signal becomes
H
attenuated. The plot in Figure 43 shows the wiper settings for a
100:1 range of voltage gain (V/V). Note the ± 10 dB of pseudologarithmic gain around 0 dB (1 V/V). This circuit is mainly
useful for gain adjustments in the range of 0.14 V/V to 4 V/V;
beyond this range the step sizes become very large and the resistance of the driving circuit can become a significant term in the
gain equation.
256
224
192
160
128
96
DIGITAL CODE – Decimal
64
32
0
0.1 1.0 10
INVERTING GAIN – V/V
Figure 43. Inverting Programmable Gain Plot
REV. B
–15–
Page 16
AD8400/AD8402/AD8403
ACTIVE FILTER
One of the standard circuits used to generate a low-pass, highpass or bandpass filter is the state variable active filter. The digital potentiometer allows full programmability of the frequency,
gain and Q of the filter outputs. Figure 44 shows the filter circuit using a +2.5 V virtual ground, which allows a ±2.5 V
input
P
and output swing. RDAC2 and 3 set the LP, HP and BP cutoff
and center frequencies respectively. These variable resistors
should be programmed with the same data (as with ganged potentiometers) to maintain the best circuit Q. Figure 45 shows
the measured filter response at the bandpass output as a function of the RDAC2 and RDAC3 settings which produce a range
of center frequencies from 2 kHz to 20 kHz. The filter gain response at the bandpass output is shown in Figure 46. At a center frequency of 2 kHz, the gain is adjusted over a –20 dB to
+20 dB range determined by RDAC1. Circuit Q is adjusted by
RDAC4. For more detailed reading on the state variable active
filter, see Analog Devices’ application note, AN-318.
10k
RDAC4
B
~
V
IN
B
RDAC1
A1
±
2.5V
10k
A2
OP279 × 2
RDAC2
0.01µF
B
A3
0.01µF
B
RDAC3
HIGHPASS
LOWPASS
A4
BANDPASS
40
20
0
–20
AMPLITUDE – dB
–40
–60
–80
20 100k100 1k 10k
–0.16
20.0000 k
FREQUENCY – Hz
200k
Figure 45. Programmed Center Frequency Bandpass
Response
40
20
0
–20
AMPLITUDE – dB
–40
–19.01
2.00000 k
Figure 44. Programmable State Variable Active Filter
–60
–80
20 100k100 1k 10k
FREQUENCY – Hz
200k
Figure 46. Programmed Amplitude Bandpass Response
–16–
REV. B
Page 17
OUTLINE DIMENSIONS
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
°
0
°
0.0196 (0.50)
0.0099 (0.25)
x 45
°
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
1
14 8
7
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
0.3444 (8.75)
0.3367 (8.55)
0.0098 (0.25)
0.0040 (0.10)
Dimensions shown in inches and (mm)
AD8400/AD8402/AD8403
0.210 (5.33)
0.160 (4.06)
0.115 (2.93)
PIN 1
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
8-Pin Plastic DIP (N-8)
0.430 (10.92)
0.348 (8.84)
8
14
MAX
0.022 (0.558)
0.014 (0.356)
PIN 1
0.100
(2.54)
BSC
5
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
SEATING
PLANE
14-Pin Plastic DIP Package (N-14)
14
1
0.022 (0.558)
0.014 (0.356)
0.795 (20.19)
0.725 (18.42)
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
8
7
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.130
(3.30)
MIN
SEATING
PLANE
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
0.195 (4.95)
0.115 (2.93)
8-Lead SOIC (SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
0.0500
(1.27)
BSC
5
0.2440 (6.20)
41
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
0.0196 (0.50)
0.0099 (0.25)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
14-Pin Narrow Body SOIC Package (SO-14)
x 45°
REV. B
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
14 8
0.177 (4.50)
0.169 (4.30)
1
PIN 1
0.0256
(0.65)
BSC
14-Lead TSSOP
0.201 (5.10)
0.193 (4.90)
7
0.0118 (0.30)
0.0075 (0.19)
(RU-14)
0.256 (6.50)
0.246 (6.25)
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
–17–
8°
0°
0.028 (0.70)
0.020 (0.50)
Page 18
AD8400/AD8402/AD8403
24-Pin Narrow Body Plastic DIP Package (N-24)
PIN 1
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.92)
PIN 1
0.0118 (0.30)
0.0040 (0.10)
24
1
0.022 (0.558)
0.014 (0.356)
24
1
13
0.280 (7.11)
0.240 (6.10)
12
0.130
(3.30)
MIN
0.325 (8.25)
0.300 (7.62)
1.275 (32.30)
1.125 (28.60)
0.100 (2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.015
(0.38)
MIN
SEATING
PLANE
24-Pin SOIC Package (SOL-24)
13
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
12
0.6141 (15.60)
0.5985 (15.20)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0125 (0.32)
0.0091 (0.23)
8
°
0
°
0.0291 (0.74)
0.0098 (0.25)
0.015 (0.381)
0.008 (0.203)
x 45
0.0500 (1.27)
0.0157 (0.40)
0.195 (4.95)
0.115 (2.93)
°
24-Lead Thin Surface Mount TSSOP Package (RU-24)
0.311 (7.90)
0.303 (7.70)
24 13
0.177 (4.50)
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.169 (4.30)
1
PIN 1
0.0256 (0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
12
0.256 (6.50)
0.246 (6.25)
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
8°
0°
0.028 (0.70)
0.020 (0.50)
–18–
REV. B
Page 19
–19–
Page 20
C1997b–12–1/97
–20–
PRINTED IN U.S.A.
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