8-Bit, 4-Channel Data
V
OUT
DGND
AG
DACAGADC
DATA I/O
(8 BITS)
M
U
X
T/H
8-BIT ADC
1.25 REF
8-BIT
DAC
RS
INT
BUSY
ST
DAC REG
ADC REG
CONTROL LOGIC
A0 A1
VDD (+5.0V)
RD WRCLK CS
AD8401
V
A
IN
V
B
IN
V
C
IN
V
D
IN
a
FEATURES
2 ms ADC with T/H
4-Channel MUX
AD899 Compatible
+5 Volt Operation
On-Chip Reference
4 ms Voltage Output DAC
Fast Bus Access Time—75 ns
APPLICATIONS
Servo Controls
Digitally Controlled Calibration
Process Control Equipment
GENERAL DESCRIPTION
The AD8401 is a complete data acquisition and control system
containing ADC, DAC, 4-channel MUX, and internal voltage
reference. Built using CBCMOS, this monolithic circuit offers
the user a complete system with very high package density and
reliability.
The converter is a successive approximation ADC with T/H,
and is capable of operating with conversion times as short as
2 µs. Analog input bandwidth is 200 kHz, and DAC output volt-
age settling time is less than 4 µs, making the AD8401 capable
of controlling servo loops with speed and precision.
The 8-bit data interface provides both read and write operation
for parallel bus interfaces to microcontrollers and DSP processors. An external 5 MHz clock sets the 2 µs conversion rate.
Slower clocks reduce the conversion time and the internal power
dissipation. The standard control lines: Reset, Busy, Interrupt,
Read and Write complete the handshaking signals for microprocessor communication. A start trigger
cise sampling intervals in synchronous sampling applications.
ST input allows pre-
Acquisition System
AD8401
FUNCTIONAL BLOCK DIAGRAM
The input multiplexer addressing is designed for direct interface
to the AD899 hard-disk drive, read-channel device with no extra
hardware or special software. Analog input range levels are likewise compatible with the AD899.
The AD8401 is designed to operate from a single +5 volt supply, which will give an ADC input range of 0 V to 3.0 V, and
DAC output range of 0 V to 2.5 V.
The AD8401 is offered in the SOIC-28 surface mount package,
and is guaranteed to operate over the extended industrial temperature range of –40°C to +85°C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
AD8401–SPECIFICA TIONS
ADC ELECTRICAL CHARACTERISTICS
(@ VDD = +5.0 V 6 5%, AG
unless otherwise noted)
DAC
= AG
= 0.0 V; f
ADC
= 5 MHz; –408C ≤ TA ≤ +858C,
CLK
Parameter Symbol Conditions Min Typ Max Units
STATIC PERFORMANCE
Resolution N 8 Bits
Total Unadjusted Error TUE ±3 LSB
Relative Accuracy INL –1 +1 LSB
Differential Nonlinearity DNL –1 +1 LSB
Offset Error V
Full-Scale Error A
∆Full-Scale/∆V
DD
OSE
E
TA = +25°C –4 +4 LSB
T
= Full Temp Range –6 +6 LSB
A
TA = +25°C –4 +4 LSB
T
= Full Temp Range –6 +6 LSB
A
TA = +25°C 1 LSB
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio SNR 44 dB
Total Harmonic Distortion THD 48 dB
Intermodulation Distortion IMD 60 dB
Frequency Response 0 to 200 kHz 0.1 dB
Track/Hold Acquisition Time t
AQ
200 ns
ANALOG INPUTS (Applies to Inputs A, B. C, D)
Unipolar Input Range V
Input Current I
Input Capacitance C
IN
IN
IN
03V
–500 +500 µA
10 pF
LOGIC INPUTS
Clock Input Current Low I
Clock Input Current High I
Input Leakage Current I
CKL
CKH
L
LOGIC OUTPUTS (Applies to Outputs DB0–DB7,
Logic Output Low Voltage V
Logic Output High Voltage V
Output Leakage Current I
Output Capacitance C
CONVERSION TIME t
Specifications subject to change without notice.
OL
OH
OZ
OZ
C
VIN = 0 V 1.6 mA
VIN = V
DD
40 µA
CS, RD, RS, ST 10 µA
INT, BUSY)
IOL = 1.6 mA 0.4 V
IOH = 200 µA 4.0 V
CS = 1 (Except INT & BUSY)10µA
CS = 1 (Except INT & BUSY)10pF
External Clock 2 µs
Table I. Multiplexer Address Input Decode
A1 A0 Input Selected
00V
01V
10V
11V
A
IN
B
IN
C
IN
D
IN
–2–
REV. 0
AD8401
DAC ELECTRICAL CHARACTERISTICS
(@ VDD = +5.0 V 6 5%, AG
to AG
; –408C ≤ TA ≤ +858C, unless otherwise noted)
DAC
DAC
= AG
= 0.0 V; RL = 2 kV, CL = 100 pF
ADC
Parameter Symbol Conditions Min Typ Max Units
STATIC PERFORMANCE
Resolution N 8 Bits
Total Unadjusted Error TUE ±2 LSB
Relative Accuracy INL –1 +1 LSB
Differential Nonlinearity DNL –1 +1 LSB
Offset Error V
Full-Scale Error A
∆Full-Scale/∆V
DD
OSE
E
TA = +25°C –2 +2 LSB
T
= Full Temp Range –2.5 +2.5 LSB
A
TA = +25°C –3 +3 LSB
T
= Full Temp Range –4 +4 LSB
A
TA = +25°C –0.5 +0.5 LSB
Load Regulation at Full-Scale –0.2 +0.2 LSB
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio SNR 44 dB
Total Harmonic Distortion THD 48 dB
ANALOG OUTPUT
Output Voltage Range OVR 0 +2.5 V
LOGIC INPUTS (Applies to DB0–DB7, CS, WR, RD, RS)
Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance C
IL
IH
L
IL
2.4 V
–10 10 µA
0.8 V
10 pF
AC CHARACTERISTICS
Voltage Output Settling Time t
Positive Full-Scale Change t
Negative Full-Scale Change t
S
POS
NEG
To ±1/2 LSB of Final Value 2 4 µs
10% to 90% 1 2 µs
90% to 10% 2 4 µs
DAC Glitch Impulse 15 nV s
Digital Feedthrough 1 nV s
VIN to V
Isolation f = 50 kHz 60 dB
OUT
POWER REQUIREMENTS
Positive Supply Current I
Specifications subject to change without notice.
DD
No Load 13 mA
REV. 0
–3–
AD8401
DGND
10pF
3kΩ
DBN
DBN
10pF
3kΩ
+5V
DGND
TIMING ELECTRICAL SPECIFICATIONS
Parameters
1, 2, 3
(@ VDD = +5.0 V 6 5%, AG
unless otherwise noted)
Symbol Condition Min Typ Max Units
DAC
= AG
= 0.0 V; f
ADC
= 5 MHz; –408C ≤ TA ≤ +858C,
CLK
DAC TIMING (See Figure 8 Timing Diagram)
WR Pulse Width t
CS to WR Setup Time t
CS to WR Hold Time t
Data Setup Time t
Data Hold Time t
1
2
3
4
5
50 ns
0ns
0ns
60 ns
0ns
ADC TIMING (See Figures 6 and 7 Timing Diagrams)
ST Pulse Width t
ST to BUSY Delay t
BUSY to INT Delay t
BUSY to CS Delay t
CS to RD Setup Time t
RD Pulse Width
4
CS to RD Hold Time t
Data Access after
Data Access after
Bus Relinquish after
RD t
RD t
RD t
RD to INT Delay t
RD to BUSY Delay t
Data Valid after
BUSY t
Data Valid after BUSY t
NOTES
1
All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2
t13 and t17 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross either 0.8 V or 2.4 V.
3
t14 is defined as the time required for the data line to change 0.5 V when loaded with the circuit of Figure 2.
4
t15 is determined by t13.
DBN
3kΩ
CL
DGND
+5V
3kΩ
DBN
CL
DGND
6
7
8
9
10
t
11
12
13
13
14
15
16
17
17
CL = 20 pF 10 75 ns
CL = 100 pF 10 135 ns
CL = 20 pF 90 ns
CL = 100 pF 135 ns
40 ns
0ns
0ns
75 ns
0ns
10 70 ns
110 ns
30 ns
85 ns
110 ns
a. High Z to V
OH
b. High Z to V
OL
Figure 1. Load Circuits for Data Access Time Test
a. V
OH
Figure 2. Load Circuits for Bus Relinquish Time Test
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . +8 V
Input Voltages . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
DD
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Package Power Dissipation . . . . . . . . . . . . . . (T
Thermal Resistance θ
JA
28-Lead SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . 53°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range (T
max) . . . . –65°C to +150°C
J
Lead Temperature Range (Soldering, 60 sec) . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
max–TA)/θ
J
JA
Model* Range Description Option
AD8401AR –40°C to +85°C 28-Lead SOIC SOL-28
AD8401Chips +25°C Die
*The AD8401 contains 1257 transistors.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8401 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
–4–
precautions are recommended to avoid performance degradation or loss of functionality.
to High Z
b. VOL to High Z
ORDERING GUIDE
Temperature Package Package
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD8401
1
23
5
6
7
8
9
10
11 12 13 14 15 16 17
18
19
20
21
22
23
24
25
2627
Die Size 91 X 121 mil = 11,011 sq mil
28
PIN CONFIGURATION
1
V
DD
2
AG
DAC
3
V
OUT
4
NC
5
A1
6
RS
7
DB7
DB6
DB5
DB4
DB3
DB2
DGND
DB1
AD8401AR
Top View
8
(Not to Scale)
9
10
11
12
13
14
NC = NO CONNECT
A0
28
27
VINA
26
VINB
25
VINC
24
VIND
23
AG
ADC
22
CLK
21
INT
20
BUSY
ST
19
RD
18
17
CS
16
WR
15
DB0
DICE CHARACTERISTICS
PIN DESCRIPTIONS
Pin# Name Description
1V
2AG
3V
DD
DAC
OUT
Positive Supply. Nominal value +5 volts. This pad requires 2 bonds for die assembly.
The substrate is common with V
DD
.
Analog Ground for the DAC. There is a separate analog ground for the ADC.
Voltage Output from the DAC.
4 NC No Connect.
5 A1 Address Input that controls multiplexer. See Table I for address decode.
6 RESET (
7–12, 14, 15 DB7 to DB0 Digital I/O Lines. DB7 (7) is the Most Significant Bit (MSB), for both the ADC and
13 DGND Digital Ground.
16
17
18
19
20
21
22 CLK External Clock Input Pin. Accepts a TTL or 5 V CMOS input logic levels.
23 AG
27–24 V
28 A0 Address input that controls multiplexer. See Table I for address decode.
REV. 0
RS) Active Low Digital Input that clears the DAC register to zero, setting the DAC to mini-
mum scale. It also asynchronously clears the
INT line of the ADC.
the DAC, and DB0 (15) is the Least Significant Bit (LSB).
WR Rising Edge Triggered Write Input. Used to load data into the DAC register.
CS Chip Select. Active Low Input
RD Active Low Read Input. When this input is active, ADC data can be read from the
ST Falling Edge Triggered Start Input. Used for applications requiring precise sample tim-
BUSY ADC Active Low, Status Output. When the ADC is performing a conversion, the
part.
RD going low starts the ADC conversion.
ing. The falling edge of
gated by
CS.
ST starts the conversion and sets the BUSY low. The ST is not
BUSY output is low.
INT Active Low Output. The Interrupt output notifies the system that the ADC has com-
ADC
A, B, C, D Four Analog Inputs
IN
pleted its conversion.
INT goes high on the rising edge of CS or RD. It will also be
forced high when RESET is asserted.
Analog ADC Ground
–5–
AD8401
V
IN
CLK
BUSY
CS , RD
OR ST
100ns
TYP
50ns TYP
MSB DECISION
DB7
LSB DECISION
DB0
t
x
50ns TYP
OPERATION
The AD8401 is a complete data acquisition and control system.
It contains the DAC, a four channel input multiplexer, a track/
hold, an ADC, as well as an internal bandgap reference. It interfaces to the microcontroller via an 8-bit digital I/O port.
D/A CONVERTER SECTION
The DAC is an 8-bit voltage mode DAC with an output that
swings from AG
to the 1.25 volt bandgap voltage. It uses an
DAC
R-2R ladder fed by PNP current sources which allow the output
to swing to ground so that the DAC operates in a unipolar mode.
AMPLIFIER SECTION
The DAC’s output is buffered by an internal high speed op
amp. The op amps output range is set at 0 V to 2.5 V. The op
amp has a 500 ns typical settling time to 0.2% for positive
slewing signals. There are differences in settling time for negative slewing signals. Signals going to zero volts will settle slightly
slower to ground than is seen in the positive direction.
V
DD
20Ω
V
AG
OUT
DAC
20Ω
n-CH
Figure 3. Equivalent Amplifier Output Stage
Current sinking capability is also limited near zero volts in single
supply operation. Figure 3 provides an equivalent amplifier output stage schematic.
Figure 4 shows the wave forms for a conversion cycle. The track
and hold begins holding the input voltage V
approximately
IN
50 ns after the falling edge of the Start command. The MSB decision is made approximately 50 ns after the second falling edge
of the CLK. If t
the CLK will be seen as the first falling clock edge. If t
is greater than 50 ns, then the falling edge of
X
is less
X
than 50 ns, the first MSB conversion will not occur until one
clock cycle later. The following bits will each be converted in a
similar manner 50 ns after each CLK edge until all eight bits
have been converted. After the end of conversion the contents of
the ADC SAR register are transferred to the output data latch,
the track and hold is returned to the track mode,
INT goes low
and the SAR is reset.
Figure 4. Operating Waveforms Using the External Clock
ANALOG INPUT
The analog inputs of the AD8401 are fed into resistor voltage
divider networks with a typical value of 8.5 kΩ. The amplifiers
driving these inputs must have an output resistance low enough
to drive these nodes without losing accuracy. Taps from the
voltage dividers are connected to the track and hold amplifier by
the multiplexer switches.
INTERNAL REFERENCE
An on-chip bandgap is provided as a voltage reference to both
the DAC and the ADC. This reference is internal to the
AD8401 and is not accessible to the user. It is laser trimmed for
both absolute accuracy and temperature coefficients. The reference is internally buffered by a separate control amplifier for both
the DAC and ADC to improve isolation between the converters.
DIGITAL I/O
The 8-bit parallel data I/O port on the AD8401 provides access
to both the DAC and the ADC. This port is TTL/CMOS compatible with three-state outputs that are ESD protected.
The data format is binary. This data coding applies to both the
DAC and the ADC. See the applications information section.
ADC SECTION
A fast successive approximation ADC is used to attain a conversion time of 2 microseconds. Start of conversion is initiated by
CS and RD. Following a Start command the BUSY signal will
become active and another Start command should not be given
until the conversion is complete.
The RESET (
INT (Interrupt or conversion complete) which normally goes
active low at the end of a conversion will be forced high by
RESET asynchronously.
RS) input does not affect A/D conversion, but the
V
IN
VIND
5kΩ
A
5kΩ
3.57kΩ
MUX
3.57kΩ
AGADC
T/H
Figure 5. Equivalent Analog Input Circuit
TRACK-AND-HOLD AMPLIFIER
Following the resistive divider at the input of the AD8401 is a
track-and-hold amplifier that captures input signals accurately
up to the 200 kHz Nyquist frequency of the ADC. To attain this
performance the T/H amplifier must have a much greater bandwidth than the signal of interest. Because of this the user must
be careful to band limit the input signal to avoid aliasing high
frequency components and noise into the passband.
The track-and-hold amplifier is internally controlled by the Start
command and is not directly available to the user. After the
Start command signal the track-and-hold is placed into the hold
mode; it returns to the track mode after the conversion is
complete.
–6–
REV. 0
BUSY
t
10
INT
t
16
t
15
CS
t
14
t
8
t
17
RD
DATA NEW DATA
HIGH Z
OLD DATA
t
12
t
11
t
9
t
13
CLOCK
The AD8401 uses an external clock that is TTL or 5 V CMOS
compatible. The external clock speed is 5 MHz and the duty
cycle may vary from 30% to 70%. The external clock can be
continuously operated between conversions.
DIGITAL INTERFACE: ADC TIMING AND CONTROL
Two basic ADC operating modes are available with the
AD8401. The first mode uses the Start (
synchronized A/D conversion. As soon as the
the T/H switches from tracking to the hold mode capturing the
present analog input-voltage sample. With the T/H holding the
analog sample the successive-approximation analog-to-digital
conversion is completed on that sample value. At the end of
conversion the T/H returns to the tracking mode. This mode of
conversion is ideal for digital signal processing applications
where precise interval sampling is necessary to minimize errors
due to sampling uncertainty or jitter. A precise clock source can
be used to drive the
ST input.
The second mode of conversion is started by the
puts going low, after which the
cessor into a WAIT state until end of conversion. Mode 2 is
asserted by connecting the
ST pin to logic high. The major advantage of this interface is that a single Read Instruction will
start and complete a new analog-to-digital conversion without
the need for carefully tailored software delays that often are not
portable when software routines are taken to a different processor running at a different clock speed.
t
6
ST
t
7
BUSY
INT
CS
RD
DATA
t
CONVERT
t
8
t
9
Figure 6. Mode 1, ADC Interface Timing
Mode 1 Interface
As shown in Figure 6, the falling edge of the ST pulse initiates a
conversion and puts the T/H amplifier into the hold mode. The
BUSY signal goes low during the whole A/D conversion time
and returns high signaling end of conversion. The
be used to interrupt the microprocessor. When the microprocessor performs a READ to access the AD8401 data, the rising
edges of
timing specification. INT can also be used to externally trigger a
pulse that activates the
a buffer or First In First Out FIFO memory. The microprocessor can then load a series of readings from this buffer memory at
a convenient time. Care must be taken not to have the
high when
operate properly. Also triggering the
fore conversion is complete will cause erroneous readings.
REV. 0
CS or RD will reset the INT output to high after the t
CS and RD and places the new data into
RD is brought low; otherwise, the AD8401 will not
ST) pin to trigger a
ST pin is asserted,
RD and CS in-
BUSY line puts the micropro-
t
15
t
10
t
13
t
11
DATA VALIDHIGH Z
t
12
t
14
INT line can
ST input
ST line a second time be-
AD8401
Figure 7. Mode 2, ADC Interface Timing
Mode 2 Interface
This interface mode can be used with microprocessors that can
be put into a WAIT state for at least 2 microseconds. The
pin must be tied to logic high for proper operation. The microprocessor begins a conversion by executing a READ instruction
that asserts the
dress. The AD8401
microprocessor’s READY (or WAIT) line into a WAIT state.
The analog input signal is captured by the T/H on the falling
edge of
the
BUSY line returns high, and then the µP completes its
READ of the new data now on the digital output port of the
AD8401. Note that while conversion is in progress the ADC
places the results from the last conversion (Old Data) on the
data bus. The Figure 7 timing diagram details the applicable
timing specification requirements.
DIGITAL INTERFACE: DAC TIMING AND CONTROL
Table II shows the truth table for DAC operation. The internal
8-bit DAC register contents are loaded from the data bus when
both
WR and CS are asserted. The DAC register determines the
D/A converter analog-output voltage. The
tive edge triggered input that loads the bus data into the DAC
register subject to the data setup and data hold timing requirements. When
will not change with changing data bus values. Figure 8 provides
the detail timing diagram for write cycle operation.
CS WR RS DAC Function
H H H No Effect
L L H No Effect
L ` H DAC Register Updated
` L H DAC Register Updated
X X L DAC Register Loaded with all Zeros
15
DATA VALID DATA
–7–
CS and RD pins at the AD8401’s decoded ad-
BUSY output then goes low, forcing the
RD. When the conversion is complete (8 clocks later),
WR input is a posi-
CS and WR are low, the DAC register contents
Table II. DAC Register Logic
CS
t
2
WR
t
1
t
4
Figure 8. Write Cycle Timing
ST
t
3
t
5
AD8401
RESET
CS
WR
DAC REGISTER
D0 D7
INPUT DATA
TO DAC LADDER
120
0
4.5
30
10
–3.5
20
–4.5
60
40
50
70
80
90
110
100
3.52.51.50.5–0.5–1.5–2.5
FULL SCALE ERROR – LSB
UNITS
SS = 300 UNITS TA = +25°C
An active low pulse, at any time, on the RESET pin asynchronously forces all DAC register bits to zero. The DAC output
voltage becomes zero volts and stays at that value until a new
data word is loaded into the DAC register with a new
mand. The equivalent input logic for the DAC register loading
is shown in Figure 9.
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
VDD = +5V
T
0.5
0
= +25°C
A
WR com-
Figure 9. Equivalent DAC Register Control Logic
–0.5
LINEARITY ERROR – LSB
–0.1
0
DIGITAL INPUT CODE – DECIMAL
19212864
Figure 10. ADC Linearity Error vs. Digital Code
1.0
VDD = +5V
= +25°C
T
A
0.5
0
–0.5
LINEARITY ERROR – LSB
–0.1
0
Figure 11. DAC Linearity Error vs. Digital Code
DIGITAL INPUT CODE – DECIMAL
19212864
256
256
–8–
Figure 12. ADC Full-Scale Error Histogram
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
ADC FULL-SCALE ERROR – LSB
–2.0
–2.5
–3.0
TEMPERATURE – °C
VDD = +5V
100–25–50 7550250
Figure 13. ADC Full-Scale Error vs. Temperature
REV. 0
240
220
200
180
160
140
120
UNITS
100
80
60
40
20
0
–3–4 43210–1–2
FULL SCALE ERROR – LSB
TA = +25°C
SS = 300 UNITS
Figure 14. DAC Full-Scale Error Histogram
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
DAC FULL SCALE ERROR – LSB
–1.5
–2.0
–2.5
TEMPERATURE – °C
x +3σ
x
x – 3σ
VDD = +5V
AD8401
VDD = +5V
2.5
2.0
1.5
1.0
0.5
OUTPUT VOLTAGE – Volts
0
Figure 17. DAC Output Swing vs. Load Resistance
100–25–50 7550250
Figure 18. DAC Output Slew Rate Positive Transition
= +25°C
T
A
RL TO V
100 10k1k 100k10
LOAD RESISTANCE – Ω
3
2
100
90
1
0
5V
0
10
5V
0%
DATA
0
1V
5V
V
OUT
WR
TIME – 1µs/DIV
RL TO GND
DD
5V
0
1µS5V
Figure 15. DAC Full-Scale Error vs. Temperature
4
3
2
1
0
–1
–2
–3
DAC FULL SCALE OUT CHANGE – LSB
–4
–5
BURN-IN TIME @ 150°C – HOURS
x +3σ
x
x – 3σ
VDD = +5V
SS = 135 UNITS
5001000 400300200
Figure 16. DAC Full-Scale Out Change vs Time
Accelerated by Burn-In
3
100
90
2
1
0
5V
10
0
0%
DATA
0
1V
5V
V
OUT
WR
1µS5V
TIME – 1µs/DIV
5V
0
Figure 19. DAC Output Slew Rate Negative Transition
REV. 0
–9–
AD8401
500mV
100
90
– 0.5V /DIV
OUT
V
10
0%
Figure 20. DAC Output Swing with Capacitive Load
VDD = +5V
TA = +25°C
CL = 1000pF
20µS
TIME – 20µs /DIV
10.0
9.5
9.0
8.5
8.0
7.5
SUPPLY CURRENT – mA
7.0
6.5
6.0
VDD = +5.25V
VDD = +4.75V
TEMPERATURE – °C
VIN = +2.4V
Figure 21. Supply Current vs. Temperature
100–25–50 7550250
60
40
20
POWER SUPPLY REJECTION – dB
0
1k 10k 1M100k
FREQUENCY – Hz
TA = +25°C
OUTPUT = FULL SCALE
V
= 5V ± 200mV
DD
Figure 22. Power Supply Rejection Ratio vs. Frequency
–10–
REV. 0
AD8401
OUTPUT
CODE
FULL SCALE
TRANSITION
123 FS
FS – 1LSB
V
IN
INPUT VOLTAGE – LSBs
1LSB = FS
256
11111111
11111110
11111101
00000011
00000010
00000001
00000000
APPLICATIONS INFORMATION
The software programming needs to format data as defined by
the transfer equations and Code Tables that follow.
DAC Transfer Equation
V
OUT
=2.500 ×
D
256
=2.500 ×
255
for a 2.50 V full scale
256
where D is the decimal value 0 through 255 of the 8-bit data
word.
Table III. DAC Unipolar Code
Nominal
Analog
DAC Register Contents General Transfer
Decimal Binary Equation Output V
255 1111 1111
129 1000 0001
128 1000 0000
127 0111 1111
1 0000 0001
0 0000 0000
2.500 ×
2.500 ×
2.500 ×
2.500 ×
2.500 ×
2.500 ×
255
256
129
256
128
256
127
256
1
256
0
256
2.490 V
1.260 V
1.250 V
1.240 V
0.010 V
0.000 V
OUT
The nominal output voltages listed in the Code Table are subject to the static performance specifications. The INL, ZeroScale and Full-Scale errors describe the total specified variation
that will be encountered from part to part. One LSB of error for
the 2.5 V FS range is 9.766 millivolts (= 2.50/256).
Although separate AGNDs exist for both the DAC and ADC to
minimize crosstalk, writing data to the DAC while the ADC is
performing a conversion may result in an incorrect conversion
from the ADC due to signal interaction between the DAC and
ADC. Therefore, to ensure correct operation of the ADC, the
DAC register should not be updated while the ADC is converting.
The AD8401 is configured for an input range of +3.0 volts Full
Scale. The nominal transfer characteristic for this range is plotted in Figure 23. The output coding is natural binary with one
LSB equal to 11.72 millivolts. Note that the first code transition
between 0 LSB and 1 LSB occurs at 5.8 mV, one half of the
11.72 mV LSB step size. The last code transition occurs at Full
Scale minus 1.5 LSBs, which is a 2.982 V input.
The AD8401 is easily interfaced to most microprocessors by using either address bits or address decode to select the appropriate multiplexer channel. Figure 24 shows how easily the AD8401
interfaces to the AD899. No additional hardware is required.
REV. 0
Figure 23. ADC 0 V to +3 V Input Transfer Characteristic
–11–
AD8401
ADDRESS BUS
T/H
VDD (+5.0V)
DGND
AD8401
8-BIT ADC
CONTROL LOGIC
ST
RD
CLOCK
1.25V REF
CS
WR
8-BIT DAC
DAC REG
ADC REG
DATA I/O
(8 BITS)
AG
DAC
AG
V
ADC
A1 A0
AD899
A1
A0
A
B
C
D
VINA
VINB
VINC
VIND
RESET
INT
BUSY
Figure 24. AD8401 Interface to the AD899 Read-Channel Hard Disk Drive Circuit
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Wide-Body SO
(SOL-28)
0.7125 (18.10)
0.6969 (17.70)
OUT
C1857–18–10/93
28 15
PIN 1
0.0500
0.0118 (0.30)
0.0040 (0.10)
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
141
0.1043 (2.65)
0.0926 (2.35)
SEATING
PLANE
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.0125 (0.32)
0.0091 (0.23)
0.3937 (10.00)
0.0291 (0.74)
0.0098 (0.25)
0.0500 (1.27)
8°
0°
0.0157 (0.40)
x 45°
PRINTED IN U.S.A.
–12–
REV. 0
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