Low Power, High Output Current, Quad Op
V
V
www.BDTIC.com/ADI
Amp, Dual-Channel ADSL/ADSL2+ Line Driver
FEATURES
Four current feedback, high current amplifiers
Ideal for use as ADSL/ADSL2+ dual-channel central office
(
CO) line drivers
Low power operation
Power supply operation from ±5 V (+10 V) up to ±12 V (+24 V)
Less than 3 mA/amp quiescent supply current for full
po
wer ADSL/ADSL2+ CO applications (20.4 dBm line
power, 5.5 CF)
Three active power modes plus shutdown
High output voltage and current drive
500 mA peak output drive current
42.6 V p-p differential output voltage
Low distortion
−93 dBc @1 MHz second harmonic
−103 dBc @ 1 MHz third harmonic
High speed: 515 V/μs differential slew rate
Additional functionality of AD8392AACP
On-chip, common-mode voltage generation
APPLICATIONS
ADSL/ADSL2+ CO line drivers
XDSL line drives
GENERAL DESCRIPTION
The AD8392A is comprised of four high output current, low
power consumption, operational amplifiers. It is particularly
well suited for the CO driver interface in digital subscriber line
systems, such as ADSL and ADSL2+. The driver is capable of
providing enough power to deliver 20.4 dBm to a line, while
compensating for losses due to hybrid insertion and back
termination resistors.
AD8392A
PIN CONFIGURATIONS
V
1
EE
2
PD0 1, 2
3
PD1 1, 2
1
+V
4
V
V
–V
OUT
OUT
–V
+V
GND
IN
IN
V
NC
IN
IN
NC
NC
1
1
5
1
6
7
CC
AD8392A
8
3
9
3
10
34
3
11
12
13
14
NC = NO CONNECT
Figure 1. AD8392AARE, 28-Lead TSSOP/EP
1
IN
+V
32 31 30 29 28 27 2526
1
NC
2
1
–V
IN
3
1
OUT
4
V
CC
5
NC
6
3
OUT
7
–V
3
IN
8
NC
91011121314
3
+V
NC = NO CONNECT
Figure 2. AD8392AACP, 5 mm × 5 mm, 32-Lead LFCSP
PD1 1, 2
1
3
IN
NC
V
PD0 1, 2
AD8392A
3, 4
GND
COM
V
28
GND
27
NC
26
NC
2
+V
25
2
EE
GND
EE
V
IN
–V
2
24
IN
V
2
23
OUT
22
NC
21
V
CC
20
V
4
OUT
19
–VIN4
18
4
+V
IN
17
PD1 3, 4
16
PD0 3, 4
15
V
EE
06477-001
1, 2
2
IN
COM
V
NC
+V
24
2
4
PD0 3, 4
NC
–V
2
23
IN
2
V
22
OUT
21
NC
V
20
CC
V
4
19
OUT
–VIN4
18
17
NC
1615
4
IN
+V
PD1 3, 4
06477-002
The AD8392A is available in two thermally enhanced packages,
a 28-lead
TSSOP/EP (AD8392AARE) and a 5 mm × 5 mm,
32-lead LFCSP (AD8392AACP). Four bias modes are available
via the use of two digital bits (PD1, PD0).
Additionally, the AD8392AACP provides V
pins for on-chip,
COM
common-mode voltage generation.
The low power consumption, high output current, high output
volt
age swing, and robust thermal packaging enable the
AD8392A to be used as the CO line drivers in ADSL and other
xDSL systems.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
AD8392A
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications........................................................................................8
Applications....................................................................................... 1
General Description......................................................................... 1
Pin Configurations ...........................................................................1
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Typical Performance Characteristics............................................. 5
Theory of Operation ........................................................................ 7
REVISION HISTORY
10/06—Revision 0: Initial Version
Supplies, Grounding, and Layout................................................8
Power Management ......................................................................8
Thermal Considerations...............................................................8
Typical ADSL/ADSL2+ Application...........................................9
Multitone Power Ratio............................................................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
Rev. 0 | Page 2 of 12
AD8392A
www.BDTIC.com/ADI
SPECIFICATIONS
VS = ±12 V or +24 V, RL = 100 Ω, G = +5, PD = (0, 0), T = 25°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth 25 37 MHz V
−3 dB Large Signal Bandwidth 23 30 MHz V
Peaking 0.06 dB V
Slew Rate 515 V/μs V
NOISE/DISTORTION PERFORMANCE
Second Harmonic Distortion −93 dBc fC = 1 MHz, V
Third Harmonic Distortion −103 dBc fC = 1 MHz, V
Multitone Input Power Ratio 70 dBc 26 kHz to 2.2 MHz, Z
Voltage Noise (RTI) 2.5 nV/√Hz f = 10 kHz
+Input Current Noise 7.6 pA/√Hz f = 10 kHz
−Input Current Noise 12.5 pA/√Hz f = 10 kHz
INPUT CHARACTERISTICS
RTI Offset Voltage −4 ±2 +4 mV V
+Input Bias Current 2 7 μA
−Input Bias Current 3 10 μA
Input Resistance 8 MΩ
Input Capacitance 1 pF
Common-Mode Rejection Ratio 63 66 dB (ΔV
OUTPUT CHARACTERISTICS
Differential Output Voltage Swing 41.2 42.6 V p-p ΔV
Single-Ended Output Voltage Swing 20.6 21.3 V p-p ΔV
Linear Output Current 500 mA RL = 10 Ω, fC = 100 kHz
POWER SUPPLY
Operating Range (Dual Supply) ±5 ±12 V
Operating Range (Single Supply) 10 24 V
Total Quiescent Current
PD1, PD0 = (0, 0) 5.8 6.5 mA/amp
PD1, PD0 = (0, 1) 3.0 3.5 mA/amp
PD1, PD0 = (1, 0) 2.6 3.0 mA/amp
PD1, PD0 = (1, 1) (Shutdown State) 0.4 0.08 mA/amp
PD = 0 Threshold 0.8 V
PD = 1 Threshold 1.8 V
+Power Supply Rejection Ratio 72 74 dB ΔV
−Power Supply Rejection Ratio 65 69 dB ΔV
= 0.1 V p-p, RF = 2 kΩ
OUT
= 4 V p-p, RF = 2 kΩ
OUT
= 0.1 V p-p, RF = 2 kΩ
OUT
= 20 V p-p, RF = 2 kΩ
OUT
= 2 V p-p
OUT
= 2 V p-p
OUT
− V
+IN
−IN
)/(ΔV
OS, DM (RTI)
OUT
, RL = 50 Ω
OUT
OS, DM (RTI)
OS, DM (RTI)
IN, CM
/ΔVCC, ΔVCC = ±1 V
/ΔVEE, ΔVEE = ±1 V
= 100 Ω differential load
LINE
)
Rev. 0 | Page 3 of 12
AD8392A
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage ±13 V (+26 V)
RMS output voltages should be considered. If R
to V
as in single-supply operation, the total power is VS × I
S−
In single supply with R
Power Dissipation See Figure 3
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Airflow increases heat dissipation, effectively reducing θ
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θ
.
JA
Figure 3 shows the maximum safe power dissipation in the
ackage vs. the ambient temperature for the LFCSP-32 and
p
TSSOP-28/EP packages on a JEDEC standard 4-layer board.
θ
values are approximations.
JA
7
6
to VS−, worst case is V
L
is referenced
L
= VS/2.
OUT
TJ = 150°C
JA
. In
OUT
.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is specified
for the device soldered in the circuit board for surface-mount
packages.
Table 3.
Package Type θ
JA
LFCSP-32 (CP) 27.27 °C/W
TSSOP-28/EP (RE) 35.33 °C/W
Maximum Power Dissipation
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
quiescent current (I
the total drive power is V
in the package and some in the load (V
). Assuming that the load (RL) is midsupply,
S
/2 × I
S
, some of which is dissipated
OUT
× I
OUT
OUT
Unit
) times the
S
).
5
4
3
2
1
MAXIMUM POWER DISSIP ATION (W )
0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
TSSOP-28/EP
TEMPERATURE (° C)
LFCSP-32
6477-003
See the Thermal Considerations section for additional thermal
design guidance.
ESD CAUTION
Rev. 0 | Page 4 of 12
AD8392A
www.BDTIC.com/ADI
TYPICAL PERFORMANCE CHARACTERISTICS
900
850
800
750
700
650
600
550
POWER CONSUMP TION (mW )
500
450
15 21
16 17 18 19 20
OUTPUT PO WER (dBm)
Figure 4. Power Consumption vs. Output
ADSL/ADSL2+ Circuit (Figure 15), V
15
PD (0, 0)
PD (0, 1)
PD (1, 0)
Power (138 kHz to 2.2 MHz),
= ±12 V, R
S
LOAD
= 100 Ω, CF = 5.5
06477-046
0
–20
–40
–60
–80
SIGNAL FE EDTHROUGH (d B)
–100
–120
100k 1G
1M 10M 100M
FREQUENCY (Hz)
Figure 7. Signal Feedthrough vs. Frequency
= ±12 V, G = +5, VIN = 800 mV p-p, PD (1, 1), RF = 2 kΩ
V
S
06477-048
10
5
0
–5
GAIN (dB)
–10
–15
–20
10k 1G
100k 1M 10M 100M
FREQUENCY (Hz)
Figure 5. Small Signal Fr
V
S
15
10
–5
GAIN (dB)
–10
–15
= ±12 V, R
5
0
= 100 Ω, G = +5, V
LOAD
PD (0, 1)
equency Response
= 100 mV p-p, RF = 2 kΩ
OUT
PD (0, 1)
PD (0, 0)
PD (1, 0)
PD (1, 0)
PD (0, 0)
2
1
CH1 500mV CH2 500mV 100ns
06477-049
6477-042
Figure 8. Power-Up Time: PD (1, 1) to PD (0, 0)
V
= ±12 V, R
S
2
1
= 100 Ω, G = +5, V
LOAD
= 1 V p-p, RF = 2 kΩ
OUT
–20
10k 1G
V
S
100k 1M 10M 100M
FREQUENCY (Hz)
Figure 6. Large Signal Frequency Response
= ±12 V, R
= 100 Ω, G = +5, V
LOAD
= 4 V p-p, RF = 2 kΩ
OUT
CH1 500mV CH2 500mV 400ns
06477-045
Figure 9. Power-Down Time: PD (0, 0) to PD (1, 1)
= ±12 V, R
V
S
= 100 Ω, G = +5, V
LOAD
Rev. 0 | Page 5 of 12
= 1 V p-p, RF = 2 kΩ
OUT
6477-041
AD8392A
Ω
www.BDTIC.com/ADI
INPUT
CHANNEL 1
2
CH1 200mV CH2 2V 400ns
Figure 10. Output Overdrive Reco
DMT W
0
–10
–20
–30
–40
–50
–60
CROSSTALK (d B)
–70
–80
–90
–100
100k 100M
Figure 11. Crosstalk vs. Frequency, Du
V
S
45
40
very, ADSL/ADSL2+ Circuit (Figure 15),
aveform, V
1M 10M
FREQUENCY (Hz)
al Differential Driver Circuit (Figure 14),
= ±12 V, VIN = 800 mV p-p
OUTPUT
CHANNEL 2
= ±12 V
S
DIFF CHANNEL 1, 2
DIFF CHANNEL 3, 4
100
10
1
OUTPUT IMPEDANCE (Ω)
0.1
0.01
6477-040
10k 1G
PD (1, 0)
100k 1M 10M 100M
FREQUENCY (Hz)
Figure 13. Output Imped
= ±12 V, G = +5, RF = 2 kΩ
V
S
PD (0, 0)
PD (0, 1)
ance vs. Frequency
06477-047
49.9Ω
2kΩ
2kΩ
100Ω
6477-053
499Ω
49.9Ω
06477-025
Figure 14. Dual Differential Driver Circuit
1.78k
35
30
25
20
DIFFERENTIAL OUTPUT (V p-p)
15
10
0 100
10 20 30 40 50 60 70 80 90
LOAD RESISTANCE (Ω)
Figure 12. Differential Output Swing vs. R
LOAD
06477-054
0.01µF
0.01µF
634Ω
87Ω
77Ω
V
CM
77Ω
87Ω
634Ω
Figure 15. ADSL/ADSL2+ Circuit
Dual Differential Driver Circuit (Figure 14)
Rev. 0 | Page 6 of 12
1µF
2kΩ
2kΩ
1.78kΩ
4.99Ω
4.99Ω
100Ω
06477-021
AD8392A
www.BDTIC.com/ADI
THEORY OF OPERATION
The AD8392A is a current feedback amplifier with high
(500 mA) output current capability. With a current feedback
amplifier, the current into the inverting input is the feedback
signal, and the open-loop behavior is that of a transimpedance,
dV
/dIIN or TZ.
O
The open-loop transimpedance is analogous to the open-loop
age gain of a voltage feedback amplifier. Figure 16 shows a
volt
plified model of a current feedback amplifier. Because R
sim
proportional to 1/g
where g
is the transconductance of the input stage. Basic
m
, the equivalent voltage gain is TZ × gm,
m
is
IN
analysis of the follower with gain circuit yields
()
V
O
G
×=
V
IN
()
Z
ST
Z
RRGST
+×+
FIN
where:
R
G +=1
R
Because G × R
F
R
G
IN
g
501≈=
m
<< RF for low gains, a current feedback
IN
amplifier has relatively constant bandwidth vs. gain, the 3 dB
point being set when |T
| = RF.
Z
Of course, for a real amplifier there are additional poles that
ntribute excess phase, and there is a value for R
co
below which
F
the amplifier is unstable. Tolerance for peaking and desired
flatness determines the optimum R
R
G
R
N
V
IN
Figure 16. Simplified Block Diagram
in each application.
F
R
F
R
IN
T
Z
I
IN
V
OUT
6477-022
The AD8392A is capable of delivering 500 mA of output
current while swinging to within 2 V of either power supply
rail. The AD8392A also has a power management system
included on-chip. It features four user-programmable power
levels (three active power modes as well as the provision for
complete shutdown).
Rev. 0 | Page 7 of 12
AD8392A
www.BDTIC.com/ADI
APPLICATIONS
SUPPLIES, GROUNDING, AND LAYOUT
The AD8392A can be powered from either single or dual
supplies, with the total supply voltage ranging from 10 V to
24 V. For optimum performance, a well regulated low ripple
supply should be used.
As with all high speed amplifiers, close attention should be paid
to
supply decoupling, grounding, and overall board layout. Low
frequency supply decoupling should be provided with 10 µF
tantalum capacitors from each supply to ground. In addition, all
supply pins should be decoupled with 0.1 µF quality ceramic
chip capacitors placed as close as possible to the driver. An
internal low impedance ground plane should be used to provide
a common ground point for all driver and decoupling capacitor
ground requirements. Whenever possible, separate ground
planes should be used for analog and digital circuitry.
High speed layout techniques sho
uld be followed to minimize
parasitic capacitance around the inverting inputs. Some practical
examples of these techniques are keeping feedback traces as
short as possible and clearing away ground plane in the area of
the inverting inputs. Input and output traces should be kept
short and as far apart from each other as practical to avoid
crosstalk. When used as a differential driver, all differential
signal traces should be kept as symmetrical as possible.
POWER MANAGEMENT
The AD8392A can be configured in any of three active bias
states as well as a shutdown state via the use of two sets of
digitally programmable logic pins. Pin PD0 (1, 2) and Pin PD1
(1, 2) control Amplifier 1 and Amplifier 2, while PD0 (3, 4) and
Pin PD1 (3, 4) control Amplifier 3 and Amplifier 4. These pins
can be controlled directly with either 3.3 V or 5 V CMOS logic
by using the GND pins as a reference. If left unconnected, the
PD pins float low, placing the amplifier in the full bias mode.
Refer to the
urrent for each of the available bias states.
c
Specifications for the per amplifier quiescent
As is shown in Figure 13, the AD8392A exhibits low output
im
pedance for the three active states. The shutdown state
(PD1, PD0 = 1, 1) provides a high impedance output.
THERMAL CONSIDERATIONS
When using a quad, high output current amplifier, such as the
AD8392A, special consideration should be given to system level
thermal design. In applications such as the ADSL/ADSL2+,
the AD8392A could be required to dissipate as much as 1.4 W
or more on-chip. Under these conditions, particular attention
should be paid to the thermal design to maintain safe operating
temperatures on the die. To aid in the thermal design, the
thermal information in the
be com
bined with what follows here.
Thermal Resistance section can
The information in Tabl e 3 and Figure 3 is based on a standard
EDEC 4-layer board and a maximum die temperature of 150°C.
J
To provide additional guidance and design suggestions, a
thermal study was performed under a set of conditions more
closely aligned with an actual ADSL/ADSL2+ application.
In a typical ADSL/ADSL2+ line card, component density
ually dictates that most of the copper plane used for thermal
us
dissipation be internal. Additionally, each ADSL/ADSL2+ port
may be allotted only 1 square inch, or even less, of board space.
For these reasons, a special thermal test board was constructed
for this study. The 4-layer board measured approximately
4 inches × 4 inches and contained two internal 1 oz copper
ground planes, each measuring 2 inches × 3 inches. The top
layer contained signal traces and an exposed copper strip
¼ inch × 3 inches to accommodate heat sinking, with no
other copper on the top or bottom of the board.
Three 28-lead TSSOPs were placed on the board representing
six ADS
L channels, or one channel per square inch of copper,
with each channel dissipating 700 mW on-chip (1.4 W per
package). The die temperature is then measured in still air and
in a wind tunnel with calibrated airflow of 100 LFM, 200 LFM,
and 400 LFM.
a
mbient temperature for each airflow condition. The figure
Figure 17 shows the power dissipation vs. the
assumes a maximum die temperature of 135°C. No heat sink
was used.
4.5
4.0
3.5
3.0
2.5
STILL AIR
2.0
POWER DISSIPATIO N (W)
1.5
1.0
5 1525354555657585
Figure 17. Power Dissipa
Temperature and Air Flow 28-Lead TSSOP/EP
400LFM
200LFM
100LFM
AMBIENT T EMPERATURE (°C)
tion vs. Ambient
TJ= 135°C
06477-051
This data is only provided as guidance to assist in the thermal
design process. Due diligence should be performed with regards
to power dissipation because there are many factors that can
affect thermal performance.
Rev. 0 | Page 8 of 12
AD8392A
(
N
+
(
−
=
(
−
(
)
−−+
N
www.BDTIC.com/ADI
TYPICAL ADSL/ADSL2+ APPLICATION
In a typical ADSL/ADSL2+ application, a differential line driver
is used to take the signal from the analog front end (AFE) and
drive it onto the twisted pair telephone line. Referring to the
typical circuit representation in Figure 18, the differential input
pears at V
ap
output is transformer coupled to the telephone line at tip and
ring. The common-mode operating point, generally midway
between the supplies, is set through V
V
IN+
R
IN
V
V
IN–
In ADSL/ADSL2+ applications, it is common practice to
conserve power by using positive feedback to synthesize the
output resistance, thereby lowering the required ohmic value
of the line matching resistors, R
somewhat unique in that the positive feedback introduced via
R3 has the effect of synthesizing the input resistance as well.
The following definitions and equations can be used to calculate
the resistor values necessary to obtain the desired gain, input
resistance, and output resistance for a given application. For
simplicity, the following calculations assume a lossless
transformer.
The following values are used in the design equations and are
a
ssumed already known or chosen by the designer.
Value Definition
V
IN
R
IN
N
V
LINE
R
m
R2
V
P
R
L
and V
IN+
R4
R
BIAS
COM
R
BIAS
R4
Figure 18. Typical ADSL/ADSL2+ Application Circuit
from the AFE, while the differential
IN−
.
COM
R3
V
V
P
R1
V
P
OA
R
m
R2
1:N
R2
R
m
V
OA
R3
. The circuit in Figure 18 is
m
TIP
RING
R
OUT
Differential input voltage
Desired differential input resistance
Transformer turns ratio
Differential output voltage at tip and ring
Each is typically 5% to 15% of the transformer reflected
line impedance
Recommended in the amplifier data sheet
Voltage at the + inputs to the amplifier, approximately
(must be less than VIN for positive input resistance)
½ V
IN
Transformer reflected line impedance
06477-024
Additional definitions for calculating resistor values include:
Value Definition
V
OA
k
A
V
β
α
Voltage at the amplifier outputs
Matching resistance reduction factor
Gain from VIN to transformer primary
Negative feedback factor
Positive feedback factor
Note: R1 must be calculated before β and α.
LINE
=
V
OA
=
1
)
kV
Rk2
m
=
R
L
R2R1R12β+
V
LINE
A =
V
VN
IN
k
1βα
With the above known quantities and definitions, the remaining
resistors can readily be calculated.
RV
22
R1−=
R4
R3
R
P
VV
P
OA
=
=
BIAS
V2
IN
V
α
=
()
α
)
VVR
PININ
m
()
R2R1R
2α
+
L
R4R3
R4R3R4
+−
RR2RR1RR1RR1R4A
2αα2
LLL
After building the circuit with the closest 1% resistor values,
th
e actual gain, input resistance, and output resistance can be
verified with the following equations.
GAIN
()
LINEtoV
R
R
IN
OUT
IN
=
1
A
−
R4
=
⎛
⎜
1
−
⎜
⎝
k
()
2
2
⎛
m
⎜
β
V
⎜
⎝
RR4
BIAS
()
+
RR4R1
+
RR4
2
BIAS
⎜
⎝
RR
⎞
L
⎟
⎟
L
⎠
m
⎞
⎟
⎟
⎠
R
R3
BIAS
2
NR
⎛
⎜
⎜
⎜
⎜
⎝
R3
+
R2R1
2
RR4
BIAS
+
+
RR4
R4
R4
⎛
+++=11β
⎞
−
⎟
⎠
BIAS
R4
R3
⎞
⎟
⎟
⎟
⎟
⎠
)
Rev. 0 | Page 9 of 12
AD8392A
www.BDTIC.com/ADI
MULTITONE POWER RATIO
The DMT signal used in ADSL/ADSL2+ systems carries data in
discrete tones or bins, which appear in the frequency domain in
evenly spaced 4.3125 kHz intervals. In applications using this
type of waveform, multitone power ratio (MTPR) is a commonly
used measure of linearity. MTPR is defined as the measured
difference from the peak of one tone that is loaded with data to
the peak of an adjacent tone that is intentionally left empty.
Figure 19 and Figure 20 show the AD8392A MTPR for a 5.5
est factor waveform for empty bins in the ADSL and extended
cr
ADSL2+ bandwidths.
0
–10
–20
–30
–40
–50
(dBm)
–60
–70
–80
–90
–100
CENTER 646.9kHz SPAN 10kHz
Figure 19. MTPR at 647 kHz
06477-043
0
–10
–20
–30
–40
–50
(dBm)
–60
–70
–80
–90
–100
CENTER 1.9664kHz SPAN 10kHz
Figure 20. MTPR at 1.966 MHz
06477-044
Rev. 0 | Page 10 of 12
AD8392A
www.BDTIC.com/ADI
OUTLINE DIMENSIONS
9.80
9.70
9.60
3.55
3.50
3.45
28
1
1.20 MAX
0.15
SEATING
0.05
PLANE
COPLANARIT Y
0.10
TOP VIEW
0.65 BSC
Figure 21. 28-Lead Thin Shrink Small
15
4.50
6.40
4.40
BSC
4.30
14
1.05
1.00
0.80
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AET
8°
0°
0.20
0.09
EXPOSED
(Pins Up)
BOTTOM VIEW
Outline with Exposed Pad [TSSOP/EP]
PAD
0.75
0.60
0.45
3.05
3.00
2.95
050806-A
(RE-28-1)
Dimensions shown in millimeters
0.08
0.60 MAX
25
24
EXPOSED
PAD
(BOTTOM VIEW)
17
16
32
1
8
9
3.50 REF
PIN 1
INDICATOR
3.25
3.10 SQ
2.95
0.25 MIN
PIN 1
INDICATOR
1.00
0.85
0.80
12° MAX
SEATING
PLANE
5.00
BSC SQ
TOP
VIEW
0.80 MAX
0.65 TYP
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
4.75
BSC SQ
0.20 REF
0.05 MAX
0.02 NOM
0.60 MAX
0.50
BSC
0.50
0.40
0.30
COPLANARITY
Figure 22. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5
mm × 5 mm Body, Very Thin Quad (CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD8392AAREZ
AD8392AAREZ-RL
AD8392AAREZ-R7
AD8392AACPZ-R2
AD8392AACPZ-RL
AD8392AACPZ-R7
1
Z = Pb-free part.
1
1
1
1
1
1
−40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP/EP) RE-28-1
−40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP/EP) RE-28-1
−40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP/EP) RE-28-1
−40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2
−40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2
−40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2
Rev. 0 | Page 11 of 12
AD8392A
www.BDTIC.com/ADI
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06477-0-10/06(0)
Rev. 0 | Page 12 of 12
Loading...