Datasheet AD8375 Datasheet (ANALOG DEVICES)

V

V

–

Ultralow Distortion IF VGA

FEATURES

Bandwidth of 630 MHz (−3 dB)
Gain range: −4 dB to +20 dB
Step size: 1 dB ± 0.2 dB
Differential input and output
Noise figure: 8 dB @ maximum gain
Output IP3 of ~50 dBm at 200 MHz
Output P1dB of 19 dBm at 200 MHz
Provides constant SFDR vs. gain
Parallel 5-bit control interface
Power-down feature
Single 5 V supply operation
24-lead, 4 mm × 4 mm LFCSP

APPLICATIONS

Differential ADC drivers
High IF sampling receivers
Wideband multichannel receivers
Instrumentation

GENERAL DESCRIPTION

The AD8375 is a digitally controlled, variable gain, wide
bandwidth amplifier that provides precise gain control, high
IP3, and low noise figure. The excellent distortion performance
and high signal bandwidth make the AD8375 an excellent gain
control device for a variety of receiver applications.

Using an advanced high speed SiGe process and incorporating
proprietary distortion cancellation techniques, the AD8375
achieves 50 dBm output IP3 at 200 MHz.

The AD8375 provides a broad 24 dB gain range with 1 dB
resolution. The gain is adjusted through a 5-pin control interface
and can be driven using standard TTL levels. The open-collector
outputs provide a flexible interface, allowing the overall signal
gain to be set by the loading impedance. Thus, the signal
voltage gain is directly proportional to the load.

The AD8375 is powered on by applying the appropriate logic
level to the PWUP pin. The quiescent current of the AD8375 is
typically 130 mA. When powered down, the AD8375 consumes
less than 5 mA and offers excellent input-to-output isolation.

AD8375

FUNCTIONAL BLOCK DIAGRAM

POS COMM

COM

VIN+

α

VIN–

REGIS TERS

GAIN DECODER

AD8375

POST-AMP

AND

A2A3A4 A1 A0

Figure 1.

Fabricated on an Analog Devices, Inc., high speed SiGe process,
the AD8375 is supplied in a compact, thermally enhanced,
4 mm × 4 mm, 24-lead LFCSP package and operates over the
temperature range of −40°C to +85°C.

40

–50

–60

–70

–80

–90

–100

HARMONIC DIST ORTIO N (dBc), O UTPUT @ 2V p-p

–110

40 60 80 100 120 140 160 180 200

Figure 2. Harmonic Distortion and Output IP3 vs. Frequency

FREQUENCY (MHz )

OIP3

HD2

HD3

PWUP

OUT+

OUT+

OUT–

OUT–

65

60

55

50

45

40

35

30

06724-001

OIP3 (dBm), OUTPUT @ 3dBm/TONE

06724-052

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

AD8375

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics............................................. 7

Circuit Description......................................................................... 12

REVISION HISTORY

8/07—Revision 0: Initial Version

Basic Structure............................................................................ 12

Applications..................................................................................... 13

Basic Connections...................................................................... 13

Single-Ended-to-Differential Conversion............................... 13

Broadband Operation................................................................ 14

ADC Interfacing......................................................................... 14

Layout Considerations............................................................... 17

Characterization Test Circuits.................................................. 17

Evaluation Board ........................................................................ 18

Outline Dimensions .......................................................................22

Ordering Guide .......................................................................... 22

Rev. 0 | Page 2 of 24

AD8375

SPECIFICATIONS

VS = 5 V, T = 25°C, RS = RL = 150 Ω at 140 MHz, 2 V p-p differential output, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth V
Slew Rate 5 V/ns

INPUT STAGE Pin VIN+ and Pin VIN−

Maximum Input Swing For linear operation (AV = −4 dB) 8.5 V p-p
Differential Input Resistance Differential 125 150 165 Ω
Common-Mode Input Voltage 1.9 V
CMRR Gain code = 00000 55 dB

GAIN

Amplifier Transconductance Gain code = 00000 0.060 0.067 0.074 S
Maximum Voltage Gain Gain code = 00000 20 dB
Minimum Voltage Gain Gain code ≥ 11000 −4 dB
Gain Step Size From gain code = 00000 to 11000 0.89 0.98 1.01 dB
Gain Flatness All gain codes, 20% fractional bandwidth for fC < 200 MHz 0.12 dB
Gain Temperature Sensitivity Gain code = 00000 8 mdB/°C
Gain Step Response For VIN = 100 mV p-p, gain code = 10100 to 00000 5 ns

OUTPUT STAGE Pin VOUT+ and Pin VOUT−

Output Voltage Swing At P1dB, gain code = 00000 12.6 V p-p
Output Impedance Differential 16||0.8 kΩ||pF

NOISE/HARMONIC PERFORMANCE

46 MHz Gain code = 00000

Noise Figure 8.3 dB
Second Harmonic V
Third Harmonic V
Output IP3 2 MHz spacing, +3 dBm per tone 50 dBm
Output 1 dB Compression Point 22 dBm

70 MHz Gain code = 00000

Noise Figure 8.3 dB
Second Harmonic V
Third Harmonic V
Output IP3 2 MHz spacing, 3 dBm per tone 51 dBm
Output 1 dB Compression Point 22 dBm

140 MHz Gain code = 00000

Noise Figure 8.3 dB
Second Harmonic V
Third Harmonic V
Output IP3 2 MHz spacing, 3 dBm per tone 51 dBm
Output 1 dB Compression Point 20 dBm

200 MHz Gain code = 00000

Noise Figure 8.3 dB
Second Harmonic V
Third Harmonic V
Output IP3 2 MHz spacing, 3 dBm per tone 50 dBm
Output 1 dB Compression Point 19 dBm

< 2 V p-p (5.2 dBm) 630 MHz

OUT

= 2 V p-p −92 dBc

OUT

= 2 V p-p −94 dBc

OUT

= 2 V p-p −98 dBc

OUT

= 2 V p-p −95 dBc

OUT

= 2 V p-p −90 dBc

OUT

= 2 V p-p −100 dBc

OUT

= 2 V p-p −85 dBc

OUT

= 2 V p-p −92 dBc

OUT

Rev. 0 | Page 3 of 24

AD8375

Parameter Conditions Min Typ Max Unit

POWER INTERFACE

Supply Voltage 4.5 5.0 5.5 V

VPOS and Output Quiescent Current Thermal connection made to exposed paddle under device 120 125 130 mA

vs. Temperature −40°C ≤ TA ≤ +85°C 150 mA

Power-Down Current PWUP low 2.5 mA

vs. Temperature −40°C ≤TA ≤ +85°C 3 mA

POWER-UP/GAIN CONTROL Pin A0 to Pin A4, Pin PWUP

VIH Minimum voltage for a logic high 1.6 V

VIL Maximum voltage for a logic low 0.8 V

Logic Input Bias Current 900 nA

Table 2. Gain Code vs. Voltage Gain Look-Up Table

5-Bit Binary Gain Code Voltage Gain (dB)

00000 +20
00001 +19
00010 +18
00011 +17
00100 +16
00101 +15
00110 +14
00111 +13
01000 +12
01001 +11
01010 +10
01011 +9
01100 +8

5-Bit Binary Gain Code Voltage Gain (dB)

01101 +7
01110 +6
01111 +5
10000 +4
10001 +3
10010 +2
10011 +1
10100 0
10101 −1
10110 −2
10111 −3
11000 −4
>11000 −4

Rev. 0 | Page 4 of 24

AD8375

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage, V
PWUP, A0 to A4 −0.6 V to (V
Input Voltage, V
DC Common Mode VCOM ± 0.25 V
VCOM ±6 mA
Internal Power Dissipation 825 mW
θJA (Exposed Paddle Soldered Down) 63.6°C/W
θJC (At Exposed Paddle) 14.6°C/W
Maximum Junction Temperature 130°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C

IN+

POS

, V

IN−

5.5 V
+ 0.6 V)

POS

−0.15 V to +4.15 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 24

AD8375

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

UP

PW

COMM

COMM

VPOS

COMM

COMM

19

20

21

22

23

24

PIN 1
INDICATOR

1VCOM
2VIN+
3VIN–

AD8375

4A4

TOP VIEW

5A3

(Not to Scale)

6A2

9

7

8

A0

A1

VPOS

Figure 3. 24-Lead LFCSP

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 VCOM Common-Mode Pin. Typically bypassed to ground using external capacitor.
2 VIN+ Voltage Input Positive.
3 VIN− Voltage Input Negative.
4 A4 MSB for the 5-Bit Gain Control Interface.
5 A3 MSB − 1 for the Gain Control Interface.
6 A2 MSB − 2 for the Gain Control Interface.
7 A1 LSB + 1 for the Gain Control Interface.
8 A0 LSB for the 5-Bit Gain Control Interface.
9, 10, 12, 13, 23 VPOS Positive Supply Pins. Should be bypassed to ground using suitable bypass capacitor.
11, 14, 20, 21, 22, 24 COMM Device Common (DC Ground).
15, 17 VOUT+ Positive Output Pins (Open Collector). Require dc bias of +5 V nominal.
16, 18 VOUT− Negative Output Pins (Open Collector). Require dc bias of +5 V nominal.
19 PWUP Chip Enable Pin. Enabled with a logic high and disabled with a logic low.

18 VOUT–
17 VOUT+
16 VOUT–
15 VOUT+
14 COMM
13 VPOS

11

12

10

VPOS

VPOS

COMM

06724-002

Rev. 0 | Page 6 of 24

AD8375

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V, TA = 25°C, RS = RL = 150 Ω, 2 V p-p output, maximum gain unless otherwise noted.

25

20

15

10

GAIN (dB)

–5

–10

11000010100

46MHz
70MHz
140MHz
200MHz

5

0

–4

5

01111

GAIN CODE

10

01010

15

00101

20

00000

06724-003

Figure 4. Gain vs. Gain Code at 46 MHz, 70 MHz, 140 MHz, and 200 MHz

1.0

0.8

0.6

0.4

0.2

0

–0.2

GAIN ERROR (d B)

–0.4

–0.6

–0.8

–1.0

–4

11000010100

5

01111

GAIN CODE

10

01010

15

00101

Figure 7. Gain Step Error, Frequency 140 MHz

20

10100

06724-006

25

20

15

10

5

GAIN (dB)

0

–5

–10

10 100 1000

FREQUENCY (MHz)

Figure 5. Gain vs. Frequency Response

10

25°C

8

85°C
–40°C

6

4

2

0

–2

GAIN ERROR (d B)

–4

–6

–8

–10

–4

11000010100

5

01111

GAIN CODE

10

01010

15

00101

Figure 6. Gain Error over Temperature at 140 MHz

20

00000

20dB
19dB
18dB
17dB
16dB
15dB
14dB
13dB
12dB
11dB
10dB
9dB
8dB
7dB
6dB
5dB
4dB
3dB
2dB
1dB
0dB
–1dB
–2dB
–3dB
–4dB

25

INPUT MAX
RATING

20

BOUNDARY

200MHz

15

10

OP1dB (dBm)

5

0

06724-004

–4 1 6 11 16 21

GAIN (dB)

140MHz
70MHz
46MHz

06724-007

Figure 8. P1dB vs. Gain at 46 MHz, 70 MHz, 140 MHz, and 200 MHz

25

20

15

10

OP1dB (dBm)

5

0

46 100 150 200 250 300 350 400 450 500

06724-005

FREQUENCY (MHz)

+25°C
+85°C
–40°C

06724-008

Figure 9. P1dB vs. Frequency at Maximum Gain, Three Temperatures

Rev. 0 | Page 7 of 24

AD8375

–

–

46MHz
70MHz
140MHz
200MHz

65

60

55

50

OIP3 (dBm)

45

40

35

06724-012

06724-013

52

51

50

49

48

47

46

45

OIP3 (dBm)

44

43

42

41

40

30 50 70 90 110 130 150 170 190 210

AV = +20dB

AV = +10dB

AV = 0dB

AV = –4dB

FREQUENCY (MHz)

Figure 10. Output Third-Order Intercept at Four Gains,

Output Level at 3 dBm/Tone

52

51

50

49

48

47

46

45

OIP3 (dBm)

44

43

42

41

40

–4 –3 –2 –1 0 1 2 3 4 5 6

AV = +20dB

AV = +10dB

P

(dBm)

OUT

AV = 0dB

AV = –4dB

Figure 11. Output Third-Order Intercept vs. Power

at Four Gains, Frequency 140 MHz

55

+25°C 20d B
–40°C 20dB
+85°C 20d B

50

+25°C 0dB
–40°C 0dB
+85°C 0dB

45

40

OIP3 (dBm)

35

30

25

06724-009

–3–2–1012345

AV = 20dB

AV = 0dB

P

PER TONE (dBm)

OUT

Figure 13. Output Third-Order Intercept vs. Power,

Frequency 140 MHz, Three Temperatures

70

–75

–80

–85

–90

IMD3 (dBc)

–95

–100

–105

–110

–4 1 6 11 16

06274-010

Figure 14. Two-Tone Output IMD vs. Gain

GAIN (dB)

at 46 MHz, 70 MHz, 140 MHz, and 200 MHz, Output Level at 3 dBm/Tone

70

65

60

55

50

–40°C

OIP3 (dBm)

45

40

35

30

40 60 80 100 120 140 160 18 0 200

+25°C

+85°C

FREQUENCY (MHz)

Figure 12. Output Third-Order Intercept vs. Frequency,

Three Temperatures, Output Level at 3 dBm/Tone

06724-011

Rev. 0 | Page 8 of 24

70

–75

–80

–85

–90

IMD3 (dBc)

–95

–100

–105

–110

40 60 80 100 120 140 160 180 200

+85°C

–40°C

+25°C

FREQUENCY (MHz)

Figure 15. Two-Tone Output IMD vs. Frequency,

Three Temperatures, Output Level at 3 dBm/Tone

06724-014

AD8375

–

–

–

–

–

–

–

–80

–85

–90

–95

–90

–95

–100

–105

85

HD2 +85°C

HD2 +25°C

HD2 –40° C

75

HD2 –4dB
HD2 0dB
HD2 +10dB
HD2 +20dB
HD3 –4dB
HD3 0dB
HD3 +10dB
HD3 +20dB

65

–70

–75

–80

–85

70

–75

–80

–85

–90

–100

–105

HARMONIC DIST ORTION HD2 (dBc)

–110

–115

40 60 80 100 120 140 160 180 200

FREQUENCY (M Hz)

Figure 16. Harmonic Distortion vs. Frequency at Four Gain Codes,

= 2 V p-p

V

OUT

HARMONIC DIST ORTION HD2 ( dBc)

75

–80

–85

–90

–95

–100

–105

–110

–115

–120

–125

HD2 +20dB
HD2 +10dB
HD2 0dB
HD2 –4dB

HD3 +20dB
HD3 +10dB
HD3 0dB
HD3 –4dB

–5 –4 –3 –2 –1 0 1 2 3 4 5

P

(dBm)

OUT

Figure 17. Harmonic Distortion vs. Power at Four Gain Codes,

Frequency 140 MHz

–90

–95

–100

–105

60

–65

–70

–75

–80

–85

–90

–95

–100

–105

–110

HARMONIC DIST ORTION HD3 (dBc)

HARMONIC DIST ORTION HD3 ( dBc)

–110

–115

HARMONIC DIST ORTIO N HD2 (dBc)

–120

–125

06724-015

–5–4–3–2–1012345

HD3 –40° C

HD3 +25°C

HD3 +85°C

P

OUT

(dBm)

–95

–100

–105

–110

HARMONIC DISTORTI ON HD3 (dBc)

06724-018

Figure 19. Harmonic Distortion vs. Power, Frequency 140 MHz,

Three Temperatures

35

30

25

20

15

NOISE FIGURE (dB)

10

5

0

–4–2 0 2 4 6 8 101214161820

06724-016

46MHz
70MHz
140MHz
200MHz

GAIN (dB)

06724-019

Figure 20. NF vs. Gain at 46 MHz, 70 MHz, 140 MHz, and 200 MHz

80

HD2 +25°C
HD3 +25°C
HD2 –40°C
HD3 –40°C

–85

HD2 +85°C
HD3 +85°C

–90

–95

–100

HARMONIC DIST ORTIO N HD2 AND HD3 (dBc)

–105

40 60 80 100 120 140 160 180 200

FREQUENCY (MHz)

Figure 18. Harmonic Distortion vs. Frequency, Three Temperatures,

= 2 V p-p

V

OUT

06274-017

Rev. 0 | Page 9 of 24

45

40

35

30

25

20

15

NOISE FIGURE (dB)

10

5

0

0 100 200 300 400 500 600 700 800 900 1000

AV = –4dB

AV = 0dB

AV = +10dB

AV = +20dB

FREQUENCY (MHz )

Figure 21. NF vs. Frequency

06724-020

AD8375

REF3 POSITION

–600mV/DIV

REF3 SCALE

0pF

10pF EACH SIDE

500mV

2

1

CH1 500mV Ω CH2 500mV Ω M10.0ns 10.0GS/s IT 10.0ps/ pt

A CH1 960mV

Figure 22. Gain Step Time Domain Response

2

1

CH1 500mV Ω CH2 500mV Ω M 20.0ns 10.0GS/s I T 20.0ps/p t

A CH1 960mV

Figure 23. ENBL Time Domain Response

INPUT

R1

R3

06724-021

REF3 500mV 2.5ns

M2.5ns 20.0GS/ s IT 10.0ps/pt
A CH4 28.0mV

06724-024

Figure 25. Pulse Response to Capacitive Loading, Gain 20 dB

REF1 POSITION
–1.02/DIV
REF1 SCALE

OUTPUT

2

REF1

06724-022

CH2 500mV M2.5n s 20Gsps

REF1 50.0mV

INPUT

IT 2.5p s/pt

50mV

RISE (C2) 1.384n s
FALL(C2) 1.39n s

A CH2 –610mV

06724-025

Figure 26. Large Signal Pulse Response

REF1 POSITION

–420mV/DIV

REF1 SCALE

2V

R1

R3
R4

REF1 2.0V 2.5ns

INPUT

0pF

10pF EACH SIDE

M2.5ns 20.0GS/ s IT 10.0ps/pt
A CH4 28.0mV

Figure 24. Pulse Response to Capacitive Loading, Gain −4 dB

06724-023

Rev. 0 | Page 10 of 24

0

–5

–10

–15

S11 MAG (dB)

–20

–25

–30

10 100 1000

FREQUE NCY (MHz)

Figure 27. S11 vs. Frequency

180

120

60

0

–60

–120

–180

S11 PHASE (Degrees)

06724-026

AD8375

0

–20

–40

–60

S12 (dB)

–80

–100

–120

0 100 200 300 400 500 600 700 800 900 1000

FREQUENCY (MHz)

Figure 28. Reverse Isolation vs. Frequency

06724-027

1.00E–09

9.00E–10

8.00E–10

7.00E–10

6.00E–10

5.00E–10

4.00E–10

DELAY ( Seconds)

3.00E–10

2.00E–10

1.00E–10

0.00E+00

+20dB
+10dB
0dB
–4dB

0 100 200 300 400 500 600 700 800 900 1000

FREQUENCY (MHz)

Figure 30. Group Delay vs. Frequency at Gain

06724-029

0

–20

–40

–60

ISOLATION (dB)

–80

–100

–120

0 100 200 300 400 500 600 700 800 900 1000

FREQUENCY (MHz)

Figure 29. Off-State Isolation vs. Frequency

06724-028

80

70

60

50

40

CMRR (dB)

30

20

10

0

0 100 200 300 400 500 600 700 800 900 1000

FREQUENCY (MHz )

Figure 31. Common-Mode Rejection Ratio vs. Frequency

06724-031

Rev. 0 | Page 11 of 24

AD8375

CIRCUIT DESCRIPTION

BASIC STRUCTURE

The AD8375 is a differential variable gain amplifier consisting
of a 150  digitally controlled passive attenuator followed by a
highly linear transconductance amplifier.

ATTENUATOR

VIN+

VCOM

VIN–

Figure 32. Simplified Schematic

Input System

The dc voltage level at the inputs of the AD8375 is set by an
internal voltage reference circuit to about 2 V. This reference is
accessible at VCOM and can be used to source or sink 100 A.
For cases where a common-mode signal is applied to the inputs,
such as in a single-ended application, an external capacitor
between VCOM and ground is required. The capacitor improves
the linearity performance of the part in this mode. This capacitor
should be sized to provide a reactance of 10  or less at the
lowest frequency of operation. If the applied common-mode
signal is dc, its amplitude should be limited to 0.25 V from
VCOM (VCOM ± 0.25 V).

The device can be powered down by pulling the PWUP pin
down to below 0.8 V. In the powered down mode, the total
current reduces to 3 mA (typical). The dc level at the inputs and
at VCOM remains at about 2 V, regardless of the state of the
PWUP pin.

Output Amplifier

The gain is based on a 150  differential load and varies as RL is
changed per the following equations:

Voltage Gain = 20 × (log(R

and

Power Gain = 10 × (log(R

AD8375

MUX BUFFERS

A0 TO A4

DIGITAL
SELECT

/150) + 1)

L

/150) + 2)

L

gm CORE

AMP

VOUT+

VOUT–

06724-032

The dependency of the gain on the load is due to the open­collector architecture of the output stage.

The dc current to the outputs of the amplifier is supplied
through two external chokes. The inductance of the chokes and
the resistance of the load determine the low frequency pole of
the amplifier. The parasitic capacitance of the chokes adds to
the output capacitance of the part. This total capacitance in
parallel with the load resistance sets the high frequency pole of
the device. Generally, the larger the inductance of the choke, the
higher its parasitic capacitance. Therefore, the value and type of
the choke should be chosen keeping this trade-off in mind.

For operation frequency of 15 MHz to 700 MHz driving a
150  load, 1 H chokes with SRF of 160 MHz or higher are
recommended (such as 0805LS-102XJBB from Coilcraft).

The supply current consists of about 50 mA through the VCC
pin and 80 mA through the two chokes combined. The latter
increases with temperature at about 2.5 mA per 10°C.

There are two output pins for each polarity and they are
oriented in an alternating fashion. When designing the board,
care should be taken to minimize the parasitic capacitance due
to the routing that connects the corresponding outputs together.
A good practice is to avoid any ground or power plane under
this routing region and under the chokes to minimize the
parasitic capacitance.

Gain Control

A 5-bit binary code changes the attenuator setting in 1 dB steps
such that the gain of the device changes from 20 dB (Code 0) to

−4 dB (Code 24 and higher).
The noise figure of the device is about 8 dB at maximum gain

setting and it increases as the gain is reduced. The increase in
noise figure is equal to the reduction in gain. The linearity of
the part measured at the output is first-order independent of
the gain setting. From 0 dB to 20 dB gain, OIP3 is approximately
50 dBm into 150  load at 140 MHz (3 dBm per tone). At gain
settings below 0 dB, it drops to approximately 45 dBm.

Rev. 0 | Page 12 of 24

AD8375

V

–

V

APPLICATIONS

BASIC CONNECTIONS

Figure 35 shows the basic connections for operating the
AD8375. A voltage between 4.5 V and 5.5 V should be applied
to the supply pins. Each supply pin should be decoupled with at
least one low inductance, surface-mount ceramic capacitor of

0.1 F placed as close as possible to the device.
The outputs of the AD8375 are open collectors that need to be

pulled up to the positive supply with 1 µH RF chokes. The
differential outputs are biased to the positive supply and require
ac coupling capacitors, preferably 0.1 µF. Similarly, the input
pins are at bias voltages of about 2 V above ground and should
be ac-coupled as well. The ac coupling capacitors and the RF
chokes are the principle limitations for operation at low
frequencies.

To enable the AD8375, the PWUP pin must be pulled high.
Taking PWUP low puts the AD8375 in sleep mode, reducing
current consumption to 5 mA at ambient.

SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION

The AD8375 can be configured as a single-ended input to
differential output driver as shown in
resistor in parallel with the input impedance of input pin
provides an impedance matching of 50 . The voltage gain and
the bandwidth of this configuration, using a 150  load,
remains the same as when using a differential input.

Figure 33. A 150 

1µH

+5

1µH

0.1µF

150Ω

0.1µF

06724-035

50Ω

AC

150Ω

37.5Ω

0.1µF

0.1µF

0.1µF

VCM

AD8375

5

A0 TO A4

Figure 33. Single-Ended-to-Differential Conversion

Using a single-ended input decreases the power gain by 3 dB
and limits distortion cancellation. Consequently, the second­order distortion is degraded. The third-order distortion remains
low to 200 MHz, as shown in

60

–65

–70

–75

–80

–85

–90

HARMONIC DISTORTION (dBc)

–95

Figure 34.

HD2

HD3

–100

0 20015010050

FREQUENCY (MHz )

06724-036

Figure 34. Harmonic Distortion vs. Frequency of

Single-Ended-to-Differential Conversion

+

S

0.1µF

10µF

18

17

16

15

14

13

0.1µF

1µH

1µH

+V

0.1µF

BALANCED

R

L

LOAD

0.1µF

S

06724-034

0.1µF

R

S

BALANCED

SOURCE

2

AC

R

S

2

PARALLEL CONTROL INTERF ACE

0.1µF

0.1µF

COMM VPOS COMM COMM COMM PWUP

1

VCOM

2

VIN+

3

VIN–

4

A4

5

A3

6

A2

A1 A0 VPOS VPOS COMM VPOS

AD8375

0.1µF

Figure 35. Basic Connections

1924 23 22 21 20

VOUT–

VOUT+

VOUT–

VOUT+

COMM

VPOS

127891011

Rev. 0 | Page 13 of 24

AD8375

–

5

V

BROADBAND OPERATION

The AD8375 uses an open-collector output structure that
requires dc bias through an external bias network. Typically,
choke inductors are used to provide bias to the open-collector
outputs. Choke inductors work well at signal frequencies where
the impedance of the choke is substantially larger than the target
ac load impedance. In broadband applications, it may not be
possible to find large enough choke inductors that offer enough
reactance at the lowest frequency of interest while offering a
high enough self resonant frequency (SRF) to support the
maximum bandwidth available from the device. The circuit in
Figure 36 can be used when frequency response below 10 MHz
is desired. This circuit replaces the bias chokes with bias resistors.
The bias resistor has the disadvantage of a greater IR drop, and
requires a supply rail that is several volts above the local 5 V
supply used to power the device. Additionally, it is necessary
to account for the ac loading effect of the bias resistors when
designing the output interface. Whereas the gain of the AD8375
is load dependent, R
optimum 150 Ω target load impedance to provide the expected
ac performance depicted in the data sheet. Additionally, to
ensure good output balance and even-order distortion
performance, it is essential that R1 = R2.

ETC1-1-13

50Ω

Figure 36. Single-Ended Broadband Operation with Resistive Pull-Ups

Using the formula for R1 (Equation 1), the values of R1 = R2
that provide a total presented load impedance of 150 Ω can be
found. The required voltage applied to the bias resistors, VR,
can be found by using the VR formula (Equation 2).

75

=

R1

R

L

and

, in parallel with R1 + R2, should equal the

L

SET TO

5V

0.1µF

0.1µF

VR

R1

R2

VR

0.1µF

0.1µF

AD8375

5

A0 TO A4

RL

5

5V

5V

37.5Ω

0.1µF

AD8375

0.1µF

37.5Ω

×

R

L

(1)

150

−

0Ω

5

A0 TO A4

3

51040

+××=−R1VR

(2)

ETC1-1-13

37.5Ω

37.5Ω

Figure 38. Wideband ADC Interfacing Example Featuring the AD9445

06724-037

1µH

1µH

For example, in the extreme case where the load is assumed to
be high impedance, R

= ∞, the equation for R1 reduces to R1 =

L

75 Ω. Using the equation for VR, the applied voltage should be
VR = 8 V. The measured single-tone low frequency harmonic
distortion for a 2 V p-p output using 75 Ω resistive pull-ups is
provided in Figure 37.

80

–82

–84

–86

–88

–90

–92

HARMONIC DISTORTION (dBc)

–94

–96

0 5 10 15 20

HD2

HD3

FREQUENCY (M Hz)

Figure 37. Harmonic Distortion vs. Frequency Using Resistive Pull-Ups

ADC INTERFACING

The AD8375 is a high output linearity variable gain amplifier
that is optimized for ADC interfacing. The output IP3 and noise
floor essentially remain constant vs. the 24 dB available gain
range. This is a valuable feature in a variable gain receiver where
it is desirable to maintain a constant instantaneous dynamic
range as the receiver gain is modified. The output noise density
is typically around 20 nV/√Hz, which is comparable to 14-/16­bit sensitivity limits. The two-tone IP3 performance of the
AD8375 is typically around 50 dBm. This results in SFDR levels
of better than 86 dB when driving the AD9445 up to 140 MHz.

There are several options available to the designer when using
the AD8375. The open-collector output provides the capability
of driving a variety of loads. Figure 38 shows a simplified
wideband interface with the AD8375 driving a AD9445. The
AD9445 is a 14-bit 125 MSPS analog-to-digital converter with a
buffered wideband input, which presents a 2 kΩ differential
load impedance and requires a 2 V p-p differential input swing
to reach full scale.

L

82Ω

82Ω

(SERIES)

L

(SERIES)

0.1µF

0.1µF

33Ω

33Ω

VIN+

AD9445

14-BIT ADC

VIN–

14

06724-039

0.1µF

0.1µF

06724-038

Rev. 0 | Page 14 of 24

AD8375

For optimum performance, the AD8375 should be driven
differentially using an input balun or impedance transformer.
Figure 38 uses a wideband 1:1 transmission line balun followed
by two 37.5  resistors in parallel with the 150  input imped­ance of the AD8375 to provide a 50  differential terminated
input impedance. This provides a wideband match to a 50 
source. The open-collector outputs of the AD8375 are biased
through the two 1 H inductors and are ac-coupled to the two
82  load resistors. The 82  load resistors in parallel with the
series-terminated ADC impedance yields the target 150 
differential load impedance, which is recommended to provide
the specified gain accuracy of the device. The load resistors are
ac-coupled from the AD9445 to avoid common-mode dc
loading. The 33  series resistors help to improve the isolation
between the AD8375 and any switching currents present at the
analog-to-digital sample and hold input circuitry.

1

0

–10

–20

–30

–40

–50

–60

–70

–80

(dBFS)

–90

–100

–110
–120

–130

–140

–150

0 5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50

3

2

+

FREQUENCY ( MHz)

SNR = 64.93dBc
SFDR = 86.37dBc
NOISE FLOO R = –108.1d B
FUND = –1.053dBFs
SECOND = –86.18dBc
THIRD = –86.22dBc

4

5

6

06724-040

Figure 39. Measured Single-Tone Performance of the

Circuit in

Figure 38 for a 100 MHz Input Signal

The circuit depicted in Figure 38 provides variable gain,
isolation and source matching for the AD9445. Using this
circuit with the AD8375 in a gain of 20 dB (maximum gain) an
SFDR performance of 86 dBc is achieved at 100 MHz, as
indicated in

Figure 39.

The addition of the series inductors L (series) in
extends the bandwidth of the system and provides response
flatness. Using 100 nH inductors as L (series), the wideband
system response of

Figure 40 is obtained. The wideband
frequency response is an advantage in broadband applications
such as predistortion receiver designs and instrumentation
applications. However, by designing for a wide analog input
frequency range, the cascaded SNR performance is somewhat
degraded due to high frequency noise aliasing into the wanted
Nyquist zone.

0

–1

–2

–3

–4

–5

(dBFs)

–6

FIRST POINT = –2.93dBFs
END POINT = –9. 66dBFs

–7

MID POINT = –2.33dBFs
MIN = –9.66dBFs

–8

MAX = –1.91dBFs

–9

–10

20 48 76 104 132 160 188 216 244 272 300

FREQUENCY (MHz )

Figure 40. Measured Frequency Response of Wideband

ADC Interface Depicted in

Figure 38

An alternative narrow-band approach is presented in Figure 41.
By designing a narrow band-pass antialiasing filter between the
AD8375 and the target ADC, the output noise of the AD8375
outside of the intended Nyquist zone can be attenuated, helping
to preserve the available SNR of the ADC. In general, the SNR
improves several dB when including a reasonable order antialias­ing filter. In this example, a low loss 1:3 input transformer is used
to match the AD8375’s 150  balanced input to a 50  unbal­anced source, resulting in minimum insertion loss at the input.

Figure 38

06724-041

Rev. 0 | Page 15 of 24

AD8375

Figure 41 is optimized for driving some of Analog Devices
popular unbuffered ADCs, such as the AD9246, AD9640,
and AD6655. Table 5 includes antialiasing filter component
recommendations for popular IF sampling center frequencies.
Inductor L5 works in parallel with the on-chip ADC input
capacitance and a portion of the capacitance presented by C4 to
form a resonant tank circuit. The resonant tank helps to ensure
the ADC input looks like a real resistance at the target center
frequency. Additionally, the L5 inductor shorts the ADC inputs

at dc, which introduces a zero into the transfer function. In
addition, the ac coupling capacitors and the bias chokes
introduce additional zeros into the transfer function. The final
overall frequency response takes on a band-pass characteristic,
helping to reject noise outside of the intended Nyquist zone.
Table 5 provides initial suggestions for prototyping purposes.
Some empirical optimization may be needed to help

compensate

for actual PCB parasitics.

50Ω

1:3

1nF

1nF

A0 TO A4

AD8375

5

1µH

1µH

1nF

301Ω

1nF

L1

L1

L3

165Ω

C2

C4

CML

L3

L5

165Ω

AD9246
AD9640
AD6655

06724-042

Figure 41. Narrow-Band IF Sampling Solution for Unbuffered ADC Application

Table 5. Interface Filter Recommendations for Various IF Sampling Frequencies

Center Frequency 1 dB Bandwidth L1 C2 L3 C4 L5

96 MHz 27 MHz 390 nH 5.6 pF 390 nH 25 pF 100 nH
140 MHz 30 MHz 330 nH 3.3 pF 330 nH 20 pF 56 nH
170 MHz 32 MHz 270 nH 2.7 pF 270 nH 20 pF 39 nH
211 MHz 32 MHz 220 nH 2.2 pF 220 nH 18 pF 27 nH

Rev. 0 | Page 16 of 24

AD8375

V

V

LAYOUT CONSIDERATIONS

There are two output pins for each polarity, and they are
oriented in an alternating fashion. When designing the board,
care should be taken to minimize the parasitic capacitance due
to the routing that connects the corresponding outputs together.
A good practice is to avoid any ground or power plane under
this routing region and under the chokes to minimize the
parasitic capacitance.

CHARACTERIZATION TEST CIRCUITS

Differential-to-Differential Characterization

The S-parameter characterization for the AD8375 was
performed using a dedicated differential input to differential
output characterization board.
characterization board. The board was designed for optimum
impedance matching into a 75  system. Because both the
input and output impedances of the AD8375 are 150 
differentially, 75  impedance runs were used to match 75 
network analyzer port impedances. On-board 1 H inductors
were used for output biasing, and the output board traces were
designed for minimum capacitance.

Figure 44 shows the layout of

+5V

50Ω

AC

+9

AD8375

5

96Ω 96Ω

0.1µF

0.1µF

330Ω

330Ω

TC3-1T

T1

0.1µF

0.1µF

A0 TO A4

Figure 43. Test Circuit for Time Domain Measurements

25Ω

25Ω

50Ω

06724-047

AC

L1

1µHL21µH

75Ω

0.1µF

AD8375

75Ω

0.1µF
5

A0 TO A4

Figure 42. Test Circuit for S-Parameters on Dedicated 75 Ω

Differential-to-Differential Board

TC3-1T

T1

50Ω

AC

0.1µF

0.1µF

75Ω TRACES75Ω TRACES

C1

0.1µF

C2

0.1µF

AD8375

5

A0 TO A4

75Ω

AC

75Ω

06724-046

L1

1µHL21µH

+5

C3

R1

0.1µF

62Ω

PAD LOSS = 11d B

R2

C4

62Ω

0.1µF

Figure 45. Test Circuit for Distortion, Gain, and Noise

Figure 44. Differential-to-Differential Characterization Board

Circuit Side Layout

R4
25Ω

ETC1-1-13

T2

50Ω

R3
25Ω

06724-043

06724-044

Rev. 0 | Page 17 of 24

AD8375

EVALUATION BOARD

Figure 46 shows the schematic of the AD8375 evaluation board.
The silkscreen and layout of the component and circuit sides
are shown in
by a single supply in the 4.5 V to 5.5 V range. The power supply
is decoupled by 10 µF and 0.1 µF capacitors at each power supply
pin. Additional decoupling, in the form of a series resistor or
inductor at the supply pins, can also be added.
the various configuration options of the evaluation board.

Figure 47 through Figure 50. The board is powered

Table 6 details

The output pins of the AD8375 require supply biasing with
1 µH RF chokes. Both the input and output pins must be ac­coupled. These pins are converted to single-ended with a pair of
baluns (Mini-Circuits TC3-1T+ and M/A-COM ETC1-1-13).
The balun at the input, T1, is used to transform a 50 Ω source
impedance to the desired 150 Ω reference level. The output
balun, T3, and the matching components are configured to
provide a 150  to 50  impedance transformation with an
insertion loss of about 11 dB.

Rev. 0 | Page 18 of 24

AD8375

OUTN

OUTP

0Ω

R30

T3

ETC1-1-13

R25

30.9Ω

VPOS

R20

C64

0.1µF

0Ω

R91

VXA

R13

VPOS

PU

R15

0Ω

0Ω

R16

C63

0.1µF

0Ω

C5

61.9Ω

C8

0.1µF

L1

1µH

L2

1µH

18

1924 23 22 21 20

VOUT–

R24

R29

VPOS

R62

C62

0.1µF

R23

30.9Ω

R19

61.9Ω

C7

0.1µF

C13

17

16

15

14

13

127891011

VPOS

VOUT–

VOUT+

COMM

VOUT+

06724-045

0.1µF

VPOS

AD8375

VPOS

COMM VPOS COMM COMM CO MM PWUP

VCOM

VIN+

VIN–

R71

T1

A4

3

4

C2

0.1µF

0Ω

R10

R72

C60

0.1µF

R2

0Ω

INN

C11

1

2

0.1µF

C1

0.1µF

R9

0Ω

R70

TC3-1T+

R1

INP

Figure 46. AD8375 Evaluation Board Schematic

C14

0.1µF

A3
5

A1 A0 VPOS VPOS COMM VPOS

A2
6

WA0WA1WA2WA3WA4

C20

10µF

VPOS

Rev. 0 | Page 19 of 24

AD8375

Table 6. Evaluation Board Configuration Options

Components Function Default Conditions

C13, C14, C20,
C63, C64, R91

T1, C1, C2, C60,
R1, R2, R9, R10,
R70 to R72

T3, C7, C8, C62
L1, L2, R15, R16,
R19, R20, R23 to R25,
R29, R30, R62

PU, R13, C5

WA0 to WA4

C11

Power Supply Decoupling. Nominal supply decoupling consists a 10 μF
capacitor to ground followed by 0.1 μF capacitors to ground positioned as
close to the device as possible.

Input Interface. T1 is a 3:1 impedance ratio balun to transform a 50 Ω single­ended input into a 150 Ω balanced differential signal. R2 grounds one side of
the differential drive interface for single-ended applications. R9, R10, and R70
to R72 are provided for generic placement of matching components. C1 and
C2 are dc blocks.

Output Interface. C7 and C8 are dc blocks. L1 and L2 provide dc biases for the
output. R19, R20, and R23 to R25 are provided for generic placement of
matching components. The evaluation board is configured to provide a 150 Ω
to 50 Ω impedance transformation with an insertion loss of about 11 dB. T3 is
a 1:1 impedance ratio balun to transform the balanced differential signal to a
single-ended signal. R30 grounds one side of the differential output interface
for single-ended applications.

Enable Interface. The AD8375 is enabled by applying a logic high voltage to
the PWUP pin. The device is disabled when the PU switch is set in the position
closest to the PU label, connecting the PWUP pin to ground. The device is
enabled when the PU switch is set in the opposite position, connecting the
PWUP to VPOS.

Parallel Interface Control. Used to hardwire A0 through A4 to the desired gain.
The bank of switches, WA4 to WA0, set the binary gain code. WA4 represents
the LSB. WA0 represents the MSB.

Voltage Reference. Input common-mode voltage ac-coupled to ground by

0.1 μF capacitor, C11.

C20 = 10 μF (size 3528)
C13, C14, C63, C64 = 0.1 μF

(size 0402)
R91 = 0 Ω (size 0402)

T1 = TC3-1+ (Mini-Circuits)
C1, C2, C60 = 0.1 μF (size 0402)
R2, R9, R10 = 0 Ω (size 0402)
R1, R70 to R72 = open (size 0402)

T3 = ETC1-1-13 (M/A-COM)
C7, C8, C62 = 0.1 μF (size 0402)
L1, L2 = 1 μH (size 0805)
R19, R20 = 61.9 Ω (size 0402)
R23, R25 = 30.9 Ω (size 0402)
R15, R16 = 0 Ω (size 0603)
R30 = 0 Ω (size 0402)
R24, R29, R62 = open (size 0402)
PU = installed
R13 = 0 Ω (size 0603)
C5 = open (size 0603)

WA0 to WA4 = instal led

C11 = 0.1 μF (size 0402)

Rev. 0 | Page 20 of 24

AD8375

06724-048

Figure 47. Component Side Silkscreen

Figure 49. Component Side Layout

06724-050

Figure 48. Circuit Side Silkscreen

06724-049

Rev. 0 | Page 21 of 24

Figure 50. Circuit Side Layout

06724-051

AD8375

OUTLINE DIMENSIONS

4.00

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING
PLANE

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

COMPLIANT TOJEDEC STANDARDS MO-220-VGGD-2

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARITY

0.08

Figure 51. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-24-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8375ACPZ-WP
AD8375ACPZ-R7
AD8375-EVALZ

1

Z = RoHS Compliant Part.

1

1

1

−40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Waffle Pack CP-24-1

−40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Reel CP-24-1
Evaluation Board

0.60 MAX

19

18

EXPOSED

(BOTTOM VIEW)

13

12

PAD

24

6

7

1

2.50 REF

PIN 1
INDICATOR

2.25

2.10 SQ

1.95

0.25 MIN

Rev. 0 | Page 22 of 24

AD8375

NOTES

Rev. 0 | Page 23 of 24

AD8375

NOTES

©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06724-0-8/07(0)

T

Rev. 0 | Page 24 of 24

TTT