Datasheet AD8367ARU-REEL-7, AD8367ARU-REEL, AD8367ARU, AD8367 Datasheet (Analog Devices)

500 MHz, Linear-in-dB VGA

a

FEATURES
Broad Range Analog Variable Gain

–2.5 dB to +42.5 dB
3 dB Cutoff Frequency of 500 MHz
Gain Up and Gain Down Modes
Linear-in-dB, Scaled 20 mV/dB
Resistive Ground Referenced Input

Nominal Z
On-Chip Square-Law Detector
Single-Supply Operation: 2.7 V to 5.5 V

APPLICATIONS
Cellular Base Station
Broadband Access
Power Amplifier Control Loops
Complete, Linear IF AGC Amplifiers
High-Speed Data I/O

GENERAL DESCRIPTION

The AD8367 is a high-performance 45 dB variable gain ampli­fier with linear-in-dB gain control for use from low frequencies
up to several hundred megahertz. The range, flatness, and accu­racy of the gain response are achieved using Analog Devices’

®

X-AMP

architecture, the most recent in a series of powerful
proprietary concepts for variable gain applications, which far
surpasses what can be achieved using competing techniques.

The input is applied to a 200 Ω resistive ladder network, having
nine sections each of 5 dB loss, for a total attenuation of 45 dB.
At maximum gain, the first tap is selected; at progressively lower
gains, the tap moves smoothly and continuously toward higher
attenuation values. The attenuator is followed by a 42.5 dB
fixed gain feedback amplifier—essentially an operational ampli­fier with a gain bandwidth product of 100 GHz—and is very
linear, even at high frequencies. The output third order intercept is
+20 dBV at 100 MHz (+27 dBm re 200 Ω), measured at an
output level of 1 V p-p with V

ⴝ 200 ⍀

IN

= 5 V.

S

with AGC Detector

AD8367

FUNCTIONAL BLOCK DIAGRAM

VPSOVPSI

ICOM

INPT

ICOM

CELLS

AD8367

9-STAGE ATTENUATOR BY 5dB

g

m

GAUSSIAN INTERPOLATOR

The analog gain-control interface is very simple to use. It is
scaled at 20 mV/dB, and the control voltage, V
50 mV at –2.5 dB to 950 mV at +42.5 dB. In the inverse-gain
mode of operation, selected by a simple pin-strap, the gain
decreases from +42.5 dB at V
V

= 950 mV. This inverse mode is needed in AGC applications,

GAIN

= 50 mV to –2.5 dB at

GAIN

which are supported by the integrated square-law detector,
whose set point is chosen to level the output to 354 mV rms,
regardless of the waveshape. A single external capacitor sets up
the loop averaging time.

The AD8367 may be powered on or off by a voltage applied to
the ENBL pin. When this voltage is at a logic LO, the total power
dissipation drops to the milliwatt range. For a logic HI, the chip
powers-up rapidly to its normal quiescent current of 26 mA at
25°C. The AD8367 is available in a 14-lead TSSOP package for
the industrial temperature range of –40°C to +85°C.

ENBL

BIAS

SQUARE

LAW

DETECTOR

DETOGAINMODE

, runs from

GAIN

ICOM

DECL

HPFL

VOUT

OCOM

X-AMP is a registered trademark of Analog Devices, Inc.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD8367–SPECIFICATIONS

(VS = 5 V, TA = 25ⴗC, System Impedance ZO = 200 ⍀, V
unless otherwise noted.)

= 5 V, f = 10 MHz,

MODE

Parameter Conditions Min Typ Max Unit

OVERALL FUNCTION

Frequency Range LF 500 MHz
GAIN Range 45 dB

INPUT STAGE Pins INPT and ICOM

Maximum Input To Avoid Input Overload 700 mV p-p
Input Resistance From INPT to ICOM 175 200 225 Ω

GAIN CONTROL INTERFACE Pin GAIN

Scaling Factor V

Gain Law Conformance 100 mV ≤ V
Maximum Gain V
Minimum Gain V
V

Step Response From 0 dB to 30 dB 300 ns

GAIN

= 5 V, 50 mV ≤ V

MODE

= 0 V, 50 mV ≤ V

V

MODE

= 0.95 V +42.5 dB

GAIN

= 0.05 V –2.5 dB

GAIN

≤ 900 mV ± 0.2 dB

GAIN

≤ 950 mV +20 mV/dB

GAIN

≤ 950 mV –20 mV/dB

GAIN

From 30 dB to 0 dB 300 ns

Small Signal Bandwidth V

= 0.5 V 5 MHz

GAIN

OUTPUT STAGE Pin VOUT

Max Output Voltage Swing RL = 1 kΩ 4.3 V p-p

R

= 200 Ω 3.5 V p-p
Output Source Resistance Series Resistance of Output Buffer 50 Ω
Output Centering Voltage

1

L

VS/2 V

SQUARE LAW DETECTOR Pin DETO

Output Set Point 354 mV rms
AGC Small Signal Response Time C

 100 pF, 6 dB Gain Step 1 s

AGC

POWER INTERFACE Pins VPSI, VPSO, ICOM, and OCOM

Supply Voltage 2.7 5.5 V
Total Supply Current ENBL High, Maximum Gain, R

 200 Ω 26 30 mA

L

(Includes Load Current)

Disable Current vs. Temperature ENBL Low 1.3 1.6 mA

–40°C ≤ TA ≤ +85°C 1.8 mA

MODE CONTROL INTERFACE Pin MODE

Mode LO Threshold Device in Negative Slope Mode of Operation 1.2 V
Mode HI Threshold Device in Positive Slope Mode of Operation 1.4 V

ENABLE INTERFACE Pin ENBL

Enable Threshold 2.5 V
Enable Response Time Time Delay Following LO to HI Transition 1.5 s

until Device Meets Full Specifications.

Enable Input Bias Current ENBL at 5 V 27 A

ENBL at 0 V 32 nA

–2–

REV. 0

AD8367

Parameter Conditions Min Typ Max Unit

f = 70 MHz

Gain Maximum Gain +42.5 dB

Minimum Gain –3.7 dB
Gain Scaling Factor 19.9 mV/dB
Gain Intercept –5.6 dB
Noise Figure Maximum Gain 6.2 dB
Output IP3 f1  70 MHz, f2  71 MHz, V

Output 1 dB Compression Point V

 0.5 V 8.5 dBm

GAIN

f = 140 MHz

Gain Maximum Gain +43.5 dB

Minimum Gain –3.6 dB
Gain Scaling Factor 19.7 mV/dB
Gain Intercept –5.3 dB
Noise Figure Maximum Gain 7.4 dB
Output IP3 f1  140 MHz, f2  141 MHz, V

Output 1 dB Compression Point V

 0.5 V 8.4 dBm

GAIN

f = 190 MHz

Gain Maximum Gain +43.5 dB

Minimum Gain –3.8 dB
Gain Scaling Factor 19.6 mV/dB
Gain Intercept –5.3 dB
Noise Figure Maximum Gain 7.5 dB
Output IP3 f1  190 MHz, f2  191 MHz, V

Output 1 dB Compression Point V

 0.5 V 8.4 dBm

GAIN

f = 240 MHz

Gain Maximum Gain +43 dB

Minimum Gain –4.1 dB
Gain Scaling Factor 19.7 mV/dB
Gain Intercept –5.2 dB
Noise Figure Maximum Gain 7.6 dB
Output IP3 f1  240 MHz, f2  241 MHz, V

Output 1 dB Compression Point V

NOTES

1

The output dc centering voltage is normally set at VS2 and can be adjusted by applying a voltage to DECL.

Specifications subject to change without notice.

 0.5 V 8.1 dBm

GAIN

 0.5 V 27.5 dBm

GAIN

20.5 dBV rms

1.5 dBV rms

 0.5 V 24.5 dBm

GAIN

17.5 dBV rms

1.4 dBV rms

 0.5 V 23.9 dBm

GAIN

16.9 dBV rms

1.4 dBV rms

 0.5 V 24.6 dBm

GAIN

17.6 dBV rms

1.1 dBV rms

REV. 0

–3–

AD8367

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage VPSO, VPSI . . . . . . . . . . . . . . . . . . . . . 5.5 V

ENBL Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V

MODE Select Voltage . . . . . . . . . . . . . . . . . . . . V

V

Control Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 V

GAIN

+ 200 mV

S

+ 200 mV

S

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 600 mV

Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 250 mW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W

θ

JA

Maximum Junction Temperature . . . . . . . . . . . . . . . . 125°C

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

PIN CONFIGURATION

ICOM

ENBL

INPT

MODE

GAIN

DETO

ICOM

1

2

3

AD8367

4

TOP VIEW

(Not to Scale)

5

6

7

14

13

12

11

10

9

8

ICOM

HPFL

VPSI

VPSO

VOUT

DECL

OCOM

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

1, 7, 14 ICOM Signal Common. Connect to low

impedance ground.

2 ENBL A HI activates the device.

3 INPT Signal Input. 200 Ω to ground.

4 MODE Gain Direction Control. HI for Positive

Slope; LO for Negative Slope.

5 GAIN Gain-Control Voltage Input

6 DETO Detector Output. Provides output cur-

rent for RSSI function and AGC control.

8 OCOM Power Common. Connect to low

impedance ground.

9 DECL Decoupling Pin. Can Be Used to

Modify the Output Reference Level.

10 VOUT Signal Output. Generally will be

ac-coupled.

11 VPSO Positive Supply Voltage. 2.7 V to 5.5 V.

VPSI and VPSO are tied together inter­nally with back-to-back PN junctions.
They should be tied together externally
and properly bypassed.

12 VPSI Positive Supply Voltage. 2.7 V to 5.5 V.

13 HPFL High-Pass Filter Connection. A capaci-

tor to ground sets the corner frequency
of the output offset control loop.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8367ARU –40°C to +85°C Tube, 14-Lead RU-14
AD8367ARU-REEL-7 –40°C to +85°C 7" Tape and Reel
AD8367-EVAL –40°C to +85°C Evaluation Board
AD8367ARU-REEL –40°C to +85°C 13" Tape and Reel

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8367 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–4–

REV. 0

50

FREQUENCY – MHz

10

4

70 25090

NOISE FIGURE – dB

110 130 150 170

190

210 230

9

8

7

6

5

+85 C

+25 C

–40

C

40

30

20

GAIN – dB

10

0

–10

10 1000100

Typical Performance Characteristics–AD8367

1V

0.9V

0.8V

0.7V

0.6V

0.5V

0.4V

0.3V

0.2V

0.1V

FREQUENCY – MHz

TPC 1. Gain vs. Frequency for Values of V

45

40

35

30

5

0

0 1.00.1

5

0

0 1.00.1

MODE ⴝ 5V

10MHz

70MHz
140MHz
240MHz

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

V

– V

GAIN

(Mode LO and Mode HI)

GAIN

V

– V

GAIN

25

20

GAIN – dB

15

10

–5

TPC 2. Gain vs. V

45

40

35

30

25

20

GAIN – dB

15

10

–5

TPC 3. Gain Conformance at 70 MHz for T  –40ⴗC,

ⴗ

C, and +85ⴗC.

+25

MODE ⴝ 0V
10MHz
70MHz
140MHz
240MHz

–40 C

+25 C

+85

GAIN

2.0

1.6

1.2

0.8

0.4

C

0

–0.4

–0.8

–1.2

–1.6

–2.0

LINEARITY ERROR – dB

TPC 4. NF (re 200 Ω) vs. Frequency at Maximum Gain

60

50

40

30

20

NOISE FIGURE – dB

10

0

0 1.00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

TPC 5. NF (re 200 ) vs. V

30

25

20

15

OIP3 – dBV rms

10

V

GAIN

– V

at 70 MHz

GAIN

10MHz

70MHz

140MHz

240MHz

37

32

27

22

17

5

0

0

0.1 0.2 0.4 0.6 0.7 0.8 0.9 1.0

0.3 0.5
V

– V

GAIN

TPC 6. OIP3 vs. V

GAIN

12

7

OIP3 – dBm (re 200⍀)

REV. 0

–5–

AD8367

30

25

20

15

OIP3 – dBV rms

10

5

0

10 1000100

FREQUENCY – MHz

TPC 7. OIP3 vs. Frequency for V

4

2

0

–2

GAIN

10MHz

140MHz

200MHz

 500 mV

70MHz

37

32

27

22

17

OIP3 – dBm (re 200⍀)

12

7

11

9

7

5

0

–10

–20

–30

–40

–50

OUTPUT IMD – dBc

–60

–70

–80

0 0.80.1 0.2 0.3 0.4 0.5 0.6 0.7 0.9

TPC 10. IMD3 vs. Gain (V

4

2

0

–2

70MHz

10MHz

V

– V

GAIN

 1 V p-p Composite)

OUT

240MHz

140MHz

11

9

7

5

–4

–6

OUTPUT 1dB COMPRESSION – dBV rms

–8

0 1.00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

V

GAIN

– V

TPC 8. Output P1dB vs. V

5

4

3

2

1

0

–1

–2

–3

OUTPUT 1dB COMPRESSION – dBV rms

–4

–5

10 1000100

FREQUENCY – MHz

GAIN

3

1

OUTPUT 1dB COMPRESSION – dBm (re 200⍀)

0

–4

–6

OUTPUT 1dB COMPRESSION – dBV rms

–8

2.5

3.0 3.5 4.0 4.5 5.0 5.5
VS – V

3

1

OUTPUT 1dB COMPRESSION – dBm (re 200⍀)

–1

TPC 11. Output Compression Point vs. Supply
Voltage at 70 MHz, V

12

11

10

9

8

7

6

5

4

3

OUTPUT 1dB COMPRESSION – dBm (re 200⍀)

2

25

20

15

10

OUTPUT IP3 – dBV rms

5

0

2.5

3.0 3.5 4.0 4.5 5.0 5.5

= 500 mV

GAIN

VS – V

32

27

22

17

OUTPUT IP3 – dBm (re 200⍀)

12

7

TPC 9. Output P1dB vs. Frequency at V

 500 mV

GAIN

TPC 12. Output Third Order Intercept vs. Supply
Voltage at 70 MHz, V

= 500 mV

GAIN

–6–

REV. 0

AD8367

250

200

150

100

RESISTANCE – ⍀

50

0

0 500100

200 300 400

FREQUENCY – MHz

0

–25

–47

–73

–95

–120

TPC 13. Input Resistance and Series Reactance vs.
Frequency at V

150

120

= 500 mV

GAIN

90

60

30

90

120

150

300mV

500mV

SERIES REACTANCE – ⍀

180

210

240

700mV

270

60

30

0

330

300

TPC 16. Output Reflection Coefficient vs. Frequency
from 10 MHz to 500 MHz for Multiple Values of V

0.5

0.4

V

GAIN

GAIN

180

210

240

300mV

500mV

700mV

300

270

TPC 14. Input Reflection Coefficient vs. Frequency
from 10 MHz to 500 MHz for Multiple Values of V

70

65

60

55

RESISTANCE – ⍀

50

45

40

0 500100

200 300 400

FREQUENCY – MHz

TPC 15. Output Resistance and Series Reactance vs.
Frequency at V

 500 mV

GAIN

REV. 0

330

20

15

10

–5

–10

0

GAIN

5

0

0.3

0.2

0.1

V – V

–0.1

–0.2

–0.3

0

V

OUT

TIME – 200ns/div

TPC 17. VGA Time Domain Response (3 dB Step)

25

20

10nF

15

GAIN – dB

10

SERIES REACTANCE – ⍀

5

0

0.1

1nF

10pF

100pF

NO CAP

1 10 100 1000 10000 100000

FREQUENCY – kHz

TPC 18. Gain vs. Frequency for Multiple Values of
HPFL Capacitor at V

GAIN

= 500 mV

–7–

AD8367

1.0

0.9

0.8

0.7

0.6

0.5

RSSI – V

0.4

0.3

0.2

0.1

0

70MHz

10MHz

–50 –40 –30 –20 –10

140MHz

240MHz

INPUT LEVEL – dBV rms

10MHz
70MHz
140MHz
240MHz

0–60

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

TPC 19. AGC RSSI (Voltage on DETO Pin) vs. Input
Power at 10 MHz, 70 MHz, 140 MHz, and 240 MHz

1.0

0.9

0.8

0.7

0.6

0.5

RSSI – V

0.4

0.3

0.2

0.1

0

–50 –40 –30 –20 –10

+85ⴗC

–40ⴗC

INPUT LEVEL – dBV rms

+25ⴗC

+25ⴗC
–40ⴗC
+85ⴗC

0–60

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

LINEARITY ERROR – dB

LINEARITY ERROR – dB

0.8

V

0.7

C

= 100pF

AGC

0.6

V – V

0.5

0.4

–2E–05 2E–05

–1E–05 0 1E–05

TIME – sec

AGC

V

OUT

TPC 22. AGC Time Domain Response (3 dB Step)

19.0097 19.7297 19.9097 20.0897 20.2697
GAIN SCALING – mV/dB

TPC 20. AGC RSSI (Voltage on DETO Pin) vs. Input
Power over Temperature at 70 MHz

16QAM

SINE

IS95FWD

2.5

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

1.0

0.9

0.8

0.7

0.6

0.5

RSSI – V

0.4

0.3

0.2

0.1

0

–50 –40 –30 –20 –10 10

–60

INPUT LEVEL – dBV rms

256QAM

WCDMA

64QAM

TPC 21. AGC RSSI (Voltage on DETO Pin) vs. Input
Power for Various Modulation Schemes

LINEARITY ERROR – dB

TPC 23. Gain Scaling Distribution at 70 MHz

–6.4 –6.0 –5.6 –5.2 –4.8–6.2 –5.8 –5.4 –5.0

INTERCEPT – dB

TPC 24. Gain Intercept Distribution at 70 MHz

–8–

REV. 0

AD8367

THEORY OF OPERATION

The AD8367 is a variable gain single-ended IF amplifier based
on Analog Devices’ patented X-AMP architecture. It offers
accurate gain control with a 45 dB span and a 3 dB bandwidth
of 500 MHz. It can be configured as a traditional VGA with
50 dB/V gain scaling or as an AGC amplifier by using the built­in rms detector. Figure 1 is a simplified block diagram of the
amplifier. The main signal path consists of a voltage-controlled
0 dB to 45 dB variable attenuator followed by a 42.5 dB fixed
gain amplifier. The AD8367 is designed to operate optimally in
a 200 Ω impedance system.

GAIN

INPT

GAIN INTERPOLATOR

gmgmg

200⍀

m

0dB –5dB –10dB –45dB

ATTENUATOR LADDER

INTEGRATOR

g

m

–42.5dB

V

OUT

OUTPUT
BUFFER

VOUT

Figure 1. The Simplified Architecture

Input Attenuator and Gain Control

The variable attenuator consists of a 200 Ω single-ended resis­tive ladder comprising nine 5 dB sections and an interpolator
that selects the attenuation factor. Each tap point down the
ladder network further attenuates the input signal by a fixed
decibel factor. Gain control is achieved by sensing different tap
points with variable transconductance stages. Based on the gain
control voltage, an interpolator selects which stage(s) are active.
For example, if only the first stage is active, the 0 dB tap point is
sensed; if the last stage is active, the 45 dB tap point is sensed.
Attenuation levels that fall between tap points are achieved by
having neighboring g

stages active simultaneously, creating a

m

weighted average of the discrete tap point attenuations. In this
way, a smooth, monotonic attenuation function is synthesized
that is linear-in-dB with a very precise scaling.

The gain of the AD8367 can be an increasing or decreasing
function of the control voltage, V

, depending on whether

GAIN

the MODE pin is pulled up to the positive supply or down to
ground. When the MODE pin is high, the gain increases with

as shown in Figure 2. The ideal linear-in-dB scaled trans-

V

GAIN

fer function is given by,

Gain (dB) =× −50 5V

where V

GAIN

GAIN

is expressed in volts. Equation 1 contains the

(1)

gain scaling factor of 50 dB/V (20 mV/dB) and the gain intercept
of –5 dB which represents the extrapolated gain for V
The gain ranges from –2.5 dB to 42.5 dB for V

GAIN

=0V.

GAIN

ranging from
50 mV to 950 mV. The deviation from (1), that is, the gain
conformance error, is also illustrated in Figure 2. The ripples in
the error are a result of the interpolation action between tap points.
The AD8367 provides better than ±0.5 dB of conformance error
over >40 dB gain range at 200 MHz and ±1 dB at 400 MHz.

44

40

36

32

28

24

20

16

GAIN – dB

12

8

4

0

–4

0 1.00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

LO MODE

HI MODE

V

GAIN

50dB/V

SLOPE

– V

GAIN

2.0

1.6

1.2

0.8

0.4

0

–0.4

–0.8

–1.2

–1.6

–2.0

–2.4

LINEARITY ERROR – dB

Figure 2. The gain function can be either an increas­ing or decreasing function of V

depending on the

GAIN

MODE pin.

The gain is a decreasing function of V

when the MODE pin

GAIN

is low. Figure 2 also illustrates this mode which is described by

Gain (dB) =−×45 50 V

GAIN

(2)

This gain mode is required in AGC applications using the built­in square-law level detector.

Input and Output Interfaces

The AD8367 was designed to operate best in a 200 Ω impedance
system. Its gain range, conformance law, noise and distortion
assume that 200 Ω source and load impedances are used. Interfacing
the AD8367 to other common impedances (from 50 Ω used at
radio frequencies to 1 kΩ presented by data-converters) can be
accomplished using resistive or reactive passive networks, whose
design depends on specific system requirements such as bandwidth,
return loss, noise figure and absolute gain range.

The input impedance of the AD8367 is nominally 200 Ω, deter­mined by the resistive ladder network. This presents a 200 Ω dc
resistance to ground, and in cases where an elevated signal poten­tial is used, ac coupling is necessary. The input signal level must
not exceed 700 mV p-p to avoid overloading the input stage. The
output impedance is determined by an internal 50 Ω damping
resistor, as shown in the simplified schematic in Figure 3.

V

FROM

INTEGRATOR

B1

V

B2

50⍀

V

OUT

Figure 3. A 50Ω Resistor is Added to the Output to
Prevent Package Resonance

REV. 0

–9–

AD8367

Power and Voltage Metrics

Although power is the traditional metric used in the analysis of
cascaded systems, most active circuit blocks fundamentally
respond to voltage. The relationship between power and voltage
is defined by the impedance level. When input and output imped­ance levels are the same, power gain and voltage gain are identical.
However, when impedance levels change between input and
output, they differ. Thus, one must be very careful to use the
appropriate gain for system chain analyses. Quantities such as
OIP3 are quoted in dBV rms as well as dBm referenced to 200 Ω.

Output Centering

The output level is centered midway between ground and the
supply if the DECL pin is left floating. Alternatively, the out­put level may be set by driving the DECL pin with the desired
reference level. As shown in Figure 5, the loop acts to suppress
deviations from the reference at outputs below its corner
frequency while not affecting signals above it. The maximum
corner frequency with no external capacitor is 500 kHz. The
corner frequency can be lowered arbitrarily by adding an exter-

nal capacitor, C
The dBV rms unit is defined as decibels relative to 1 V rms. In a
200 Ω environment, the conversion from dBV rms to dBm requires
the addition of 7 dB to the dBV rms value. For example, a
+2 dBV rms level corresponds to +9 dBm.

Noise and Distortion

Since the AD8367 consists of a passive variable attenuator

A capacitor at pin DECL is recommended to decouple the

reference level to which the output is centered.

followed by a fixed gain amplifier, the noise and distortion
characteristics as a function of the gain voltage are easily pre­dicted. The input-referred noise increases in proportion to the
attenuation level. Figure 4 shows noise figure, NF, as a func­tion of V

for the MODE pin pulled high. The minimum

GAIN

NF of 7.5 dB occurs at maximum gain and increases 1 dB for
every 1 dB reduction in gain. In receiver applications, the
minimum NF should occur at the maximum gain where the
received signal presumably is weak. At higher levels, a lower
gain is needed, and the increased NF becomes less important.

f

HP

(kHz)

FROM
INPUT

HP

=

:

C

HP

C

HP

10

(nF)+ .

002

g

m

HPFL

MAIN

AMPLIFIER

DECL

(3)

VOUT

V

MID

ⴝ 1

A

V

60

50

NF

40

30

20

IIP3

10

IIP3 – dBV

0

–10

–20

–30

0 1.00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

V

GAIN

– V

60

50

40

30

20

10

0

–10

–20

–30

NF – dB

Figure 4. Noise Figure and Input Third Order Inter­cept vs. Gain (R

SOURCE

 200 Ω)

The input-referred distortion varies in a similar manner to the
noise. Figure 4 illustrates how the third-order intercept point at
the input, IIP3, behaves as a function of V

. The highest IIP3

GAIN

of 20 dBV rms (27 dBm re 200 Ω) occurs at minimum gain. The
IIP3 then decreases 1 dB for every 1 dB increase in gain. At lower
levels, a degraded IIP3 is acceptable. Overall, the dynamic range,
represented by the difference between IIP3 and NF, remains
reasonably constant as a function of gain. The output distortion
and compression are essentially independent of the gain. At low
gains, when the input level is high, input overload may occur,
causing premature distortion.

Figure 5. The dc output level is centered to mid
supply by a control loop whose corner frequency is
determined by CHP.

RMS Detection

The AD8367 contains a square-law detector that senses the output

signal and compares it to a calibrated set-point of 354 mV rms

which corresponds to a 1 V p-p sine wave. Any difference between

the output and set-point generates a current which is integrated by

an external capacitor, C

, connected from the DETO pin to

AGC

ground, to provide an AGC control voltage. There is also an

internal 5 pF capacitor on the DETO pin.

The resulting voltage is used as an AGC bias. For this appli-

cation, the MODE pin is pulled low and the DETO pin is

tied to the GAIN pin. The output signal level is then regu-

lated to 354 mV rms. The AGC bias represents a calibrated

rms measure of the received signal strength (RSSI). Since in

the AGC mode the output signal is forced to the 354 mV rms

set-point (–9.02 dBV rms), Equation 2 can be recast to

express the strength of the received signal, V

of the AGC bias V

VV

IN RMS DETO−

DETO

,

=− + ×(dBV rms) 54 02 50.

IN-RMS

, in terms

(4)

where –54.02 dBV rms  –45 dB  9.02 dBV rms.

For small changes in input signal level, V

characteristic single-pole time constant, τ

tional to C

τµ

,

AGC

AGC AGC

C( s) (nF)=×10

responds with a

DETO

, which is propor-

AGC

(5)

where the internal 5 pF capacitor has been lumped with the

external capacitor to give C

AGC

.

–10–

REV. 0

AD8367

APPLICATIONS

The AD8367 can be configured either as a variable-gain amplifier
whose gain is controlled externally through the GAIN pin or as an
AGC amplifier, using a supply voltage of 2.7 V to 5.5 V. The
supply to the VPSO and VPSI pins should be decoupled using a
low-inductance 0.1 F surface-mount ceramic capacitor, as close
to the device as possible. Additional supply decoupling may be
provided by a small series resistor. A 10 nF capacitor from pin
DECL to OCOM is recommended to decouple the output refer­ence voltage.

Input and Output Matching

The AD8367 is designed to operate in a 200 Ω impedance sys­tem. The output amplifier is a low output impedance voltage
buffer with a 50 Ω damping resistor to desensitize it from load
reactance and parasitics. The quoted performance includes the
voltage division between the 50 Ω resistor and the 200 Ω load.
The AD8367 can be reactively matched to an impedance other
than 200 Ω using traditional step-up and step down matching
networks or high quality transformers. Table I lists the 50 Ω
S-parameters for the AD8367 at a V

 750 mV.

GAIN

Figure 6 illustrates an example where the AD8367 is matched to
50 Ω at 140 MHz. As shown in the Smith Chart, the input match­ing network shifts the input impedance from Z

to 50 Ω with an

IN

insertion loss of less than 2 dB over a 5 MHz bandwidth. For the
output network, the 50 Ω load is made to present 200 Ω to the
AD8367 output. Table II provides the component values required
for 50 Ω matching at several frequencies of interest.

In situations where added loss and noise can be tolerated, a
resistive pad can be used to provide broad-band near-matched
impedances at the device terminals and the terminations.
Minimum-loss L-pad networks are used on the evaluation board
(see Figure 19) to allow easy interfacing to standard 50 Ω test
equipment. Each pad introduces an 11.5 dB power loss
(5.5 dB voltage loss).

1

3

Z

IN

–3

XS

C

AC

0.1␮F

13pF

Z

LOAD

XP

OUT

150nH

R

SOURCE

0.3333

–0.3333

f

ⴝ 140MHz, ZIN ⴝ 193.4 ⴚ j46.3⍀, Z

C

ⴝ 50⍀, R

R

SOURCE

XS

IN

120nH

XP

IN

50⍀

V

5pF

S

Z

IN

R

SOURCE

0.3333 1 3

LOAD

SERIES L

–1

ⴝ 50⍀

SHUNT C

ⴝ 229 ⴚ j8.8⍀

LOAD

AD8367

Z

IN

Z

OUT

Figure 6. Reactive Matching Example for f  140 MHz

OUT

R

LOAD

50⍀

REV. 0

Table I. S-Parameters for 50 Ω System for VS= 5 V, and V

GAIN

= 0.75 V

Frequency (MHz) S11 S21 S12 S22

−3

10 0.64⬔0° 8.5⬔177° 2 × 10

70 0.64⬔–1.5° 9.0⬔168° 5 × 10

140 0.63⬔–3.0° 10.0⬔152° 9 × 10

190 0.63⬔–3.7° 10.4⬔138° 9 × 10

⬔153° 0.02⬔11°

−4

⬔106° 0.02⬔54°

−4

⬔80° 0.06⬔88°

−4

⬔147° 0.09⬔83°

240 0.62⬔–4.9° 10.8⬔125° 1 × 10−3⬔148° 0.1⬔76°

Table II. Reactive Matching Components for a 50 Ω System, RS = 50 Ω, R

Frequency (MHz) XS

IN

XP

(pF) XS

IN

(pF) XP

OUT

LOAD

OUT

10 1.5 H 120 180 1.8 H

70 220 nH 15 27 270 nH

140 120 nH 7 13 150 nH

190 82 nH 4 10 100 nH

240 68 nH 3 7 82 nH

–11–

= 50 Ω

AD8367

VGA Operation

The AD8367 is a general-purpose VGA suitable for use in a
wide variety of applications where voltage-control of gain is
needed. While having a 500 MHz bandwidth, its use is not
limited to high frequency signal processing. Its accurate, tem­perature- and supply-stable linear-in-dB scaling will be valuable
wherever it is important to have a more dependable response to
the control voltage than is usually offered by VGAs of this sort.
For example, there is no preclusion to its use in speech-band­width systems.

Figure 7 shows the basic connections. The capacitor C

at Pin

HP

HPFL may be used to alter the high-pass corner frequency of
the signal path, and is associated with the offset control loop that
eliminates the inherent variation in the internal dc balance of the
signal path as the gain is varied (“offset ripple”). This frequency
should be chosen to be about a decade below the lowest frequency
component of the signal. If made much lower than necessary,
the offset loop will not be able to track the variations that occur
when there are rapid changes in V

. The control of offset is

GAIN

important even when the output is ac-coupled because of the poten­tial reduction of the upper and lower voltage range at this pin.

However, in many applications these components will be unnec­essary, since an internal network provides a default high-pass
corner of about 500 kHz. For C

 1 nF, the modified corner

HP

is at ~10 kHz; it scales downward with increasing capacitance.
TPC 18 shows representative response curves for the indicated
component values.

V

C1

1␮F

ICOM

1

2

ENBL

V

IN

V

GAIN

3

4

5

6

7

INPT

MODE

GAIN

DETO

ICOM

AD8367

ICOM

HPFL

VPSI

VPSO

VOUT

DECL

OCOM

14

13

12

11

10

9

8

C

HP

C4, 0.1␮F

C5
10nF

, 0.1␮F

VOUT

C2

0.1␮F

R6

4.7⍀

R5

4.7⍀
C3

0.1␮F

P

AGC Operation

The AD8367 may be used as an AGC amplifier as shown in
Figure 8. For this application, the accurate internal square-law
detector is employed. The output of this detector is a current
that varies in polarity depending on whether the rms value of the
output is greater or less than its internally-determined “set-point”
of 354 mV rms. This is 1 V p-p for sine-wave signals, but the peak
amplitude for other signals, such as Gaussian noise, or those carry­ing complex modulation, will invariably be somewhat greater.
However, for all waveforms having a crest factor of less than 5,
and when using a supply voltage of 4.5 V to 5.5 V, the rms value
will be correctly measured and delivered at V
lower supplies, the rms value of V

is unaffected (the set-

OUT

. When using

OUT

point is determined by a band-gap reference) but the peak crest
factor capacity is reduced.

The output of the detector is delivered to Pin DETO. The detector
can source up to 60 µA and can sink up to 11 µA. For a sine-wave
output signal, and under conditions where the AGC loop is settled,
the detector output also takes the form of a sine-wave, but at twice
the frequency and having a mean value of zero. If the input to the
amplifier increases the mean of this current also increases, and
charges the external loop filter capacitor C
voltages. Conversely, a reduction in V

toward more positive

AGC

below the set-point of

OUT

354 mV rms causes this voltage to fall toward ground. The capacitor
voltage is the AGC bias; this may be used as an RSSI (Received
Signal Strength Indicator) output, and is scaled exactly as V

GAIN

,

that is, 20 mV/dB.

V

C1

1␮F

ICOM

1

2

ENBL

V

IN

V

AGC

C

AGC

0.1␮F

3

4

5

6

7

INPT

MODE

GAIN

DETO

ICOM

AD8367

ICOM

HPFL

VPSI

VPSO

VOUT

DECL

OCOM

14

13

12

11

10

9

8

C

HP

C4, 0.1␮F

C5
10nF

, 10nF

VOUT

C2

0.1␮F

R6

4.7⍀

R5

4.7⍀
C3

0.1␮F

P

Figure 7. Basic Connections for Voltage-Controlled
Gain Mode

Modulated Gain Mode

The AD8367 may be used as a means of modulating the signal
level. It should be kept in mind, however, that the gain is a
nonlinear (exponential) function of V

; thus it is not suitable

GAIN

for normal amplitude-modulation functions. The small-signal
bandwidth of the gain interface is ~5 MHz and the slew-rate is
of the order of ± 500 dB/s. During gain slewing from close to
minimum to maximum gain (or vice versa) the internal interpo­lation processes in an X-AMP-based VGA rapidly scan the full
range of gain values. The gain and offset ripple associated with
this process may cause transient disturbances in the output.
Therefore, it is inadvisable to use high-amplitude pulse drives
with rise and fall times below 200 ns.

–12–

Figure 8. Basic Connections for AGC Operation

A valuable feature of using a square law detector is that the
RSSI voltage is a true reflection of signal power, and may be
converted to an absolute power measurement for any given
source impedance. The AD8367 may thus be employed as a
true-power meter, or decibel-reading ac voltmeter, as distinct
from its basic amplifier function.

The AGC mode of operation requires that the correct gain direc­tion is chosen. Specifically, the gain must fall as V

increases to

AGC

restore the needed balance against the set-point. Therefore, the
MODE pin must be pulled low. This accurate leveling function is
shown in Figure 9, where the rms output is held to within 0.1 dB
of the set point for >35 dB range of input levels.

The dynamics of this loop are controlled by C
conjunction with an on-chip equivalent resistance R
which form an effective time-constant T

AGC

AGC

 R

acting in

of 10 kΩ

AGC

AGC CAGC

. The

loop thus operates as a single-pole system with a loop bandwidth
of 1/(2 T

). Because the gain control function is linear in

AGC

decibels, this bandwidth is independent of absolute signal level.
Figure 10 illustrates the loop dynamics for a 30 dB change in
input signal level with C

 100 pF.

AGC

REV. 0

AD8367

–1.2

–1.3

–1.4

–1.5

–1.6

–1.7

–1.8

–1.9

POUT – dBm (re 200⍀)

–2.0

–2.1

–2.2

–50 10–40

–30 –20 –10 0

PIN – dBm (re 200⍀)

Figure 9. Leveling Accuracy of the AGC Function

– arb

OUT

– V; V

AGC

V

–0.4

1.0

0.8

0.6

0.4

0.2

–0.2

–0.6

0

0405

10 15 20 25 30 35

V

OUT

TIME – ␮s

V

AGC

Figure 10. AGC Response to a 32 dB Step in Input



Level (f

It is important to understand that R
with C

50 MHz)

does not act as if in shunt

. Rather, the error-correction process is that of a true

AGC

AGC

integrator, to guarantee an output that is exactly equal in rms
amplitude to the specified set-point. For large changes in input
level, the integrating action of this loop will be most apparent.
The slew rate of V

is determined by the peak output current

AGC

from the detector and the capacitor. Thus, for a representative
value of C

 3 nF, this rate is about 20 V rms or 10 dB/s,

AGC

while the small-signal bandwidth is 1 kHz.

Most AGC loops incorporating a true error-integrating technique
have a common weakness. When driven from an increasingly
larger signal, the AGC bias increases to reduce the gain. But
eventually, the gain will fall to its minimum value, for which
further increase in this bias will have no effect on the gain. That
is, the voltage on the loop capacitor will be forced progressively
higher because the detector output is a current, and the AGC
bias is its integral. Consequently there will always be a precipi­tous increase in this bias voltage when the input to the AD8367
exceeds that value which overdrives the detector, and because
the minimum gain is –2.5 dB, that will happen for all inputs
+2.5 dB greater than the set-point of ~350 mV rms. If possible,
the user should ensure that this limitation is preserved, prefer­ably with a guard-band of 5 dB to 10 dB below overload.

In some cases, it may be found that, if driven into AGC over­load, the AD8367 will require unusually long times to recover;
that is, the voltage at DETO will remain at an abnormally high
value and the gain will be at its lowest value. To avoid this situa­tion, it is recommended that a clamp be placed on the DETO
pin as shown in Figure 11.

RB

0.5V

RA

1

AD8367

2

AGC

3

4

5

6

7

MODE

GAIN

DETO

ICOM

+V

S

V

Q1
2N2907

C

AGC

0.1␮F

14

13

12

11

10

9

8

Figure 11. External Clamp to Prevent AGC Overload.
The resistive divider network, RA and RB, should be
designed such that the base of Q1 is driven to 0.5 V.

Modifying the AGC Set Point

If an AGC set point other than the internal one is desired, an
external detector may be used. Figure 12 depicts a method that uses
an external true-rms detector and error integrator to operate the
AD8367 as a closed-loop AGC system with a user-settable
operating level.

The AD8361 (U2) produces a dc output level which is proportional
to the rms value of its input, taken as a sample of the AD8367 (U1)
output. This dc voltage is compared to an externally-supplied set­point voltage, and the difference is integrated by the AD820 (U3)
to form the gain control voltage which is applied to the GAIN
input of the AD8367 through the divider composed of R4 and R5.
This divider is included in order to minimize overload recovery
time of the loop by having the integrator saturate at a point that
only slightly overdrives the gain control input of the AD8367. The
scale factor at V

is influenced by the values of R4 and R5; for

AGC

the values shown, the factor is 86 mV/dB. Note that in this circuit
the AD8367’s MODE pin must be pulled high to obtain correct
feedback polarity because the integrator inverts the polarity of the
feedback signal.

The relationship between set-point voltage and the rms output
voltage of the AD8367 is as follows:

+

VV

OUT RMS SET−

=×

()R1.225

×

225 7 5

(6)

where 225 is the input resistance of the AD8361 and 7.5 is its
conversion gain. For R1  200 Ω, this reduces to V

V

 0.25.

SET

OUT –RMS



Capacitor C2 sets the averaging time for the rms detector. This
should be made long enough to provide sufficient smoothing of the
detector’s output in the presence of the modulation on the RF
signal. A level fluctuation of less than 1 dB (<5% to 10%) p-p at the
AD8361’s output is a reasonable value. A considerably longer
time-constant will needlessly lower the AGC bandwidth, while a
short time-constant can degrade the accuracy of the true-rms
measurement process. Components C1, R2, and R3 set the control
loop’s bandwidth and stability. The maximum stable loop bandwidth
will be limited by the rms detector’s averaging time constant as
discussed above.

REV. 0

–13–

AD8367

RF INPUT

10nF

10nF

1

VPOS

R1

2

20pF

3

4

IREF

RFIN

PWDN

200⍀

R3
82k⍀

2

V

SET

3

66⍀

ICOM

1

2

10nF

R6

Vg

R5

10k⍀

3

4

5

6

7

ENBL

INPT

MODE

GAIN

DET0

ICOM

AD8367

U1

R4

33k⍀

ICOM

HPFL

VPSI

VPSO

VOUT

DECL

OCOM

14

13

0.1␮F

12

11

10

9

8

AD820

V

AGC

C5

0.1␮F

6

0.1␮F

10nF

C1

3.3nF

U3

5V

4

7

Figure 12. Example of Using an External Detector to Form an AGC Loop

5V
V

INTO A

OUT

200⍀ LOAD

AD8361

U2

R2

150k⍀

SREF

VRMS

FLTR

COMM

8

7

6

5

12k⍀

C2

0.27␮F

Vrms

For an input signal consisting of a 4.096 MS/s QPSK modulated
carrier, the relationship between V

and the output power for

SET

this setup is shown in Figure 13. The exponential shape reflects
the linear-in-magnitude response of the AD8361. The adjacent
channel power ratio (ACPR) as a function of output power is
illustrated in Figure 14. The minima occur where the distortion
and integrated noise powers cross over.

The component values shown in Figure 12 were chosen for a
64-QAM signal at 500 kS/s at a carrier frequency of 150 MHz.
The response time of the loop as shown is roughly 5 ms for an
abrupt input level change of 40 dB. Figure 15 shows the dynamic
performance of the loop with a step-modulated CW signal applied
to the input for a V

4.0

3.5

3.0

2.5

– V

2.0

SET

V

1.5

1.0

0.5

0

–20 10–15 –10 –50 5

of about 1 V.

SET

POUT – dBm Into 200⍀

10MHz

380MHz

Figure 13. AGC Set-Point Voltage vs. Output Power
(QPSK: 4.096 MS/s;



0.22; 1 User)

–20

–25

–30

–35

–40

ACP R – dBc

–45

–50

–55

–60

–20 10–15 –10 –50 5

380MHz

POUT – dBm Into 200⍀

140MHz

10MHz

70MHz

Figure 14. ACPR versus Output Power for QPSK



OUT

TIME – sec

0.22; 1 User)

V

g

Waveform (4.096 MS/s;

1.0

0.5

0.0

– arb

OUT

Vg – V; V

–0.5

–1.0

–1.5

–2.0

0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040

0

V

–14–

Figure 15. AGC Dynamic Response: 8367 AGC with
an External Detector

REV. 0

R7

SW2

10k⍀

1

2

3

4

5

6

7

AD8367

ICOM

ENBL

INPT

MODE

GAIN

DETO

ICOM

INPUT

TP3

MODE

J1

R1

57.6⍀

174⍀

GAIN

R2

TP4

SW1

LK1

C

AGC

0.1␮F

Figure 16. Evaluation Board Schematic

Table III. Suggested Component Values For External AGC
Detector Circuit

Rate C1 C2 R2 R3

Modulation Type Sym/s ␮F ␮Fk⍀ k⍀

QPSK 1.23 M 0.0022 0.033 150 62

QPSK 4 M 0.0022 0.015 150 39

π/4 DQPSK 24.3 K 0.033 0.68 150 51

64 QAM 100 K 0.015 1.5 150 51

64 QAM 500 K 0.0068 0.33 150 62

64 QAM 4 M 0.0022 0.068 150 100

ICOM

HPFL

VPSI

VPSO

VOUT

DECL

OCOM

14

13

CHP, 10nF

12

11

10

9

8

RHP, 0⍀

C5
10nF

C1

1␮F

R4

174⍀

C2

0.1␮F

R6

4.7⍀

C4

0.1␮F

TP1

R5

4.7⍀
C3

0.1␮F

V

P

R3

57.6⍀

AD8367

J2

OUTPUT

Evaluation Board

Figure 16 shows the schematic of the AD8367 evaluation board.
The board is powered by a single supply of 2.7 V to 5.5 V. Table
IV details the various configuration options of the evaluation board.

Figure 17. Layout of Component Side

Figure 18. Silkscreen of Component Side

Characterization Setup and Methods

Minimum-loss L-pad matching networks were used to interface
standard 50 Ω test equipment to the 200 Ω input impedance during
the characterization process. Using a 57.6 Ω shunt resistor followed
by a 174 Ω series resistor provides a broadband match between the
50 Ω test equipment and the 200 Ω device impedance as illustrated
in Figure 19. The insertion loss of this network is 11.5 dB.

AD8367

174⍀

57.6⍀

174⍀

57.6⍀

Figure 19. Characterization Test Setup

REV. 0

–15–

AD8367

Table IV. Evaluation Board Configuration Options

Component Function Default Condition

TP1, TP2 Supply and Ground Vector Pins Not Applicable

TP3, TP4 Mode and Gain Vector Pins Not Applicable

SW1 VGA/AGC Select: Used to select VGA (position A) or AGC SW1  A

(position B) mode of operation. SW2 must be set for position A for
AGC mode of operation.

SW2 MODE Select: Used to select positive or negative VGA slope. SW2  B

Set to position B for an increasing gain with V
decreasing gain law.

LK1 Device Enable: When LK1 is installed, the ENBL pin is connected SW3  PWUP

to the positive supply and the AD8367 is in operating mode.

R1, R2 Input Interface: R1 and R2 are used to provide an L-pad impedance- R1  57.6 Ω (Size 0603)

transforming network. The broadband matching network transforms R2  174 Ω (Size 0603)
a 50  source to match a 200 Ω load with 11.5 dB of insertion loss.

R3, R4, C4 Output Interface: R3 and R4 are used to transform a 50 Ω load ter- R3  57.6 Ω (Size 0603)

mination to look like a 200 Ω load with 11.5 dB of insertion loss. R4  174 Ω (Size 0603)
The AC coupling capacitor, C4, can be increased to obtain a lower C4  0.1 F (Size 0603)
high-pass corner frequency.

C1, C2, C3, R5, R6 Power Supply Decoupling: The nominal supply decoupling consists C1  1 F (Size 0603)

of a 1 F capacitor to ground, a 4.7 Ω series resistor, and a 0.1 FR5  R6  4.7 Ω (Size 0805)
capacitor to ground. The same de-coupling network should be used on C2  C3  0.1 F (Size 0603)
both VPSI and VPSO supply lines.

C5 Internal Supply Decoupling: Capacitor C5 provides mid-supply C5  10 nF (Size 0603)

decoupling.

C

C

HPFL

AGC

Filter Capacitor: HPFL capacitor, sets the high pass corner frequency. C

AGC Filter Capacitor: Capacitor, C

, sets closed loop AGC C

AGC

response time.

R7 Mode Pullup Resistor R7  10 kΩ (Size 0805)

, position A for

GAIN

 0.1 F (Size 0805)

HPFL

R

 0 Ω (Size 0603)

HP

= 0.1 F (Size 0805)

AGC

C02710–.8–10/01(0)

PIN 1

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

14-Lead (TSSOP)

(RU-14)

0.201 (5.10)

0.193 (4.90)

14

0.0256
(0.65)

BSC

8

0.177 (4.50)

0.169 (4.30)

71

0.0433 (1.10)
MAX

0.0118 (0.30)

0.0075 (0.19)

0.256 (6.50)

0.246 (6.25)

0.0079 (0.20)

0.0035 (0.090)

8ⴗ
0ⴗ

–16–

PRINTED IN U.S.A.

0.028 (0.70)

0.020 (0.50)

REV. 0