Datasheet AD8347ARU-REEL7, AD8347ARU-REEL, AD8347ARU, AD8347 Datasheet (Analog Devices)

0.8 GHz–2.7 GHz

a

Direct Conversion Quadrature Demodulator

FEATURES
Integrated RF and Baseband AGC Amplifiers
Quadrature Phase Accuracy 1ⴗ Typ
I/Q Amplitude Balance 0.3 dB Typ
Third Order Intercept (IIP3) +11.5 dBm @ Min Gain
Noise Figure 11 dB @ Max Gain
AGC Range 69.5 dB
Baseband Level Control Circuit
Low LO Drive –8 dBm
ADC Compatible I/Q Outputs
Single Supply 2.7 V–5.5 V
Power-Down Mode
Package 28-Lead TSSOP

APPLICATIONS
Cellular Basestations
Radio Links
Wireless Local Loop
IF Broadband Demodulator
RF Instrumentation
Satellite Modems

AD8347

FUNCTIONAL BLOCK DIAGRAM

LOIN

VPS1

IOPN
IOPP

VCMO

IAIN

COM3

IMXO

COM2

RFIN
RFIP

VPS2

IOFS

VREF

1
2
3
4
5
6
7
8

9
10
11
12
13
14

AD8347

SPLITTER

SPLITTER

BIAS

PHASE

PHASE

DET

GAIN

CONTROL

LOIP

28

COM1

27
26

QOPN

25

QOPP

24

QAIN

23

COM3

22

QMXO

21

VPS3

20

VDT1

19

VAGC

18

VDT2

17

VGIN

16

QOFS

15

ENBL

*

GENERAL DESCRIPTION

The AD8347 is a broadband Direct Quadrature Demodulator
with RF and baseband Automatic Gain Control (AGC) amplifiers.
It is suitable for use in many communications receivers,
performing Quadrature demodulation directly to baseband
frequencies. The input frequency range is 800 MHz to 2.7 GHz.
The outputs can be connected directly to popular A-to-D converters
such as the AD9201 and AD9283.

The RF input signal goes through two stages of variable gain
amplifiers prior to two Gilbert-cell Mixers. The LO quadrature
phase splitter employs polyphase filters to achieve high quadra­ture accuracy and amplitude balance over the entire operating
frequency range. Separate I & Q channel variable-gain amplifiers
follow the baseband outputs of the mixers. The RF and baseband

*U.S. Patents Issued and Pending

amplifiers together provide 69.5 dB of gain control. A precision
control circuit sets the Linear-in-dB RF gain response to the gain
control voltage.

Baseband level detectors are included for use in an AGC loop to
maintain the output level. The demodulator dc offsets are
minimized by an internal loop, whose time constant is controlled
by external capacitor values. The offset control can also be
overridden by forcing an external voltage at the offset nulling pins.

The baseband variable gain amplifier outputs are brought off-chip
for filtering before final amplification. By inserting a channel
selection filter before each output amplifier high-level out-of­channel interferers can be eliminated. Additional internal circuitry
also allows the user to set the dc common-mode level at the
baseband outputs.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD8347–SPECIFICATIONS

(VS = 5 V; TA = 25ⴗC; FLO = 1.9 GHz; V
R

= 10 k⍀, dBm with respect to 50 ⍀, unless otherwise noted.)

LOAD

= 1 V; FRF = 1.905 GHz; PLO = –8 dBm,

VCMO

Parameter Conditions Min Typ Max Unit

OPERATING CONDITIONS

LO/RF Frequency Range 0.8 2.7 GHz
LO Input Level –10 0 dBm
VGIN Input Level 0.2 1.2 V
V

SUPPLY (VS

) 2.7 5.5 V

Temperature Range –40 +85 °C

RF AMPLIFIER/DEMODULATOR From RFIP/RFIN to IMXO and QMXO

(IMXO/QMXO Load >1 kΩ)

AGC Gain Range 69.5 dB
Conversion Gain (Max) V
Conversion Gain (Min) V
Gain Linearity V
Gain Flatness F
Input P1 dB V

Third Order Input Intercept (IIP3) F

= 0.2 V (Max Gain) 39.5 dB

VGIN

= 1.2 V (Min Gain) –30 dB

VGIN

= 0.3 V to 1 V ±2dB

VGIN

= 0.8 GHz – 2.7 GHz, F

LO

= 0.2 V –30 dBm

VGIN

V

= 1.2 V –2 dBm

VGIN

= 1.905 GHz, +11.5 dBm

RF1

F

= 1.906 GHz, –10 dBm Each Tone,

RF2

= 1 MHz 0.7 dB p-p

BB

(Min Gain)

Second Order Input Intercept (IIP2) F

= 1.905 GHz, +25.5 dBm

RF1

F

= 1.906 GHz, –10 dBm Each Tone,

RF2

(Min Gain)
LO Leakage (RF) At RFIP –60 dBm
LO Leakage (MXO) At IMXO/QMXO –42 dBm
Demodulation Bandwidth –3 dB 90 MHz
Quadrature Phase Error F
I/Q Amplitude Imbalance F

= 1.9 GHz –3 ±1 +3 Degree

RF

= 1.9 GHz 0.3 dB

RF

Noise Figure Max Gain 11 dB
Mixer AGC Output Level See TPC 30 24 mV p-p
Baseband DC Offset At IMXO/QMXO, Max Gain 2 mV

(Corrected, Ref to VREF)
Mixer Output Swing Level at which IMD3 = 45 dBc

= 200 Ω 65 mV p-p

R

LOAD

R

= 1 kΩ 65 mV p-p

LOAD

Mixer Output Impedance 3 Ω

BASEBAND OUTPUT AMPLIFIER From IAIN to IOPP/IOPN and

QAIN to QOPP/QOPN

R

= 10 kΩ

LOAD

Gain 30 dB
Bandwidth –3 dB (See TPC 18) 65 MHz

– V

Output DC Offset (Differential) (V
Common-Mode Offset (V

IOPP

IOPP

) –200 ±50 +200 mV

IOPN

+ V

IOPN

)/2 – V

VCMO

–40 ±5 +40 mV

Group Delay Flatness 0 MHz–50 MHz 1.8 ns p-p
Second Order Intermod. Distortion F

Third Order Intermod. Distortion F

1 = 5 MHz, FIN2 = 6 MHz, –49 dBc

IN

1 = VIN2 = 8 mV p-p

V

IN

1 = 5 MHz, FIN2 = 6 MHz, –67 dBc

IN

V

1 = VIN2 = 8 mV p-p

IN

Input Bias Current 2 µA
Input Impedance 1储3MΩ储pF

Output Swing Limit (Upper) V

– 1.3 V

S

Output Swing Limit (Lower) 0.4 V

–2–

REV. 0

AD8347

Parameter Conditions Min Typ Max Unit

CONTROL INPUT/OUTPUTS

VCMO Input @ VS = 2.7 V 1 V

= 5 V 0.5 1 2.5 V

@ V

Gain Control Input Bias Current VGIN <1 µA
Offset Input Overriding Current IOFS, QOFS 10 µA

VREF Output R

RESPONSE FROM RF INPUT TO IMXO/QMXO Connected Directly to
FINAL BB AMP IAIN/QAIN Respectively

Gain @ V
Gain @ V

= 0.2 V 65.5 69.5 72.5 dB

VGIN

= 1.2 V –3 +0.5 +4 dB

VGIN

Gain Slope –96.5 –89 –82.5 dB/V
Gain Intercept Linear extrapolation back to 88 94 101 dB

LO/RF INPUT (See TPC 26 Through 29 for More Detail)

LOIP Input Return Loss Measuring LOIP LOIN, ac-coupled to –4 dB

RFIP Input Return Loss RFIP Input Pin –10 dB

ENABLE

Power-Up Control Low = Standby 0 0.5 V
Power-Up Control High = Enabled +V
Power-Up Time Time for Final BB Amps to be Within

Power-Down Time Time for Supply Current to be <4 mA

POWER SUPPLIES V

Voltage 2.7 5.5 V
Current (Enabled) @ 5 V 48 64 80 mA

Current (Standby) @ 5 V 400 µA
Current (Standby) @ 3.3 V 80 µA

Specifications subject to change without notice.

S

= 10 kΩ 0.95 1.00 1.05 V

LOAD

theoretical value at VGIN = 0

Ground with 100 pF.
Measuring Through Evaluation Board
Balun with Termination –9.5 dB

– 1 +V

S

S

V

90% of Final Amplitude

= 5 V 20 µs

@ V

S

= 2.7 V 10 µs

@ V

S

@ V

= 5 V 30 µs

S

@ VS = 2.7 V 1.5 ms

, V

PS2

, V

PS3

PS1

REV. 0

–3–

AD8347

ABSOLUTE MAXIMUM RATINGS

Supply Voltage V

PS1

, V

PS2

, V

PS3

*

. . . . . . . . . . . . . . . . . . . 5.5 V

LO and RF Input Power . . . . . . . . . . . . . . . . . . . . . . 10 dBm

Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 500 mW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W

␪

JA

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering 60 sec) . . . . . . . . . . . . . 300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8347ARU –40°C to +85°C Tube (28-Lead TSSOP) Thin RU-28

AD8347ARU-REEL 13" Tape and Reel
AD8347ARU-REEL7 7" Tape and Reel
AD8347-EVAL Evaluation Board

PIN CONFIGURATION

1

LOIN

2

VPS1

3

IOPN

4

IOPP

5

VCMO

6

IAIN

COM3

IMXO

COM2

RFIN
RFIP

VPS2

IOFS

VREF

7
8

9
10
11
12
13
14

AD8347

TOP VIEW

(Not to Scale)

Shrink Small Outline Package

LOIP

28

COM1

27
26

QOPN

25

QOPP

24

QAIN

23

COM3

22

QMXO

21

VPS3

20

VDT1

19

VAGC

18

VDT2

17

VGIN

16

QOFS

15

ENBL

VPS3

DET 1

VREF

VREF

DET 2

VDT2 QMXO QOPPQOFSVAGCVDT1 QAIN

VREF

PHASE

SPLITTER

VREF

IAIN

2

VCMO

IOPPIOFS IOPN

PHASE

SPLITTER

1

VCMO

QOPN

ENBL

RFIN

RFIP

VGIN

VPS2 IMXO

VPS1

AD8347

BIAS
CELL

GAIN

CONTROL

INTERFACE

Figure 1. Block Diagram

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8347 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

VCMO

LOIN

LOIP

COM3
COM2
COM3
COM1

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. 0

AD8347

PIN FUNCTION DESCRIPTIONS

Pin Equiv.
No. Mnemonic Cir. Description

1, 28 LOIN, LOIP A LO Input. For optimum performance, these inputs should be driven differentially. Typical input

drive level is equal to –8 dBm. To improve the match to a 50 Ω source, connect a 200 Ω shunt

resistor between LOIP and LOIN. A single-ended drive is also possible but this will slightly
increase LO leakage.

2 VPS1 Positive Supply for LO Section. This pin should be decoupled with 0.1 µF and 100 pF capacitors.

3, 4 IOPN, IOPP B

5 VCMO C Baseband Amplifier Common-Mode Voltage. The voltage applied to this pin sets the output

6 IAIN D I Channel Baseband Amplifier Input. This pin, which has a high input impedance, should be

7, 23 COM3 Ground for Biasing and Baseband Sections
8, 22 IMXO, QMXO B I & Q Channel Baseband Mixer/VGA Outputs. These are low impedance outputs whose bias

9 COM2 RF Section Ground
10, 11 RFIN, RFIP E RF Input. RFIN must be ac-coupled to ground. The RF input signal should be ac-coupled into

12 VPS2 Positive Supply for RF Section. This pin should be decoupled with 0.1 µF and 100 pF capacitors.

13, 16 IOFS, QOFS F I Channel and Q Channel Offset Nulling Inputs. To null the dc-offset on the I Channel and

14 VREF G Reference Voltage Output. This output voltage (1 V) is the main bias level for the device and

15 ENBL H Chip Enable Input. Active high.
17 VGIN C Gain Control Input. The voltage on this pin controls the gain on the RF and baseband VGAs.

18, 20 VDT2, VDT1 D Detector Inputs. These pin are the inputs to the on-board detector. VDT2 and VDT1, which

19 VAGC I AGC Output. This pin provides the output voltage from the on-board detector. In AGC mode,

21 VPS3 Positive Supply for Biasing and Baseband Sections. This pin should be decoupled with 0.1 µF

24 QAIN D Q Channel Baseband Amplifier Input. This pin, which has a high input impedance, should be

25, 26 QOPP, QOPN B Q Channel Differential Baseband Output. Typical output swing is equal to 1 V p-p differential.

27 COM1 LO Section Ground

I Channel Differential Baseband Output. Typical output swing is equal to 760 mV p-p differential
in AGC mode

common-mode level of the baseband amplifiers. This pin can either be connected to VREF
(Pin 14) or to a reference voltage from another device (typically an ADC).

biased to VREF (approximately 1 V). If IAIN is connected directly to IMXO, biasing will be
provided by IMXO. If an ac-coupled filter is placed between IMXO and IAIN, this pin can be

biased from VREF through a 1 kΩ resistor. The gain from IAIN to the differential outputs

IOPN/IOPP is 30 dB.

levels are equal to VREF. IMXO and QMXO are typically connected to IAIN and QAIN
respectively, either directly or through filters. These outputs have a maximum current limit of

about 1.5 mA. This allows for a 600 mV p-p swing into a 200 Ω load. This corresponds to an

input level of –40 dBm @ max gain of 39.5 dB. At lower output levels, IMXO and QMXO, can
drive a lower load resistance, subject to the same current limit.

RFIP. For a broadband 50 Ω input impedance, connect a 200 Ω resistor from the signal side of

RFIP’s coupling capacitor to ground. Please note that RFIN and RFIP are not interchangeable
differential inputs. RFIN is the ground reference for the input system.

Q Channel Mixer Outputs (IMXO, QMXO), connect a 0.1 µF capacitor from these pins to

ground. Alternately, a forced voltage of approximately 1 V on these pins will disable the offset
compensation circuit.

can be used to externally bias the inputs and outputs of the baseband amplifiers.

The gain control is applied in parallel to all VGAs. The gain control voltage range is from 0.2 V
to 1.2 V and corresponds to a gain range from +39.5 dB to –30 dB. This is the gain to the output
of the baseband VGAs (i.e., QMXO and IMXO). There is an additional 30 dB of gain in the
baseband amplifiers. Note that the gain control function has a negative sense (i.e., increasing
control voltage decreases gain). In AGC mode, this pin is connected directly to VAGC.

have high input impedances, are normally connected to IMXO and QMXO respectively.

this pin is connected directly to VGIN.

and 100 pF capacitors.

biased to VREF (approximately 1 V). If QAIN is connected directly to QMXO, biasing will be
provided by QMXO. If an ac-coupled filter is placed between QMXO and QAIN, this pin can

be biased from VREF through a 1 kΩ resistor. The gain from QAIN to the differential outputs

QOPN/QOPP is 30 dB.

The common-mode level on these pins is programmed by the voltage on VCMO.

. The common mode level on these pins is programmed by the voltage on VCMO.

REV. 0

–5–

AD8347

VPS3

VAGC

COM3

EQUIVALENT CIRCUITS

LOIN

LOIP

VPS1

COM1

IAIN

QAIN

VPS3

Circuit A

PHASE

SPLITTER

CONTINUES

RFIP

RFIN

VPS2

COM3

Circuit B

VPS3

IOPP, IOPN,
QOPP, QOPN,
IMXO, QMXO

VCMO

IOFS

QOFS

VPS3

CURRENT MIRROR

COM3

Circuit C

VPS3

CURRENT MIRROR

Circuit D

COM3

Circuit G

COM3

VPS3

VREF

COM2

Circuit E

VPS3

ENBL

COM3

Circuit H

Figure 2. Equivalent Circuits

COM3

Circuit F

Circuit I

–6–

REV. 0

RF AMP AND DEMODULATOR



BASEBAND FREQUENCY – MHz

1

GAIN – dB

100

30

31

32

33

34

35

36

37

38

10

39

40

41

42

VS = 5V,
TA = +25ⴗC

VS = 2.7V, TA = –40ⴗC

VS = 2.7V, TA = +25ⴗC

VS = 5V, TA = –40ⴗC

VS = 2.7V, T

A

= +85ⴗC

VS = 5V, TA = +85ⴗC

Typical Performance Characteristics–

AD8347

45
40
35
30
25
20
15
10

–5

MIXER GAIN – dB
–10

–15

–20

–25

–30

–35

TA = –40ⴗC

TA = +85ⴗC

TA = +25ⴗC

5
0

TA = +25ⴗC

TA = +85ⴗC

0.2

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
V

– V

GIN

TPC 1. Gain and Linearity Error vs. V

= 1900 MHz, FBB = 1 MHz

F

LO

45

MIXER GAIN – dB

–10
–15
–20
–25
–30
–35

40
35
30
25
20
15

10

5
0

–5

0.2

TA = –40ⴗC

TA = +85ⴗC

TA = –40ⴗC

TA = +25ⴗC

TA = +85ⴗC

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

TA = +25ⴗC

V

– V

GIN

TPC 2. Gain and Linearity Error vs. V
F

= 1900 MHz, FBB = 1 MHz

LO

TA = –40ⴗC

, VS = 5 V,

GIN

, VS = 2.7 V,

GIN

14
12
10
8
6
4
2
0
–2
–4
–6
–8
–10
–12

14
12
10
8
6
4
2
0

–2
–4
–6
–8
–10

LINEARITY ERROR – dB

LINEARITY ERROR – dB

3.0



2.5

2.0

1.5
VS = 2.7V, TA = –40ⴗC

1.0

GAIN – dB

0.5

VS = 5V, TA = –40ⴗC

0

–0.5

–1.0

800

1000 1200 1400 1600 1800 2000 2200

TPC 4. Gain vs. FLO, V

–27



–28

VS = 2.7V, TA = +25ⴗC

–29
–30

–31

–32

GAIN – dB

–33

VS = 5V, TA = +85ⴗC

–34
–35
–36

–37

800

1000 1200 1400 1600 1800 2000 2200

TPC 5. Gain vs. FLO, V

VS = 2.7V, TA = +25ⴗC

VS = 5V,
T

RF FREQUENCY – MHz

VS = 5V,
T

VS = 5V, TA = –40ⴗC

RF FREQUENCY – MHz

= +25ⴗC

A

VS = 5V, TA = +85ⴗC

VS = 2.7V, TA = +85ⴗC

2400 2600

= 0.7 V, FBB = 1 MHz

GIN

= +25ⴗC

A

GIN

VS = 2.7V, TA = –40ⴗC

VS = 2.7V, TA = +85ⴗC

2400 2600

= 1.2 V, FBB = 1 MHz

REV. 0

40



39

VS = 2.7V, TA = –40ⴗC

38

37
36

VS = 2.7V, TA = +85ⴗC

35

GAIN – dB

34

33

32
31

30

800

1000 1200 1400 1600 1800 2000 2200

VS = 2.7V, TA = +25ⴗC

VS = 5V, TA = +85ⴗC

RF FREQUENCY – MHz

TPC 3. Gain vs. FLO, V

VS = 5V,

= +25ⴗC

T

A

VS = 5V, TA = –40ⴗC

2400 2600

= 0.2 V , FBB = 1 MHz

GIN

–7–

TPC 6. Gain vs. FBB, V

= 0.2 V, FLO = 1900 MHz

GIN

AD8347

10



9
8
7
6
5
4
3
2

GAIN – dB

1
0

–1
–2
–3
–4
–5

1

VS = 2.7V, TA = +25ⴗC

VS = 5V, TA = –40ⴗC

VS = 5V, TA = +85ⴗC

VS = 2.7V, TA = –40ⴗC

BASEBAND FREQUENCY – MHz

TPC 7. Gain vs. FBB, V

–25



–26

–27

VS = 5V,

–28

= +25ⴗC

T

A

–29

–30

GAIN – dB

–31

–32

VS = 2.7V,

–33

TA = +85ⴗC

–34

–35

1

BASEBAND FREQUENCY – MHz

TPC 8. Gain vs. FBB, V

VS = 2.7V, TA = +85ⴗC

VS = 5V,

= +25ⴗC

T

A

10

= 0.7 V, FLO = 1900 MHz

GIN

VS = 2.7V, TA = –40ⴗC

VS = 2.7V,

= +25ⴗC

T

A

VS = 5V,

= –40ⴗC

T

A

VS = 5V, TA = +85ⴗC

10

= 1.2 V, FLO = 1900 MHz

GIN

100

100

15

VS = 2.7V,





14

= +85ⴗC

T

A

13
12

11

10

VS = 2.7V, TA = +25ⴗC

IIP3 – dBm

9

8
7

6

5

800 2400 26001000 1200 1400 1600 1800 2000 2200

TPC 10. IIP3 vs. FLO, V

–10





–12

VS = 5V, TA = +25ⴗC

–14

–16

–18
–20

IIP3 – dBm

–22
–24

V

= 5V, TA = –40ⴗC

S

–26

–28

–30

800 2400 26001000 1200 1400 1600 1800 2000 2200

TPC 11. IIP3 vs. FLO, V

VS = 5V, TA = +85ⴗC

VS = 5V, TA = +25ⴗC

VS = 2.7V, TA = –40ⴗC

VS = 5V, TA = –40ⴗC

RF FREQUENCY – MHz

VS = 2.7V,
T

A

VS = 2.7V, TA = –40ⴗC

VS = 5V, TA = +85ⴗC

RF FREQUENCY – MHz

= 1.2 V, FBB = 1 MHz

GIN

= +85ⴗC

= 0.2 V, FBB = 1 MHz,

GIN

VS = 2.7V,
T

= +25ⴗC

A

0



–5

–10

–15

–20

INPUT P1dB – dBm

–25

–30

–35

0.20

VS = 5V,

= –40ⴗC

T

A

VS = 2.7V, TA = –40ⴗC

0.30

VS = 2.7V, TA = +85ⴗC

= 5V,

V

S

= +85ⴗC

T

A

VS = 2.7V,

= +25ⴗC

T

A

VS = 5V,

= +25ⴗC

T

A

1.20

V

– V

GIN

1.101.000.900.800.700.600.500.40

TPC 9. Input 1 dB Compression Point (OP1 dB) vs. V

= 1900 MHz, FBB = 1 MHz

F

LO

GIN

15



VS = 2.7V, TA = –40ⴗC

14

VS = 5V, TA = +85ⴗC

13

IIP3 – dBm

12

11

VS = 2.7V,
TA = +25ⴗC

10

0 100510

,

TPC 12. IIP3 vs. FBB, V

VS = 5V, TA = –40ⴗC

15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95

BASEBAND FREQUENCY – MHz

–8–

VS = 2.7V, TA = +85ⴗC

VS = 5V, TA = +25ⴗC

= 1.2 V, FLO = 1900 MHz

GIN

REV. 0

–10



V

GIN

– V

NOISE FIGURE – dB

0.2

40

10

30

20

50

60

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

70

–30

–25

–20

–15

–10

–5

0

5

10

15

VS = 2.7V

VS = 5V

VS =2.7V

VS = 5V

0

IIP3



–12
–14

VS = 5V, TA = +85ⴗC

–16
–18
–20
–22
–24

IIP3 – dBm

–26
–28

VS = 2.7V,

–30

T

–32
–34

0 100510

VS = 2.7V, TA = +85ⴗC

VS = 5V, TA = +25ⴗC

= –40ⴗC

A

15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95

BASEBAND FREQUENCY – MHz

TPC 13. IIP3 vs. FBB, V

VS = 5V, TA = –40ⴗC

VS = 2.7V,
T

= +25ⴗC

A

= 0.2 V, FLO = 1900 MHz

GIN

TPC 16. Noise Figure and IIP3 vs. V

ⴗ

Temperature = 25

C, FLO = 1900 MHz, FBB = 1 MHz

AD8347

,

GIN

50





45

40

35

IIP2 – dBm

30

25

20

800

1000 1200 1400 1600 1800 2000 2200 2400 2600

TPC 14. IIP2 vs. FLO, V
Tone1 = 5 MHz, –10 dBm, Baseband Tone2 = 6 MHz,
–10 dBm, Temperature = 25ⴗC, VS = 5 V

13.0





12.5

12.0

11.5

11.0

NOISE FIGURE – dB

10.5

REV. 0

10.0
800

1000 1200 1400 1600 1800 2000 2200 2400 2600

TPC 15. Noise Figure vs. LO Frequency (FLO),
Temperature = 25

RF FREQUENCY – MHz

= 1.2 V, Baseband

GIN

VS = 5V

V

= 2.7V

S

LO FREQUENCY – MHz

ⴗ

C, V

= 0.2 V, FBB = 1 MHz

GIN

–9–

2.5



2.0

1.5

1.0

0.5

0

–0.5

–1.0

LO FREQUENCY = 800MHz

–1.5

–2.0

QUADRATURE PHASE ERROR – Degrees

–2.5

–20

–18 –16 –14 –12 –10 –8 –6 –4

LO FREQUENCY = 2700MHz

LO FREQUENCY = 1900MHz

–20

LO INPUT LEVEL – dBm

TPC 17a. Quadrature Error vs. LO Power Level,

ⴗ

C,

V

Temperature = 25

14.0



13.5

13.0

12.5

12.0

11.5

11.0

NOISE FIGURE – dB

10.5

10.0

9.5

9.0

–20

–18 –16 –14 –12 –10 –8 –6 –4

2700MHz

1900MHz

LO INPUT LEVEL – dBm

= 0.2 V, VS = 5 V

GIN

800MHz

–20

TPC 17b. Noise Figure vs. LO Input Level,
Temperature = 25

ⴗ

C, V

= 0.2 V, VS = 5 V

GIN

AD8347

BASEBAND OUTPUT AMPLIFIERS

34

TA = –40ⴗC, V

32

30

28

TA = +85ⴗC, VS = 2.7V

26

24

GAIN – dB

22

20

18

16

1 10010

= 5V

S

TA = +25ⴗC, VS = 5V

BASEBAND FREQUENCY – MHz

TPC 18. Gain vs. FBB, V

5

TA = –40ⴗC, VS = 5V

0

–5

–10

OP1 – dBV rms

–15

–20

–25

1 10010

TA = –40ⴗC, VS = 2.7V

TA = +25ⴗC, VS = 2.7V

TA = +85ⴗC, VS = 2.7V

BASEBAND FREQUENCY – MHz

TPC 19. OP1 vs. FBB, V

TA = –40ⴗC, VS = 2.7V

TA = +25ⴗC, VS = 2.7V

TA = +85ⴗC, VS = 5V

= 1 V

VCMO

TA = +85ⴗC, VS = 5V

TA = +25ⴗC,

= 5V

V

S

= 1 V

VCMO

20

15

10

5
0

–5

–10

–15

–20

–25

BASEBAND AMPLIFIER OUTPUT IP3 – dBV rms

–30

–2

COMMON-MODE OFFSET – mV

–4

–6

VS = 5V, TA = –40ⴗC





VS = 2.7V, TA = +25ⴗC

VS = 2.7V,
T

1

= +85ⴗC

A

VS = 2.7V, TA = –40ⴗC

BASEBAND FREQUENCY – MHz

TPC 20. OIP3 vs. FBB, V

8





VS = 2.7V, MEAN + ␴

6

4

2

0

VS = 2.7V, MEAN – ␴

0.5 3.52.0

VS = 2.7V, MEAN

VS = 5V, MEAN

1.0 1.5 2.5 3.0
V

VCMO

VS = 5V, TA = 25ⴗC

10

VCMO

VS = 5V, MEAN – ␴

– V

VS = 5V,
T

= 1 V

= +85ⴗC

A

VS = 5V,
MEAN + ␴

100

TPC 21. Common-Mode Output Offset Voltage vs. V

ⴗ

Temperature = 25

C (␴ = 1 Standard Deviation)

VCMO

,

–10–

REV. 0



BASEBAND FREQUENCY – MHz

I TO Q AMPLITUDE MISMATCH – dB

0

–0.2

–0.8

–0.4
–0.6

0

0.2

5 10152025303540

0.4

–1.0

0.6

0.8

1.0

TA = +25ⴗC

TA = –40ⴗC

TA = +85ⴗC

RF AMP/DEMOD AND BASEBAND OUTPUT AMPLIFIERS

AD8347

75





65

55

VS = 2.7V,

= +85ⴗC

T

45

A

35

25

VOLTAGE GAIN – dB

15

5

–5

0.2 0.80.5

0.3 0.4 0.6 0.7

VS = 5V, TA = +85ⴗC

VS = 2.7V, TA = –40ⴗC

= 5V, TA = –40ⴗC

V

S

V

= 2.7V, TA = +25ⴗC

S

V

= 5V, TA = +25ⴗC

S

V

GIN

TPC 22. Voltage Gain vs. V

= 1 MHz

F

BB

2.5



2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

QUADRATURE PHASE ERROR – Degrees

–2.0

–2.5

800

VS = 5V, TA = +25ⴗC

VS = 5V, TA = +85ⴗC

1000 1200 1400 1600 1800 2000 2200

RF FREQUENCY – MHz

– V

0.9 1.0 1.1 1.2

, FLO = 1900 MHz,

VGIN

VS = 5V, TA = –40ⴗC

2400 2600

TPC 25. I/Q Amplitude Imbalance vs. FBB,

ⴗ

Temperature = 25

0

C, VS = 5 V



–2

–4

–6

–8

RETURN LOSS – dBm

–10

–12

RF WITH TERMINATION

RF WITHOUT TERMINATION

1000 1200 1400 1600 1800 2000 2200

800

RF FREQUENCY – MHz

2400 2600

TPC 23. Quadrature Phase Error vs. FLO, V
V

= 5 V

S

2.5



2.0

1.5

1.0

0.5

QUADRATURE PHASE ERROR – Degrees

–0.5

–1.0
–1.5

–2.0

–2.5

0

0

5 10152025303540

TA = +85ⴗC

TA = –40ⴗC

BASEBAND FREQUENCY – MHz

TPC 24. Quadrature Phase Error vs. FBB, V
V

= 5 V

S

REV. 0

TA = +25ⴗC

VGIN

VGIN

= 0.7 V,

= 0.7 V,

TPC 26. Return Loss of RFIP vs. FRF, V

2.7GHz

2.7GHz

WITH TERMINATION

800MHz

WITHOUT TERMINATION

TPC 27. S11 of RFIN vs. FRF, V

–11–

VGIN

800MHz

= 0.7 V, VS = 5 V

VGIN

= 0.7 V, VS = 5 V

AD8347

0



–2

–4

–6

–8

RETURN LOSS – dBm

–10

–12

–14

800

TPC 28. Return Loss of LOIP vs. FLO, V

LO PORT WITHOUT TERMINATION

LO PORT WITH TERMINATION

1000 1200 1400 1600 1800 2000 2200

RF FREQUENCY – MHz

WITH TERMINATION

800MHz

2.7GHz

WITHOUT TERMINATION

2.7GHz

800MHz

2400 2600

= 0.7 V, VP = 5 V

VGIN

30



25

20

15

10

5

MIXER OUTPUT VOLTAGE – mV p-p

0

–70

TA = +85ⴗC

TA = –40ⴗC

TA = +25ⴗC

TA = +85ⴗC

TA = +25ⴗC

TA = –40ⴗC

–60 –50 –40 –30 –20 –10 0 10

RF INPUT POWER – dBm

1.20

1.00

0.80

0.60

0.40

0.20

0

TPC 30. AGC Voltage and Mixer Output Level vs. RF Input
Power, F

= 1900 MHz, F

LO

85

= 1 MHz, VS = 5 V

BB



80

75

70

VP = 5.5V

65

60

SUPPLY CURRENT – mA

55

50

45

–40

VP = 2.7V

–30 –20 –100 102030

VP = 5V

VP = 3V

TEMPERATURE – ⴗC

40 50

60 70 80

AGC VOLTAG E – V

TPC 29. S11 of LOIN vs. FLO, V

= 0.7 V, VS = 5 V

VGIN

TPC 31. Supply Current vs. Temperature, V

= 1 V

V

VCMO

VGIN

= 0.7 V,

–12–

REV. 0

VPS3

VPS2 IMXO

VPS1

VREF

IAIN

AD8347

IOPPIOFS IOPN

AD8347

ENBL

RFIN

RFIP

VGIN

BIAS

CELL

GAIN

CONTROL

INTERFACE

DET 1

VREF

DET 2

VDT2 QMXO QOPPQOFSVAGCVDT1 QAIN

Figure 3. Block Diagram

CIRCUIT DESCRIPTION
OVERVIEW

The AD8347 is a direct I/Q demodulator usable in digital
wireless communication systems including Cellular, PCS, and
Digital Video receivers. An RF signal in the frequency range of
800 MHz–2700 MHz is directly downconverted to the I & Q
components at baseband using a Local Oscillator (LO) signal at
the same frequency as the RF signal.

The RF input signal goes through two stages of variable gain
amplifiers before splitting up to reach two Gilbert-cell Mixers.
The mixers are driven by a pair of Local Oscillator (LO)
signals which are in quadrature (90 degrees of phase difference).
The outputs of the mixers are applied to baseband I & Q channel
variable-gain amplifiers. The outputs from these baseband
variable
filtering.
fixed-gain
outputs from the external filters
A-to-D Converters.

gain amplifiers are brought out to pins for external

The filter outputs are then applied to a pair of on-chip,
baseband amplifiers. These amplifiers gain up the

to a level compatible with most

A sum-of-squares detector is available for
use in an Automatic Gain Control (AGC) loop to set the output
level. The RF and baseband amplifiers provide approximately

69.5 dB of gain control range. Additional on-chip circuits allow
the setting of the dc level at the I & Q channel baseband out­puts, as well as nulling the dc offset at each channel.

RF Variable Gain Amplifiers (VGA)

These amplifiers use the patented X-AMP approach with NPN­differential pairs separated by sections of resistive attenuators.
The gain control is achieved through a gaussian interpolator
where the control voltage sets the tail currents to be supplied to
the different differential pairs according to the gain desired. In
the first amplifier, the combined output currents from the trans­conductance cells go through a cascode stage to resistive loads
with inductive peaking. In the second amplifier the differential
currents are split and fed to the two Gilbert-cell mixers through
separate cascode stages.

Mixers

Two double balanced Gilbert-cell mixers, one for each channel,
perform the In-phase (I) and Quadrature (Q) down conversion.
Each mixer has four cross-connected transistor pairs which are

X-AMP is a registered trademark of Analog Devices, Inc.

REV. 0

–13–

VREF

VCMO

LOIN

LOIP

COM3
COM2
COM3
COM1

PHASE

SPLITTER

VREF

2

VCMO

PHASE

SPLITTER

1

VCMO

QOPN

terminated in resistive loads and feed the differential baseband
variable gain amplifiers for each channel. The bases of the mixer
transistors are driven by the quadrature LO signals.

Baseband Variable Gain Amplifiers

The baseband VGA’s also use the X-AMP approach with NPN­differential pairs separated by sections of resistive attenuators.
The same interpolator controlling the RF amplifiers controls the
tail currents of the differential pairs. The outputs of these ampli­fiers are provided off chip for external filtering. Automatic offset
nulling minimizes the dc offsets at both I & Q channels. The
common-mode output voltage is set to be the same as the reference
voltage (1.0 V) generated in the Bias section, also made available
at the VREF pin.

Output Amplifiers

The output amplifiers gain up the signal coming back from each
of the external filters to a level compatible with most high speed
A-to-D converters. These amplifiers are based on an active-feedback
design to achieve the high gain bandwidth and low distortion.

LO and Phase-Splitters

The incoming LO signal is applied to a polyphase phase-splitter
to generate the LO signals for the I channel and Q channel
mixers. The polyphase phase-splitters are RC networks con­nected in a cyclical manner to achieve gain balance and phase
quadrature. The wide operating frequency range of these phase­splitters is achieved by cascading multiple sections of these
networks with staggered RC constants. Each branch goes through
a buffer to make up for the loss and high frequency roll-off. The
output from the buffers then go into another polyphase phase­splitter to enhance the accuracy of phase quadrature. Each LO
signal gets buffered again to drive the mixers.

Output Level Detector

Two signals proportional to the square of each output channel
are summed together and compared to a built-in threshold to
create an AGC voltage (VAGC). The inputs to this rms detector
are referenced to VREF.

Bias

An accurate reference circuit generates the reference currents
used by the different sections. The reference circuit is controlled
by an external power-up (ENBL) logic signal which, when set
low, puts the whole chip into a sleep mode typically requiring

AD8347

less than
of 1.0 V,
baseband circuits, is made available for external use.

400 µA of supply current. The reference voltage (VREF)

which serves as the common-mode reference for the

RF Input and Matching

The RF input signal should be ac-coupled into the RFIP pin and
RFIN should be ac-coupled to ground. To improve broadband

matching to a 50 Ω source, a 200 Ω resistor may be connected

OPERATING THE AD8347
Basic Connections

Figure 4 shows the basic connections for operating the AD8347.
The device is powered through three power supply pins: VPS1,
VPS2, and VPS3. These pins supply current to different parts of
the overall circuit. VPS1 and VPS2 power the Local Oscillator (LO)
and RF sections, respectively, while VPS3 powers the baseband
amplifiers. While all of these pins should be connected to the same
supply voltage, each pin should be separately decoupled

using two

capacitors. 100 pF and 0.1 µF are recommended (values close

to these may also be used).

A supply voltage in the range 2.7 V to 5.5 V should be used. The
quiescent current is 64 mA when operating from a 5 V supply.
By pulling the ENBL pin low, the device goes into its power- down

mode. The power-down current is 400 µA when operating on a
5 V supply and 80 µA on a 2.7 V supply.

Like the supply pins, the individual sections of the circuit are
separately grounded. COM1, COM2, and COM3 provide ground
for the LO, RF, and baseband sections respectively. All of these

from the signal side of RFIP’s coupling capacitor to ground.

LO Drive Interface

For optimum performance the LO inputs, LOIN and LOIP,
should be driven differentially. M/A-COM balun, ETC1-1-13
is recommended. Unless an (ac-coupled) transformer is being
used to generate the differential LO, the inputs must be ac-coupled

as shown. To improve broadband matching to a 50 Ω source, a
200 Ω shunt resistor may be connected between LOIP and LOIN.

An LO drive level of –8 dBm is recommended. TPC 17a shows
the relationship between LO drive level, LO frequency, and
quadrature error for a typical device.

A single-ended drive is also possible as shown in Figure 5, but
this will slightly increase LO leakage. The LO signal should be
applied through a coupling capacitor to LOIP, and LOIN should
be ac-coupled to ground. Because the inputs are fully differen­tial, the drive orientation can be reversed. As in the case of the

differential drive, a 200 Ω resistor connected across LOIP and
LOIN improves the match to a 50 Ω source.

pins should be connected to the same low impedance ground.

RF INPUT

0.8GHz–2.7GHz
0dBm MAX

(AGC MODE)

C1

100pF

R1
200⍀

100pF

+V

S

(2.7V–5.5V)

C9

C6

0.1␮F

C5

100pF

VPS1

C7

0.1␮F

C8

100pF

VPS2

0.1␮F

C10

100pF

VPS3

VREF

IMXO

AD8347

BIAS

ENBL

RFIN

RFIP

C2

VGIN

CELL

GAIN

CONTROL

INTERFACE

DET 1

VAGCVDT1

VREF

DET 2

VDT2

QMXO QOPP

C15

0.1␮F

24mV p-p

(AGC MODE)

1V BIAS (VREF)

C13

0.1␮F

IOFS

VREF

SPLITTER

VREF

QOFS

C14

0.1␮F

24mV p-p

(AGC MODE)

1V BIAS (VREF)

IAIN

PHASE

2

VCMO

QAIN

IOPP

PHASE

SPLITTER

VCMO

1

IOPN

QOPN

VCMO

LOIN

LOIP

COM3
COM2
COM3
COM1

C4

100pF

R17

200⍀

C3

100pF

ETC 1-1-13
(M/A-COM)

IOPP

760mV p-p
DIFFERENTIAL
(AGC MODE)

= 1V

V

CM

IOPN

LO INPUT

–8dBm

0.8GHz–2.7GHz

3

4

15

T1

QOPN

760mV p-p
DIFFERENTIAL
(AGC MODE)

= 1V

V

CM

Figure 4. Basic Connections

–14–

QOPP

REV. 0

AD8347

100pF

LO

200⍀

100pF

LOIN

AD8347

LOIP

Figure 5. Single-Ended LO Drive

Operating the VGA

A three-stage VGA sets the gain in the RF section. Two of the
three stages come before the mixer while the third amplifies the
mixer output. All three stages are driven in parallel. The gain
range of the first RF VGA and that of the second RF VGA
combined with the mixer are both –13 dB to +10 dB. The
gain range of the baseband VGA is –4 dB to +19.5 dB. So the
overall gain range from the RF input to the IMXO/QMXO pins
is –30 dB to approximately +39.5 dB.

The gain of the VGA is set by the voltage on the VGIN pin,
which is a high impedance input. The gain control function
(which is linear-in-dB) and linearity are shown in TPC 1 and
TPC 2 at 1.9 GHz. Note that the sense of the gain control
voltage is negative so as the gain control voltage ranges from 0.2 V
to 1.2 V, the gain decreases from +39.5 dB to –30 dB.

Mixer Output Level and Drive Capability

I & Q channel baseband outputs, IMXO and QMXO are low
impedance outputs (R

, the voltage on Pin 14. The achievable output level on

V

VREF

@ 3 Ω) whose bias level is equal to

OUT

IMXO/QMXO is limited by their current drive capability of

1.5 mA max. This would allow for a 600 mV p-p swing into a

200 Ω load. At lower output levels, IMXO and QMXO can

drive smaller load resistances, subject to the same current limit.

These output stages are not, however, designed to drive 50 Ω

loads directly.

Operating the VGA in AGC Mode

While the VGA can be driven by an external source such as a
DAC, the AD8347 has an on-board sum of squares detector
which allows the AD8347 to operate in an automatic leveling
mode. The connections for operating in this mode are shown in
Figure 4. The two mixer outputs are connected to the detector
inputs VDT1 and VDT2. The summed detector output drives
an internal integrator which in turn delivers a gain correction

voltage to the VAGC pin. A 0.1 µF capacitor from VAGC to

ground sets the dominant pole of the integrator circuit. VAGC,
which should be connected to VGIN, adjusts gain until an
internal threshold is reached. This threshold corresponds to a level
at the IMXO/QMXO pins of approximately 8.5 mV rms. This
level will change slightly as a function of RF input power (see
TPC 30). For a CW (sine wave) input this corresponds to

RF
INPUT

C1

100pF

R1
200⍀

C2

100pF

C6

0.1␮F

100pF

VPS1

ENBL

RFIN

RFIP

VGIN

C5

C7

0.1␮F

CONTROL

INTERFACE

+VS +5V

C8

100pF

VPS2

AD8347

BIAS
CELL

GAIN

C9

0.1␮F

C10

100pF

VPS3

DET 1

R19
1k⍀

R20
4k⍀

120mV p-p

1V BIAS

C13

0.1␮F

IOFS

QOFS

C14

0.1␮F

1V BIAS

IAIN

VREF

PHASE

SPLITTER

VREF

VREF

VAGCVDT1

IMXO

VREF

DET 2

VDT2

QMXO QOPP

R21

4k⍀

R22

1k⍀

120mV p-p

2

VCMO

QAIN



IOPP

PHASE

SPLITTER

VCMO

1

IOPN

QOPN

VCMO

LOIN

LOIP

COM3
COM2

COM3
COM1

2.5V

C4

100pF

R17

200⍀

C3

100pF

3.8V p-p
DIFFERENTIAL
V

CM

LO INPUT

0.8GHz–2.7GHz

3

4

15

T1
ETC 1-1-13
(M/A-COM)

3.8V p-p
DIFFERENTIAL
V

CM

IOPP

= 2.5V

IOPN

–8dBm

QOPN

= 2.5V

QOPP

REV. 0

Figure 6. Adjusting AGC Level to Increase Baseband Amplifier Output Swing

–15–

AD8347

approximately 24 mV p-p. If this signal is applied directly to the
subsequent baseband amplifier stage, the final baseband output
is 760 mV p-p differential. (See Baseband Amplifier section.)

If the VGA gain is being set from an external source, the on-board
detector inputs (VDT1 and VDT2) are not used and should be
tied to VREF.

Note that in subsequent sections, peak-to-peak calculations
assume a sine wave input. If the input signal has a higher peak­to-average ratio, the mixer output peak-to-peak voltage at which
the AGC loop settles will be higher.

Changing the AGC Setpoint

The AGC circuit can be easily set up to level at voltages higher
than the nominal 24 mV p-p as shown in Figure 6. The voltages
on Pins IMXO and QMXO are attenuated before being applied
to the detector inputs. In the example shown, an attenuation
factor of 0.2 (–14 dB) between IMXO/QMXO and the detector
inputs, will cause the VGA to level at approximately 120 mV p-p
(note that resistor divider network must be referenced to V

VREF

This results in a peak-to-peak output swing at the baseband
amplifier outputs of 3.8 V differential, that is, 1.6 V to 3.4 V on
each side. Note that V

has been increased to 2.5 V to avoid

VCMO

signal clipping at the baseband outputs. Due to the attenuation
between the mixer output and the detector input, the variation
in the settled mixer output level, versus RF input power, will be
greater than the variation shown in TPC 30. The variation will
be greater by a factor equal to the inverse of the attenuation factor.

Baseband Amplifiers

The final baseband amplifier stage takes the signals from IMXO/

The differential output offset voltages of the baseband amplifiers

are typically ±50 mV. This offset voltage results from both input

and output effects.

The overall signal-to-noise ratio can be improved by increasing
the VGA gain by driving it with an external voltage or by changing
the setpoint of the AGC circuit. (See Changing the AGC Setpoint.)

Driving Capacitive Loads

In applications where the baseband amplifiers are driving unbal­anced capacitive loads, some series resistance should be placed
between the amplifier and the capacitive load. For example, for

a 10 pF load, four 220 Ω series resistors (one in each baseband

output) should be used.

External Baseband Amplification

The baseband output offset voltage and noise can be reduced by
bypassing the internal baseband amplifiers and amplifying the
mixer output signal using a high quality differential amplifier. In
the example shown in Figure 7, two AD8132 differential ampli-

).

fiers are used to gain the mixer output signals up by 20 dB. In this
example, the setpoint of the AGC circuit has been increased so that
the input to the external amplifiers is approximately 72 mV p-p.
This results in final baseband output signals of 720 mV p-p.

The closed-loop bandwidth of the amplifiers in Figure 7 is equal
to roughly 20 MHz. Higher bandwidths are achievable, but at
the cost of lower closed-loop gain. In Figure 7, the output common
mode levels (VOCM, Pin 2) of the differential amplifiers are set
by the AD8347’s VREF (approximately 1 V). The output common
mode levels can also be set externally (e.g., by the reference voltage

from an ADC).
QMXO and amplifies them by 30 dB, or a factor of 31.6. This
results in a maximum system gain of 69.5 dB. When the VGA is
in AGC mode, the baseband I & Q outputs (IOPN, IOPP,
QOPN, and QOPP) deliver a differential voltage of approxi­mately 760 mV p-p (380 mV p-p on each side).

The single-ended input signal to the baseband amplifiers is
applied at the high impedance inputs IAIN and QAIN. As can
be seen in Figure 4, the baseband amplifier operates internally
as a differential amplifier, with the second input being driven by
V

. As a result, the input signal to the baseband amplifier

VREF

should be biased at V

VREF

.

The output common-mode level of the baseband amplifiers is
set by the voltage on Pin 5, VCMO. This pin can either be
connected to VREF (Pin 14) or to an external reference voltage
from a device such as an analog-to-digital converter (ADC).
V

has a nominal range from 0.5 V to 2.5 V. However, since

VCMO

the baseband amplifiers can only swing down to 0.4 V, higher
values of V

will generally be required to avoid low-end

VCMO

signal clipping. On the other hand, the positive swing at each
output is limited to 1.3 V below the supply voltage. So the max
p-p swing is given by 2 ⫻ (V

– 1.3 – 0.4) V differentially.

PS

For example, in order for the baseband output amplifier to be able
to deliver an output swing of 2 V p-p (1 V p-p on each side),
V

must be in the range from 0.9 V to 2.5 V.

VCMO

+5V

AD8347

IMXO

VDT1

VREF

VDT2

QMXO

72mV p-p

R23

10k⍀

R25

20k⍀

72mV p-p

R22

20k⍀

R24

10k⍀

R17A
499⍀

R18A
499⍀

R17B
499⍀

R18B
499⍀

R19A

4.99k⍀

AD8132

4.99k⍀
R20A

4.99k⍀

R19B

4.99k⍀

R20B

AD8132

–5V

0.1␮F

0.1␮F
–5V

+5V

0.1␮F

0.1␮F

10␮F

720mV p-p
DIFFERENTIAL

= 1V

V

CM

10␮F

10␮F

720mV p-p
DIFFERENTIAL

= 1V

V

CM

10␮F

Figure 7. External Baseband Amplification Example

–16–

REV. 0

AD8347

Filter Design Considerations

Baseband low-pass or band-pass filtering can be conveniently
performed between the mixer outputs (IMXO/QMXO) and the
input to the baseband amplifiers. Because the output impedance

of the mixer is low (roughly 3 Ω) and the input impedance of

the baseband amplifier is high, it is not practical to design a
filter which is reactively matched to these impedances. An LC
filter can be matched by placing a series resistor at the mixer
output and a shunt resistor (terminated to V

) at the input to

VREF

the baseband amplifier.

Because the mixer output drive level is limited to a maximum cur­rent of 1.5 mA, the characteristic impedance of the filter should be

greater than 50 Ω, especially if larger signal swings are to be achieved.
Figure 8 shows the schematic for a 100 Ω, fourth order elliptic

low-pass filter with a 3 dB cutoff frequency of 20 MHz. Source

and load impedances of approximately 100 Ω ensure that the

filter sees a matched source and load. This also ensures that the

mixer output is driving an overall load of 200 Ω. Note that the

shunt termination resistor is tied to VREF and not to ground.
The frequency response and group delay of this filter are shown
in Figures 9 and 10.

IMXO

AD8347

RS

95.3⍀

4.7pF

L

1

0.68␮H

C1

R3
2⍀

C3

8.2pF

L

R4

3

2⍀

1.2␮H

C2
150pF

C4
82pFRL100⍀

VREF VDT1

IAIN

(SEE

TEXT)

Figure 8. Typical Baseband Low-Pass Filter

0

–10

–20

–30

–40

–50

ATTENTUATION – dB

–60

–70

–80

1 10010

FREQUENCY – MHz

Figure 9. Frequency Response of 20 MHz Baseband
Low-Pass Filter

50
45

40

35

30

25
20

GROUP DELAY – ns

15

10

5

0

1 10010

FREQUENCY – MHz

Figure 10. Group Delay of 20 MHz Baseband Low-Pass
Filter

If the VGA is operating in AGC mode, the detector input (VDT1/
VDT2) can be tied either to the input or output of the filter.
Connecting the detector input to the input of the filter (i.e.,
IMXO and QMXO) will cause the VGA leveling point to be
determined by the composite of the wanted signal and any unfiltered
components such as blockers or signal harmonics. Connecting
VDT1/VDT2 to the outputs of the filters ensures that the leveling
point of the AGC circuit is based upon the amplitude of the
filtered output only. The latter option is more desirable as it
results in a more constant baseband output. However, when
using this method, the leveling point of the AGC should be set
so that out-of-band blockers do not overdrive the mixer output.

DC Offset Compensation

Feedthrough of the LO signal to the RF input port results in
self-mixing of the LO signal. This produces a dc component
at the mixer output that is frequency-dependent.

The AD8347 includes an internal circuit which actively nulls
out any dc offsets that appear at the mixer output. The dc-bias
level of the mixer output (which should ideally be equal to V

VREF

,
the bias level for the baseband sections of the chip) is continually
being compared to V
output level and V

VREF

. Any differences between the mixer

VREF

, will force a compensating voltage on to

the mixer output.

The time constant of this correction loop is set by the capacitors
which are connected to pins IOFS and QOFS (each output can

be compensated separately). For normal operation 0.1 µF capacitors

are recommended. The corner frequency of the compensation
loop is given approximately by the equation

f

dB

3

CinF

()

OFS

OFS

C

40

=µ

The corner frequency must be set to a frequency that is much
lower than the symbol rate of the demodulated data. This prevents
the compensation loop from falsely interpreting the data stream
as a changing offset voltage.

To disable the offset compensation circuits, IOFS and QOFS
should be tied to VREF.

REV. 0

–17–

AD8347

Evaluation Board

Figure 11 shows the schematic of the AD8347 evaluation board.
Note that uninstalled components are indicated with the “open”
designation. The board is powered by a single supply in the
range of 2.7 V to 5.5 V. Table I details the various configuration
options of the evaluation board.

IMXO

RFIP

TP1

+V

S

R35

C17

(OPEN)

+V

S

TP2

TP3

0⍀

R36

0⍀

C1

0.1␮F

C16

0.1␮F

LK1

(OPEN)

0.1␮F

C6

0.1␮F

R6
0⍀

R8

LK5

R39

(OPEN)

C11

100pF

R18

C12

200⍀

100pF

C8

C7

100pF

C13

0.1␮F

J6

IOPN

J5

IOPP

J11

VCMO

L3

(OPEN)L2(OPEN)L1(OPEN)

J7

C20

(OPEN)

C4

(OPEN)

C21

(OPEN)

C19

(OPEN)

C18

(OPEN)

C22

(OPEN)

J4

C5

100pF

J3

LO

100pF

1
2
3
4
5
6
7
8

9
10
11
12
13
14

C2

LOIP
VPS1
IOPN
IOPP
VCMO
IAIN
COM3
IMXO
COM2
RFIN
RFIP
VPS2
IOFS
VREF

4
3

R17

200⍀

AD8347

5

T1
ETC 1-1-13

1

LOIN

COM1

QOPN

QOPP

QAIN

COM3

QMXO

VPS3
VDT1

VAGC

VDT2

VGIN
QOFS
ENBL

C3
100pF

28
27
26
25
24
23
22
21
20
19
18
17
16
15

LK2

TP5

C10

100pF

LK4

R40
(OPEN)

R33

0⍀

C9

0.1␮F

LK3

(OPEN)

+V

S

LK6

R34

V

POS

SW1

C25

(OPEN)

A

B

L4

(OPEN)

C30

(OPEN)

L6

(OPEN)L5(OPEN)

C26

(OPEN)

C29

(OPEN)

(OPEN)

C28

TP6

R37

0⍀

R38

0⍀

C31

(OPEN)

C15

0.1␮F

C14

0.1␮F

C27

(OPEN)

J1
QOPN

J2
QOPP

J8
QMXO

J9
VAGC

J10
VGIN

Figure 11. Evaluation Board Schematic

–18–

REV. 0

Figure 12. Silkscreen of Component Side

AD8347

REV. 0

Figure 13. Layout of Component Side Figure 14. Layout of Circuit Side

–19–

AD8347

Table I. Evaluation Board Configuration Options

Component Function Default Condition

TP1, TP4, TP5 Power Supply and Ground Vector Pins Not Applicable
TP2, TP6 IOFS and QOFS Probe Points Not Applicable
TP3 VREF Probe Point Not Applicable
LK1, J11 Baseband Amplifier Output Bias: Installing this link connects VREF LK1 Installed

to VCMO. This sets the bias level on the baseband amplifiers to VREF,
which is equal to approximately 1 V. Alternatively, the bias level of the
baseband amplifiers can be set by applying an external voltage to SMA
connector J11.

LK2, LK6, LK3, J9, J10 AGC Mode: Installing LK2 and LK6 connects the mixer outputs IMXO LK2, LK6, LK3 Installed

and QMXO to the detector inputs VDT2 and VDT1. By installing LK3,
which connects VGIN to VAGC, the AGC mode is activated. The AGC
voltage can be observed on SMA connector J9. With LK3 removed, the
gain control signal for the internal variable gain amplifiers should be
applied to SMA connector J10.

LK4, LK5 Baseband Filtering: Installing LK4 and LK5, connects the mixer LK4, LK5 Installed

R6, R33, outputs IMXO and QMXO directly to the baseband amplifier inputs R6 = R33 = 0 Ω (Size 0603)
L1–L5 IAIN and QAIN. With R6 and R33 installed (0 Ω), IAIN and QAIN L1–L5 = Open (Size 0805)

C4, C17–C22, C25–C31

can be observed on SMA connectors J7 and J8. By removing LK4 and LK5

R8, R34, R39, R40 and installing R8 and R34, LC filters can be inserted between the Open (Size 0805)

mixer outputs and the baseband amplifier inputs. R8 and R34 can be R8 = R34 = Open (0603)
used to increase the effective output impedance of IMXO and QMXO. R39 = R40 = Open (0603)
(These outputs have low output impedances.) R39 and R40 can be used
to provide terminations for the filter at IAIN and QAIN. (IAIN and QAIN
are high impedance inputs.) R39 and R40 are terminated to VREF.

R35, R36, R37, R38 Baseband Amplifier Output Series Resistors R35 = R36 = R37 = R38 =

SW1 Device Enable: When in position A, the ENBL pin is connected to +V

and the AD8347 is in operating mode. In position B, the ENBL pin is
grounded, putting the device in power-down mode.

C4, C17–C22, C25–C31 =

0 Ω (Size 0603)

SW1 = A

S

C02675–.8–10/01(0)

PIN 1

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead TSSOP

(RU-28)

0.386 (9.80)

0.378 (9.60)

28

0.0256 (0.65)
BSC

0.0118 (0.30)

0.0075 (0.19)

15

141

0.0433 (1.10)

0.0035 (0.090)

0.177 (4.50)

0.169 (4.30)

MAX

0.0079 (0.20)

0.256 (6.50)

0.246 (6.25)

8ⴗ
0ⴗ

PRINTED IN U.S.A.

0.028 (0.70)

0.020 (0.50)

–20–

REV. 0