Datasheet AD8339 Datasheet (ANALOG DEVICES)

Page 1
DC to 50 MHz, Quad I/Q Demodulator

FEATURES

Quad integrated I/Q demodulator 16 phase select on each output (22.5° per step) Quadrature demodulation accuracy
Phase accuracy: ±1° Amplitude imbalance: ±0.05 dB
Bandwidth
4LO: LF to 200 MHz RF: LF to 50 MHz
Baseband: determined by external filtering Output dynamic range: 160 dB/Hz LO drive: >0 dBm (50 Ω), single-ended sine wave Supply: ±5 V Power consumption: 73 mW/channel (290 mW total) Power-down via SPI (each channel and complete chip)

APPLICATIONS

Medical imaging (CW ultrasound beamforming) Phased array systems
Radar
Adaptive antennas Communication receivers
RSTS
SCLK
SDI SDO
CSB
RF2P
RF2N
4LOP
4LON
RF3P
RF3N
VPOS
VNEG
and Phase Shifter
AD8339

FUNCTIONAL BLOCK DIAGRAM

RF1PRF1N
AD8339
SERIAL
INTERFACE
÷4
90°
BIAS
RF4PRF4N
Figure 1.
I1OP
Q1OP
I2OP
Q2OP
I3OP
Q3OP
I4OP
Q4OP
06587-001

GENERAL DESCRIPTION

The AD8339 is a quad I/Q demodulator configured to be driven by a low noise preamplifier with differential outputs. It is optimized for the LNA in the AD8332/AD8334/AD8335 family of VGAs. The part consists of four identical I/Q demodulators with a 4× local oscillator (LO) input that divides the signal and generates the necessary 0° and 90° phases of the internal LO that drive the mixers. The four I/Q demodulators can be used independently of each other (assuming that a common LO is acceptable) because each has a separate RF input.
Continuous wave (CW) analog beamforming (ABF) and I/Q demodulation are combined in a single 40-lead, ultracompact chip scale device, making the AD8339 particularly applicable in high density ultrasound scanners. In an ABF system, time domain coherency is achieved following the appropriate phase alignment and summation of multiple receiver channels. A reset pin synchronizes multiple ICs to start each LO divider in the same quadrant. Sixteen programmable 22.5° phase increments are available for each channel. For example, if Channel 1 is used as a reference and Channel 2 has an I/Q phase lead of 45°, the user can phase align Channel 2 with Channel 1 by choosing the appropriate phase select code.
The mixer outputs are in current form for convenient summa­tion. The independent I and Q mixer output currents are summed and converted to a voltage by a low noise, high dynamic range, current-to-voltage (I-V) transimpedance amplifier, such as the
AD8021 or the AD829. Following the current summation, the
combined signal is applied to a high resolution analog-to-digital converter (ADC), such as the AD7665 (16-bit, 570 kSPS).
An SPI-compatible serial interface port is provided to easily program the phase of each channel; the interface allows daisy chaining by shifting the data through each chip from SDI to SDO. The SPI also allows for power-down of each individual channel and the complete chip. During power-down, the serial interface remains active so that the device can be programmed again.
The dynamic range is typically 160 dB/Hz at the I and Q outputs. The AD8339 is available in a 6 mm × 6 mm, 40-lead LFCSP and is specified over the industrial temperature range of
−40°C to +85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
Page 2
AD8339

TABLE OF CONTENTS

Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Equivalent Input Circuits ................................................................ 7
Typical Performance Characteristics ............................................. 8
Test Circuits ..................................................................................... 14
Theory of Operation ...................................................................... 18
Quadrature Generation ............................................................. 19
I/Q Demodulator and Phase Shifter ........................................ 19
Dynamic Range and Noise ........................................................ 19
Multichannel Summation ......................................................... 20
Serial Interface ................................................................................ 23
ENBL Bits .................................................................................... 23
Applications Information .............................................................. 24
Logic Inputs and Interfaces ....................................................... 24
Reset Input .................................................................................. 24
LO Input ...................................................................................... 24
Evaluation Board ............................................................................ 25
Connections to the Board ......................................................... 26
Test Configurations .................................................................... 26
AD8339-EVALZ Artwork ......................................................... 33
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35

REVISION HISTORY

2/09—Rev. 0 to Rev. A
Change to Figure 1 ........................................................................... 1
Change to Table 2 ............................................................................. 5
Added Exposed Pad Notation to Figure 2;
Changes to Table 3 ............................................................................ 6
Changes to Figure 3; Added Figure 4;
Renumbered Sequentially ................................................................ 7
Changes to Theory of Operation Section .................................... 18
Changes to Dynamic Range and Noise Section, ........................ 20
Changes to Channel Summing Section ....................................... 21
Added Figure 55 .............................................................................. 22
Changes to Serial Interface Section, ENBL Bits Section,
Figure 56, and Figure 57 ................................................................ 23
Changes to Evaluation Board Section and Figure 58 ................. 25
Changes to Connections to the Board Section and Table 5 ...... 26
Changes to Figure 60 ...................................................................... 27
Changes to Figure 61 ...................................................................... 28
Changes to Table 7 .......................................................................... 29
Changes to Figure 63 ...................................................................... 30
Changes to Figure 64 ...................................................................... 31
Changes to Figure 65 ...................................................................... 32
Changes to Figure 66 and Figure 67 ............................................. 33
Changes to Figure 68 and Figure 69 ............................................. 34
Deleted Table 8 ................................................................................ 35
Updated Outline Dimensions ....................................................... 35
8/07—Revision 0: Initial Version
Rev. A | Page 2 of 36
Page 3
AD8339

SPECIFICATIONS

VS = ±5 V, TA = 25°C, 4fLO = 20 MHz, f noted. Single-channel AD8021 LPF values: R
= 5.01 MHz, f
RF
= 787  and C
FILT
= 10 kHz, PLO 0 dBm, per channel performance, dBm (50 ), unless otherwise
BB
= 2.2 nF (see Figure 53).
FILT
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
OPERATING CONDITIONS
Local Oscillator (LO) Frequency
Range
4× internal LO at Pin 4LOP and Pin 4LON, square wave drive via LVDS (see Figure 64)
0.01 200 MHz
RF Frequency Range Mixing DC 50 MHz Baseband Bandwidth Limited by external filtering DC 50 MHz LO Input Level 0 13 dBm Supply Voltage (VS) ±4.5 ±5.0 ±5.5 V Temperature Range −40 +85 °C
DEMODULATOR PERFORMANCE
Input Impedance RF, differential 25||10 kΩ||pF LO, differential 100||4 kΩ||pF Transconductance
Demodulated I
; each Ix or Qx output after low-pass
OUT/VIN
1.15 mS
filtering measured from RF inputs, all phases Dynamic Range IP1dB − input referred noise (dBm) 160 dB/Hz Maximum Input Swing Differential; inputs biased at 2.5 V; Pin RFxP, Pin RFxN 2.8 V p-p Peak Output Current (No Filtering) 0° phase shift ±2.4 mA 45° phase shift ±3.1 mA Input P1dB
Ref = 50 Ω 14.8 dBm Ref = 1 V rms 1.85 dBV Third-Order Intermodulation (IM3) f
= 5.010 MHz, f
RF1
= 5.015 MHz, fLO = 5.023 MHz
RF2
Equal Input Levels Baseband tones: 0 dBm @ 8 kHz and 13 kHz −60 dBc Unequal Input Levels Baseband tones: −1 dBm @ 8 kHz and −31 dBm @ 13 kHz −66 dBc
Third-Order Input Intercept (IIP3)
f
= 5.010 MHz, f
RF1
= 5.015 MHz, fLO = 5.023 MHz 31 dBm
RF2
LO Leakage Measured at RF inputs, worst phase, measured into 50 Ω −118 dBm
Measured at baseband outputs, worst phase, AD8021
−68 dBm
disabled, measured into 50 Ω Conversion Gain All codes, see Figure 42 −1.3 dB Input Referred Noise Output noise/conversion gain (see Figure 47) 11.8 nV/√Hz Output Current Noise Output noise/R
12.9 pA/√Hz
FILT
Noise Figure With AD8334 LNA R R R
= 50 Ω, RFB = ∞ 8.4 dB
S
= 50 Ω, RFB = 1.1 kΩ 9.1 dB
S
= 50 Ω, RFB = 274 Ω 11.5 dB
S
Bias Current Pin 4LOP and Pin 4LON −3 μA Pin RFxP and Pin RFxN −45 μA LO Common-Mode Range Pin 4LOP and Pin 4LON (each pin) 0.2 3.8 V RF Common-Mode Voltage
For maximum differential swing; Pin RFxP and Pin RFxN
(dc-coupled to AD8334 LNA output)
2.5 V
Output Compliance Range Pin IxOP and Pin QxOP −1.5 +0.7 V
PHASE ROTATION PERFORMANCE One channel is reference; others are stepped
Phase Increment 16 phase steps per channel 22.5 Degrees Quadrature Phase Error Ix to Qx; all phases, 1σ −2 ±1 +2 Degrees I/Q Amplitude Imbalance Ix to Qx; all phases, 1σ ±0.05 dB Channel-to-Channel Matching Phase match I-to-I and Q-to-Q; −40°C < TA < +85°C ±1 Degrees Amplitude match I-to-I and Q-to-Q; −40°C < TA < +85°C ±0.1 dB
Rev. A | Page 3 of 36
Page 4
AD8339
Parameter Test Conditions/Comments Min Typ Max Unit
LOGIC INTERFACES
Pin SDI, Pin CSB, Pin SCLK, Pin RSET
Logic Level High 1.5 V Logic Level Low 0.9 V
Pin RSTS
Logic Level High 1.8 V
Logic Level Low 1.2 V Bias Current Logic high (pulled to 5 V) 0.5 μA Logic low (pulled to GND) 0 μA Input Resistance 4 MΩ LO Divider RSET Setup Time
RSET rising or falling edge to 4LOP or 4LON (differential)
rising edge LO Divider RSET High Pulse Width 20 ns LO Divider RSET Response Time 200 ns Phase Response Time Measured from CSB going high 5 μs Enable Response Time
Measured from CSB going high (with 0.1 μF capacitor on
Pin LODC); no channel enabled At least one channel enabled 500 ns Output Pin SDO loaded with 5 pF and next SDI input
Logic Level High 1.7 1.9 V Logic Level Low 0.2 0.5 V
SPI TIMING CHARACTERISTICS Pin SDI, Pin SDO, Pin CSB, Pin SCLK, Pin RSTS
SCLK Frequency f
10 MHz
CLK
CSB Fall to SCLK Setup Time t1 0 ns SCLK High Pulse Width t2 10 ns SCLK Low Pulse Width t3 10 ns
100 ns
Data Access Time (SDO) After SCLK
t
4
Rising Edge
2 ns
Data Setup Time Before SCLK Rising
t
5
Edge
t
Data Hold Time After SCLK Rising
2 ns
6
Edge SCLK Rise to CSB Rise Hold Time t7 15 ns CSB Rise to SCLK Rise Hold Time t8 0 ns
POWER SUPPLY Pin VPOS, Pin VNEG
Supply Voltage ±4.5 ±5.0 ±5.5 V Current VPOS, all phase bits = 0 35 mA VNEG, all phase bits = 0 −18 mA
Over Temperature,
−40°C < T
< +85°C
A
VPOS, all phase bits = 0 33 36 mA
VNEG, all phase bits = 0 −19 −17 mA Quiescent Power Per channel, all phase bits = 0 66 mW Per channel maximum (depends on phase bits) 88 mW Disable Current All channels disabled; SPI stays on 2.75 mA PSRR VPOS to Ix/Qx outputs, @ 10 kHz −85 dB VNEG to Ix/Qx outputs, @ 10 kHz −85 dB
5 ns
12 15 μs
Rev. A | Page 4 of 36
Page 5
AD8339

ABSOLUTE MAXIMUM RATINGS

Table 2.
Parameter Rating
Voltages
Supply Voltage (VS) ±6 V RF Inputs 6 V to GND 4LO Inputs 6 V to GND Outputs (IxOP, QxOP) +0.7 V to −6 V Digital Inputs +6 V to −1.4 V SDO Output 6 V to GND LODC Pin VPOS − 1.5 V to +6 V
Thermal Data (4-Layer JEDEC Board,
No Airflow, Exposed Pad Soldered to PCB)
θJA 32.2°C/W θJB 17.8°C/W θJC 2.7°C/W ψJT 0.3°C/W
ψJB 16.7°C/W Maximum Junction Temperature 150°C Maximum Power Dissipation
(Exposed Pad Soldered to PCB) Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C
2 W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 5 of 36
Page 6
AD8339

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RSTS
SDI
COMM
VPOS
RF1P
RF1N
RSET
I1OP
Q1OP
VNEG
3839 3640
RF2N
1
RF2P
229
COMM
3
COMM
4
SCLK
5
CSB
6
VPOS
7
VPOS
8
RF3P
9 10
RF3N
37 35
PIN 1 INDICATOR
AD8339
TOP VIEW
(Not to Scale)
1413 171211 1815 16 20
34 33
3132
30
Q2OP
I2OP
28
VPOS
27
VPOS
26
4LOP
25
4LON
24
VNEG
23
VNEG
22
I3OP
21
19
Q3OP
SDO
RF4P
RF4N
VPOS
NOTES
1. THE EXPO SED PAD IS NOT CONNECTED I NTERNALLY. FOR INCREASED RELIABILITY OF THE SOL DER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE.
I4OP
Q4OP
VPOS
LODC
COMM
VNEG
06587-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 9, 10, 13, 14, 37, 38
RF1P to RF4P, RF1N to RF4N
RF Inputs. Require external 2.5 V bias for optimum symmetrical input differential swing if ±5 V supplies
are used. 3, 4, 15, 36 COMM Ground. 5 SCLK Serial Interface Clock. 6 CSB Serial Interface Chip Select Bar. Active low. 7, 8, 11, 16,
27, 28, 35
VPOS
Positive Supply. These pins should be decoupled with a ferrite bead in series with the supply and a
0.1 μF capacitor between the VPOS pins and ground. Because the VPOS pins are internally connected,
one set of supply decoupling components on each side of the chip should be sufficient. 12 SDO Serial Interface Data Output. Normally connected to the SDI pin of the next chip or left open. 17 LODC
Decoupling Pin for LO. A 0.1 μF capacitor should be connected between this pin and ground. The value
of this capacitor affects the chip enable/disable times. 18, 19, 21, 22,
29, 30, 32, 33
I1OP to I4OP, Q1OP to Q4OP
I/Q Outputs. These outputs provide a bidirectional current that can be converted back to a voltage via a
transimpedance amplifier. Multiple outputs can be summed by simply connecting them (wire-OR). The
bias voltage should be set to 0 V or less by the transimpedance amplifier (see Figure 53). 20, 23, 24, 31 VNEG
Negative Supply. These pins should be decoupled with a ferrite bead in series with the supply and a
0.1 μF capacitor between the VNEG pins and ground. Because the VNEG pins are internally connected,
one set of supply decoupling components for the chip should be sufficient. 25, 26 4LON, 4LOP
LO Inputs. No internal bias; optimally biased by an LVDS driver. For best performance, these inputs
should be driven differentially. If driven by a single-ended sine wave at 4LOP or 4LON, the signal level
should be >0 dBm (50 Ω) with external bias resistors. 34 RSET Reset for LO Interface. Logic threshold is at ~1.3 V and therefore can be driven by >1.8 V CMOS logic. 39 SDI
Serial Interface Data Input. Logic threshold is at ~1.3 V and therefore can be driven by >1.8 V CMOS
logic. 40 RSTS
Reset for SPI Interface. Logic threshold is at ~1.5 V with ±0.3 V hysteresis and should be driven by >3.3 V
CMOS logic. For quick testing without the need to program the SPI, the voltage on the RSTS pin should
be pulled to −1.4 V; this enables all four channels in the phase (I = 1, Q = 0) state. EP
Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints
and maximum thermal capability, it is recommended that the pad be soldered to the ground plane.
Rev. A | Page 6 of 36
Page 7
AD8339
V
V

EQUIVALENT INPUT CIRCUITS

POS
VPOS
SCLK
CSB
SDI
RSET
COMM
LOGIC
INTERFACE
06587-003
Figure 3. SCLK, CSB, SDI, and RSET Logic Inputs
VPOS
RSTS
COMM
LOGIC
INTERFACE
06587-104
Figure 4. RSTS Logic Input
VPOS
LODC
COMM
Figure 6. LO Decoupling Pin
POS
RFxP
RFxN
COMM
Figure 7. RF Inputs
COMM
06587-005
06587-006
VNEG
IxOP QxOP
06587-007
4LOP
4LON
COMM
Figure 5. Local Oscillator Inputs
06587-004
Figure 8. Output Drivers
Rev. A | Page 7 of 36
Page 8
AD8339

TYPICAL PERFORMANCE CHARACTERISTICS

VS = ±5 V, TA = 25°C, 4fLO = 20 MHz, fLO = 5 MHz, fRF = 5.01 MHz, fBB = 10 kHz, 4fLO − LVDS drive; per channel performance shown is typical of all channels, differential voltages, dBm (50 ), phase select code = 0000, unless otherwise noted (see Figure 42).
1.5
f = 1MHz
1.0
0.5
CODE 1000
0
–0.5
IMAGINARY (Normalized)
–1.0
–1.5
–2.0 –1.5 1.5–1.0 1.0–0.5 0 0.5 2.0
CODE 0100
I
CODE 1100
REAL (Normalized)
Q
CODE 0011
CODE 0010
CODE 0001
CODE 0000
06587-008
Figure 9. Normalized Vector Plot of Phase, Ch 2, Ch 3, and Ch 4 vs. Ch 1;
Ch 1 Fixed at 0°; Ch 2, Ch 3, and Ch 4 Stepped 22.5°/Step; All Codes Displayed
360
2
f = 5MHz
1
0
–1
CHANNEL 3 CHANNEL 4
–2
2
f = 1MHz
1
PHASE ERROR (Deg rees)
0
–1
CHANNEL 3 CHANNEL 4
–2
0000 1111
0010 0100 0110 1000 1010 1100 1110
CODE (Binary)
Figure 12. Representative Phase Error vs. Binary Phase Select Code
at 1 MHz and 5 MHz; Ch 3 and Ch 4 Are Displayed with Respect to Ch 1
06587-011
315
270
225
180
135
PHASE DELAY (Degrees)
90
45
0 0000 1111
0010 0100 0110 1000 1010 1100 1110
5MHz
1MHz
CODE (Binary)
Figure 10. Representative Phase Delay vs. Binary Phase Select Code
at 1 MHz and 5 MHz; Ch 3 and Ch 4 Are Displayed with Respect to Ch 1
1.0 f = 5MHz
0.5
0
–0.5
CHANNEL 3 CHANNEL 4
–1.0
1.0 f = 1MHz
0.5
AMPLITUDE ERRO R (dB)
0
–0.5
CHANNEL 3 CHANNEL 4
–1.0
0000 1111
0010 0100 0110 1000 1010 1100 1110
CODE (Binary)
Figure 11. Representative Amplitude Error vs. Binary Phase Select Code
at 1 MHz and 5 MHz; Ch 3 and Ch 4 Are Displayed with Respect to Ch 1
21
06587-009
C2 500mV C4 500mV
R1 500mV 20µs R2 500mV 20µs
20.0µs/DIV
2.5MS/s 400n s/PT A C2 30.0mV
06587-012
Figure 13. Representative Phase Delays of the I or Q Outputs;
Ch 2 Is Displayed with Respect to Ch 1, for Delays of 22.5°, 45°, 67.5°, and 90°
1
I OUTPUT OF CHANNEL 1 SHOWN
0
–1
CONVERSION GAIN (dB)
–2
CODE 0000 CODE 0001 CODE 0010
06587-010
CODE 0011
–3
1M 50M10M
RF FREQ UENCY (Hz)
06587-013
Figure 14. Conversion Gain vs. RF Frequency, First Quadrant,
Baseband Frequency = 10 kHz
Rev. A | Page 8 of 36
Page 9
AD8339
8
6
4
2
0
–2
–4
–6
QUADRATURE PHASE ERRO R (Degrees)
–8
1M 50M10M
RF FREQUENCY (Hz)
06587-014
Figure 15. Representative Range of Quadrature Phase Error vs. RF Frequency
for All Channels and Codes
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
I/Q AMPLITUDE IMBALANCE (dB)
–0.4
–0.5
100 100k
1k 10k
BASEBAND FREQUENCY (Hz)
06587-017
Figure 18. Representative Range of I/Q Amplitude Imbalance vs. Baseband
Frequency for All Channels and Codes (See Figure 44)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
QUADRATURE PHASE ERROR (Degrees)
–2.0
100 100k10k1k
BASEBAND FREQUENCY (Hz)
06587-015
Figure 16. Representative Range of Quadrature Phase Error vs. Baseband
Frequency for All Channels and Codes (See Figure 44)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
I/Q AMPLITUDE IMBALANCE (dB)
–0.4
–0.5
1M 50M10M
RF FREQUENCY (Hz)
06587-016
Figure 17. Representative Range of I/Q Amplitude Imbalance vs.
RF Frequency for All Channels and Codes
3
f
= 10kHz
BB
2
1
0
–1
AMPLITUDE MATCH (dB)
–2
–3
1M 50M10M
RF FREQUENCY (Hz)
06587-018
Figure 19. Typical Channel-to-Channel Amplitude Match vs. RF Frequency,
First Quadrant, over the Range of Operating Temperatures
8
f
= 10kHz
BB
6
4
2
0
–2
PHASE ERROR (Deg rees)
–4
–6
–8
1M 50M10M
RF FREQUENCY (Hz)
06587-019
Figure 20. Typical Channel-to-Channel Phase Error vs. RF Frequency,
First Quadrant, over the Range of Operating Temperatures
Rev. A | Page 9 of 36
Page 10
AD8339
1.4 I OUTPUT OF CHANNEL 1 SHOWN TRANSCONDUC TANCE = [(V
1.3
/787)/VRF]
BB
–10
0
0dBm
1.2
1.1
1.0
TRANSCONDUCTANCE (mS)
PHASE DELAY = 0°
0.9
PHASE DELAY = 22.5° PHASE DELAY = 45° PHASE DELAY = 67.5°
0.8
1M 50M10M
RF FREQ UENCY (Hz)
Figure 21. Transconductance vs. RF Frequency
06587-020
–20
–30
–40
IM3 (dBc)
–50
–60
–70
IM3 PRODUCTS
LO = 5.023MHz RF1 = 5.015MHz RF2 = 5.010MHz
1M 50M10M
Figure 24. Representative Range of IM3 vs. RF Frequency, First Quadrant
for First Quadrant Phase Delays
10
0
–10
–20
–30
–40
CONVERSION GAIN (dB)
–50
–60
–70
05
0.5 1.0 1.5 2.0 2.5 3. 0 3.5 4.0 4. 5
COMMON-MODE VOLTAGE (V)
+85°C +25°C –40°C
06587-021
.0
Figure 22. LO Common-Mode Range at Three Temperatures
35
30
25
20
15
OIP3 (dBm)
10
5
0
1M 50M10M
Figure 25. Representative Range of OIP3 vs. RF Frequency, First Quadrant
1338 18
06587-023
RF FREQ UENCY (Hz)
(See Figure 49)
06587-024
RF FREQ UENCY (Hz)
(See Figure 49)
20
18
16
14
12
10
8
IP1dB (dBm)
6
4
2
0
1M 50M10M
RF FREQ UENCY (Hz)
Figure 23. Representative Range of IP1dB vs. RF Frequency,
Baseband Frequency = 10 kHz, First Quadrant (See Figure 43)
06587-022
Rev. A | Page 10 of 36
35
30
25
20
15
OIP3 (dBm)
10
5
0
1k 100k
BASEBAND FREQUENCY (Hz)
10k
Figure 26. Representative Range of OIP3 vs. Baseband Frequency
(See Figure 48)
06587-025
Page 11
AD8339
0
LO LEVEL = 0dBm
–10
–20
–30
–40
–50
–60
LO LEAKAGE (dBm)
–70
–80
–90
1M 50M10M
RF FREQ UENCY (Hz)
06587-026
Figure 27. Representative Range of LO Leakage vs. RF Frequency
at I and Q Outputs
0
LO LEVEL = 0dBm
–20
–40
–60
–80
LO LEAKAGE (dBm)
–100
–120
–140
1M 50M10M
RF FREQ UENCY (Hz)
06587-027
Figure 28. Representative Range of LO Leakage vs. RF Frequency at RF Inputs
20
18
16
14
12
10
8
NOISE FI GURE (dB)
6
4
2
0
1M 50M10M
RF FREQ UENCY (Hz)
Figure 30. Noise Figure vs. RF Frequency (When Driven by AD8334 LNA)
172
170
168
166
164
162
160
158
DYNAMIC RANGE (dB)
156
154
152
1M 50M10M
RF FREQ UENCY (Hz)
Q1 Q2 Q3 Q4
Q1 + Q2 + Q3 + Q4
I1 + I2
I3 + I4 Q1 + Q2 Q3 + Q4
I1 + I2 + I3 + I4
Figure 31. Dynamic Range vs. RF Frequency, IP1dB Minus Noise Level
06587-029
06587-030
16
14
12
10
8
6
NOISE (nV/Hz)
4
2
0
1M 50M10M
RF FREQUENCY ( Hz)
–142.9
–144.1
–145.4
–147.0
–148.
–151.4
–154.9
–161.0
9
Figure 29. Representative Range of Input Referred Noise vs. RF Frequency
Rev. A | Page 11 of 36
0
–2
–4
–6
–8
NOISE (d Bm)
06587-028
GAIN (dB)
–10
–12
–14
–16
–3.5 1. 0
–3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5
GAIN = VBB/V
DELAY = 0° DELAY = 22.5° DELAY = 45° DELAY = 67.5°
VOLTAGE (V)
RF
06587-031
Figure 32. Output Compliance Range for Four Values of Phase Delay
(See Figure 50)
Page 12
AD8339
T
CH3 AMPL
3.18V
3
3
CH2 AMPL 370mV
2
2
CH2 AMPL 790mV
CH3 AMPL
5.04V
CH2 500mV CH3 1.00V M200ns A CH3 600mV
T 608.000ns
06587-032
Figure 33. Enable Response vs. CSB (Filter Disabled to Show Response)
with a Previously Enabled Channel (See Figure 44)
3
2
CH2 AMPL
1.82V
CH3 1.00V CH2 500mV M2.00µs A CH3 780mV
T 7.840µs
06587-033
Figure 34. Enable Response vs. CSB (Filter Disabled to Show Response) with
No Channels Previously Enabled (See Figure 44)
CH3 2.00V CH2 500mV M200µs A CH3 2.52mV
T –175.200ns
Figure 36. LO Reset Response (see Figure 45)
3
2
CH3 1.00V CH2 1.00V
CH4 1.00V
M40.0µs A CH3 640mV
T 46.4000µs
Figure 37. Phase Switching Response at 45° (Top: CSB)
06587-035
06587-036
CH3 AMPL
3.18V
3
CH2 AMPL 210mV
2
CH3 1.00V CH2 500mV M200µs A CH3 600mV
T –492.00ns
Figure 35. Disable Response vs. CSB (Top: CSB)
(See Figure 44)
06587-034
Rev. A | Page 12 of 36
3
2
CH3 1.00V CH2 1.00V
CH4 1.00V
M40.0µs A CH3 640mV
T 46.4000µs
Figure 38. Phase Switching Response at 90° (Top: CSB)
06587-037
Page 13
AD8339
60
50
3
2
CH3 1.00V CH2 1.00V
CH4 1.00V
M40.0µs A CH3 640mV
T 46.4000µs
Figure 39. Phase Switching Response at 180° (Top: CSB)
0
–10
–20
–30
–40
–50
PSRR (dB)
–60
–70
–80
–90
–100
10k 100k 50M
FREQUENCY (Hz)
VNEG
VPOS
1M 10M
40
30
20
SUPPLY CURRENT (mA)
10
06587-038
0
–50 90
–30 –10 10 30 50 70
Figure 41. Supply Current vs. Temperature
06587-039
VPOS
VNEG
06587-040
TEMPERATURE ( °C)
Figure 40. PSRR vs. Frequency (see Figure 51)
Rev. A | Page 13 of 36
Page 14
AD8339
A
A
A

TEST CIRCUITS

D8021
787
2.2nF
2.2nF
787
AD8021
OSCILLOSCOPE
06587-041
LPF
50
SIGNAL GENERATOR
120nH
FB
0.1µF
0.1µF
AD8334
LNA
20
RFxP
RFxN
20
SIGNAL
GENERATOR
IxOP
AD8339
QxOP
4LOP
50
Figure 42. Default Test Circuit
D8021
100
10nF
10nF
100
AD8021
OSCILLOSCOPE
06587-042
LPF
50
SIGNAL GENERATOR
120nH
FB
0.1µF
0.1µF
AD8334
LNA
20
RFxP
RFxN
20
SIGNAL
GENERATOR
IxOP
AD8339
QxOP
4LOP
50
Figure 43. P1dB Test Circuit
D8021
AD8334
0.1µF
LNA
20
RFxP
RFxN
20
SIGNAL
GENERATOR
AD8339
QxOP
4LOP
50
IxOP
787
787
AD8021
OSCILLOSCOPE
06587-043
LPF
50
SIGNAL GENERATOR
120nH
FB
0.1µF
Figure 44. Phase and Amplitude vs. Baseband Frequency
Rev. A | Page 14 of 36
Page 15
AD8339
A
A
A
AD8334
0.1µF
LNA
20
20
SIGNAL
GENERATOR
RFxP
RFxN
AD8339
QxOP
4LOPRSET
50
IxOP
50
SIGNAL GENERATOR
LPF
50
SIGNAL GENERATOR
120nH
FB
0.1µF
787
787
D8021
AD8021
OSCILLOSCOPE
06587-044
Figure 45. LO Reset Response
D8334
LPF
50
SIGNAL GENERATOR
120nH
FB
0.1µF
0.1µF
LNA
20
RFxP
RFxN
20
SIGNAL
GENERATOR
IxOP
AD8339
QxOP
4LOP
50
OSCILLOSCOPE
5050
06587-045
Figure 46. RF Input Range
D829
6.98k
270pF
270pF
6.98k
AD829
SPECTRUM
ANALYZER
06587-046
120nH
FB
0.1µF
0.1µF
AD8334
LNA
20
20
0.1µF
GENERATOR
RFxP
RFxN
SIGNAL
IxOP
AD8339
QxOP
4LOP
50
Figure 47. Noise
Rev. A | Page 15 of 36
Page 16
AD8339
A
A
A
SIGNAL
GENERATOR
GENERATOR
SIGNAL
SPLITTER
–9.5dB
50
50
120nH
FB
0.1µF
0.1µF
AD8334
LNA
20
RFxP
RFxN
20
SIGNAL
GENERATOR
IxOP
AD8339
QxOP
4LOP
50
787
100pF
100pF
787
D8021
AD8021
SPECTRUM
ANALYZER
06587-047
Figure 48. OIP3 vs. Baseband Frequency
D8021
SIGNAL
GENERATOR
GENERATOR
SIGNAL
SPLITTER
–9.5dB
50
50
120nH
FB
0.1µF
0.1µF
AD8334
LNA
20
RFxP
RFxN
20
SIGNAL
GENERATOR
IxOP
AD8339
QxOP
4LOP
50
787
2.2nF
2.2nF
787
AD8021
SPECTRUM
ANALYZER
06587-048
Figure 49. OIP3 and IM3 vs. RF Frequency
D8021
787
2.2nF
2.2nF
787
AD8021
OSCILLOSCOPE
06587-049
LPF
50
SIGNAL GENERATOR
120nH
FB
0.1µF
0.1µF
AD8334
LNA
20
RFxP
RFxN
20
SIGNAL
GENERATOR
IxOP
AD8339
QxOP
4LOP
50
Figure 50. Output Compliance Range
Rev. A | Page 16 of 36
Page 17
AD8339
VPOS
VPOS
0.1µF
GENERATOR
RFxP
AD8339
RFxN
SIGNAL
SIGNAL GENERATOR
VPOS
IxOP
QxOP
4LOP
Figure 51. PSRR
SPECTRUM ANALYZER
06587-050
Rev. A | Page 17 of 36
Page 18
AD8339

THEORY OF OPERATION

RSTS40SDI
39
RF1P38RF1N37COMM36VPOS35RSET34I1OP
33
Q1OP32VNEG
31
RF2N
RF2P
COMM
COMM
SCLK
CSB
VPOS
VPOS
RF3P
RF3N
1
2
3
4
SERIAL
5
6
7
8
9
10
INTERFACE
(SPI)
BIAS
90°
V TO I
V TO I
LOCAL OSCILLATO R DIVIDE BY 4
V TO I
V TO I
CURRENT
MIRROR
CURRENT
MIRROR
CURRENT
MIRROR
CURRENT
MIRROR
CURRENT
MIRROR
CURRENT
MIRROR
CURRENT
MIRROR
CURRENT
MIRROR
30
Q2OP
29
I2OP
28
VPOS
27
VPOS
26
4LOP
25
4LON
24
VNEG
23
VNEG
22
I3OP
21
Q3OP
AD8339
12
VPOS11SDO
RF4P13RF4N14COMM15VPOS16LODC17I4OP
Figure 52. AD8339 Block Diagram
The AD8339 is a quad I/Q demodulator with a programmable phase shifter for each channel. The primary application is phased array beamforming in medical ultrasound. Other potential applications include phased array radar and smart antennas for mobile communications. The AD8339 can also be used in applications that require multiple well-matched I/Q demodulators. The AD8339 is architecturally very similar to its predecessor, the AD8333. The major differences are
The addition of a serial (SPI) interface that allows daisy
chaining of multiple devices
Reduced power per channel
Figure 52 shows the block diagram and pinout of the AD8339. The analog inputs include the four RF inputs, which accept signals from the RF sources, and a local oscillator (applied to differential input pins marked 4LOP and 4LON) common to all channels.
18
20
Q4OP19VNEG
06587-051
Each channel can be shifted up to 347.5° in 16 increments, or
22.5° per increment, via the SPI port. The AD8339 has two reset inputs: RSET synchronizes the LO dividers when multiple AD8339s are used in arrays; RSTS sets all the SPI port control bits to 0. RSTS is used for testing or to disable the AD8339 without the need to program it via the SPI port.
The I and Q outputs are current-formatted and summed together for beamforming applications. A transimpedance amplifier using an AD8021 op amp is a nearly ideal method for summing multiple channels and current-to-voltage conversion because each of the AD8339 outputs is terminated by a virtual ground. A further advantage of the transimpedance amplifier is the simple implementation of high-pass filtering and the flexible number of channels accommodated.
Rev. A | Page 18 of 36
Page 19
AD8339
Fo

QUADRATURE GENERATION

The internal 0° and 90° LO phases are digitally generated by a divide-by-4 logic circuit. The divider is dc-coupled and inherently broadband; the maximum LO frequency is limited only by its switching speed. The duty cycle of the quadrature LO signals is intrinsically 50% and is unaffected by the asymmetry of the externally connected 4LO input. Furthermore, the divider is implemented such that the 4LO signal reclocks the final flip­flops that generate the internal LO signals and thereby minimizes noise introduced by the divide circuitry.
For optimum performance, the 4LO input is driven differentially, but it can also be driven single-ended. A good choice for a drive is an LVDS device as is done on the AD8339 evaluation board. The common-mode range on each pin is approximately 0.2 V to
3.8 V with the nominal ±5 V supplies. The minimum 4LO level is frequency dependent when driven
by a sine wave. For optimum noise performance, it is important to ensure that the LO source has very low phase noise (jitter) and adequate input level to ensure stable mixer core switching. The gain through the divider determines the LO signal level vs. RF frequency. The AD8339 can be operated at very low frequen­cies at the LO inputs if a square wave is used to drive the LO, as is done with the LVDS driver on the evaluation board.
Beamforming applications require a precise channel-to-channel phase relationship for coherence among multiple channels. A reset pin is provided to synchronize the LO divider circuits in different AD8339s when they are used in arrays. The RSET pin resets the dividers to a known state after power is applied to multiple AD8339s. A logic input must be provided to the RSET pin when using more than one AD8339. Note that at least one channel must be enabled for the LO interface to also be enabled and the LO reset to work. See the
Reset Input section for more
information.

I/Q DEMODULATOR AND PHASE SHIFTER

The I/Q demodulators consist of double-balanced Gilbert cell mixers. The RF input signals are converted into currents by transconductance stages that have a maximum differential input signal capability of 2.8 V p-p. These currents are then presented to the mixers, which convert them to baseband (RF − LO) and twice RF (RF + LO). The signals are phase shifted according to the codes programmed into the SPI latch (see Table 4); the phase bits are labeled PHx0 through PHx3, where 0 indicates LSB and 3 indicates MSB. The phase shift function is an integral part of the overall circuit. The phase shift listed in Column 1 of Tab
le 4 is defined as being between the baseband I or Q channel outputs. As an example, for a common signal applied to a pair of RF inputs to an AD8339, the baseband outputs are in phase for matching phase codes. However, if the phase code for Channel 1 is 0000 and that of Channel 2 is 0001, then Channel 2 leads
nnel 1 by 22.5°.
Cha
llowing the phase shift circuitry, the differential current signal is converted from differential to single-ended via a current mirror. An external transimpedance amplifier is needed to convert the I and Q outputs to voltages.
Table 4. Phase Select Code for Channel-to-Channel Phase Shift
Φ Shift PHx3 (MSB) PHx2 PHx1 PHx0 (LSB)
0° 0 0 0 0
22.5° 0 0 0 1 45° 0 0 1 0
67.5° 0 0 1 1 90° 0 1 0 0
112.5° 0 1 0 1 135° 0 1 1 0
157.5° 0 1 1 1 180° 1 0 0 0
202.5° 1 0 0 1 225° 1 0 1 0
247.5° 1 0 1 1 270° 1 1 0 0
292.5° 1 1 0 1 315° 1 1 1 0
337.5° 1 1 1 1

DYNAMIC RANGE AND NOISE

Figure 53 is an interconnection block diagram of all four channels of the AD8339. More channels are easily added to the summation (up to 16 when using an AD8021 as the summation amplifier) by wire-OR connecting the outputs as shown for four channels. For optimum system noise performance, the RF input signal is provided by a very low noise amplifier, such as the LNA of the
AD8332, AD8334, or AD8335. In beamforming applications,
the I and Q outputs of a number of receiver channels are summed (for example, the four channels illustrated in Figure 53). The dynamic range of the system increases by the factor 10 log where N is the number of channels (assuming random uncorre­lated noise). The noise in the 4-channel example of Figure 53 is increased by 6 dB while the signal quadruples (12 dB), yielding an aggregate SNR improvement of 6 dB (12 − 6).
Judicious selection of the RF amplifier ensures the least degrada­tion in dynamic range. The input referred spectral voltage noise density (e
) of the AD8339 is nominally ~11 nV/√Hz. For the
n
noise of the AD8339 to degrade the system noise figure (NF) by 1 dB, the combined noise of the source and the LNA should be approximately twice that of the AD8339, or 22 nV/√Hz. If the noise of the circuitry before the AD8339 is less than 22 nV/√Hz, the system NF degrades more than 1 dB. For example, if the noise contribution of the LNA and source is equal to the AD8339, or 11 nV/√Hz, the degradation is 3 dB. If the circuit noise preceding the AD8339 is 1.3× as large as that of the AD8339 (or ~14 nV/√Hz), the degradation is 2 dB. For a circuit noise 1.45× that of the AD8339 (16 nV/√Hz), the degradation is 1.5 dB.
10
(N),
Rev. A | Page 19 of 36
Page 20
AD8339
To determine the input referred noise, it is important to know the active low-pass filter (LPF) values R
FILT
and C
, shown in
FILT
Figure 53. Typical filter values for a single channel are 1.58 kΩ for R
and 1 nF for C
FILT
; these values implement a 100 kHz
FILT
single-pole LPF. If two channels are summed, as is done on the AD8339 evaluation board, the resistor value is halved (787 ) and the capacitor value is doubled (2.2 nF), maintaining the same pole frequency at twice the AD8339 current.
If the RF and LO are offset by 10 kHz, the demodulated signal is 10 kHz and is passed by the LPF. The single-channel mixing gain from the RF input to the AD8021 output (for example, I1´, Q1´) is approximately 1.7× (4.7 dB) for 1.58 kΩ and 1 nF, or 6 dB less for filter values of 787  and 2.2 nF (0.85× or −1.3 dB). The noise contributed by the AD8339 is then 11 nV/√Hz × 1.7 or ~18.7 nV/√Hz at the AD8021 output. The combined noise of the AD8021 and the 1.58 kΩ feedback resistor is 6.3 nV/√Hz, so the total output referred noise is approximately 19.7 nV/√Hz. This value can be adjusted by increasing the filter resistor while
AD8332, AD8334 LN A
TRANS
MITTER
TRANSDUCE R
OR AD8335 PREAM P
T/R SW
T/R SW
T/R SW
R
FB
R
FB
R
FB
2
2
2
AD8339
2
2
2
2
2
2
maintaining the corner frequency, thereby increasing the gain. The factor limiting the magnitude of the gain is the output swing and drive capability of the op amp selected for the I-to-V converter, in this example, the AD8021.
The limitation on the number of channels summed is the drive capability of the amplifier, as explained in detail in the Channel Summing section.

MULTICHANNEL SUMMATION

Analog Beamforming

Beamforming, as applied to medical ultrasound, is defined as the phase alignment and summation of signals generated from a common source, but received at different times by a multielement ultrasound transducer. Beamforming has two functions: it imparts directivity to the transducer, enhancing its gain, and it defines a focal point within the body from which the location of the returning echo is derived. The primary application for the AD8339 is in analog beamforming circuits for ultrasound.
2
2
2
2
2
2
I1
Q1
I2
Q2
I3
Q3
C
FILT
R
FILT
C
FILT
R
FILT
AD8021
I
Q
AD7665 OR
AD7686
16-BIT ADC
AD7665 OR
AD7686
16-BIT ADC
I DATA
Q DATA
T/R SW
R
FB
2
QUADRATURE
DIVIDER
2
2
90°
CLOCK DATA
SYSTEM TIMING
2
2
CONTROLL ER
SDI
I4
Q4
AD8021
06587-052
Figure 53. Interconnection Block Diagram for the AD8339
Rev. A | Page 20 of 36
Page 21
AD8339

Combining Phase Compensation and Analog Beamforming

Modern ultrasound machines used for medical applications employ an array of receivers for beamforming, with typical CW Doppler array sizes of up to 64 receiver channels that are phase shifted and summed together to extract coherent information. When used in multiples, the desired signals from each of the channels can be summed to yield a larger signal (increased by a factor N, where N is the number of channels), and the noise is increased by the square root of the number of channels. This technique enhances the signal-to-noise performance of the machine. The critical elements in a beamformer design are the means to align the incoming signals in the time domain and the means to sum the individual signals into a composite whole.
In traditional analog beamformers incorporating Doppler, a V-to-I converter per channel and a crosspoint switch precede passive delay lines used as a combined phase shifter and summing circuit. The system operates at the carrier frequency (RF) through the delay line, which also sums the signals from the various channels, and then the combined signal is down­converted by a very large dynamic range I/Q demodulator.
The resultant I and Q signals are filtered and then sampled by two high resolution analog-to-digital converters. The sampled signals are processed to extract the relevant Doppler information.
Alternatively, the RF signal can be processed by downconversion on each channel individually, phase shifting the downconverted signal, and then combining all channels. The AD8333 and the AD8339 implement this architecture. The downconversion is done by an I/Q demodulator on each channel, and the summed current output is the same as in the delay line approach. The subsequent filters after the I-to-V conversion and the ADCs are similar.
TRANSDUCER
ELEMENTS TE1
THROUG
H TE4
CONVERT US TO
ELECTRICAL
SIGNALS AD8334
E1
The AD8339 integrates the phase shifter, frequency conversion, and I/Q demodulation into a single package and directly yields the baseband signal. Figure 54 is a simplified diagram showing the concept for all four channels. The ultrasound wave (US wave) is received by four transducer elements, TE1 through TE4, in an ultrasound probe and generates signals E1 through E4. In this example, the phase at TE1 leads the phase at TE2 by 45°.

Channel Summing

Figure 55 shows a 16-channel beamformer using AD8339s, AD8021s, and an AD797. The number of channels summed is limited by the current drive capability of the amplifier used to implement the active low-pass filter and current-to-voltage converter. An AD8021 sums up to 16 AD8339 outputs.
In an ultrasound application, the instantaneous phase difference between echo signals is influenced by the transducer-element spacing, the wavelength (λ), the speed of sound in the media, the angle of incidence of the probe to the target, and other factors. In Figure 54, the signals E1 through E4 are amplified 19 dB by the low noise amplifiers in the AD8334; for lower power portable ultrasound applications, the AD8335 can be used instead of the AD8334 for the lowest power per channel. For optimum signal­to-noise performance, the output of the LNA is applied directly to the input of the AD8339. To sum the signals E1 through E4, E2 is shifted 45° relative to E1 by setting the phase code in Channel 2 to 0010, E3 is shifted 90° (0100), and E4 is shifted 135° (0110). The phase aligned current signals at the output of the AD8339 are summed in an I-to-V converter to provide the combined output signal with a theoretical improvement in dynamic range of 6 dB for the four channels.
S1 THROUGH S4
ARE NOW IN
PHASE
S1
19dB LNA
AD8339
PHASE BIT
SETTINGS
CH 1
PHASE SET
FOR 135°
LAG
4 US WAVES
ARE DELAYED
45° EACH WITH
RESP
ECT TO
EACH OTHER
135°
90°
45°
E2
E3
E4
19dB LNA
19dB LNA
19dB LNA
CH 2
PHASE SET
FOR 90°
LAG
CH 3
PHASE SET
FOR 45°
LAG
CH 4
PHASE SET
FOR 0°
LAG
Figure 54. Simplified Example of the AD8339 Phase Shifter
Rev. A | Page 21 of 36
S2
S3
S4
SUMMED
OUTPUT
S1 + S2 + S3 + S4
06587-053
Page 22
AD8339
UP TO 16 AD8339 I OR Q
OUTPUTS AT 3.1mA PEAK
EACH WHEN PHASE SHIFT IS
SET FOR 45°
FIRST ORDER
SUMMING
AMPLIFIER(S)
C1
LPF1
18nF
88kHz
R1
100
+5V
2

3
+
–5V
0.1µF
AD8021
0.1µF
+2.8V BASEBAND
SIGNAL
HPF
1100Hz
C2
R2
1µF
698
FROM OTHER
AD8021
SUMMING AMPLIFIERS
SECOND ORDER
SUMMING AMPLIFIER
LPF2
81kHz
R3
698
C3
5.6nF
2
3
+
R4
0.1µF
AD797
0.1µF
–10V
+10V
06587-155
Figure 55. 16-Channel Beamformer Using the AD8339
Rev. A | Page 22 of 36
Page 23
AD8339

SERIAL INTERFACE

The AD8339 contains a 4-wire, SPI-compatible digital interface (SDI, SCLK, CSB, and SDO). The interface comprises a 20-bit shift register plus a latch. The shift register is loaded MSB first. Phase selection and channel enabling information are contained in the 20-bit word. Figure 56 is a bit map of the data-word, and Figure 57 is the timing diagram.
The shift direction is to the right with MSB first. Because the latch is implemented with D-flip-flops (DFF) and CSB acts as the clock to the latch, any time that CSB is low, the latch flip­flops monitor the shift register outputs. As soon as CSB goes high, the data present in the register is latched. New data can be loaded into the shift register at any time.
Twenty bits are required to program each AD8339; the data is transferred from the register to the latch when CSB goes high. Depending on the data, the corresponding channels are enabled, and the phases are selected. Figure 57 illustrates the timing for two sequentially programmed devices.
Note that the data is latched into the register flip-flops on the rising edge of SCLK. SDO also transitions on the rising edge of SCLK.
TO PHASE SELECT AND
CSB
RSTS
LATCH
BIAS BLOCKS FOR
CHANNEL ENABLES
TO OTHER AD8339s
ENABLE BITS PH SEL CH 1 PH SEL CH 2 PH SEL CH 3 PH SEL CH 4
CH 1 CH 3 CH 4 CH 3 CH 3CH 3 CH 3 CH 4 CH 4CH 4CH 4CH 1 CH 1 CH 1 CH 1 CH 2 CH 2 CH 2 CH 2CH 2
TO CHANNEL 1 PHASE
SELECT BLOCK
MSBLSB MSBLSB MSBLSB MSBLSB MSBLSB
TO CHANNEL 2 PHAS E
SELECT BLOCK

ENBL BITS

When all four ENBL bits are low, only the SPI port is powered up. This feature allows for low power consumption (~13 mW per AD8339 or 3.25 mW per channel) when the CW Doppler function is not needed. Because the SPI port stays alive even with the rest of the chip powered down, the part can be awakened again by simply programming the port. As soon as the CSB signal goes high, the part turns on again. Note that this takes a fair amount of time because of the external capacitor on the LODC pin. It takes ~10 μs to 15 μs with the recommended 0.1 μF decoupling capacitor. The decoupling capacitor on this pin is intended to reduce bias noise contribution in the LO divider chain. The user can experiment with the value of this decoupling capacitor to determine the smallest value without degrading the dynamic range within the frequency band of interest.
The SPI also has an additional pin that can be used in a test mode or as a quick way to reset the SPI and depower the chip. All bits in both the shift register and the latch are reset low when the RSTS pin is pulled above ~1.5 V. For quick testing without the need to program the SPI, the voltage on the RSTS pin should be first pulled high and then pulled to −1.4 V. This enables all four channels in the phase (I = 1, Q = 0) state (all phase bits are 0000); the channel enable bits are all set to 1. This is an untested threshold not intended for continuous operation.
TO CHANNEL 3 PHASE
SELECT BLOCK
TO CHANNEL 4 PHASE
SELECT BLOCK
SHIFT
REGISTER
SCLK
CSB
SCLK
SDI
SDO
SDI
SDO TO NEXT AD8339
06587-054
CH 1 CH 3 CH 4 CH 3 CH 3CH 3 CH 3 CH 4 CH 4CH 4CH 4CH 1 CH 1 CH 1 CH 1 CH 2 CH 2 CH 2 CH 2CH 2
TO OTHER AD8339s
MSBLSB
MSBLSB MSBLSB MSBLSB MSBLSB
Figure 56. Serial Interface Showing the 20-Bit Shift Register and Latch
t
8
t
1
t
2
t
t
t
3
5
6
DATA FOR AD8339 #1
t
4
DATA FOR AD8339 #2
t
7
06587-055
Figure 57. Timing Diagram
Rev. A | Page 23 of 36
Page 24
AD8339

APPLICATIONS INFORMATION

The AD8339 is the key component of a phase shifter system that aligns time-skewed information contained in RF signals. Combined with a variable gain amplifier (VGA) and a low noise amplifier (LNA) as in the AD8332/AD8334/AD8335 VGA family, the AD8339 forms a complete analog receiver for a high performance ultrasound CW Doppler system.

LOGIC INPUTS AND INTERFACES

The SDI, SCLK, SDO, CSB, and RSET pins are CMOS com­patible to 1.8 V. The threshold of the RSTS pin is 1.5 V with a hysteresis of ±0.3 V. Each logic input pin is Schmitt trigger activated, with a threshold centered at ~1.3 V and a hysteresis of ±0.1 V around this value.
The only logic output, SDO, generates a signal that has a logic low level of ~0.2 V and a logic high level of ~1.9 V to allow for easy interfacing to the next AD8339 SDI input. Note that the capacitive loading for the SDO pin should be kept as small as possible (<5 pF), ideally only a short trace to the SDI pin of the next chip. The output slew is limited to approximately ±500 A, which limits the speed when a large capacitor is connected. Excessive values of parasitic capacitance on the SDO pin can affect the timing and loading of data into the SDI input of the next chip.

RESET INPUT

The RSET pin is used to synchronize the LO dividers in AD8339 arrays. Because they are driven by the same internal LO, the four channels in any AD8339 are inherently synchronous. However, when multiple AD8339s are used, it is possible that their dividers wake up in different phase states. The function of the RSET pin is to phase align all the LO signals in multiple AD8339s.
The 4LO divider of each AD8339 can be initiated in one of four possible states: 0°, 90°, 180°, or 270° relative to other AD8339s. The internally generated I/Q signals of each AD8339 LO are always at a 90° angle relative to each other, but a phase shift can occur during power-up between the dividers of multiple AD8339s used in a common array.
The LO divider reset function has been improved in the AD8339 compared with the AD8333. The RSET pin still provides an asynchronous reset of the LO dividers by forcing the internal LO to hang; however, in the AD8339, the LO reset function is fast and does not require a shutdown of the 4LO input signal.
The RSET mechanism also allows the measurement of non­mixing gain from the RF input to the output. The rising edge of the active high RSET pulse can occur at any time; however, the duration should be ≥20 ns minimum. When the RSET pulse transitions from high to low, the LO dividers are reactivated on the next rising edge of the 4LO clock. To guarantee synchronous operation of an array of AD8339s, the RSET pulse must go low on all devices before the next rising edge of the 4LO clock. Therefore, it is best to have the RSET pulse go low on the falling edge of the 4LO clock; at the very least, the t ≥5 ns. An optimal timing setup is for the RSET pulse to go high on a 4LO falling edge and to go low on a 4LO falling edge; this gives 10 ns of setup time even at a 4LO frequency of 50 MHz (12.5 MHz internal LO).
Check the synchronization of multiple AD8339s using the following procedure:
1. Activate at least one channel per AD8339 by setting the
appropriate channel enable bit in the serial interface.
2. Set the phase code of all AD8339 channels to the same
logic state, for example, 0000.
3. Apply the same test signal to all devices to generate a sine
wave in the baseband output and measure the output of one channel per device.
4. Apply an RSET pulse to all AD8339s.
5. Because all the phase codes of the AD8339s should be the
same, the combined signal of multiple devices should be N times greater than a single channel. If the combined signal is less than N times one channel, one or more of the LO phases of the individual AD8339s is in error.
SETUP
should be

LO INPUT

The LO input is a high speed, fully differential analog input that responds to differences in the input levels (and not logic levels). The LO inputs can be driven with a low common-mode voltage amplifier, such as the National Semiconductor® DS90C401 LVDS driver. The graph in Figure 22 shows the range of common-mode voltages. Logic families such as TTL or CMOS are unsuitable for direct coupling to the LO input.
Rev. A | Page 24 of 36
Page 25
AD8339

EVALUATION BOARD

Figure 58 is a photograph of the AD8339 evaluation board; the schematic diagrams are shown in Figure 63, Figure 64, and Figure 65. Four single-ended RF inputs can be phase aligned using the LNA inputs of an AD8334 and the 16 phase adjust­ment options of the AD8339. The RF input signals can be derived from three sources, user selectable by jumpers. Test points enable signal tracing at various circuit nodes.
The AD8339-EVALZ requires bipolar 5 V power supplies. A 3.3 V on-board regulator provides power for the USB and EEPROM devices. The AD8339 is configured using the software provided on the CD included with the evaluation board, or using an external digital pattern generator via the 20-pin flat-cable connector P1.
Figure 58. AD8339 Evaluation Board
Rev. A | Page 25 of 36
06587-157
Page 26
AD8339

CONNECTIONS TO THE BOARD

Table 5 is a list of equipment required to activate the board with suggested test equipment, and Figure 61 shows a typical setup. A green LED glows (signifying that the 5 V power through the USB is present) when the computer is connected via the USB. However, the LED does not signify that the program is running.
Selecting the frequency of the generators is quite simple. As an example, select an RF frequency of interest, for example, 5 MHz. Then select the 4LO frequency, which is four times the RF frequency, in this example, 20 MHz. The output frequency is 0 Hz. Note that the AD8021 outputs are at either a positive or negative dc voltage under this condition of perfect RF and 4LO frequency lock; it is more likely that the signal is slowly varying if the lock is not perfect.
To detect an output, advance or retard the RF frequency by the desired baseband frequency. A baseband frequency of 10 kHz at the output results from an RF frequency of 5.01 MHz or 4.99 MHz.
Table 5. Recommended Equipment List
Description Suggested Equipment PC with Windows® XP Any recent laptop Signal Generators (2) with
Synchronizing Connectors 4-Channel Oscilloscope Tektronix DPO7104 or equivalent Power Supplies Agilent E3631A or equivalent Scope Probes (4) Tektronix P6104 or equivalent
Rohde & Schwarz SMT03 or equivalent

TEST CONFIGURATIONS

The three test configuration options for the AD8339-EVALZ are common input, independent input, and AD9271 drive.

Common Input Signal Drive

Figure 59 is a block diagram showing the simplest way to use the evaluation board, with a common signal applied to all four AD8339 inputs in parallel. Boards are configured this way as shipped. The inputs of each of the channels are connected in common by means of jumpers, as shown in Tab le 6, although they can just as easily be connected to any of the AD8334 LNA outputs. As shown in Figure 64, two pairs of summing amplifiers provide the I and Q outputs so that Channel 1 and Channel 2 can be observed independently of Channel 3 and Channel 4.
Using a common input signal source as shown in Figure 61, the same input is applied to all four channels of the AD8339. To observe an output at the I or Q connectors, simply enable the appropriate channel or channels using the menu shown in Figure 62. For example, if only Channel 1 is enabled and the phases are set to 0°, a waveform is seen at the I1 + I2 and Q1 + Q2 outputs. If Channel 2 is enabled with the phase also set to 0°, the amplitude of the waveforms doubles. If the Channel 1 phase is 0° and the Channel 2 phase is set to 180°, the output becomes zero, because the phases of the two channels cancel each other out.
When using the common input drive mode, it is important that only the top two positions of P4A and P4B be used to avoid shorting the LNA outputs together.

Independent Channel Drive

Independent input mode means that each channel is driven by an LNA. The LNA inputs of the AD8334 can be driven by up to four independent signal generators or from a single generator. If the user chooses this mode, it is important not to connect the LNA inputs in parallel because of the active matching feature. Any standard splitter can be used.

AD9271 Input Drive

Connectors P3A, P3B, P4A, and P4B are configured to route input signals from the AD8334 LNA outputs or from an AD9271 evaluation board. The AD9271 is an octal ultrasound front end with a 12-bit ADC for each channel. When using an AD9271 as an input drive, consult the AD9271 data sheet for setup details.
The AD9271 evaluation board is attached to the AD8339 by inserting the three plastic standoffs into the three guide holes in the AD8339-EVALZ board; all the jumpers in P3 and P4 are removed. The bottom connectors of the AD9271 board engage P3 and P4 and route the LNA outputs of the AD9271 to the AD8339. Figure 60 is a photograph of the two boards attached.
Table 6. P3, P4 Input Jumper Configuration
Common Input Independent Input
P4A-1 to P4B-1, top two
positions (2)
RF12N, RF12P, RF23N, RF23P,
RF34N, RF34P
P3A-1 to P3B-1, P4A-1 to P4B-1
P3A-1 to P3B-1, P4A-1 to P4B-1, all positions (8)
Rev. A | Page 26 of 36
Page 27
AD8339
AD8334
COMMON
SIGNAL
PATH
LNA AD8339
CH 1 RF
CH 2 RF
CH 3 RF
CH 4 RF
I1
Q1
I2
Q2
I3
Q3
I4
Q4
I TO V
I TO V
I TO V
I TO V
Q1 + Q2
I1 + I2
I3 + I4
Q3 + Q
4
06587-057
Figure 59. AD8339 Test Configuration—Common Input Signal Drive
06587-159
Figure 60. AD8339-EVALZ with AD9271 Evaluation Board Attached as Input Source
Rev. A | Page 27 of 36
Page 28
AD8339
TOP: SIGNAL GENERATOR FO R 4LO INPUT (FOR EX AMPLE, 20M Hz, 1Vp-p ) BOTTOM : SIGNAL GENERATOR FO R RF INPUT ( FOR EXAMPL E, 5.01MHz )
SYNCHRONIZE
GENERATORS
CABLE
USB
PERSONAL COMPUTER
+5V
POWER SUPPLY
–5V
4LO INPUT
Figure 61. AD8339-EVALZ Typical Test Setup
Rev. A | Page 28 of 36
OUTPUTS
06587-059
Page 29
AD8339

Using the SPI Port

Channel and phase selection are accessed via the SPI port on the AD8339, and the evaluation board provides two means of access. If it is desired to exercise the SPI input with custom waveforms, the SDI, SCLK, and CSB pins are available at the auxiliary connector P1. A digital pattern generator can be programmed in conformance with the timing diagram shown in Figure 57.
The most convenient way to select channels and phase delays is through the USB port of a PC using the executable program provided on the CD or at the Analog Devices, Inc., website. Copy the .EXE and .MSI files into the same folder on the PC. Double-click the .EXE file to install the program and place a shortcut on the desktop. Double-clicking the desktop icon opens the control menu, as shown in Figure 62.
The menu consists of an array of options that are self-explanatory. Channels are enabled or disabled by selecting the channels in the Channel Enable list, and the 16 phase options are selected from the list box for each of the channels.

Hardwired Jumpers

Hardwired jumpers provide for interconnection of channels and as a means for measuring output voltages at various strategic nodes (see Tab le 7).
As shipped, the evaluation board is configured to connect all the AD8339 RF inputs to a single LNA output. In this configur­ation, the phases of the four channels can be shifted throughout the full range and the outputs can be viewed on a multichannel scope using one of the channels as a reference. To operate all the LNA channels independently, it is only necessary to move the input shorting jumpers to the channel RF outputs.
06587-060
Figure 62. SPI Software Control Menu
Table 7. Jumper and Header List
Jumper, Header Description
CSB Connects the chip select input to the connector or the USB inputs—normally connected to USB (test) CSBG Grounds the CSB input—shipped omitted EN12, EN34 Enables or disables Channel 1 through Channel 4—boards shipped enabled I1234 Sums all four I-channel current outputs together—shipped omitted Q1234 Sums all four Q-channel current outputs together—shipped omitted RF1 to RF4 Test points for the LNA outputs—a differential probe fits these RSTS Resets the SPI input—shipped omitted RSET Resets the local oscillator input—shipped omitted SCLK Connects the serial clock input to the connector or to the USB inputs—normally connected to USB (test) SDI Connects the serial data input to the connector or to the USB input—normally connected to USB (test) SLKG Grounds the serial clock input—shipped omitted 4LO Test pins for the 4LO level shifter output—a differential probe fits these
Rev. A | Page 29 of 36
Page 30
AD8339
120nH
IN2
LON2
LOP2
LOP3
LON3
C61
0.1µF
IN3
L8
120nH
5V
L7
IN2S
RF2
RF3
IN3S
CFB2
18nF
RFB2
274
R44 20
R43 20
L16
120 nH
L17
120nH
C46
0.1µF
R46 20
R45 20
RFB3
274
CFB3
18nF
C10
22pF
C88
0.1µF
IN1
C60
0.1µF
C8
22pF
0.1µF
0.1µF
0.1µF
C87
0.1µF
0.1µF
0.1µF
IN4
C43
C44
C45
C47
C48
LOP1 LON1
RF1
60
21
RFB4 274
COM1X
COM4 X
20
R47
R50 20
C53
0.1µF
C54
0.1µF
57
58
59
VIP1
LOP1
LON1
U1
AD8334
LON4
LOP4
VIP 4
24
23
22
C49
0.1µF
C50
0.1µF
R48 20
RF4
C6
22pF
63
PIN 1
18
C62
0.1µF
C12
22pF
CFB1
RFB1
18nF
274
C68
0.1µF
61
62
INH1
19
INH4
CFB4 18nF
LMD1
LMD4
20
C55
0.1µF
COM1
COM4
L10
120nH
C67
0.1µF
IN1S
64
COM2
1
INH2
2
LMD2
IDENTIFIER
3
COM2X
4
LON2
5
LOP2
6
VIP2
7
VIN2
8
VPS2
9
VPS3 NC
10
VIN3 COM34
11
VIP3
12
LOP3
13
LON3
14
COM3X
15
LMD3
16
INH3
COM3
17
L9
120nH
IN4S
R49 20
56
VIN1
VIN4
25
L12
120nH
5V
55
26
VPS1
VPS4
R64
L13 120nH
R63
0
0
54
GAIN12
GAIN34
27
C85
0.1µF
C86
0.1µF
0.1µF
0.1µF
C66
53
C63
EN
EN12 EN34 DIS
51
52
EN12
HILO
29
C56
0.1µF
EN34
VCM 4
30
CLMP12
CLMP34
28
5V
C58
0.1µF
50
31
VCM1
VCM 3
EN
DIS
VCM2
C57
0.1µF
5V
49
COM12
VOH1
VOL1
VPS12
VOL2
VOH2
COM12
MODE
VOH3
VOL3
VPS34
VOL4
VOH4
COM34
NC
32
C59
0.1µF
48
47 NC
46 NC
45
44 NC
43 NC
42
41
40
39
38 NC
37
36
35 NC
34 NC
33
C65
0.1µF
C64
0.1µF
L14
120nH
120nH
5V
L15
5V
LON4
LOP4
06587-061
Figure 63. Schematic—LNA Section
Rev. A | Page 30 of 36
Page 31
AD8339
R1
R3
1k
1kR41k
CSB
CSBG
CSB
SCLK
SLKG
SCLK
5.23k
2.8 k
4.22k
5.23k
2.8 k
4.22k
1
P4
5V
R68
R72
R66
5V
R67
R70
R65
P 1
RF
RF1 2 P
2
R610R62
TP_RF1P
10
SDI
RSTS
R32
R36
2.8k
5.23k
5V
R31
R30
2.8k
4.22 k
R71
2.8k
RF2N
RF2P
VPOS
0.1 µF
R69
2.8k
RF3P
RF3N
VPOS
RF1 N
3
0
74
912 6 3912
SLKG
CSBG
C16
RF1 2 N
4
TP_RF1N
1
RF
2
RF2P
3
COMM
4
COMM
5
SCLK
6
CSB
7
VPOS
8
VPOS
9
RF3P
10
RF3N Q3O P
VPOS
C17
SDO
0.1 µF
SDO-T P
RF2 P
R59 0
6
RF2N
RF23N
78
RF23P
56
R60 0
TP_RF2P
RF3P
TP_RF2N
1
2
3
403839
RSTS
2
N
PIN 1 IDENTIFIER
11
SDO
R58 0
TP_RF3P
SDI
SDO
12
5V
N 3
RF
9
R57 0
SDI
RF1P RF1N
RF1P
RF4P
13
R34
2.8k
RF3 4 P
RF3 4 N
10
11
12
R56 0
TP_RF3N
TP_RF4P
VPIS
VPOS
C1
0.1µF
37
36
RF1N
COMM
DUT
AD8339
RF4N
COMM
14
15
C18
0.1 µF
R33
2.8k
P5 COMMON 1 LNA TO 4 RF INPUTS
R51 0
TP_RF4N
17410
2
5V
4
6
8
SDO
10
12
14
16
18
20
L2
120n H
C31
0.1µF RSET
35
34
RSET
VPOS
VPOS
LODC
16
17
C19
0. 1µF
VPOS
R36
5.23k
R30
4.22 k
ENGAGES WIT H CONNECTOR ON AD9271 EVAL B OAR D
P3
P1
12
3
5
7
9
11
13
15
17
19
5V
VNIS
33
32
31
I1OP
I4OP
18
Q2OP
Q1OP
VNEG
VPOS
VPOS
4LOP
4LON
VNEG
VNEG
Q4OP
VNEG
19
20
5V
VNEG
COM PONENT S SHOWN IN
GRAY ARENOT INSTALLED
VNEG
I2OP
I3OP
L1
120n H
R6 0
R5 0
C27
0.1µF
30
29
28
27
26
25
24
23
22
21
C20
0. 1µF
VPOS
VNEG
–5V
Q1OP
R21
0
R20
0
R19
0
R18
0
C30
0.1µF
4LO
R8 0
R7 0
Q4OP
I4OP
C29
0.1µF
I1OP
R16
­U3
AD8021
+
4
-
U4
AD8021
+
4
VPOS
4
­U5
AD8021
+
4
­U6 AD 8021
+
4
5V
1
5
7
787
C83
2. 2nF
6
5
C84 5PF
C26
0.1µF R13
787
C81
2. 2nF
6
5
C82 5PF
R28
3.48k
R37
1.5k
R10
787
C79
2. 2nF
6
5
C80 5PF
C22
0.1µF R42
787
C32
2. 2nF
6
5
C33 5PF
C52
0.1µF
U7 DS90 C401M
7
6
–VA
–VA
–VA
–VA
0. 1µF
C28
R17
0
R14
0
R11
0
R38
0
R54
49. 9
Q1 + Q2
I1 + I2
LOP
I3 + I4
Q3 + Q4
C25
0. 1µF
VA
R15
0
R12
100
VA
R2 0
VA
0
I1234Q1234
R27
VA
R9 0
0. 1µF
C23
0. 1µF
DS90 C401M
C21
0. 1µF
C51
0.1 µ F
0.1 µF
C34
C24
U7
8
2
1
8
3
27
1
8
3
3
2
27
1
8
3
27
1
8
3
PROU TP1
PROU TP2
PROUTN1
FR OM A D8334 LNAS
PROU TP3
PROUTN2
PROU TP4
PROUTN3
PROUTN4
06587-062
Figure 64. Schematic—IQ Demodulator and Phase Shifter
Rev. A | Page 31 of 36
Page 32
AD8339
5V
GND
C9
L11
1µF
120nH
10V
+
C77
0.1µF
3.3V
C78
0.1µF
W3
312
IN
OUT
A6
OUT
TAB
ADP3339AKCZ-3.3
1
RDY0/SLRD
NC
2
RDY1/SLWR
5V
0.1µF
C2 12pF
0.1µF
3.3V
0.1µF
VCC
WP
SCL
SDA
C69
C70
C71
R39
10k
8
7
6
5
NC
NC
3. 3V
3
4
5
6
7
8
9
10
11
12
13
14
AVCC
XTALOUT
XTALIN
AGND
AVCC
DPLUS
DMINUS
AGND
VCC
GND
IFCLK/P E0/TOUT
RESERVED
15 16
R52
22.1k
R53
22.1k
12 pF
A7
USB
TYPE B
24LC00/P
C3
GND
Y1
24MHz
D+
4
Z1
23
1
499
CR1
VBUS
R55
1
2
3
4
3.3V
D–
0.1µF
A0
A1
A2
VSS
3.3V
C72
5VS
RED ORGGRN BLUE
–5VS
PLUS
MINUS
C14
10µF
25V
C38
0.1µF
GND
+
C13
10µF
+
25V
120nH
3.3V
L6
5V
C7
0.1 µF
120nH
C37
0.1µF
L5
–5V
NC NC NC NC NC NC
VCC
GND
+
C11
10µF
25V
L4
120nH
C36
0.1µF
50 4956 55 5154 53 52
PD7/FD15
PD6/FD14
CLKOUT /PE1/T1OUT
CY7C68013A-56LFXC
SCL
SDA
PB0/FD0
VCC
17 18 19 21
NC
C73
0.1µF
PB1/FD1
NC
PB2/FD2
20
NC
3. 3V
VAS –VAS
C15
10µF
+
25V
L3
120nH
C35
0.1µF
VA
PD5/FD13
–VA
48 47 4346 45 44
PD4/FD12
PD3/FD11
U2
PB4/FD4
22
R22
0
R23
0
R24
0
R25
0
R26
0
23 24
NC
PB5/FD5
NC
PB3/FD3
NC
P2
–VAS
VAS
–5VS
5VS
C5
22pF
NC NC NC
PD1/FD9
PD2/FD10
PB6/FD6
PB7/FD7
25 26 27
NC
NC
3.3V
R41
100k
VCC
PD0/FD8
WAKEUP
RESET#
GND
PA7/FLAGD/ SLCS
PA6/PKTEND
PA5/FIF OADR1
PA4/FIF OADR0
PA3/WU2
PA2/SLOE
PA1/INT1#
PA0/INT0#
VCC
CTL2/FLAGC
CTL1/FLAGB
CTL0/FLAGA
GND
VCC
GND
28
C74
0.1µF
3.3V
C76
0.1µF
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
NC
NC
NC
NC
NC
NC
NC
BLK TEST
LOOP
(9)
3. 3V
R40 100k
C4 22pF
CSB (SHT2)
SCLK (SHT2)
SDI (SHT2)
C75
0.1µF
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
3.3V
06587-063
Figure 65. Schematic—USB
Rev. A | Page 32 of 36
Page 33
AD8339

AD8339-EVALZ ARTWORK

Figure 66 through Figure 69 show the artwork for the AD8339-EVALZ.
06587-064
Figure 66. AD8339-EVALZ Component Side Copper
Figure 67. AD8339-EVALZ Wiring Side Copper
Rev. A | Page 33 of 36
6587-065
Page 34
AD8339
06587-066
Figure 68. AD8339-EVALZ Component Side Silkscreen
06587-067
Figure 69. AD8339-EVALZ Assembly
Rev. A | Page 34 of 36
Page 35
AD8339

OUTLINE DIMENSIONS

PIN 1
INDICATOR
1.00
0.85
0.80
12° MAX
SEATING PLANE
6.00
BSC SQ
TOP
VIEW
0.80 MAX
0.65 TYP
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
5.75
BSC SQ
0.20 REF
0.05 MAX
0.02 NOM
0.60 MAX
0.50
BSC
0.50
0.40
0.30
COPLANARITY
0.08
0.60 MAX
31
30
EXPOSED
(BOTTOM VIEW)
21
20
40
1
PAD
10
11
4.50 REF
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
PIN 1 INDICATOR
4.25
4.10 SQ
3.95
0.25 MIN
072108-A
Figure 70. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option
AD8339ACPZ AD8339ACPZ-R7 AD8339ACPZ-RL AD8339-EVALZ
1
Z = RoHS Compliant Part.
1
−40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40-1
1
−40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40-1
1
−40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40-1
1
Evaluation Board
Rev. A | Page 35 of 36
Page 36
AD8339
NOTES
©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06587-0-2/09(A)
Rev. A | Page 36 of 36
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