Datasheet AD8331, AD8332, AD8334 Datasheet (ANALOG DEVICES)

Ultralow Noise VGAs with

VINV

V

Preamplifier and Programmable R

FEATURES

Ultralow noise preamplifier

Voltage noise = 0.74 nV/√Hz
Current noise = 2.5 pA/√Hz

3 dB bandwidth

AD8331: 120 MHz
AD8332, AD8334: 100 MHz

Low power

AD8331: 125 mW/channel
AD8332, AD8334: 145 mW/channel

Wide gain range with programmable postamp

−4.5 dB to +43.5 dB

+7.5 dB to +55.5 dB
Low output-referred noise: 48 nV/√Hz typical
Active input impedance matching
Optimized for 10-bit/12-bit ADCs
Selectable output clamping level
Single 5 V supply operation
AD8332 and AD8334 available in lead frame chip scale package

APPLICATIONS

Ultrasound and sonar time-gain controls
High performance AGC systems
I/Q signal processing
High speed, dual ADC drivers

GENERAL DESCRIPTION

The AD8331/AD8332/AD8334 are single-, dual-, and quad­channel ultralow noise, linear-in-dB, variable gain amplifiers
(VGAs). Optimized for ultrasound systems, they are usable as a
low noise variable gain element at frequencies up to 120 MHz.

Included in each channel are an ultralow noise preamplifier
(LNA), an X-AMP® VGA with 48 dB of gain range, and a
selectable gain postamplifier with adjustable output limiting.
The LNA gain is 19 dB with a single-ended input and
differential outputs. Using a single resistor, the LNA input
impedance can be adjusted to match a signal source without
compromising noise performance.

The 48 dB gain range of the VGA makes these devices suitable
for a variety of applications. Excellent bandwidth uniformity is
maintained across the entire range. The gain control interface
provides precise linear-in-dB scaling of 50 dB/V for control
voltages between 40 mV and 1 V. Factory trim ensures excellent
part-to-part and channel-to-channel gain matching.

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

AD8331/AD8332/AD8334

FUNCTIONAL BLOCK DIAGRAM

IPLOPLON

LNA

INH

LMD

+

19dB

–

LNA VCM

BIAS

AD8331/AD8332/AD8334

–

48dB

ATTENUATOR

+

VGA BIAS AND

INTERPOL ATOR

Figure 1. Signal Path Block Diagram

60

50

40

30

20

GAIN (dB)

10

0

–10

100k 1M 10M 100M 1G

V

GAIN

V

GAIN

V

GAIN

V

GAIN

V

GAIN

V

GAIN

FREQUENCY (Hz)

Figure 2. Frequency Response vs. Gain

Differential signal paths result in superb second- and third­order distortion performance and low crosstalk.

The VGA’s low output-referred noise is advantageous in driving
high speed differential ADCs. The gain of the postamplifier can
be pin selected to 3.5 dB or 15.5 dB to optimize gain range and
output noise for 12-bit or 10-bit converter applications. The
output can be limited to a user-selected clamping level,
preventing input overload to a subsequent ADC. An external
resistor adjusts the clamping level.

The operating temperature range is −40°C to +85°C. The
AD8331 is available in a 20-lead QSOP package, the AD8332 is
available in 28-lead TSSOP and 32-lead LFCSP packages, and
the AD8334 is available in a 64-lead LFCSP package.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

= 1V

= 0.8V

= 0.6V

= 0.4V

= 0.2V

= 0V

V

ENB

CM

MID

3.5dB/15. 5dB

21dB

GAIN

CONTROL

INTERFACE

GAIN

PA

CLAMP

HIGH GAIN

MODE

HILO

VOH

VOL

RCLMP

03199-002

IN

03199-001

AD8331/AD8332/AD8334

TABLE OF CONTENTS

Features .............................................................................................. 1

Variable Gain Amplifier ............................................................ 27

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ...........................8

Typical Performance Characteristics........................................... 12

Test Circ uit s .....................................................................................20

Measurement Considerations................................................... 20

Theory of Operation ...................................................................... 24

Overview...................................................................................... 24

Low Noise Amplifier (LNA)..................................................... 25

Postamplifier............................................................................... 28

Applications..................................................................................... 30

LNA—External Components.................................................... 30

Driving ADCs............................................................................. 32

Overload...................................................................................... 32

Optional Input Overload Protection. ...................................... 33

Layout, Grounding, and Bypassing.......................................... 33

Multiple Input Matching ........................................................... 33

Disabling the LNA...................................................................... 33

Ultrasound TGC Application................................................... 34

High Density Quad Layout ....................................................... 34

Outline Dimensions .......................................................................39

Ordering Guide .......................................................................... 40

Rev. E | Page 2 of 40

AD8331/AD8332/AD8334

REVISION HISTORY

4/06—Rev. D to Rev. E

Added AD8334................................................................... Universal

Changes to Figure 1 and Figure 2....................................................1

Changes to Table 1 ............................................................................4

Changes to Table 2 ............................................................................7

Changes to Figure 7 through Figure 9 and Figure 12.................12

Changes to Figure 13, Figure 14, Figure 16, and Figure 18.......13

Changes to Figure 23 and Figure 24 .............................................14

Changes to Figure 25 through Figure 27......................................15

Changes to Figure 31 and Figure 33 through Figure 36.............16

Changes to Figure 37 through Figure 42......................................17

Changes to Figure 43, Figure 44, and Figure 48..........................18

Changes to Figure 49, Figure 50, and Figure 54..........................19

Inserted Figure 56 and Figure 57 ..................................................20

Inserted Figure 58, Figure 59, and Figure 61...............................21

Changes to Figure 60 ......................................................................21

Inserted Figure 63 and Figure 65 ..................................................22

Changes to Figure 64 ......................................................................22

Moved Measurement Considerations Section ............................2

Inserted Figure 67 and Figure 68 ..................................................23

Inserted Figure 70 and Figure 71 ..................................................24

Change to Figure 72........................................................................24

Changes to Figure 73 and Low Noise Amplifier Section ...........25

Changes to Postamplifier Section .................................................28

Changes to Figure 80 ......................................................................29

Changes to LNA—External Components Section......................30

Changes to Logic Inputs—ENB, MODE, and HILO Section....31

Changes to Output Decoupling and Overload Sections ............32

Changes to Layout, Grounding, and Bypassing Section............33

Changes to Ultrasound TGC Application Section......................34

Added High Density Quad Layout Section .................................34

Inserted Figure 94............................................................................38

Updated Outline Dimensions........................................................39

Changes to Ordering Guide...........................................................40

3/06—Rev. C to Rev. D

Updated Format .................................................................Universal

Changes to Features and General Description..............................1

Changes to Table 1 ............................................................................3

Changes to Table 2 ............................................................................6

Changes to Ordering Guide...........................................................34

11/03—Rev. B to Rev. C

Addition of New Part......................................................... Universal

Changes to Figures............................................................. Universal

Updated Outline Dimensions........................................................32

5/03—Rev. A to Rev. B

Edits to Ordering Guide.................................................................32

Edits to Ultrasound TGC Application Section ...........................25

Added Figure 71, Figure 72, and Figure 73..................................26

Updated Outline Dimensions........................................................31

2/03—Rev. 0 to Rev. A

0

Edits to Ordering Guide.................................................................32

Rev. E | Page 3 of 40

AD8331/AD8332/AD8334

SPECIFICATIONS

TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RFB = 280 Ω, CSH = 22 pF, f = 10 MHz, R

−4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.

Table 1.

Parameter Conditions Min Typ Max Unit

LNA CHARACTERISTICS

Gain Single-ended input to differential output 19 dB
Input to output (single ended) 13 dB

Input Voltage Range AC-coupled ±275 mV

Input Resistance RFB = 280 Ω 50 Ω
R
R
R
R

= 412 Ω 75 Ω

FB

= 562 Ω 100 Ω

FB

= 1.13 kΩ 200 Ω

FB

= ∞ 6 kΩ

FB

Input Capacitance 13 pF

Output Impedance Single-ended, either output 5 Ω

−3 dB Small Signal Bandwidth V

= 0.2 V p-p 130 MHz

OUT

Slew Rate 650 V/μs

Input Voltage Noise RS = 0 Ω, HI or LO gain, RFB = ∞, f = 5 MHz 0.74 nV/√Hz

Input Current Noise RFB = ∞, HI or LO gain, f = 5 MHz 2.5 pA/√Hz

Noise Figure f = 10 MHz, LOP output

Active Termination Match RS = RIN = 50 Ω 3.7 dB
Unterminated RS = 50 Ω, RFB = ∞ 2.5 dB

Harmonic Distortion @ LOP1 or LOP2 V

= 0.5 V p-p, single-ended, f = 10 MHz

OUT

HD2 −56 dBc
HD3 −70 dBc

Output Short-Circuit Current Pin LON, Pin LOP 165 mA
LNA + VGA CHARACTERISTICS

−3 dB Small Signal Bandwidth V

= 0.2 V p-p

OUT

AD8331 120 MHz
AD8332, AD8334 100 MHz

−3 dB Large Signal Bandwidth V

= 2 V p-p

OUT

AD8331 110 MHz
AD8332, AD8334 90 MHz

Slew Rate

AD8331 LO gain 300 V/μs
HI gain 1200 V/μs
AD8332, AD8334 LO gain 275 V/μs

HI gain 1100 V/μs
Input Voltage Noise RS = 0 Ω, HI or LO gain, RFB = ∞, f = 5 MHz 0.82 nV/√Hz
Noise Figure V

= 1.0 V

GAIN

Active Termination Match RS = RIN = 50 Ω, f = 10 MHz, measured 4.15 dB
R

= RIN = 200 Ω, f = 5 MHz, simulated 2.0 dB

S

Unterminated RS = 50 Ω, RFB = ∞, f = 10 MHz, measured 2.5 dB

R

= 200 Ω, RFB = ∞, f = 5 MHz, simulated 1.0 dB

S

Output-Referred Noise

AD8331 V
V
AD8332, AD8334 V

V

= 0.5 V, LO gain 48 nV/√Hz

GAIN

= 0.5 V, HI gain 178 nV/√Hz

GAIN

= 0.5 V, LO gain 40 nV/√Hz

GAIN

= 0.5 V, HI gain 150 nV/√Hz

GAIN

Output Impedance, Postamplifier DC to 1 MHz 1 Ω

= ∞, CL = 1 pF, VCM pin floating,

CLMP

Rev. E | Page 4 of 40

AD8331/AD8332/AD8334

Parameter Conditions Min Typ Max Unit

Output Signal Range, Postamplifier RL ≥ 500 Ω, unclamped, either pin VCM ± 1.125 V

Differential 4.5 V p-p

Output Offset Voltage V

AD8331 Differential −50 ±5 +50 mV
Common mode −125 −25 +100 mV
AD8332, AD8334 Differential −20 ±5 +20 mV

Common mode −125 –25 +100 mV
Output Short-Circuit Current 45 mA
Harmonic Distortion V

AD8331

HD2 f = 1 MHz −88 dBc
HD3 −85 dBc
HD2 f = 10 MHz −68 dBc
HD3 −65 dBc

AD8332, AD8334

HD2 f = 1 MHz −82 dBc
HD3 −85 dBc
HD2 f = 10 MHz −62 dBc

HD3 −66 dBc
Input 1 dB Compression Point V
Two-Tone Intermodulation Distortion (IMD3)

AD8331 V
V
AD8332, AD8334 V
V

Output Third-Order Intercept

AD8331 V
V
AD8332, AD8334 V

V

Channel-to-Channel Crosstalk (AD8332, AD8334) V
Overload Recovery V
Group Delay Variation 5 MHz < f < 50 MHz, full gain range ±2 ns

ACCURACY

Absolute Gain Error

2

0.10 V < V

0.95 V < V
Gain Law Conformance

3

Channel-to-Channel Gain Matching 0.1 V < V

GAIN CONTROL INTERFACE (Pin GAIN)

Gain Scaling Factor 0.10 V < V
Gain Range LO gain −4.5 to +43.5 dB

HI gain 7.5 to 55.5 dB

Input Voltage (V

) Range 0 to 1.0 V

GAIN

Input Impedance 10 MΩ
Response Time 48 dB gain change to 90% full scale 500 ns

COMMON-MODE INTERFACE (PIN VCMn)

Input Resistance

4

Output CM Offset Voltage VCM = 2.5 V −125 −25 +100 mV
Voltage Range V

= 0.5 V

GAIN

= 0.5 V, V

GAIN

= 0.25 V, V

GAIN

= 0.72 V, V

GAIN

= 0.5 V, V

GAIN

= 0.72 V, V

GAIN

= 0.5 V, V

GAIN

= 0.5 V, V

GAIN

= 0.5 V, V

GAIN

= 0.5 V, V

GAIN

= 0.5 V, V

GAIN

= 0.5 V, V

GAIN

= 1.0 V, VIN = 50 mV p-p/1 V p-p, f = 10 MHz 5 ns

GAIN

0.05 V < V

0.1 V < V

GAIN

GAIN

= 1 V p-p, HI gain

OUT

= 1 V p-p, f = 1 MHz to 10 MHz 1 dBm

OUT

= 1 V p-p, f = 1 MHz −80 dBc

OUT

= 1 V p-p, f = 10 MHz −72 dBc

OUT

= 1 V p-p, f = 1 MHz −78 dBc

OUT

= 1 V p-p, f = 10 MHz −74 dBc

OUT

= 1 V p-p, f = 1 MHz 38 dBm

OUT

= 1 V p-p, f = 10 MHz 33 dBm

OUT

= 1 V p-p, f = 1 MHz 35 dBm

OUT

= 1 V p-p, f = 10 MHz 32 dBm

OUT

= 1 V p-p, f = 1 MHz −98 dB

OUT

< 0.10 V −1 +0.5 +2 dB

GAIN

< 0.95 V −1 ±0.3 +1 dB

GAIN

< 1.0 V −2 −1 +1 dB

GAIN

< 0.95 V ±0.2 dB
< 0.95 V ±0.1 dB

< 0.95 V 48.5 50 51.5 dB/V

GAIN

1

Current limited to ±1 mA 30 Ω

= 2.0 V p-p 1.5 to 3.5 V

OUT

Rev. E | Page 5 of 40

AD8331/AD8332/AD8334

Parameter Conditions Min Typ Max Unit

ENABLE INTERFACE

(PIN ENB, PIN ENBL, PIN ENBV)
Logic Level to Enable Power 2.25 5 V
Logic Level to Disable Power 0 1.0 V

Input Resistance Pin ENB 25 kΩ
Pin ENBL 40 kΩ
Pin ENBV 70 kΩ

Power-Up Response Time V
V
HILO GAIN RANGE INTERFACE (PIN HILO)

Logic Level to Select HI Gain Range 2.25 5 V

Logic Level to Select LO Gain Range 0 1.0 V

Input Resistance 50 kΩ
OUTPUT CLAMP INTERFACE

(PIN RCLMP; HI OR LO GAIN)

Accuracy

HILO = LO R
HILO = HI R

MODE INTERFACE (PIN MODE)

Logic Level for Positive Gain Slope 0 1.0 V

Logic Level for Negative Gain Slope 2.25 5 V

Input Resistance 200 kΩ
POWER SUPPLY (PIN VPS1, PIN VPS2,

PIN VPSV, PIN VPSL, PIN VPOS)

Supply Voltage 4.5 5.0 5.5 V

Quiescent Current per Channel

AD8331 20 25 mA
AD8332, AD8334 20 29 mA

Power Dissipation per channel No signal

AD8331 125 mW
AD8332, AD8334 145 mW

Power-Down Current

AD8332 (VGA and LNA Disabled) 50 300 600 μA
AD8331 (VGA and LNA Disabled) 50 240 400 μA

LNA Current

AD8331 (ENBL) Each channel 7.5 11 15 mA
AD8332, AD8334 (ENBL) Each channel 7.5 12 15 mA

VGA Current

AD8331 (ENBV) 7.5 14 20 mA
AD8332, AD8334 (ENBV) 7.5 17 20 mA

PSRR V

1

All dBm values are referred to 50 Ω.

2

The absolute gain refers to the theoretical gain expression in Equation 1.

3

Best-fit to linear-in-dB curve.

4

The current is limited to ±1 mA typical.

= 30 mV p-p 300 μs

INH

= 150 mV p-p 4 ms

INH

= 2.74 kΩ, V

CLMP

= 2.21 kΩ, V

CLMP

= 1 V p-p (clamped) ±50 mV

OUT

= 1 V p-p (clamped) ±75 mV

OUT

= 0 V, f = 100 kHz −68 dB

GAIN

Rev. E | Page 6 of 40

AD8331/AD8332/AD8334

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Voltage

Supply Voltage (VPSn, VPSV, VPSL, VPOS) 5.5 V
Input Voltage (INHn) VS + 200 mV
ENB, ENBL, ENBV, HILO Voltage VS + 200 mV
GAIN Voltage 2.5 V

Power Dissipation

AR Package

1

0.96 W
CP-20 Package (AD8331) 1.63 W
CP-32 Package (AD8332) 1.97 W
RQ Package

1

0.78 W
CP-64 Package (AD8334) 0.91 W

Temperature

Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C

θ

JA

AR Package
CP-20 Package
CP-32 Package
RQ Package
CP-64 Package

1

Four-layer JEDEC board (2S2P).

2

Exposed pad soldered to board, nine thermal vias in pad—JEDEC, 4-layer

board J-STD-51-9.

3

Exposed pad soldered to board, 25 thermal vias in pad—JEDEC, 4-layer

board J-STD-51-9.

1

2

2

1

3

68°C/W
40°C/W
33°C/W
83°C/W

24.2°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. E | Page 7 of 40

AD8331/AD8332/AD8334

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

LMD

INH

VPSL

LON

LOP

COML

VIP

VIN

MODE

GAIN

1

2

3

4

5

6

(Not to Scale)

7

8

9

10

PIN 1
INDICAT OR

AD8331

TOP VIEW

20

19

18

17

16

15

14

13

12

11

COMM

ENBL

ENBV

COMM

VOL

VOH

VPOS

HILO

RCLMP

VCM

03199-003

Figure 3. 20-Lead QSOP Pin Configuration (AD8331)

Table 3. 20-Lead QSOP Pin Function Description (AD8331)

Pin No. Mnemonic Description

1 LMD LNA Signal Ground
2 INH LNA Input
3 VPSL LNA 5 V Supply
4 LON LNA Inverting Output
5 LOP LNA Noninverting Output
6 COML LNA Ground
7 VIP VGA Noninverting Input
8 VIN VGA Inverting Input
9 MODE Gain Slope Logic Input
10 GAIN Gain Control Voltage
11 VCM Common Mode Voltage
12 RCLMP Output Clamping Level
13 HILO Gain Range Select (HI or LO)
14 VPOS VGA 5 V Supply
15 VOH Noninverting VGA Output
16 VOL Inverting VGA Output
17 COMM VGA Ground
18 ENBV VGA Enable
19 ENBL LNA Enable
20 COMM VGA Ground

Rev. E | Page 8 of 40

AD8331/AD8332/AD8334

1

LMD2

INH2

VPS2

LON2

LOP2

COM2

VIP2

VIN2

VCM2

GAIN

RCLMP

VOH2

VOL2

COMM

2

3

4

5

6

7

(Not to Scale)

8

9

10

11

12

13

14

PIN 1
INDICATO R

AD8332

TOP VIEW

Figure 4. 28-Lead TSSOP Pin Configuration (AD8332)

28

LMD1

27

INH1

26

VPS1

25

LON1

24

LOP1

23

COM1

22

VIP1

21

VIN1

20

VCM1

19

HILO

18

ENB

17

VOH1

16

VOL1

15

VPSV

03199-004

LON1

VPS1

INH1

LMD1

LMD2

INH2

VPS2

LON2

NC = NO CONNECT

1

2

3

4

5

6

7

8

LOP1

COM1

PIN 1
INDICATO R

LOP2

COM2

VIP1

VIN1

VCM1

29303132 28 252627

AD8332

TOP VIEW

(Not to Scale)

VIP2

VIN2

VCM2

HILO

ENBL

ENBV

COMM

24

VOH1

23

VOL1

22

VPSV

21

20

NC

19

VOL2

18

VOH2

17

14139121110

15 16

GAIN

MODE

COMM

RCLMP

03199-005

Figure 5. 32-Lead LFCSP Pin Configuration (AD8332)

Table 4. 28-Lead TSSOP Pin Function Description (AD8332)

Pin No. Mnemonic Description

1 LMD2 CH2 LNA Signal Ground
2 INH2 CH2 LNA Input
3 VPS2 CH2 Supply LNA 5 V
4 LON2 CH2 LNA Inverting Output
5 LOP2 CH2 LNA Noninverting Output
6 COM2 CH2 LNA Ground
7 VIP2 CH2 VGA Noninverting Input
8 VIN2 CH2 VGA Inverting Input
9 VCM2 CH2 Common-Mode Voltage
10 GAIN Gain Control Voltage
11 RCLMP Output Clamping Resistor
12 VOH2 CH2 Noninverting VGA Output
13 VOL2 CH2 Inverting VGA Output
14 COMM VGA Ground (Both Channels)
15 VPSV VGA Supply 5 V (Both Channels)
16 VOL1 CH1 Inverting VGA Output
17 VOH1 CH1 Noninverting VGA Output
18 ENB Enable—VGA/LNA
19 HILO VGA Gain Range Select (HI or LO)
20 VCM1 CH1 Common-Mode Voltage
21 VIN1 CH1 VGA Inverting Input
22 VIP1 CH1 VGA Noninverting Input
23 COM1 CH1 LNA Ground
24 LOP1 CH1 LNA Noninverting Output
25 LON1 CH1 LNA Inverting Output
26 VPS1 CH1 LNA Supply 5 V
27 INH1 CH1 LNA Input
28 LMD1 CH1 LNA Signal Ground

Table 5. 32-Lead LFCSP Pin Function Description (AD8332)

Pin No. Mnemonic Description

1 LON1 CH1 LNA Inverting Output
2 VPS1 CH1 LNA Supply 5 V
3 INH1 CH1 LNA Input
4 LMD1 CH1 LNA Signal Ground
5 LMD2 CH2 LNA Signal Ground
6 INH2 CH2 LNA Input
7 VPS2 CH2 LNA Supply 5 V
8 LON2 CH2 LNA Inverting Output
9 LOP2 CH2 LNA Noninverting Output
10 COM2 CH2 LNA Ground
11 VIP2 CH2 VGA Noninverting Input
12 VIN2 CH2 VGA Inverting Input
13 VCM2 CH2 Common-Mode Voltage
14 MODE Gain Slope Logic Input
15 GAIN Gain Control Voltage
16 RCLMP Output Clamping Level Input
17 COMM VGA Ground
18 VOH2 CH2 Noninverting VGA Output
19 VOL2 CH2 Inverting VGA Output
20 NC No Connect
21 VPSV VGA Supply 5 V
22 VOL1 CH1 Inverting VGA Output
23 VOH1 CH1 Noninverting VGA Output
24 COMM VGA Ground
25 ENBV VGA Enable
26 ENBL LNA Enable
27 HILO VGA Gain Range Select (HI or LO)
28 VCM1 CH1 Common-Mode Voltage
29 VIN1 CH1 VGA Inverting Input
30 VIP1 CH1 VGA Noninverting Input
31 COM1 CH1 LNA Ground
32 LOP1 CH1 LNA Noninverting Output

Rev. E | Page 9 of 40

AD8331/AD8332/AD8334

COM2

COM1

INH1

LMD1

COM1X

LON1

LOP1

VIP1

VIN1

VPS1

GAIN12

CLMP12

EN12

EN34

VCM1

VCM2

LMD4

COM4X

58 5764 63 5962 61 60

AD8334

TOP VIEW

(Not to Scale)

VIP4

VIN4

LOP4

LON4

VPS4

2825 26 272017 18 19 21 22 23 24

GAIN34

CLMP34

29 30 31 32

HILO

VCM4

INH2

1

LMD2

LON2

LOP2

VIP2

VIN2

VPS2

VPS3

VIN3

VIP3

LOP3

LON3

LMD3

INH3

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

COM3

COM2X

COM3X

NC = NO CONNECT

PIN 1
INDICATO R

INH4

COM4

Figure 6. 64-Lead LFCSP Pin Configuration (AD8334)

Table 6. 64-Lead LFCSP Pin Function Description (AD8334)

Pin No. Mnemonic Description

1 INH2 CH2 LNA Input
2 LMD2 CH2 LNA V

Bypass (AC-Coupled to GND)

MID

3 COM2X CH2 LNA Ground Shield
4 LON2 CH2 LNA Feedback Output (for R

FBK

)
5 LOP2 CH2 LNA Output
6 VIP2 CH2 VGA Positive Input
7 VIN2 CH2VGA Negative Input
8 VPS2 CH2 LNA Supply 5 V
9 VPS3 CH3 LNA Supply 5 V
10 VIN3 CH3VGA Negative Input
11 VIP3 CH3 VGA Positive Input
12 LOP3 CH3 LNA Positive Output
13 LON3 CH3 LNA Feedback Output (for R

FBK

)
14 COM3X CH3 LNA Ground Shield
15 LMD3 CH3 LNA V

Bypass (AC-Coupled to GND)

MID

16 INH3 CH3 LNA Input
17 COM3 CH3 LNA Ground
18 COM4 CH4 LNA Ground
19 INH4 CH4 LNA Input
20 LMD4 CH4 LNA V

Bypass (AC-Coupled to GND)

MID

21 COM4X CH4 LNA Ground Shield
22 LON4 CH4 LNA Feedback Output (for R

FBK

)
23 LOP4 CH4 LNA Positive Output
24 VIP4 CH4 VGA Positive Input
25 VIN4 CH4VGA Negative Input
26 VPS4 CH4 LNA Supply 5 V
27 GAIN34 Gain Control Voltage for CH3 and CH4
28 CLMP34 Output Clamping Level Input for CH3 and CH4

50 4956 55 5154 53 52

48

COM12

47

VOH1

46

VOL1

45

VPS12

44

VOL2

43

VOH2

42

COM12

41

MODE

40

NC

NC

39

COM34

38

VOH3

37

VOL3

36

VPS34

35

VOL4

34

VOH4

33

COM34

NC

VCM3

03199-006

Rev. E | Page 10 of 40

AD8331/AD8332/AD8334

Pin No. Mnemonic Description

29 HILO Gain Select for Postamp 0 dB or 12 dB
30 VCM4 CH4 Common-Mode Voltage—AC Bypass
31 VCM3 CH3 Common-Mode Voltage—AC Bypass
32 NC No Connect
33 COM34 VGA Ground, CH3 and CH4
34 VOH4 CH4 Positive VGA Output
35 VOL4 CH4 Negative VGA Output
36 VPS34 VGA Supply 5V CH3 and CH4
37 VOL3 CH3 Negative VGA Output
38 VOH3 CH3 Positive VGA Output
39 COM34 VGA ground CH3 and CH4
40 NC No Connect
41 MODE Gain Control SLOPE, Logic Input, 0 = Positive
42 COM12 VGA Ground CH1 and CH2
43 VOH2 CH2 Positive VGA Output
44 VOL2 CH2 Negative VGA Output
45 VPS12 CH2 VGA Supply 5 V CH1 and CH2
46 VOL1 CH1 Negative VGA Output
47 VOH1 CH1 Positive VGA Output
48 COM12 VGA Ground CH1 and CH2
49 VCM2 CH2 Common-Mode Voltage—AC Bypass
50 VCM1 CH1 Common-Mode Voltage—AC Bypass
51 EN34 Shared LNA/VGA Enable, CH3 and CH4
52 EN12 Shared LNA/VGA Enable, CH1 and CH2
53 CLMP12 Output Clamping Level Input, CH1 and CH2
54 GAIN12 Gain Control Voltage CH1 and CH2
55 VPS1 CH1 LNA Supply 5 V
56 VIN1 CH1 VGA Negative Input
57 VIP1 CH1 VGA Positive Input
58 LOP1 CH1 LNA Positive Output
59 LON1 CH1 LNA Feedback Output (for R
60 COM1X CH1 LNA Ground Shield
61 LMD1 CH1 LNA V

Bypass (AC-Coupled to GND)

MID

62 INH1 CH1 LNA Input
63 COM1 CH1 LNA Ground
64 COM2 CH2 LNA Ground

FBK

)

Rev. E | Page 11 of 40

AD8331/AD8332/AD8334

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RFB = 280 Ω, CSH = 22 pF, f = 10 MHz, R

−4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.

60

50

40

30

20

GAIN (dB)

10

0

–10

0 0.2 0.4 0.6 0.8 1.0 1.1

Figure 7. Gain vs. V

ASCENDING GAIN MODE
DESCENDI NG GAI N MODE

(WHERE AVAILABLE)

GAIN

HILO = HI

HILO = LO

V

(V)

GAIN

and MODE (MODE Available on AC Package)

2.0

1.5

1.0

0.5

0

–0.5

GAIN ERROR (dB)

–1.0

–1.5

–2.0

0 0.2 0.4 0.6 0.8 1.0 1.1

Figure 8. Absolute Gain Error vs. V

2.0

1.5

1.0

0.5

0

–0.5

GAIN ERROR (dB)

–1.0

–1.5

–2.0

0 0.2 0.4 0.6 0.8 1.0 1.1

Figure 9. Absolute Gain Error vs. V

1MHz

–40°C

10MHz

V

GAIN

30MHz

50MHz

70MHz

V

GAIN

(V)

at Three Temperatures

GAIN

(V)

at Various Frequencies

GAIN

03199-007

+25°C

+85°C

03199-008

03199-009

50

40

30

20

PERCENT OF UNI TS (%)

10

0
–0.5 –0.4 –0. 3 –0.2 –0. 1 0 0.1 0. 2 0.3 0.4 0.5

25

20

15

10

5

0

25

20

15

PERCENT OF UNI TS (%)

10

5

0

Figure 11. Gain Match Histogram for V

50

40

30

20

10

GAIN (dB)

0

–10

–20

100k 1M 10M 100M 500M

Figure 12. Frequency Response for Various Values of V

= ∞, CL = 1 pF, VCM pin floating,

CLMP

SAMPLE SIZE = 80 UNITS
V

= 0.5V

GAIN

GAIN ERROR (dB)

Figure 10. Gain Error Histogram

SAMPLE SIZE = 50 UNITS
V

= 0.2V

GAIN

V

= 0.7V

GAIN

0.01

–0.17

–0.15

–0.13

–0.11

–0.09

–0.07

CHANNEL TO CHANNEL G AIN MATCH (d B)

–0.05

V

V

V

V

V

V

FREQUENCY (Hz)

–0.03

GAIN

GAIN

GAIN

GAIN

GAIN

GAIN

–0.01

= 1V

= 0.8V

= 0.6V

= 0.4V

= 0.2V

= 0V

0.03

0.05

0.07

0.09

0.11

= 0.2 V and 0.7 V

GAIN

03199-010

03199-011

0.13

0.15

0.17

0.19

0.21

03199-012

GAIN

Rev. E | Page 12 of 40

AD8331/AD8332/AD8334

60

50

40

30

20

GAIN (dB)

10

0

V

V

V

V

V

V

GAIN

GAIN

GAIN

GAIN

GAIN

GAIN

= 1V

= 0.8V

= 0.6V

= 0.4V

= 0.2V

= 0V

0

V

= 1V p-p

OUT

–20

V

= 1.0V

GAIN

V

V

GAIN

GAIN

= 0.7V

= 0.4V

–40

–60

CROSSTALK (d B)

–80

–100

AD8332

AD8334

–10

100k 1M 10M 100M 500M

FREQUENCY (Hz)

Figure 13. Frequency Response for Various Values of V

, HILO = HI

GAIN

03199-013

30

V

= 0.5V

GAIN

20

10

0

GAIN (dB)

–10

–20

–30

100k 1M 10M 100M 500M

= RS = 75Ω

R

IN

RIN = RS = 100Ω

= RS = 200Ω

R

IN

R

= RS = 500Ω

IN

R

FREQUENCY (Hz)

= RS = 1kΩ

IN

RIN = RS = 50Ω

03199-014

Figure 14. Frequency Response for Various Matched Source Impedances

30

V

= 0.5V

GAIN

R

=

∞

FB

20

10

0

GAIN (dB)

–10

–20

–30

100k 1M 10M 100M 500M

Figure 15. Frequency Response, Unterminated LNA, R

FREQUENCY (Hz)

= 50 Ω

S

03199-015

–120

100k 1M 10M 100M

FREQUENCY (Hz)

03199-016

Figure 16. Channel-to-Channel Crosstalk vs.

Frequency for Various Values of V

50

45

40

35

30

1µF

25

COUPLING

20

GROUP DELAY (ns)

15

10

5

0
100k 1M 10M 100M

0.1µF
COUPLING

FREQUENCY (Hz)

GAIN

03199-017

Figure 17. Group Delay vs. Frequency for Two Values of AC Coupling

20

HI GAIN

10

0

–10

–20

20

LO GAIN

10

OFFSET VOLTAGE (mV)

0

–10

–20

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

V

GAIN

(V)

T = +85°C
T = +25°C
T = –40°C

T = +85°C
T = +25°C
T = –40°C

03199-018

Figure 18. Representative Differential Output Offset Voltage vs.

at Three Temperatures

V

GAIN

Rev. E | Page 13 of 40

AD8331/AD8332/AD8334

R

IN

R

FB

= 100Ω,

= 549Ω

50j

–50j

RIN = 50Ω,
R

FB

= 200Ω,

R

IN

R

FB

R

= 200Ω

IN

R

IN

= 270Ω

= 1.1kΩ

= 500Ω

= 1kΩ

R

IN

f

= 100kHz

RIN = 50Ω

100j

–100j

FB

R

= 100Ω

IN

03199-022

35

30

25

20

15

% TOTAL

10

5

0

SAMPLE SIZE = 100

0.2V < V

49.6 50.550.450.350.250.150. 049.949.849.7

GAIN

< 0.7V

Figure 19. Gain Scaling Factor Histogram

100

SINGLE ENDED, PIN VOH OR VOL
R

=

∞

L

10

1

OUTPUT IMPEDANCE (Ω)

GAIN SCALING FACTOR

25j

R

= 6kΩ,

IN

R

=

∞

FB

0Ω 17Ω

RIN = 75Ω,
R

= 412Ω

FB

03199-019

–25j

Figure 22. Smith Chart, S11 vs. Frequency,

0.1 MHz to 200 MHz for Various Values of R

20

VIN = 10mV p-p

15

10

5

0

GAIN (dB)

–5

0.1
100k 100M10M1M

Figure 20. Output Impedance vs. Frequency

10k

RFB = 6.65kΩ, CSH = 0pF

1k

100

INPUT IMPEDANCE (Ω)

10

100k 100M10M1M

R

R

= 1.1kΩ, CSH = 1.2pF

FB

= 412Ω, CSH = 12pF

R

FB

Figure 21. LNA Input Impedance vs.

Frequency for Various Values of R

FREQUENCY (Hz)

= 3.01kΩ, CSH = 0pF

FB

R

= 549Ω, CSH = 8.2pF

FB

FREQUENCY (Hz)

R

=∞, CSH = 0pF

FB

RFB = 270Ω, CSH = 22pF

and C

FB

–10

= 75Ω

R

03199-020

–15

100k 1M 10M 100M 500M

FREQUENCY (Hz)

Figure 23. LNA Frequency Response, Single Ended, for Various Values of R

IN

03199-023

IN

20

15

RFB =

∞

10

5

0

GAIN (dB)

–5

–10

03199-021

–15

100k 1M 10M 100M 500M

FREQUENCY (Hz)

03199-024

Figure 24. Frequency Response for Unterminated LNA, Single Ended

SH

Rev. E | Page 14 of 40

AD8331/AD8332/AD8334

500

f

= 10MHz

400

300

200

100

OUTPUT REFERRED NOISE (nV/ Hz)

0

LO GAIN

HI GAIN

0 0.2 0.4 0.6 0.8 1.0

AD8332
AD8334

AD8331

V

GAIN

(V)

Figure 25. Output-Referred Noise vs. V

2.5
RS = 0, RFB =∞, V
HILO = LO OR HI

2.0

GAIN

= 1V,

03199-025

GAIN

1.00
RS = 0, RFB =∞,

V

= 1V, f = 10M Hz

GAIN

0.95

0.90

0.85

0.80

0.75

0.70

0.65

INPUT NOISE (nV/ Hz)

0.60

0.55

0.50

–50 –30 –10 10 30 50 70 90

TEMPERATURE ( °C)

Figure 28. Short-Circuit, Input-Referred Noise vs. Temperature

10

f = 5MHz, RFB =∞,

= 1V

V

GAIN

03199-028

1.5

INPUT NOISE (nV/ Hz)

1.0

0.5
100k 1M 10M 100M

FREQUENCY (Hz)

Figure 26. Short-Circuit, Input-Referred Noise vs. Frequency

100

10

1

INPUT NOISE (nV/ Hz)

0.1

0 0.2 0.4 0.6 0.8 1.0

RS = 0, RFB =∞,
HILO = LO OR HI, f = 10MHz

V

(V)

GAIN

Figure 27. Short-Circuit, Input-Referred Noise vs. V

GAIN

1

INPUT NOISE (nV/ Hz)

03199-026

0.1
1 10 100 1k

Figure 29. Input-Referred Noise vs. R

7

INCLUDES NOISE OF VGA

6

5

4

3

NOISE FI GURE (dB)

2

1

03199-027

SIMULATION

0

50 100 1k

Figure 30. Noise Figure vs. R

R

THERMAL NOISE

S

ALONE

SOURCE RESIST ANCE (Ω)

R

= 50Ω

IN

R

= 75Ω

IN

= 100Ω

R

IN

= 200Ω

R

IN

R

=

∞

FB

SOURCE RESIST ANCE (Ω)

for Various Values of R

S

03199-029

S

03199-030

IN

Rev. E | Page 15 of 40

AD8331/AD8332/AD8334

–

–

–

35

30

25

20

15

NOISE FI GURE (dB)

10

5

HILO = L O, R

HILO = HI, R

HILO = LO, R

HILO = HI, RIN = 50Ω

=

∞

FB

=

∞

IN

IN

f = 10MHz, RS = 50ΩPREAMP LIMITED

= 50Ω

HARMONIC DIST ORTIO N (dBc)

30

–40

–50

–60

–70

–80

f = 10MHz,

= 1V p-p

V

OUT

HILO = HI , HD2

HILO = HI , HD3

HILO = L O, HD2

HILO = L O, HD3

0

0 0.10.20.30.40.50.60.70.80.91.01.1

Figure 31. Noise Figure vs. V

30

25

20

15

10

NOISE FI GURE (dB)

HILO = LO, R

5

0

10 15 20 25 30 35 40 45 50 55 60

= 50Ω

IN

HILO = L O, R

V

(V)

GAIN

f = 10MHz, RS = 50Ω

HILO = HI, RIN = 50Ω

HILO = HI, R

=

∞

FB

GAIN (dB)

GAIN

=

∞

FB

Figure 32. Noise Figure vs. Gain

0

G = 30dB,
V

= 1V p-p

OUT

–10

–20

–30

–40

–50

–60

–70

HARMONIC DISTORTION (dBc)

–80

–90

1M 10M 100

FREQUENCY (Hz)

HILO = L O, HD2

HILO = LO , HD3

HILO = HI, HD2

HILO = HI, HD3

Figure 33. Harmonic Distortion vs. Frequency

03199-031

03199-032

03199-033

–90

0 200018001600140012001000800600400200

Figure 34. Harmonic Distortion vs. R

40

f = 10MHz,

= 1V p-p

V

OUT

–50

–60

–70

HARMONIC DIST ORTIO N (dBc)

–80

–90

0 10203040

Figure 35. Harmonic Distortion vs. C

20

f = 10MHz,
GAIN = 30d B

–40

–60

HILO = HI, HD2

–80

HARMONIC DIST ORTIO N (dBc)

–100

01234

R

LOAD

HILO = LO, HD3

HILO = HI, HD2

C

LOAD

HILO = L O, HD2

V

(V p-p)

OUT

(Ω)

LOAD

HILO = L O, HD2

HILO = HI, HD3

(pF)

LOAD

HILO = LO, HD3

HILO = HI , HD3

Figure 36. Harmonic Distortion vs. Differential Output Voltage

03199-034

03199-035

50

03199-036

Rev. E | Page 16 of 40

AD8331/AD8332/AD8334

0

V

= 1V p-p

OUT

–20

INPUT RANGE
LIMITED WHEN

–40

HILO = LO

–60

–80

DISTORTION (dBc)

–100

–120

0 0.1 0. 2 0.3 0.4 0. 5 0.6 0.7 0.8 0. 9 1.0

HILO = HI, HD3

HILO = L O, HD2

V

(V)

GAIN

Figure 37. Harmonic Distortion vs. V

HILO = L O, HD3

HILO = HI, HD2

, f = 1 MHz

GAIN

0

V

= 1V p-p

OUT

–20

INPUT RANGE
LIMITED WHEN

–40

HILO = LO

–60

HILO = LO, HD2

HILO = L O, HD3

03199-037

0

V

= 1V p-p COMPOSITE (

OUT

G = 30dB

–10

–20

–30

–40

–50

IMD3 (dBc)

–60

–70

–80

–90

1M 10M 100M

f

+

f

)

1

2

FREQUENCY (Hz)

HILO = LO

HILO = HI

Figure 40. IMD3 vs. Frequency

40

10MHz HILO = HI

35

30

25

20

1MHz HILO = HI

1MHz HILO = LO

10MHz HILO = LO

03199-040

–80

DISTORTION (dBc)

HILO = HI , HD3

–100

–120

0 0.1 0. 2 0.3 0.4 0. 5 0.6 0.7 0.8 0. 9 1.0

V

GAIN

(V)

Figure 38. Harmonic Distortion vs. V

HILO = HI, HD2

, f = 10 MHz

GAIN

10

f = 10MHz

0

–10

HILO = HI

–20

INPUT POWER (dBm)

–30

–40

0 0.1 0. 2 0.3 0.4 0. 5 0.6 0.7 0.8 0. 9 1.0

V

GAIN

HILO = LO

(V)

Figure 39. Input 1 dB Compression vs. V

GAIN

15

OUTPUT I P3 (dBm)

10

5

V

= 1V p-p COMPOSITE (

03199-038

0

010.90. 80.70.60. 50. 40.30.20. 1

OUT

Figure 41. Output Third-Order Intercept vs. V

2mV

100

90

10

0

50mV 10ns

03199-039

Figure 42. Small Signal Pulse Response, G = 30 dB,

V

GAIN

f

+

f

)

1

2

(V)

GAIN

03199-041

.0

3199-042

Top: Input, Bottom: Output Voltage, HILO = HI or LO

Rev. E | Page 17 of 40

AD8331/AD8332/AD8334

(V p-p)

OUT

V

(V)

OUT

V

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

–1

0

0545403530252015105

4

3

2

1

0

Figure 46. Clamp Level vs. R

G = 40dB

INPUT

HILO = HI

R

R

CLMP

R

CLMP

R

CLMP

HILO = LO

(kΩ)

CLMP

= 48.1kΩ

R

CLMP

= 7.15kΩ

= 2.67kΩ

03199-046

0

CLMP

= 16.5kΩ

20mV

100

90

10

0

500mV 10ns

Figure 43. Large Signal Pulse Response, G = 30 dB,

HILO = HI or LO, Top: Input, Bottom: Output Voltage

2

G = 30dB

1

INPUT

(V)

0

OUT

V

CL = 0pF
CL = 10pF
CL = 22pF
CL = 47pF

3199-043

–1

INPUT IS NOT TO SCALE

–2

–50 50403020100–10–20–30–40

TIME (ns)

Figure 44. Large Signal Pulse Response for Various Capacitive Loads,

= 0 pF, 10 pF, 20 pF, 50 pF

C

L

500mV

200mV 400ns

3199-045

Figure 45. Pin GAIN Transient Response,

Top: V

, Bottom: Output Voltage

GAIN

–2

–3

CLMP

03199-047

3199-048

03199-044

–4

–30–20–100 1020304050607080

TIME (ns)

Figure 47. Clamp Level Pulse Response for 4 Values of R

200mV

100

90

10

0

100ns

Figure 48. LNA Overdrive Recovery, V

= 0.27 V VGA Output Shown

V

GAIN

0.05 V p-p to 1 V p-p Burst,

INH

Rev. E | Page 18 of 40

AD8331/AD8332/AD8334

1V

100

90

10

0

Figure 49. VGA Overdrive Recovery, V

= 1 V VGA Output Shown Attenuated by 24 dB

V

GAIN

1V

100

90

10

0

Figure 50. VGA Overdrive Recovery, V

= 1 V VGA Output Shown Attenuated by 24 dB

V

GAIN

2V

200mV 1ms

Figure 51. Enable Response, Top: V

ENB

INH

INH

, Bottom: VB

100ns

3199-049

4 mV p-p to 70 mV p-p Burst,

100ns

3199-050

4 mV p-p to 275 mV p-p Burst,

3199-051

, V

= 30 mV p-p

OUT

INH

2V

1V 1ms

Figure 52. Enable Response, Large Signal,

, Bottom: V

B

Top: V

ENB

0

–10

–20

–30

–40

PSRR (dB)

–50

–60

–70

–80

100k 1M 10M 100M

VPSV, V

GAIN

, V

= 150 mV p-p

OUT

INH

VPS1, V

= 0.5V

FREQUENCY (Hz)

GAIN

VPS1, V

= 0.5V

GAIN

Figure 53. PSRR vs. Frequency (No Bypass Capacitor)

140

V

= 0.5V

GAIN

QUIESCENT S UPPLY CURRENT (mA)

130

120

110

100

90

80

70

60

50

40

30

20

–40 100806040200–20

AD8334

AD8332

AD8331

TEMPERATURE ( °C)

Figure 54. Quiescent Supply Current vs. Temperature

= 0V

3199-052

03199-053

03199-054

Rev. E | Page 19 of 40

AD8331/AD8332/AD8334

TEST CIRCUITS

MEASUREMENT CONSIDERATIONS

Figure 55 through Figure 68 show typical measurement
configurations and proper interface values for measurements
with 50 Ω conditions.

FERRITE

BEAD

0.1µF

120nH

22pF

0.1µF

Figure 55. Gain and Bandwidth Measurements

Short-circuit input noise measurements are made using
The input-referred noise level is determined by dividing the
output noise by the numerical gain between Point A and Point B
and accounting for the noise floor of the spectrum analyzer.
The gain should be measured at each frequency of interest and
with low signal levels because a 50 Ω load is driven directly. The
generator is removed when noise measurements are made.

NETWO RK ANALYZE R

50Ω50Ω

18nF

270Ω

INH

LMD

NETWORK ANALYZER

0.1µF

DUT

0.1µF

INOUT

237Ω

237Ω

28Ω

28Ω

1:1

03199-055

Figure 62.

50Ω50Ω

INOUT

10kΩ

18nF

FERRITE

10kΩ

BEAD
120nH

22pF

0.1µF

0.1µF

INH

LMD

DUT

0.1µF

0.1µF

237Ω

237Ω

28Ω

28Ω

1:1

03199-056

Figure 56. Frequency Response for Various Matched Source Impedances

FERRITE

BEAD

120nH

22pF

Figure 57. Frequency Response for Unterminated LNA, R

NETWORK ANALYZER

0.1µF
INH

LMD

0.1µF

DUT

50Ω50Ω

0.1µF

0.1µF

INOUT

237Ω

237Ω

28Ω

28Ω

1:1

03199-057

= 50 Ω

S

Rev. E | Page 20 of 40

AD8331/AD8332/AD8334

R

R

K

NETWORK ANALY ZE

50Ω50Ω

INOUT

10kΩ

18nF

LNA

0.1µF

18nF

INH

LMD

0.1µF
AND
10µF

0.1µF
AND
10µF

270Ω

DUT

0.1µF

0.1µF

VGA

237Ω

237Ω

237Ω

237Ω

28Ω

28Ω

28Ω

28Ω

1:1

03199-058

50Ω1:1

03199-059

FERRITE

BEAD
120nH

22pF

0.1µF
AND

10µF

INH

LMD

0.1µF

Figure 58. Group Delay vs. Frequency for Two Values of AC Coupling

NETWORK
ANALYZER

FERRITE

BEAD

OUT

120nH

50Ω

Figure 59. LNA Input Impedance vs. Frequency in Standard and Smith Chart (S11) Formats

0.1µF

22pF

NETWORK ANALY ZE

50Ω50Ω

INOUT

LNA

0.1µF

0.1µF

0.1µF

VGA

0.1µF

0.1µF

237Ω

237Ω

28Ω

28Ω

1:1

03199-060

FERRITE

BEAD

120nH

22pF

0.1µF
INH

LMD

0.1µF

Figure 60. Frequency Response for Unterminated LNA, Single Ended

NETWOR

FERRITE

BEAD

120nH

22pF

18nF

270Ω

0.1µF

0.1µF

INH

LMD

DUT

0.1µF

0.1µF

237Ω

237Ω

1:1

28Ω

28Ω

Figure 61. Short-Circuit, Input-Referred Noise

IN

ANALYZER

50Ω

03199-061

Rev. E | Page 21 of 40

AD8331/AD8332/AD8334

–

SPECTRUM

ANALYZER

0.1µF

0.1µF

BA

50Ω

IN

1:1

3199-062

SPECTRUM
ANALYZER

22pF

GAIN

INH

LMD

0.1µF

49.9Ω

50Ω

SIGNAL GE NERATOR

TO MEASURE G AIN

DISCONNECT F OR

NOISE MEAS UREMENT

0.1µF

1Ω

FERRITE

BEAD
120nH

Figure 62. Noise Figure

18nF

270Ω

50Ω

LPF

SIGNAL
GENERATOR

–6dB

0.1µF

22pF

0.1µF

AD8332

INH

LMD

0.1µF

0.1µF

1kΩ

1kΩ

28Ω

28Ω

–6dB

1:1

50Ω

IN

03199-063

Figure 63. Harmonic Distortion vs. Load Resistance

SPECTRUM

IN

ANALYZER

50Ω

03199-064

50Ω

LPF

SIGNAL
GENERATOR

–6dB

0.1µF

22pF

0.1µF

18nF

AD8332

INH

LMD

270Ω

0.1µF

0.1µF

237Ω

237Ω

28Ω

28Ω

–6dB

1:1

Figure 64. Harmonic Distortion vs. Load Capacitance

50Ω

50Ω

SIGNAL
GENERATORS

+22dB

+22dB

6dB

–6dB

FERRITE

COMBINER

–6dB

18nF

270Ω

BEAD

0.1µF

120nH

22pF

INH

LMD

0.1µF

Figure 65. IMD3 vs. Frequency

DUT

0.1µF

0.1µF

237Ω

237Ω

28Ω

28Ω

1:1

–6dB

SPECTRUM
ANALYZER

INPUT

50Ω

03199-065

Rev. E | Page 22 of 40

AD8331/AD8332/AD8334

E

18nF

INH

LMD

270Ω

DUT

0.1µF

0.1µF

237Ω

28Ω

237Ω

28Ω

50Ω

FERRITE

BEAD
120nH

22pF

0.1µF

0.1µF

OSCILLOSCOP

50Ω

IN

1:1

3199-066

Figure 66. Pulse Response Measurements

OSCILLOSCOPE

18nF

INH

LMD

270Ω

0.1µF

DUT

0.1µF

TO PIN GAIN

OR ENxx

255Ω

255Ω

DIFF

PROBE

GENERATOR

NETWORK

ANALYZER

CH1

PULSE

50Ω

CH2

9.5dB

03199-067

FERRITE

BEAD

120nH

22pF

50Ω

RF
SIGNAL
GENERATOR

0.1µF

0.1µF

Figure 67. GAIN and Enable Transient Response

50Ω

PROBE

DIFF

INOUT

PROBE

POWER

3199-068

FERRITE

BEAD

120nH

22pF

50Ω

RF
SIGNAL
GENERATOR

0.1µF

18nF

0.1µF

270Ω

INH

LMD

TO POWER
PIN(S)

0.1µF

DUT

0.1µF

50Ω

255Ω

255Ω

Figure 68. PSRR vs. Frequency

Rev. E | Page 23 of 40

AD8331/AD8332/AD8334

VINV

O

VCM

V

V

V

V

THEORY OF OPERATION

OVERVIEW

The following discussion applies to all part numbers. Figure 69,
Figure 70, and Figure 71 are functional block diagrams of the
AD8331, AD8332, and AD8334, respectively.

INH

LMD

INH1

LMD1

LMD2

INH2

IPLOPLON

V

MID

+

LNA

–

LNA
BIAS

–

ATTENUAT OR

–48dB

+

VGA BIAS AND

INTERPOLATOR

AD8331

ENBL

ENBV GAIN

Figure 69. AD8331 Functional Block Diagram

+19dB

LNA 1

LNA 2

LON1 LOP1

BIAS

(V

MID

)

IP1

IN1

–

+

+

–

ATTENUATOR

–48dB

VGA BIAS AND

INTERPOLAT OR

ATTENUATOR

–48dB

AD8332

LON2 LOP2

VIP2

VIN2

ENB

Figure 70. AD8332 Functional Block Diagram

GAIN

INT

CM1

V

MID

V

MID

VCM2

GAIN

INT

21dB

21dB

3.5dB/

15.5dB

CLAMP

3.5dB/

15.5dB

CLAMP

PA21dB

PA1

PA2

HIL

VOH

VOL

RCLMP

MODE

HILO

VOH1

VOL1

GAIN

VOL2

VOH2

RCLMP

LON1 LOP1VIP1VIN1 EN12

INH1

LMD1

LMD2

INH2

LON2

LOP2

VIP2

VIN2

MODE

VIN3

VIP3

03199-069

LOP3

LON3

INH3

LMD3

LMD4

INH4

LNA 1

LNA 2

LNA 3

LNA 4

LNA
BIAS

LNA
BIAS

–

ATTENUATO R

–48dB

+

VGA BIAS AND

INTERPOL ATOR

+

ATTENUATO R

–48dB

–

GAIN UP/

DOWN

–

ATTENUATO R

–48dB

+

VGA BIAS AND

INTERPOL ATOR

+

ATTENUATO R

–48dB

–

AD8334

Figure 71. AD8334 Functional Block Diagram

Each channel contains an LNA that provides user-adjustable
input impedance termination, a differential X-AMP VGA, and a
programmable gain postamplifier with adjustable output voltage
limiting.

3199-070

external components.

INH

LMD

Figure 72 shows a simplified block diagram with

VIN

48dB

ATTENUATOR

VIP

BIAS AN

INTERPOLATO

PRE-AMPLIFIER

19dB

+

LNA

–

BIAS

)

(V

MID

LON

LOP

CM1

V

MID1

V

MID2

V

MID3

V

MID4

VCM4EN34VIN4VIP4LON4 LOP4

SIGNAL PATH

V

VCM

D

R

21dB

GAIN

INT

21dB

21dB

GAIN

INT

21dB

21dB

MID

GAIN

INTERFAC E

CLAMP

PA1

PA2

PA3

PA4

CLAMP34

3.5dB/15. 5dB

HILO

POST-

AMP

CLAMP

CLMP12

VOH1

VOL1

GAIN12

HILO

VOL2

VOH2

VCM2

VCM3

VOH3

VOL3

GAIN34

VOL4

VOH4

CLMP34

03199-071

VOH

VOL

RCLMP

GAIN

03199-072

Figure 72. Simplified Block Diagram

Rev. E | Page 24 of 40

AD8331/AD8332/AD8334

The linear-in-dB gain-control interface is trimmed for slope
and absolute accuracy. The gain range is 48 dB, extending from

−4.5 dB to +43.5 dB in HI gain and +7.5 dB to +55.5 dB in LO
gain mode. The slope of the gain control interface is 50 dB/V,
and the gain control range is 40 mV to 1 V. Equation 1 and
Equation 2 are the expressions for gain.

GAIN (dB) = 50 (dB/V) × V

− 6.5 dB, (HILO = LO) (1)

GAIN

or
GAIN (dB) = 50 (dB/V) × V

The ideal gain characteristics are shown in

60

50

40

30

+ 5.5 dB, (HILO = LO) (2)

GAIN

Figure 73.

HILO = HI

LOW NOISE AMPLIFIER (LNA)

Good noise performance relies on a proprietary ultralow noise
preamplifier at the beginning of the signal chain, which minimizes
the noise contribution in the following VGA. Active impedance
control optimizes noise performance for applications that benefit
from input matching.

A simplified schematic of the LNA is shown in
is capacitively coupled to the source. An on-chip bias generator
establishes dc input bias voltages of 3.25 V and centers the
output common-mode levels at 2.5 V. A Capacitor C
same value as the Input Coupling Capacitor C
from the LMD pin to ground.

C

FB

VPOSLOP

I

0

Figure 74. INH

is connected

INH

R

FB

I

0

LON

LMD

of the

20

GAIN (dB)

10

0

–10

0 0.2 0.4 0.6 0.8 1.0 1.1

ASCENDING GAIN MODE
DESCENDING GAIN MODE

(WHERE AVAILABLE)

Figure 73. Ideal Gain Control Characteristics

HILO = LO

V

(V)

GAIN

03199-073

The gain slope is negative with the MODE pulled high (where
available):

GAIN (dB) = −50 (dB/V) × V

+ 45.5 dB, (HILO = LO) (3)

GAIN

or
GAIN (dB) = −50 (dB/V) × V

+ 57.5 dB, (HILO = HI) (4)

GAIN

The LNA converts a single-ended input to a differential output
with a voltage gain of 19 dB. If only one output is used, the gain
is 13 dB. The inverting output is used for active input impedance
termination. Each of the LNA outputs is capacitively coupled to
a VGA input. The VGA consists of an attenuator with a range of
48 dB followed by an amplifier with 21 dB of gain for a net gain
range of −27 dB to +21 dB. The X-AMP gain-interpolation
technique results in low gain error and uniform bandwidth, and
differential signal paths minimize distortion.

The final stage is a logic programmable amplifier with gains of

3.5 dB or 15.5 dB. The LO and HI gain modes are optimized for
12-bit and 10-bit ADC applications, in terms of output-referred
noise and absolute gain range. Output voltage limiting can be
programmed by the user.

C

INH

R

S

INH

C

SH

Figure 74. Simplified LNA Schematic

Q1 Q2

I

0I0

LMD

C

LMD

03199-074

The LNA supports differential output voltages as high as 5 V p-p
with positive and negative excursions of ±1.25 V, about a
common-mode voltage of 2.5 V. Because the differential gain
magnitude is 9, the maximum input signal before saturation is
±275 mV or +550 mV p-p. Overload protection ensures quick
recovery time from large input voltages. Because the inputs are
capacitively coupled to a bias voltage near midsupply, very large
inputs can be handled without interacting with the ESD protection.

Low value feedback resistors and the current-driving capability
of the output stage allow the LNA to achieve a low input-referred
voltage noise of 0.74 nV/√Hz. This is achieved with a current
consumption of only 11 mA per channel (55 mW). On-chip
resistor matching results in precise single-ended gains of 4.5×
(9× differential), critical for accurate impedance control. The
use of a fully differential topology and negative feedback
minimizes distortion. Low HD2 is particularly important in
second harmonic ultrasound imaging applications. Differential
signaling enables smaller swings at each output, further
reducing third-order distortion.

Rev. E | Page 25 of 40

AD8331/AD8332/AD8334

Active Impedance Matching

The LNA supports active impedance matching through an external
shunt feedback resistor from Pin LON to Pin INH. The input
resistance, R

, is given by Equation 5, where A is the single-

IN

ended gain of 4.5, and 6 kΩ is the unterminated input impedance.

R

×

R

R

C

is needed in series with RFB because the dc levels at Pin LON

FB

FB

=

IN

1

k6

A

+

and Pin INH are unequal. Expressions for choosing R
of R

and for choosing CFB are found in the Applicat ions section.

IN

C

and the ferrite bead enhance stability at higher frequencies

SH

k6

FB

=

k33

(5)

R

+

FB

in terms

FB

where the loop gain is diminished and prevent peaking. Frequency
response plots of the LNA are shown in

Figure 23 and Figure 24.
The bandwidth is approximately 130 MHz for matched input
impedances of 50 Ω to 200 Ω and declines at higher source
impedances. The unterminated bandwidth (when R

= ∞) is

FB

approximately 80 MHz.

Each output can drive external loads as low as 100 Ω in addition
to the 100 Ω input impedance of the VGA (200 Ω differential).
Capacitive loading up to 10 pF is permissible. All loads should
be ac-coupled. Typically, Pin LOP output is used as a single­ended driver for auxiliary circuits, such as those used for
Doppler ultrasound imaging, and Pin LON drives R

.

FB

Alternatively, a differential external circuit can be driven from
the two outputs in addition to the active feedback termination.
In both cases, important stability considerations discussed in
the

Applications section should be carefully observed.

The impedance at each LNA output is 5 Ω. A 0.4 dB reduction
in open-circuit gain results when driving the VGA, and 0.8 dB
with an additional 100 Ω load at the output. The differential
gain of the LNA is 6 dB higher. If the load is less than 200 Ω on
either side, a compensating load is recommended on the
opposite output.

LNA Noise

The input-referred voltage noise sets an important limit on
system performance. The short-circuit input voltage noise of
the LNA is 0.74 nV/√Hz or 0.82 nV/√Hz (at maximum gain),
including the VGA noise. The open-circuit current noise is

2.5 pA/√Hz. These measurements, taken without a feedback
resistor, provide the basis for calculating the input noise and
noise figure performance of the configurations in

Figure 75.
Figure 76 and Figure 77 are simulations extracted from these
results, and the 4.1 dB NF measurement with the input actively
matched to a 50 Ω source. Unterminated (R

= ∞) operation

FB

exhibits the lowest equivalent input noise and noise figure.
Figure 76 shows the noise figure vs. source resistance, rising at
low R

, where the LNA voltage noise is large compared to the

S

source noise, and again at high R

due to current noise. The

S

VGA’s input-referred voltage noise of 2.7 nV/√Hz is included in
all of the curves.

+

V

IN

–

+

V

IN

–

+

V

IN

–

Figure 75. Input Configurations

7

6

5

4

3

NOISE FI GURE (dB)

2

1

SIMULATION

0

50 100 1k

Figure 76. Noise Figure vs. R
Active Matched and Unterminated Inputs

7

INCLUDES NOISE OF VGA

6

5

4

3

NOISE FI GURE (dB)

2

1

SIMULATION

0

50 100 1k

Figure 77. Noise Figure vs. R

UNTERMINATED

R

IN

R

S

V

OUT

RESISTIVE TERMINATION

R

IN

R

S

R

S

ACTIVE IM PEDANCE MATCH

R

R

S

RIN=

RESISTIVE TERMINAT ION

= 50Ω

R

IN

R

= 75Ω

IN

R

= 100Ω

IN

= 200Ω

R

IN

R

FB

for Various Fixed Values of RIN, Actively Matched

S

R

IN

R

FB

1 + 4.5

INCLUDES NOISE OF VGA

(R

= RIN)

S

ACTIVE IM PEDANCE MATCH

UNTERMINATED

RS (Ω)

=

∞

RS (Ω)

V

FB

V

for Resistive,

S

OUT

OUT

03199-075

03199-076

03199-077

Rev. E | Page 26 of 40

AD8331/AD8332/AD8334

The primary purpose of input impedance matching is to
improve the system transient response. With resistive termination,
the input noise increases due to the thermal noise of the
matching resistor and the increased contribution of the LNA’s
input voltage noise generator. With active impedance matching,
however, the contributions of both are smaller than they would
be for resistive termination by a factor of 1/(1 + LNA Gain).
Figure 76 shows their relative noise figure (NF) performance. In
this graph, the input impedance was swept with R

to preserve

S

the match at each point. The noise figures for a source impedance
of 50  are 7.1 dB, 4.1 dB, and 2.5 dB, respectively, for the
resistive, active, and unterminated configurations. The noise
figures for 200  are 4.6 dB, 2.0 dB, and 1.0 dB, respectively.

Figure 77 is a plot of the NF vs. RS for various values of RIN,
which is helpful for design purposes. The plateau in the NF for
actively matched inputs mitigates source impedance variations.
For comparison purposes, a preamp with a gain of 19 dB and
noise spectral density of 1.0 nV/√Hz, combined with a VGA
with 3.75 nV/√Hz, yields a noise figure degradation of
approximately 1.5 dB (for most input impedances), significantly
worse than the AD8332 performance.

The equivalent input noise of the LNA is the same for single­ended and differential output applications. The LNA noise figure
improves to 3.5 dB at 50 Ω without VGA noise, but this is
exclusive of noise contributions from other external circuits
connected to LOP. A series output resistor is usually
recommended for stability purposes when driving external
circuits on a separate board (see the

Applications section). In

low noise applications, a ferrite bead is even more desirable.

VARIABLE GAIN AMPLIFIER

The differential X-AMP VGA provides precise input
attenuation and interpolation. It has a low input-referred noise
of 2.7 nV/√Hz and excellent gain linearity. A simplified block
diagram is shown in

GAIN

g

m

VIP

VIN

Figure 78.

GAIN INTERPOLATOR

(BOTH CHANNEL S)

6dB

R

2R

Figure 78. Simplified VGA Schematic

48dB

POSTAMP

+

–

POSTAMP

03199-078

X-AMP VGA

The input of the VGA is a differential R-2R ladder attenuator
network with 6 dB steps per stage and a net input impedance of
200 Ω differential. The ladder is driven by a fully differential
input signal from the LNA and is not intended for single-ended
operation. LNA outputs are ac-coupled to reduce offset and
isolate their common-mode voltage. The VGA inputs are biased
through the ladder’s center tap connection to VCM, which is
typically set to 2.5 V and is bypassed externally to provide a
clean ac ground.

The signal level at successive stages in the input attenuator
falls from 0 dB to −48 dB in 6 dB steps. The input stages of the
X-AMP are distributed along the ladder, and a biasing interpolator,
controlled by the gain interface, determines the input tap point.
With overlapping bias currents, signals from successive taps
merge to provide a smooth attenuation range from 0 dB to

−48 dB. This circuit technique results in excellent, linear-in-dB
gain law conformance and low distortion levels and deviates
±0.2 dB or less from the ideal. The gain slope is monotonic with
respect to the control voltage and is stable with variations in
process, temperature, and supply.

The X-AMP inputs are part of a gain-of-12 feedback amplifier
that completes the VGA. Its bandwidth is 150 MHz. The input
stage is designed to reduce feedthrough to the output and to
ensure excellent frequency response uniformity across gain
setting (see

Figure 12 and Figure 13).

Gain Control

Position along the VGA attenuator is controlled by a single­ended analog control voltage, V

, with an input range of

GAIN

40 mV to 1.0 V. The gain control scaling is trimmed to a slope
of 50 dB/V (20 mV/dB). Values of V

beyond the control

GAIN

range saturate to minimum or maximum gain values. Both
channels of the AD8332 are controlled from a single gain
interface to preserve matching. Gain can be calculated using
Equation 1 and Equation 2.

Gain accuracy is very good because both the scaling factor and
absolute gain are factory trimmed. The overall accuracy relative
to the theoretical gain expression is ±1 dB for variations in
temperature, process, supply voltage, interpolator gain ripple,
trim errors, and tester limits. The gain error relative to a best-fit
line for a given set of conditions is typically ±0.2 dB. Gain
matching between channels is better than 0.1 dB (

Figure 11
shows gain errors in the center of the control range). When
V

< 0.1 or > 0.95, gain errors are slightly greater.

GAIN

Rev. E | Page 27 of 40

AD8331/AD8332/AD8334

The gain slope can be inverted, as shown in Figure 73 (available
in most versions). The gain drops with a slope of −50 dB/V
across the gain control range from maximum to minimum gain.
This slope is useful in applications, such as automatic gain
control, where the control voltage is proportional to the
measured output signal amplitude. The inverse gain mode is
selected by setting the MODE pin HI.

Gain control response time is less than 750 ns to settle within 10%
of the final value for a change from minimum to maximum gain.

VGA Noise

In a typical application, a VGA compresses a wide dynamic
range input signal to within the input span of an ADC. While
the input-referred noise of the LNA limits the minimum
resolvable input signal, the output-referred noise, which
depends primarily on the VGA, limits the maximum
instantaneous dynamic range that can be processed at any one
particular gain control voltage. This limit is set in accordance
with the quantization noise floor of the ADC.

Output and input-referred noise as a function of V
plotted in

Figure 25 and Figure 27 for the short-circuited input

GAIN

are

conditions. The input noise voltage is simply equal to the output
noise divided by the measured gain at each point in the control
range.

The output-referred noise is flat over most of the gain range,
because it is dominated by the fixed output-referred noise of the
VGA. Values are 48 nV/√Hz in LO gain mode and 178 nV/√Hz
in HI gain mode. At the high end of the gain control range, the
noise of the LNA and source prevail. The input-referred noise
reaches its minimum value near the maximum gain control
voltage, where the input-referred contribution of the VGA
becomes very small.

At lower gains, the input-referred noise, and thus noise figure,
increases as the gain decreases. The instantaneous dynamic
range of the system is not lost, however, because the input
capacity increases with it. The contribution of the ADC noise
floor has the same dependence as well. The important
relationship is the magnitude of the VGA output noise floor
relative to that of the ADC.

With its low output-referred noise levels, these devices ideally
drive low voltage ADCs. The converter noise floor drops 12 dB
for every 2 bits of resolution and drops at lower input full-scale
voltages and higher sampling rates. ADC quantization noise is
discussed in the

Applications section.

The preceding noise performance discussion applies to a
differential VGA output signal. Although the LNA noise
performance is the same in single-ended and differential
applications, the VGA performance is not. The noise of the
VGA is significantly higher in single-ended usage, because the
contribution of its bias noise is designed to cancel in the differential

signal. A transformer can be used with single-ended applications
when low noise is desired.

Gain control noise is a concern in very low noise applications.
Thermal noise in the gain control interface can modulate the
channel gain. The resultant noise is proportional to the output
signal level and usually only evident when a large signal is
present. Its effect is observable only in LO gain mode, where the
noise floor is substantially lower. The gain interface includes an
on-chip noise filter, which reduces this effect significantly at
frequencies above 5 MHz. Care should be taken to minimize
noise impinging at the GAIN input. An external RC filter can be
used to remove V

source noise. The filter bandwidth should be

GAIN

sufficient to accommodate the desired control bandwidth.

Common-Mode Biasing

An internal bias network connected to a midsupply voltage
establishes common-mode voltages in the VGA and postamp.
An externally bypassed buffer maintains the voltage. The bypass
capacitors form an important ac ground connection, because
the VCM network makes a number of important connections
internally, including the center tap of the VGA’s differential
input attenuator, the feedback network of the VGA’s fixed gain
amplifier, and the feedback network of the postamplifier in both
gain settings. For best results, use a 1 nF and a 0.1 µF capacitor
in parallel, with the 1 nF nearest to the VCM pin. Separate
VCM pins are provided for each channel. For dc-coupling to a
3 V ADC, the output common-mode voltage is adjusted to

1.5 V by biasing the VCM pin.

POSTAMPLIFIER

The final stage has a selectable gain of 3.5 dB (×1.5) or 15.5 dB
(×6), set by the logic pin, HILO.
diagram.

Gm2

+

Gm1

VCM

–

F1

Gm2

Gm1

Figure 79. Postamplifier Block Diagram

Separate feedback attenuators implement the two gain settings.
These are selected in conjunction with an appropriately scaled
input stage to maintain a constant 3 dB bandwidth between the
two gain modes (~150 MHz). The slew rate is 1200 V/µs in HI
gain mode and 300 V/µs in LO gain mode. The feedback
networks for HI and LO gain modes are factory trimmed to
adjust the absolute gains of each channel.

Figure 79 is a simplified block

F2

VOH

VOL

3199-079

Rev. E | Page 28 of 40

AD8331/AD8332/AD8334

V

Noise

The topology of the postamplifier provides constant input­referred noise with the two gain settings and variable
output-referred noise. The output-referred noise in HI gain
mode increases (with gain) by four. This setting is recommended
when driving converters with higher noise floors. The extra gain
boosts the output signal levels and noise floor appropriately. When
driving circuits with lower input noise floors, the LO gain mode
optimizes the output dynamic range.

Although the quantization noise floor of an ADC depends on a
number of factors, the 48 nV/√Hz and 178 nV/√Hz levels are
well suited to the average requirements of most 12-bit and 10-bit
converters, respectively. An additional technique, described in
the

Applications section, can extend the noise floor even lower

for possible use with 14-bit ADCs.

Output Clamping

Outputs are internally limited to a level of 4.5 V p-p differential
when operating at a 2.5 V common-mode voltage. The postamp
implements an optional output clamp engaged through a
resistor from R

to ground. Table 8 shows a list of

CLMP

recommended resistor values.

Output clamping can be used for ADC input overload
protection, if needed, or postamp overload protection when
operating from a lower common-mode level, such as 1.5 V. The
user should be aware that distortion products increase as output
levels approach the clamping levels, and the user should adjust
the clamp resistor accordingly. For additional information, see
the

Applications section.

The accuracy of the clamping levels is approximately ±5% in LO
or HI mode.
few values of R

Figure 80 illustrates the output characteristics for a

.

CLMP

5.0

4.5

4.0

3.5

3.0

(V)

OL

2.5

,

OH

2.0

V

1.5

1.0

0.5

0

R

=

∞

CLMP

8.8kΩ

3.5kΩ

= 1.86kΩ

R

CLMP

3.5kΩ

8.8kΩ

R

=

∞

CLMP

–3 –2 –1 0 1 2 3

V

(V)

INH

Figure 80. Output Clamping Characteristics

03199-080

Rev. E | Page 29 of 40

AD8331/AD8332/AD8334

(

)

V

A

APPLICATIONS

C

LNA—EXTERNAL COMPONENTS

The LMD pin (connected to the bias circuitry) must be bypassed to
ground and signal sourced to the INH pin capacitively coupled
using 2.2 nF to 0.1 F capacitors (see

The unterminated input impedance of the LNA is 6 k. The
user can synthesize any LNA input resistance between 50  and
6 k. R

is calculated according to Equation 6 or selected from

FB

Table 7.

R

k33 ×

IN

R

=

FB

–k6

(6)

()

R

IN

Table 7. LNA External Component Values for Common
Source Impedances

RIN (Ω) RFB (Nearest STD 1% Value, Ω) CSH (pF)

50 280 22
75 412 12
100 562 8
200 1.13 k 1.2
500 3.01 k None
6 k

∞

When active input termination is used, a decoupling capacitor
(C

) is required to isolate the input and output bias voltages of

FB

the LNA.

Figure 81).

None

LMD

GAIN

1nF

0.1µF

1

LMD2

2

INH2

5V

3

VPS2

4

LON2

5

LOP2

6

COM2

7

10

11

12

13

14

8

9

VIP2

VIN2

VCM2

GAIN

RCLMP

VOH2

VOL2

COMM

*SEE TEXT

1nF0.1µF

1nF0.1µF

LMD1

INH1

VPS1

LON1

LOP1

COM1

VIP1

VIN1

VCM1

HILO

ENB

VOH1

VOL1

VPSV

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1nF

FB

C

*

SH

*

C

FB

*

R

FB

1nF

LNA OUT

0.1µF

1nF

5V

5V

*

*

0.1µF

VGA OUT

VGA OUT

5V

0.1µF

Figure 81. Basic Connections for a Typical Channel (AD8332 Shown)

LN

DECOUPLING

R

RESISTO R

FB

0.1µF

5V

0.1µF

TO EXT

CIRCUIT

LNA

SOURCE

03199-081

The shunt input capacitor, C

, reduces gain peaking at higher

SH

frequencies where the active termination match is lost due to
the gain roll-off of the LNA at high frequencies. The value of
C

diminishes as RIN increases to 500 Ω, at which point no

SH

capacitor is required. Suggested values for C
200 Ω are shown in

Table 7.

for 50 Ω ≤ RIN ≤

SH

When a long trace to Pin INH is unavoidable, or if both LNA
outputs drive external circuits, a small ferrite bead (FB) in series
with Pin INH preserves circuit stability with negligible effect on
noise. The bead shown is 75 Ω at 100 MHz (Murata BLM21 or
equivalent). Other values can prove useful.

Figure 82 shows the interconnection details of the LNA output.
Capacitive coupling between the LNA outputs and the VGA
inputs is required because of the differences in their dc levels
and the need to eliminate the offset of the LNA. Capacitor
values of 0.1 µF are recommended. There is 0.4 dB loss in gain
between the LNA output and the VGA input due to the 5 Ω
output resistance. Additional loading at the LOP and LON
outputs affect LNA gain.

VCM

LNA

DECOUPLING

RESISTO R

VIP

VIN

50Ω

50Ω

100Ω

100Ω

TO EXT

CIRCUIT

5Ω

LON

LNA

C

SH

LOP

5Ω

Figure 82. Interconnections of the LNA and VGA

Both LNA outputs are available for driving external circuits.
Pin LOP should be used in those instances when a single-ended
LNA output is required. The user should be aware of stray
capacitance loading of the LNA outputs, in particular LON. The
LNA can drive 100 Ω in parallel with 10 pF. If an LNA output is
routed to a remote PC board, it tolerates a load capacitance up
to 100 pF with the addition of a 49.9 Ω series resistor or ferrite
75 Ω/100 MHz bead.

Gain Input

The GAIN pin is common to both channels of the AD8332. The
input impedance is nominally 10 MΩ and a bypass capacitor
from 100 pF to1 nF is recommended.

03199-082

Rev. E | Page 30 of 40

AD8331/AD8332/AD8334

–

Parallel connected devices can be driven by a common voltage
source or DAC. Decoupling should take into account any
bandwidth considerations of the drive waveform, using the total
distributed capacitance.

If gain control noise in LO gain mode becomes a factor,
maintaining ≤15 nV/√Hz noise at the GAIN pin ensures
satisfactory noise performance. Internal noise prevails below
15 nV/√Hz at the GAIN pin. Gain control noise is negligible in
HI gain mode.

VCM Input

The common-mode voltage of Pin VCM, Pin VOL, and Pin VOH
defaults to 2.5 V dc. With output ac-coupled applications, the
VCM pin is unterminated; however, it must still be bypassed in
close proximity for ac grounding of internal circuitry. The VGA
outputs can be dc connected to a differential load, such as an
ADC. Common-mode output voltage levels between 1.5 V and

3.5 V can be realized at Pin VOH and Pin VOL by applying the
desired voltage at Pin VCM. DC-coupled operation is not
recommended when driving loads on a separate PC board.

The voltage on the VCM pin is sourced by an internal buffer
with an output impedance of 30 Ω and a ±2 mA default output
current (see

Figure 83). If the VCM pin is driven from an
external source, its output impedance should be <<30 Ω and its
current drive capability should be >>2 mA. If the VCM pins of
several devices are connected in parallel, the external buffer
should be capable of overcoming their collective output currents.
When a common-mode voltage other than 2.5 V is used, a
voltage-limiting resistor, R

, is needed to protect against

CLMP

overload.

INTERNAL

2mA MAX

AC GROUNDING F OR
INTERNAL CIRCUI TRY

CIRCUITRY

30Ω

Figure 83. VCM Interface

VCM

100pF

RO << 30Ω

0.1µF

NEW V

CM

03199-083

Logic Inputs—ENB, MODE, and HILO

The input impedance of all enable pins is nominally 25 kΩ and
can be pulled up to 5 V (a pull-up resistor is recommended) or
driven by any 3 V or 5 V logic families. The enable pin, ENB,
powers down the VGA—when pulled low, the VGA output
voltages are near ground. Multiple devices can be driven from a
common source. Consult

Table 3 , Tabl e 4, Ta ble 5, and Tabl e 6

for circuit functions controlled by the enable pins.

Optional Output Voltage Limiting

The RCLMP pin provides the user with a means to limit the
output voltage swing when used with loads that have no
provisions for prevention of input overdrive. The peak-to-peak
limited voltage is adjusted by a resistor to ground, and

Table 8
lists several voltage levels and the corresponding resistor value.
Unconnected, the default limiting level is 4.5 V p-p.

Note that third harmonic distortion increases as waveform
amplitudes approach clipping. For lowest distortion, the clamp
level should be set higher than the converter input span. A
clamp level of 1.5 V p-p is recommended for a 1 V p-p linear
output range, 2.7 V p-p for a 2 V p-p range, or 1 V p-p for
a 0.5 V p-p operation. The best solution is determined
experimentally.

Figure 84 shows third harmonic distortion
as a function of the limiting level for a 2 V p-p output signal.
A wider limiting level is desirable in HI gain mode.

20

V

= 0.75V

GAIN

–30

–40

–50

HD3 (dBc)

–60

–70

–80

1.5 2.0 2.5 3.0 4.03.5 4.5 5. 0

Figure 84. HD3 vs. Clamping Level for 2 V p-p Differential Input

CLAMP LIMIT LEVEL (V p-p)

HILO = LO

HILO = HI

03199-084

Table 8. Clamp Resistor Values

Clamp Resistor Value (kΩ)

Clamp Level (V p-p)

HILO = LO HILO = HI

0.5 1.21

1.0 2.74 2.21

1.5 4.75 4.02

2.0 7.5 6.49

2.5 11 9.53

3.0 16.9 14.7

3.5 26.7 23.2

4.0 49.9 39.2

4.4 100 73.2

Pin HILO is compatible with 3 V or 5 V CMOS logic families. It
is either connected to ground or pulled up to 5 V, depending on
the desired gain range and output noise.

Rev. E | Page 31 of 40

AD8331/AD8332/AD8334

X

X

Output Decoupling

When driving capacitive loads greater than about 10 pF, or long
circuit connections on other boards, an output network of
resistors and/or ferrite beads can be useful to ensure stability.
These components can be incorporated into a Nyquist filter
such as the one shown in

Figure 81. In Figure 81, the resistor
value is 84.5 Ω. The AD8332-EVAL incorporates 100  in
parallel with a 120 nH bead. Lower value resistors are permissible
for applications with nearby loads or with gains less than 40 dB.
The exact values of these components can be selected empirically.

An antialiasing noise filter is typically used with an ADC. Filter
requirements are application dependent.

When the ADC resides on a separate board, the majority of
filter components should be placed nearby to suppress noise
picked up between boards and to mitigate charge kickback from
the ADC inputs. Any series resistance beyond that required for
output stability should be placed on the ADC board.

Figure 85
shows a second-order, low-pass filter with a bandwidth of
20 MHz. The capacitor is chosen in conjunction with the 10 pF
input capacitance of the ADC.

OPTIONAL

BACKPLANE

84.5Ω

84.5Ω

0.1µF

0.1µF

1.5µH

1.5µH

158Ω

158Ω

18pF

ADC

03199-085

Figure 85. 20 MHz Second-Order, Low-Pass Filter

DRIVING ADCs

The output drive accommodates a wide range of ADCs. The
noise floor requirements of the VGA depend on a number of
application factors, including bit resolution, sampling rate, full­scale voltage, and the bandwidth of the noise/antialias filter. The
output noise floor and gain range can be adjusted by selecting
HI or LO gain mode.

4V p-p DIFF,

VOH

VOL

48nV/ Hz

187Ω

2:1

187Ω

2V p-p DIFF,

24nV/ Hz

374Ω

LPF

ADC

AD6644

03199-086

Figure 86. Adjusting the Noise Floor for 14-Bit ADCs

OVERLOAD

These devices respond gracefully to large signals that overload
its input stage and to normal signals that overload the VGA
when the gain is set unexpectedly high. Each stage is designed
for clean-limited overload waveforms and fast recovery when
gain setting or input amplitude is reduced.

Signals larger than ±275 mV at the LNA input are clipped to

MODE

Figure 48

-AMP

OVERLOAD

25mV

41dB

24.5dB

5 V p-p differential prior to the input of the VGA.
shows the response to a 1 V p-p input burst. The symmetric
overload waveform is important for applications, such as CW
Doppler ultrasound, where the spectrum of the LNA outputs
during overload is critical. The input stage is also designed to
accommodate signals as high as ±2.5 V without triggering the
slow-settling ESD input protection diodes.

Both stages of the VGA are susceptible to overload. Postamp
limiting is more common and results in the clean-limited
output characteristics found in
cases. The graph in

Figure 87 summarizes the combinations of

Figure 49. Recovery is fast in all

input signal and gain that lead to the different types of overload.

43.5

GAIN (dB)

POSTAMP

OVERLOAD

15mV

LO GAIN

MODE

-AMP

OVERLOAD

25mV

29dB

24.5dB

56.5

GAIN (dB)

POSTAMP

OVERLOAD

4mV

HI GAIN

The relative noise and distortion performance of the two gain
modes can be compared in

Figure 25 and Figure 31 through
Figure 41. The 48 nV/√Hz noise floor of the LO gain mode is
suited to converters with higher sampling rates or resolutions
(such as 12 bits). Both gain modes can accommodate ADC full-

–4.5

1m

INPUT AMP LITUDE (V)

Figure 87. Overload Gain and Signal Conditions

LNA OVERLOAD

0.2750.110m

7.5

1

1m 0.2750.110m 1

INPUT AMPLITUDE (V)

LNA OVERLOAD

03199-087

scale voltages as high as 4 V p-p. Because distortion performance
remains favorable for output voltages as high as 4 V p-p (see
Figure 36), it is possible to lower the output-referred noise even
further by using a resistive attenuator (or transformer) at the
output. The circuit in

Figure 86 has an output full-scale range of
2 V p-p, a gain range of −10.5 dB to +37.5 dB, and an output
noise floor of 24 nV/√Hz, making it suitable for some 14-bit
ADC applications.

The previously mentioned clamp interface controls the
maximum output swing of the postamp and its overload
response. When the clamp feature is not used, the output level
defaults to approximately 4.5 V p-p differential centered at

2.5 V common mode. When other common-mode levels are set
through the VCM pin, the value of R

should be selected for

CLMP

graceful overload. A value of 8.3 kΩ or less is recommended for

1.5 V or 3.5 V common-mode levels (7.2 kΩ for HI gain mode).
This limits the output swing to just above 2 V p-p differential.

Rev. E | Page 32 of 40

AD8331/AD8332/AD8334

V

OPTIONAL INPUT OVERLOAD PROTECTION

Applications in which high transients are applied to the LNA
input can benefit from the use of clamp diodes. A pair of back­to-back Schottky diodes can reduce these transients to manageable
levels.

Figure 88 illustrates how such a diode-protection scheme

can be connected.

OPTIONAL
SCHOTTKY

OVERLOAD

CLAMP

231

BAS40-04

FB

0.1µF
2

C

R

C

FB

SH

R

FB

SH

3

4

INH

VPSL

LON

COMM

ENBL

20

19

03199-088

Figure 88. Input Overload Clamping

When selecting overload protection, the important parameters
are forward and reverse voltages and t
BAS40-04 series shown in

Figure 88 has a τrr of 100 ps and VF of

(or τrr). The Infineon

rr

310 mV at 1 mA. Many variations of these specifications can be
found in vendor catalogs.

LAYOUT, GROUNDING, AND BYPASSING

Due to their excellent high frequency characteristics, these
devices are sensitive to their PCB environment. Realizing
expected performance requires attention to detail critical to
good high speed board design.

MULTIPLE INPUT MATCHING

Matching of multiple sources with dissimilar impedances can be
accomplished as shown in

Figure 90. A relay and low supply
voltage analog switch can be used to select between multiple
sources and their associated feedback resistors. An

ADG736

dual SPDT switch is shown in this example; however, multiple
switches are also available and users are referred to the Analog
Devices Selection Guide for switches and multiplexers.

DISABLING THE LNA

Where accessible, connection of the LNA enable pin to ground
powers down the LNA, resulting in a current reduction of about
half. In this mode, the LNA input and output pins can be left
unconnected; however, the power must be connected to all the
supply pins for the disabling circuit to function.
illustrates the connections using an AD8331 as an example.

1

NC

LMD

AD8331

2

NC

INH

C

FB

0.018µF

5

NC

3

VPSL

4

LON

COMM

ENBL

ENBV

COMM

20

19

18

17

Figure 89

5V

A multilayer board with power and ground planes is
recommended with blank areas in the signal layers filled with
ground plane. Be certain that the power and ground pins
provided for robust power distribution to the device are
connected. Decouple the power supply pins with surface-mount
capacitors as close as possible to each pin to minimize impedance
paths to ground. Decouple the LNA power pins from the VGA
supply using ferrite beads. Together with the capacitors, ferrite
beads eliminate undesired high frequencies without reducing
the headroom. Use a larger value capacitor for every 10 chips to
20 chips to decouple residual low frequency noise. To minimize
voltage drops, use a 5 V regulator for the VGA array.

Several critical LNA areas require special care. The LON and
LOP output traces must be as short as possible before connecting to
the coupling capacitors connected to Pin VIN and Pin VIP. R

FB

must be placed near the LON pin as well. Resistors must be
placed as close as possible to the VGA output pins, VOL and
VOH, to mitigate loading effects of connecting traces. Values
are discussed in the

Output Decoupling section.

Signal traces must be short and direct to avoid parasitic effects.
Wherever there are complementary signals, symmetrical layout
should be employed to maintain waveform balance. PCB traces
should be kept adjacent when running differential signals over a
long distance.

5

NC

LOP

6

COML

0.1µF

VIN

0.1µF

MODE

7

8

9

VIP

VIN

MODE

10

GAIN

GAIN

16

VOL

VOUT

15

VOH

14

VPOS 5V

13

HILO

RCLMP

VCM

HILO

12

11

VCM

R

CLMP

03199-089

Figure 89. Disabling the LNA

Rev. E | Page 33 of 40

AD8331/AD8332/AD8334

18nF

200Ω

50Ω

0.1µF

Figure 90. Accommodating Multiple Sources

SELECT R

INH

LMD

AD8332

ADG736

FB

LNA

1.13kΩ

280Ω

LON

5Ω

LOP

5Ω

03199-090

ULTRASOUND TGC APPLICATION

The AD8332 ideally meets the requirements of medical and
industrial ultrasound applications. The TGC amplifier is a key
subsystem in such applications, because it provides the means
for echolocation of reflected ultrasound energy.

Figure 91 through Figure 93 are schematics of a dual, fully
differential system using the AD8332 and the
high speed ADC with conversion speeds as high as 65 MSPS.

AD9238, 12-bit

Using the EVAL-AD8332/AD9238 evaluation board and a high
speed ADC FIFO evaluation kit connected to a laptop, an FFT
can be performed on the AD8332. With the on-board clock of
20 MHz, minimal low-pass filtering, and both channels driven
with a 1 MHz filtered sine wave, the THD is −75 dB, noise floor
is −93 dB, and HD2 is −83 dB.

HIGH DENSITY QUAD LAYOUT

The AD8334 is the ideal solution for applications with limited
board space.
away from this very compact quad VGA. Note that none of the
signal paths crosses and that all four channels are spaced apart
to eliminate crosstalk.

In this example, all of the components shown are 0402 size;
however, the same layout is executable at the expense of slightly
more board area. The sketch also assumes that both sides of the
printed circuit board are available for components, and that the
bypass and power supply decoupling circuitry is located on the
wiring side of the board.

Figure 94 represents four channels routed to and

Rev. E | Page 34 of 40

AD8331/AD8332/AD8334

S3

E

IN2

TP3

(RED)

TP4

L19
SAT

L20
SAT

+5V

120nH FB

120nH FB

FILTER

C67

SAT

TB1
+5V

(BLACK)

TB2

GND

OPTIONAL 4-POLE LOW-PASS

VIN+B

C66
SAT

–B

V

IN

TP5

C50

0.1µF
C49

0.1µF

L12
120nH FB

C80

22pF

+5VLNA

C41

0.1µF

C53

0.1µF

C48

0.1µF

C83
1nF

C69

R27

100Ω

L11

120nH FB

L10

120nH FB

R26

100Ω

C68
1nF

JP5

IN2

C74
1nF

C78

1nF

CFB2

+

C46
1µF

L7

+5VGA

L6

+5VLNA

L17

SAT

JP12

L18

SAT

18nF

RFB2

274Ω

0.1µF

VCM1

JP13

TP2 GAIN

TP7 GND

(R

CLMP

DC2H

C54

0.1µF

C55

0.1µF

JP7

DC2L

C51

R3

JP8

)

0.1µF

AD8332ARU

1

LMD2

2

INH2

3

VPS2

4

LON2

5

LOP2

6

COM2

7

VIP2

8

VIN2

9

VCM2

10

GAIN

11

RCLMP

12

VOH2

13

VOL2

14

COM

+5VGA

C45

0.1µF

LMD1

INH1

VPS1

LON1

LOP1

COM1

VIP1

VIN1

VCM1

HILO

ENB

VOH1

VOL1

VPSV

C85
1nF

28

27

26

+5VLNA

25

24

23

22

21

20

C77
1nF

19

+5VGA

18

17

16

15

C70

0.1µF

JP6

IN1

ENABLE
JP16
DISABLE

120nH FB

120nF FB

22pF

C42

0.1µF

C43

0.1µF

R24

100Ω

L9

L8

R25

100Ω

C79

VCM1

120nH FB

CFB1
18nF

RFB1
274Ω

C59

0.1µF

C58

0.1µF

C56

0.1µF

JP10

L13

+5VGA

HI GAIN
JP10
LO GAIN

JP9

JP17

TP6

C60

0.1µF

OPTIONAL 4-POLE LOW-PASS

L1

SAT

L14
SAT

FILTER

L15
SAT

C64

SAT

SAT

E

L16

S1

IN1

VIN+A

C65
SAT

VIN–A

03199-091

Figure 91. Schematic, TGC, VGA Section Using an AD8332 and AD9238

Rev. E | Page 35 of 40

AD8331/AD8332/AD8334

V

ADP3339AKC-3.3

+5V

312

OUT

IN

OUT

TAB

S2

EXT CLOCK

R17

49.9Ω

+3.3VCLK

C86

0.1µF

V

DD

20MHz

GND

SG-636PCE

2

OUT

R1

L5

120nH FB

L4

120nH FB

L3

120nH FB

L2

120nH FB

C31

0.1µF

C30

0.1µF

C29

0.1µF

C1

0.1µF

VIN+_A

V

–_A

IN

C35

0.1µF

C36

0.1µF

R12

1.5kΩ

R4

1.5kΩ

C33

10µF

6.3V

+

R5

33Ω

R6

33Ω

C17

0.1µF

GND

C44
1µF

+

VREF

C38

0.1µF

C34

10µF

6.3V

10µF

C37

0.1µF

1.5kΩ1. 5kΩ

0.1µF

R8

R20

ADCLK

TP 13

8965

C20

0.1µF

JP11JP3

4.7kΩ

TP 12

JP1

1

33Ω

R7

33Ω

R41

DATA

CLK

2

VIN–B

V

+B

IN

C63

0.1µF

+3.3VCLK

R18
499Ω

R16
5kΩ

R19
499Ω

4.7kΩ

C47

+

10µF

6.3V

EXT

JP4

3

2

1

INT

14

OE

3

ADCLK

U5

74VHC04

U5

74VHC04

4312

U5

74VHC04

U5

74VHC04

U6

U5

74VHC04

1213

SPARES

U5

74VHC04

1011

Figure 92. Converter Schematic, TGC Using an AD8332 and AD9238

C32

0.1µF

C39

C16

10µF

0.1µF

C19
1nF

3

6.3V

+3.3VAVDD

C2

+

C61

18pF

C18
1nF

C40

TP9

+

C12
10µF

6.3V

C15
1nF

C62

18pF

R9
0Ω

+3.3VADDIG

C52

10nF

C57

10nF

DNC

DNC

D0_B

D1_B

D2_B

D3_B

D4_B

D5_B

0.1µF

C26

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

C22

0.1µF

AGND

VIN+_A

VIN–_A

AGND

AVDD

REFT_A

REFB_A

VREF

SENSE

REFB_B

REFT_B

AVDD

AGND

VIN–_B

VIN+_B

AGND

AVDD

CLK_B

DCS

DFS

PDWN_B

OEB_B

DNC

DNC

D0_B

D1_B

D2_B

DRGND

DRVDD

D3_B

D4_B

D5_B

C24
1nF

C21
1nF

AVDD

CLK_A

SHARED_REF

MUX_SELECT

PDWN_A

OEB_A

OTR_A

D11_A (MSB)

D10_A

D9_A

D8_A

DRGND

DRVDD

D7_A

D6_A

D5_A

D4_A

U1 A/D CONVERTER AD9238

D3_A

D2_A

D1_A

D0_A

DNC

DNC

DRVDD

DRGND

OTR_B

D11_B (MSB)

D10_B

D9_B

D8_B

D7_B

D6_B

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

ADCLK

R10
0Ω

4.7kΩ

R15
0Ω

R11
100Ω

SHARED

Y

R14

+3.3VADDIG

OTR_A

D11_A

D10_A

D9_A

D8_A

C23

0.1µF

D7_A

D6_A

D5_A

D4_A

D3_A

D2_A

D1_A

D0_A

DNC

DNC

C13
1nF

OTR_B

D11_B

D10_B

D9_B

D8_B

D7_B

D6_B

JP2

REF

N

+3.3VADDIG

C25
1nF

C14

0.1µF

C11

+

10µF

6.3V

03199-092

Rev. E | Page 36 of 40

AD8331/AD8332/AD8334

R40
22Ω

22 × 4

18

RP 1

7

2

6

3

54

18

22 × 4

RP2

7

2

6

3

54

18

22 × 4

RP 3

7

2

6

3

54

18

22 × 4

RP 4

7

2

6

3

54

2

4

6

8

10

12

14

HEADER UP MALE NO SHROUD

16

18

20

22

24

26 25

28 27

30

34

36

38

40

SAM080UPM

1

3

5

7

9

11

13

15

17

19

21

23

29

3132

33

35

37

39

OTR_A

D11_A

D10_A

D9_A

D8_A

D7_A

D6_A

D5_A

D4_A

D3_A

D2_A

D1_A

D0_A

DNC

DNC

DATACLKA

22 × 4

1

RP 9

2

3

4

1

22 × 4

RP 10

2

3

4

1

22 × 4

RP 11

2

3

4

1

22 × 4

RP 12

2

3

4

1

G1

74VHC541

19

G2

2

8

A1

7

3

A2

6

4

A3

5

5

A4

8

6

A5

7

7

A6

6

8

A7

5

9

A8

U10

VCC

GND

20

+

10

18

Y1

17

Y2

16

Y3

15

Y4

14

Y5

13

Y6

12

Y7

11

Y8

C3

0.1µF

C28
10µF

6.3V

+3.3VDVDD

+3.3VDVDD

1

G1

74VHC541

19

G2

8

2

A1

3

7

A2

6

4

A3

5

5

A4

8

6

A5

7

7

A6

8

6

A7

5

9

A8

20

U7

VCC

GND

10

18

Y1

17

Y2

16

Y3

15

Y4

14

Y5

13

Y6

12

Y7

11

Y8

C8

0.1µF

C10

0.1µF

+

C76
10µF

6.3V

OTR_B

D11_B

D10_B

D9_B

D8_B

D7_B

D6_B

D5_B

D4_B

D3_B

D2_B

D1_B

D0_B

DNC

DNC

19

8

1

22 × 4

RP 13

7

2

6

3

5

4

22 × 4

8

1

RP 14

7

2

6

3

5

4

18

22 × 4

RP 15

19

7

2

6

3

5

4

22 × 4

8

1

RP 16

7

2

6

3

5

4

DATACLK

+3.3VDVDD

1

2

3

4

5

6

7

8

9

G1

74VHC541

G2

A1

A2

A3

A4

A5

A6

A7

A8

20

U2

VCC

GND

10

18

Y1

17

Y2

16

Y3

15

Y4

14

Y5

13

Y6

12

Y7

11

Y8

++

C7

0.1µFC90.1µF

C27
10µF

6.3V

+3.3VDVDD

1

2

3

4

5

6

7

8

9

G1

G2

A1

A2

A3

A4

A5

A6

A7

A8

74VHC541

20

VCC

U3

GND

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

C4

10

0.1µFC50.1µFC60.1µF

18

17

16

15

14

13

12

11

+

C75
10µF

6.3V

Figure 93. Interface Schematic, TGC Using an AD8332 and AD9238

22 × 4

18

RP 5

7

2

6

3

54

8

22 × 4

1

RP 6

7

2

6

3

54

18

22 × 4

RP 7

7

2

6

3

54

18

22 × 4

RP 8

7

2

6

3

54

R39
22Ω

42

44

46

48 47

52

HEADER UP MALE NO SHROUD

54 53

56 55

58

60

62

64

66

68

70

72

74

76

78

80

SAM080UPM

41

43

45

4950

51

57

59

61

63

65

67

69

71

73

75

77

79

03199-093

Rev. E | Page 37 of 40

AD8331/AD8332/AD8334

CH 1 LNA INPUT

CH 2 LNA INPUT

CH 3 LNA INPUT

64

1

INH2

2

LMD2

3

COM2X

4

LON2

5

LOP2

6

VIP2

7

VIN2

8

VPS2

9

VPS3

10

VIN3

11

VIP3

12

LOP3

13

LON3

14

COM3X

15

LMD3

16

INH3

INH1

COM2

COM3

LMD1

COM1

COM4

INH4

LMD4

20

58 575962 61 6063

LOP1

LON1

COM1X

POWER SUPPLY DECOUPLING

LOCATED O N WIRING SIDE

COM4X

LON4

LOP4

21

22 23 24

VIP1

AD8334

VIP4

50 4956 55 5154 53 52

VIN1

VPS1

VIN4

VPS4

EN12

EN34

HILO

VCM4

30 31 32

VCM1

VCM3

GAIN12

CLMP12

GAIN34

CLMP34

29

2825 26 2717 18 19

VCM2

COM12

VOH1

VOL1

VPS12

VOL2

VOH2

COM12

MODE

COM34

VOH3

VOL3

VPS34

VOL4

VOH4

COM34

NC

48

47

46

45

44

43

42

41

40

NC

39

38

37

36

35

34

33

CH 1 DIFFERENTIAL

OUTPUT

CH 2 DIFFERENTIAL

OUTPUT

CH 3 DIFFERENTIAL

OUTPUT

CH 4 DIFFERENTIAL

OUTPUT

CH 4 LNA INPUT

3199-094

Figure 94. Signal Path and Board Layout for AD8334

Rev. E | Page 38 of 40

AD8331/AD8332/AD8334

C

Y

OUTLINE DIMENSIONS

9.80

9.70

9.60

0.345

0.341

0.337

PIN 1

0.15

0.05

OPLANARIT

0.10

28

0.65
BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AE

1.20 MAX

SEATING

PLANE

15

4.50

4.40

4.30

0.20

0.09

6.40 BSC

141

Figure 95. 28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

5.00

BSC SQ

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING
PLANE

TOP

VIEW

BSC SQ

0.80 MAX

0.65 TYP

0.30

0.23

0.18

Figure 97. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

PIN 1

8°
0°

0.75

0.60

0.45

0.010

0.004

COPLANARITY

0.004

0.08

0.60 MAX

25

24

EXPOSED

PAD

(BOTTOM VIEW)

17

16

3.50 REF

0.60 MAX

0.50

4.75

0.05 MAX

0.02 NOM

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

BSC

0.50

0.40

0.30

COPLANARIT Y

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

20 11

1

0.065

0.049

BSC

0.012

0.008

0.025

COMPLIANT TO JEDEC STANDARDS MO-137-AD

0.069

0.053

10

SEATING
PLANE

0.158

0.154

0.150

0.244

0.236

0.228

0.010

0.006

8°
0°

Figure 96. 20-Lead Shrink Small Outline Package [QSOP]

(RQ-20)

Dimensions shown in Inches

PIN 1

32

1

8

9

INDICATOR

3.25

3.10 SQ

2.95

0.25 MIN

THE EXPOSE PAD IS NOT CONNECTED
INTERNALLY. FOR I NCREASED RELIABILITY
OF THE SOL DER JOINTS AND MAXIMUM
THERMAL CAPABIL ITY IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO
THE GROUND PLANE.

041806-A

0.050

0.016

Rev. E | Page 39 of 40

AD8331/AD8332/AD8334

1.00

0.85

0.80

SEATING

PLANE

12° MAX

9.00

BSC SQ

PIN 1
INDICATOR

TOP

VIEW

0.80 MAX

0.65 TYP

0.50 BSC

0.60 MAX

8.75

BSC SQ

0.45

0.40

0.35

0.05 MAX

0.02 NOM

0.20 REF

*

COMPLIANT TO JEDEC S TANDARDS MO-220-VMMD-4

EXCEPT FOR EXPOSED PAD DIMENSION

49

48

33

32

0.60 MAX

EXPOSED PAD

(BOTTOM VIEW)

7.50
REF

0.30

0.25

0.18

64

17

PIN 1
INDICATOR

1

*

4.85

4.70 SQ

4.55

16

THE EXPOSE PAD IS NOT CONNECTED
INTERNALL Y. FOR INCREASED RELIABIL ITY
OF THE S OLDER JOI NTS AND MAXI MUM
THERMAL CAPABILITY I T IS RECO MMENDED
THAT THE PAD BE SOLDERED TO
THE GROUND PL ANE.

031706-A

Figure 98. 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

9 mm × 9 mm Body, Very Thin Quad

(CP-64-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8331ARQ –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20
AD8331ARQ-REEL –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20
AD8331ARQ-REEL7 –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20
AD8331ARQZ
AD8331ARQZ-RL
AD8331ARQZ-R7
AD8331-EVAL Evaluation Board with AD8331ARQ
AD8332ACP-R2 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2
AD8332ACP-REEL –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2
AD8332ACP-REEL7 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2
AD8332ACPZ-R7
AD8332ACPZ-RL
AD8332ARU –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD8332ARU-REEL –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD8332ARU-REEL7 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD8332ARUZ
AD8332ARUZ-R7
AD8332ARUZ-RL
AD8332-EVAL Evaluation Board with AD8332ARU
EVAL-AD8332/AD9238 Evaluation Board with AD8332ARU and AD9238 ADC
AD8334ACPZ-WP
AD8334ACPZ-REEL
AD8334ACPZ-REEL7
AD8334-EVAL Evaluation Board with AD8334ACP

1

Z = Pb-free part.

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03199-0-4/06(E)

1

1

1

1

1

1

1

1

1

1

1

–40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20
–40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20
–40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20

–40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2
–40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2

–40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
–40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
–40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28

–40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1
–40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1
–40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1

Rev. E | Page 40 of 40