Datasheet AD8328 Datasheet (ANALOG DEVICES)

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FEATURES

Supports DOCSIS and EuroDOCSIS standards for reverse

path transmission systems
Gain programmable in 1 dB steps over a 59 dB range
Low distortion at 60 dBmV output

−57.5 dBc SFDR at 21 MHz

−54 dBc SFDR at 65 MHz
Output noise level @ minimum gain 1.2 nV/√Hz
Maintains 300 Ω output impedance Tx-enable and

Tx-disable condition
Upper bandwidth: 107 MHz (full gain range)
5 V supply operation
Supports SPI interfaces

APPLICATIONS

DOCSIS and EuroDOCSIS cable modems
CATV set-top boxes
CATV telephony modems
Coaxial and twisted pair line drivers

Cable Line Driver

AD8328

FUNCTIONAL BLOCK DIAGRAM

BYP

AD8328

IN+

IN–

DIFF
OR
SINGLE
INPUT
AMP

ZIN (SINGLE) = 800Ω

(DIFF) = 1.6kΩ

Z

IN

GND

VERNIER

DATEN

ATTENUATIO N

CORE

8

DECODE

8

DATA LATCH

8

SHIFT

REGISTER

SDATA CLK TXEN

POWER

POWER- DOWN

Figure 1.

AMP

Z
300Ω

LOGIC

OUT

SLEEP

DIFF =

V

OUT+

V

OUT–

RAMP

03158-001

V

V

GENERAL DESCRIPTION

The AD83281 is a low cost amplifier designed for coaxial line
driving. The features and specifications make the AD8328
ideally suited for MCNS-DOCSIS and EuroDOCSIS applications.
The gain of the AD8328 is digitally controlled. An 8-bit serial
word determines the desired output gain over a 59 dB range,
resulting in gain changes of 1 dB/LSB.

The AD8328 accepts a differential or single-ended input signal.
The o

utput is specified for driving a 75 Ω load through a 2:1

transformer.

Distortion performance of −53 dBc is achieved with an output

el up to 60 dBmV at 65 MHz bandwidth over a wide

lev
temperature range.

This device has a sleep mode function that reduces the quiescent

urrent to 2.6 mA and a full power-down function that reduces

c
power-down current to 20 µA.

The AD8328 is packaged in a low cost 20-lead LFCSP and
a 20-lead QSO
and has an operational temperature range of −40°C to +85°C.

P. The AD8328 operates from a single 5 V supply

50

–52

–54

–56

–58

–60

–62

DISTORTION (dBc)

–64

–66

–68

–70

5 152535455565

Figure 2. Worst Harmonic Distortion vs. Frequency

1

Patent pending.

V

= 60dBmV

OUT

@ MAX GAIN,
THIRD HARMONIC

V

OUT

@ MAX GAIN,
SECOND HARMONIC

= 60dBmV

FREQUENCY (MHz )

03158-002

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

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TABLE OF CONTENTS

Features.............................................................................................. 1

Signal Integrity Layout Considerations................................... 11

Applications....................................................................................... 1

Functional Block Diagram ..............................................................1

General Description......................................................................... 1

Revision History ...............................................................................2

Specifications..................................................................................... 3

Logic Inputs (TTL-/CMOS-Compatible Logic)....................... 4

Timing Requirements.................................................................. 4

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions........................... 7

Typical Performance Characteristics............................................. 8

Applications..................................................................................... 10

General Applications..................................................................10

Circuit Description.....................................................................10

SPI Programming and Gain Adjustment................................ 10

Initial Power-Up......................................................................... 12

RAMP Pin and BYP Pin Features............................................ 12

Transmit Enable (TXEN) and

Distortion, Adjacent Channel Power, and DOCSIS .............. 12

Noise and DOCSIS..................................................................... 12

Evaluation Board Features and Operation.............................. 12

Differential Signal Source ......................................................... 13

Differential Signal from Single-Ended Source....................... 13

Single-Ended Source.................................................................. 13

Overshoot on PC Printer Ports ................................................ 13

Installing Visual Basic Control Software................................. 13

Running AD8328 Software....................................................... 14

Controlling Gain/Attenuation of the AD8328....................... 14

Transmit Enable and Sleep Mode............................................. 14

Memory Functions..................................................................... 14

SLEEP

...................................... 12

Input Bias, Impedance, and Termination................................ 10

Output Bias, Impedance, and Termination............................. 10

Power Supply............................................................................... 11

REVISION HISTORY

10/05—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Table 4............................................................................ 6

Updated Outline Dimensions....................................................... 17

Changes to Ordering Guide.......................................................... 18

11/02—Revision 0: Initial Version

Outline Dimensions....................................................................... 17

Ordering Guide............................................................................... 18

Rev. A | Page 2 of 20

AD8328

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SPECIFICATIONS

TA = 25°C, VS = 5 V, RL = RIN = 75 Ω, VIN (differential) = 29 dBmV. The AD8328 is characterized using a 2:1 transformer1 at the device output.

Table 1.

Parameter Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Specified AC Voltage Output = 60 dBmV, max gain 29 dBmV
Input Resistance Single-ended input 800 Ω
Differential input 1600 Ω
Input Capacitance 2 pF

GAIN CONTROL INTERFACE

Voltage Gain Range 58 59.0 60 dB

Maximum Gain Gain code = 60 decimal codes 30.5 31.5 32.5 dB
Minimum Gain Gain code = 1 decimal code −28.5 −27.5 −26.5 dB
Output Step Size 0.6 1.0 1.4 dB/LSB
Output Step Size Temperature Coefficient TA = −40°C to +85°C ±0.0005 dB/°C

OUTPUT CHARACTERISTICS

Bandwidth (−3 dB) All gain codes (1 to 60 decimal codes) 107 MHz
Bandwidth Roll-Off f = 65 MHz 1.2 dB
1 dB Compression Point2 Maximum gain, f = 10 MHz, output referred 17.9 18.4 dBm

Minimum gain, f = 10 MHz, input referred 2.2 3.3 dBm

Output Noise2

Maximum Gain f = 10 MHz 135 151 nV/√Hz
Minimum Gain f = 10 MHz 1.2 1.3 nV/√Hz
Tx Disable f = 10 MHz 1.1 1.2 nV/√Hz

Noise Figure2

Maximum Gain f = 10 MHz 16.7 17.7 dB

Differential Output Impedance Tx enable and Tx disable 75 ± 30%3 Ω

OVERALL PERFORMANCE

Second-Order Harmonic Distortion
f = 33 MHz, V
f = 65 MHz, V
Third-Order Harmonic Distortion

f = 65 MHz, V

POWER CONTROL

POWER SUPPLY

Minimum gain 18 26 34 mA
Tx disable (TXEN = 0) 1 2.6 3.5 mA

OPERATING TEMPERATURE RANGE −40 +85 °C

2, 6

ACPR

−58 −56 dBc

Isolation (Tx Disable)2 Maximum gain, f = 65 MHz −85 −81 dB

Tx Enable Settling Time Maximum gain, VIN = 0 2.5 μs
Tx Disable Settling Time Maximum gain, VIN = 0 3.8 μs
Output Switching Transients2 Equivalent output = 31 dBmV 2.5 6 mV p-p
Equivalent output = 61 dBmV 16 54 mV p-p
Output Settling

Due to Gain Change Minimum to maximum gain 60 ns
Due to Input Step Change Maximum gain, VIN = 29 dBmV 30 ns

Operating Range 4.75 5 5.25 V
Quiescent Current Maximum gain 98 120 140 mA

4, 5

4, 5

f = 21 MHz, V

= 60 dBmV @ maximum gain −67 −56 dBc

OUT

= 60 dBmV @ maximum gain −61 −55 dBc

OUT

= 60 dBmV @ maximum gain −57.5 −56 dBc

OUT

= 60 dBmV @ maximum gain −54 −52.5 dBc

OUT

mode (power-down)

SLEEP

1 20 100 μA

Rev. A | Page 3 of 20

AD8328

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1

TOKO 458 PT-1087 used for above specifications. Typical insertion loss of 0.3 dB @ 10 MHz.

2

Guaranteed by design and characterization to ±4 sigma for TA = 25°C.

3

Measured through a 2:1 transformer.

4

Specification is worst case over all gain codes.

5

Guaranteed by design and characterization to ±3 sigma for TA = 25°C.

6

VIN = 29 dBmV, QPSK modulation, 160 kSPS symbol rate.

LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC)

DATEN

, CLK, SDATA, TXEN,

Table 2.

Parameter Min Typ Max Unit

Logic 1 Voltage 2.1 5.0 V
Logic 0 Voltage 0 0.8 V
Logic 1 Current (V
Logic 0 Current (V
Logic 1 Current (V
Logic 0 Current (V
Logic 1 Current (V
Logic 0 Current (V

= 5 V) CLK, SDATA, DATEN

INH

= 0 V) CLK, SDATA, DATEN

INL

= 5 V) TXEN 50 190 μA

INH

= 0 V) TXEN −250 −30 μA

INL

= 5 V) SLEEP

INH

= 0 V) SLEEP

INL

SLEEP

, VCC = 5 V; full temperature range.

0 20 nA
–600 –100 nA

50 190 μA

−250 −30 μA

TIMING REQUIREMENTS

Full temperature range, VCC = 5 V, tR = tF = 4 ns, f

Table 3.

Parameter Min Typ Max Unit

Clock Pulse Width (tWH) 16.0 ns
Clock Period (tC) 32.0 ns
Setup Time SDATA vs. Clock (tDS) 5.0 ns
Setup Time DATEN vs. Clock (tES)
Hold Time SDATA vs. Clock (tDH) 5.0 ns
Hold Time DATEN vs. Clock (tEH)
Input Rise and Fall Times, SDATA, DATEN, Clock (tR, tF)

= 8 MHz, unless otherwise noted.

CLK

15.0 ns

3.0 ns
10 ns

Rev. A | Page 4 of 20

AD8328

S

A

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t

DS

SDATA

CLK

VALID DATA- WORD G 1

MSB. . . .LSB

t

C

t

WH

VALID DATA- WORD G 2

t

EH

GAIN TRANSFER (G1)

t

GS

GAIN TRANSFER (G2)

t

OFF

t

ON

03158-003

DATEN

TXEN

ANALOG

OUTPUT

t

ES

8 CLOCK CYCLES

SIGNAL AMPL ITUDE (p -p)

Figure 3. Serial Interface Timing

VALID DATA BIT

DAT

CLK

MSB-1MSB MSB-2

t

DS

t

DH

Figure 4. SDATA Timing

3158-004

Rev. A | Page 5 of 20

AD8328

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ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage VCC 6 V
Input Voltage

V

, V

1.5 V p-p

IN+

IN−

DATEN, SDATA, CLK, SLEEP, TXEN
Internal Power Dissipation

QSOP (θJA = 83.2°C/W)

LFCSP (θJA = 30.4°C/W)
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering 60 sec 300°C

1

Thermal resistance measured on SEMI standard 4-layer board.

2

Thermal resistance measured on SEMI standard 4-layer board, paddle

soldered to board.

1

2

−0.8 V to +5.5 V

700 mW
700 mW

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 6 of 20

AD8328

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

GND

2

V

CC

3

GND

4

GND

V

V

GND

DATEN

SDATA

CLK

AD8328

5

IN+

TOP VIEW

(Not to Scale)

6

IN–

7

8

9

10

NC = NO CONNECT

Figure 5. 20-Lead QSOP Pin

Table 5. 20-Lead QSOP and 20-Lead LFCSP Pin Function Descriptions

Pin No.
20-Lead
QSOP

1, 3, 4, 7,
11, 20

Pin No.
20-Lead
LFCSP

1, 2, 5, 9,
18, 19

Mnemonic Description

GND Common External Ground Reference.

2, 19 17, 20 VCC Common Positive External Supply Voltage. A 0.1 μF capacitor must decouple each pin.
5 3 V
6 4 V
8 6

Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 μF capacitor.

IN+

Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 μF capacitor.

IN−

DATEN

9 7 SDATA

10 8 CLK

12 10

SLEEP

13 11 NC
14 12 BYP
15 13 V
16 14 V

Negative Output Signal

OUT−

Positive Output Signal

OUT+

17 15 RAMP
18 16 TXEN Logic 0 Disables Forward Transmission. Logic 1 enables forward transmission.

20

GND

V

19

CC

18

TXEN

17

RAMP

V

16

OUT+

15

V

OUT–

14

BYP

13

NC

12

SLEEP

GND

11

03158-005

Configuration

GND

GND

V

IN+

V

IN–

GND

Figure 6. 20-Lead LFCSP Pin Configuration

CC

GND

V

1

2

AD8328

3

TOP VIEW

(Not to Scale)

4

5

678910

DATEN

SDATA

CC

TXEN

GND

V

161720 19 18

15

RAMP

V

14

OUT+

V

13

OUT–

12

BYP

11

NC

CLK

GND

SLEEP

03158-006

Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register.
A Logic 0-to-Logic 1 transition transfers the latched data to the attenuator core (updates the gain)

and simultaneously inhibits serial data transfer into the register.
A Logic 1-to-Logic 0 transition inhibits the data latch (holds the previous gain state) and

simultaneously enables the register for serial data load.
Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the

internal register with the most significant bit (MSB) first.
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit

master-slave register.
A Logic 0-to-Logic 1 transition latches the data bit, and a Logic 1-to-Logic 0 transfers the data bit

to the slave. This requires the input serial data-word to be valid at or before this clock transition.
Low Power Sleep Mode. In the sleep mode, the AD8328’s supply current is reduced to 20 μA.

A Logic 0 powers down the part (high Z

state), and a Logic 1 powers up the part.

OUT

No Connect.
Internal Bypass. This pin must be externally ac-coupled (0.1 μF capacitor).

External RAMP Capacitor (Optional)

Rev. A | Page 7 of 20

AD8328

–

R

–

–

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TYPICAL PERFORMANCE CHARACTERISTICS

DISTORTION (dBc)

55

–60

–65

–70

V

= 61dBmV

OUT

@ MAX GAI N

V

= 60dBmV

OUT

@ MAX GAIN

V

= 59dBmV

OUT

@ MAX GAIN

–55

–60

DISTORTION (dBc)

–65

50

V
@ MAX GAIN

= 61dBmV

OUT

V

= 60dBmV

OUT

@ MAX GAIN

V

OUT

@ MAX GAIN

= 59dBmV

–75

515253545556

FREQUENCY (MHz)

03158-007

5

Figure 7. Second-Order Harmonic Distortion vs.

Freque

ncy for Various Output Powers

50

= 60dBmV

V

OUT

@ MAX GAIN

–55

–60

TION (dBc)

–65

DISTO

–70

–75

515253545556

TA = –40°C

FREQUENCY (MHz)

T

A

= +25°C

= +85°C

T

A

03158-008

5

Figure 8. Second-Order Harmonic Distortion vs. Frequency vs. Temperature

10

0

–10

–20

–30

–40

(dBm)

OUT

–50

P

–60

–70

–80

–90

C0

c11

c11

C0

cu1

CH PWR
ACP

SPAN 750kHz75kHz/DIV

60dBmV

–58.2dB

cu1

03158-009

Figure 9. Adjacent Channel Power

–70

515253545556

FREQUENCY (M Hz)

03158-010

5

Figure 10. Third-Order Harmonic Distortion vs.

ncy for Various Output Powers

Freque

50

= 60dBmV

V

OUT

@ MAX GAI N

–55

–60

DISTORTI ON (dBc)

–65

515253545556

T

= +85°C

A

FREQUENCY (MHz )

TA = –40°C

T

= +25°C

A

03158-011

5

Figure 11. Third-Order Harmonic Distortion vs. Frequency vs. Temperature

60

V

= 57dBmV/TO NE

OUT

50

@ MAX GAI N

40

30

20

10

(dBmV)

OUT

0

V

–10

–20

–30

–40

41.6 41.7 41.8 41.9 42.0 42.1 42.2 42.3 42.4 42. 5

FREQUENCY (MHz )

03158-012

Figure 12. Two-Tone Intermodulation Distortion

Rev. A | Page 8 of 20

AD8328

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40

30

DEC60

20

DEC54

10

DEC48

DEC42

0

DEC36

GAIN (dB)

DEC30

–10

DEC24

–20

DEC18

DEC12

–30

–40

0.1 1 10 100 1000

DEC 1 TO DEC 6

FREQUENCY (MHz )

Figure 13. AC Response

1.4

f = 10MHz

1.2

03158-013

0

TXEN = 0

–10

V

= 29dBmV

IN

–20

–30

–40

–50

–60

ISOLATION (dB)

–70

–80

–90

–100

1 10 100 1000

MAX GAIN

MIN GAIN

FREQUENCY (MHz)

Figure 16. Isolation in Transmit Disable Mode vs. Frequency

1.6

1.2

0.8

03158-016

1.0

OUTPUT STEP SIZE (dB)

0.8

0.6
0 6 12 18 24 30 36 42 48 54 60

140

f

= 10MHz

Hz)

TXEN = 1

120

100

80

60

40

20

OUTPUT REFERRED VOLTAGE NOISE (nV/

0

0 6 12 18 24 30 36 42 48 54 60

GAIN CONTROL (Decimal Code)

Figure 14. Output Step Siz

GAIN CONTRO L (Decimal Code)

e vs. Gain Control

Figure 15. Output Referred Voltage Noise vs. Gain Control

0.4

0

–0.4

GAIN ERROR (d B)

–0.8

–1.2

03158-014

–1.6

0 6 12 18 24 30 36 42 48 54 60

GAIN CONTRO L (Decimal Code)

f

= 10MHz

f

= 5MHz

f

= 42MHz

f

= 65MHz

03158-017

Figure 17. Gain Error vs. Gain Control

130

120

110

100

90

80

70

60

50

40

QUIESCENT S UPPLY CURRENT (mA)

03158-015

30

20

0 10203040506

GAIN CO NTROL (Decim al Cod e)

0

03158-018

Figure 18. Supply Current vs. Gain Control

Rev. A | Page 9 of 20

AD8328

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APPLICATIONS

GENERAL APPLICATIONS

The AD8328 is primarily intended for use as the power
amplifier (PA) in Data Over Cable Service Interface Specification
(DOCSIS)-certified cable modems and CATV set-top boxes.
The upstream signal is either a QPSK or QAM signal generated
by a DSP, a dedicated QPSK/QAM modulator, or a DAC. In all
cases, the signal must be low-pass filtered before being applied
to the PA to filter out-of-band noise and higher order
harmonics from the amplified signal.

Due to the varying distances between the cable modem and the
he

ad-end, the upstream PA must be capable of varying the
output power by applying gain or attenuation. The ability to
vary the output power of the AD8328 ensures that the signal
from the cable modem has the proper level once it arrives at the
head-end. The upstream signal path commonly includes a
diplexer and cable splitters. The AD8328 has been designed to
overcome losses associated with these passive components in
the upstream cable path.

CIRCUIT DESCRIPTION

The AD8328 is composed of three analog functions in the
power-up or forward mode. The input amplifier (preamp) can
be used single-ended or differentially. If the input is used in the
differential configuration, it is imperative that the input signals
be 180° out of phase and of equal amplitude. A vernier is used
in the input stage for controlling the fine 1 dB gain steps. This
stage then drives a DAC, which provides the bulk of the
AD8328’s attenuation. The signals in the preamp and DAC gain
blocks are differential to improve the PSRR and linearity. A
differential current is fed from the DAC into the output stage.
The output stage maintains 300 Ω differential output impedance,
which maintains proper match to 75 Ω when used with a 2:1
balun transformer.

5

SPI PROGRAMMING AND GAIN ADJUSTMENT

The AD8328 is controlled through a serial peripheral interface
(SPI) of three digital data lines: CLK,

DATEN

, and SDATA.
Changing the gain requires eight bits of data to be streamed into
the SDATA port. The sequence of loading the SDATA register
begins on the falling edge of the

DATEN

pin, which activates
the CLK line. With the CLK line activated, data on the SDATA
line is clocked into the serial shift register on the rising edge of
the CLK pulses, MSB first. The 8-bit data-word is latched into
the attenuator core on the rising edge of the

DATEN

line. This
provides control over the changes in the output signal level. The
serial interface timing for the AD8328 is shown in Figure 3 and
Figure 4. The programmable gain range of the AD8328 is

−28 dB t

o +31 dB with steps of 1 dB per least significant bit
(LSB). This provides a total gain range of 59 dB. The AD8328
was characterized with a differential signal on the input and a
TOKO 458PT-1087 2:1 transformer on the output. The AD8328
incorporates supply current scaling with gain code, as shown in
Figure 18. This allows reduced power consumption when
o

perating in lower gain codes.

INPUT BIAS, IMPEDANCE, AND TERMINATION

The V
the input signal should be ac-coupled as shown in Figure 20.
Th

1.6 kΩ, while the single-ended input is 800 Ω. The high input
impedance of the AD8328 allows flexibility in termination and
properly matching filter networks. The AD8328 exhibits
optimum performance when driven with a pure differential
signal.

and V

IN+

inputs have a dc bias level of VCC/2; therefore,

IN−

e differential input impedance of the AD8328 is approximately

OUTPUT BIAS, IMPEDANCE, AND TERMINATION

The output stage of the AD8328 requires a bias of 5 V. The 5 V
power supply should be connected to the center tap of the
output transformer. In addition, the V
tap of the transformer should be decoupled as seen in Figure 20.

applied to the center

CC

V

CC

V

IN+

AD8328

V

1

V

IN

2

1

V

IN

2

Figure 19. Characterization Circuit

IN–

BYP

GND

V

V

OUT+

OUT–

R

L

03158-019

Rev. A | Page 10 of 20

AD8328

V

Z

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CC

= 150Ω

IN

Table 6. Adjacent Channel Power

Adjacent Channel Symbol Rate (kSym/s)
Channel Symbol Rate (kSym/s) 160 320 640 1280 2560 5120

160 −58 −60 −63 −66 −66 −64
320 −58 −59 −60 −64 −66 −65
640 −60 −58 −59 −61 −64 −65
1280 −62 −60 −59 −60 −61 −63
2560 −64 −62 −60 −59 −60 −61
5120 −66 −65 −62 −61 −59 −60

The output impedance of the AD8328 is 300 , regardless
o

f whether the amplifier is in transmit enable or transmit
disable mode. This, when combined with a 2:1 voltage ratio
(4:1 impedance ratio) transformer, eliminates the need for
external back termination resistors. If the output signal is being
evaluated using standard 50  test equipment, a minimum loss
75  to 50  pad must be used to provide the test circuit with
the proper impedance match. The AD8328 evaluation board
provides a convenient means to implement a matching attenuator.
Soldering a 43.3  resistor in the R15 placeholder and an 86.6 
resistor in the R16 placeholder allows testing on a 50  system.
When using a matching attenuator, it should be noted that there
is a 5.7 dB of power loss (7.5 dB voltage) through the network.

POWER SUPPLY

The 5 V supply should be delivered to each of the VCC pins via a
low impedance power bus to ensure that each pin is at the same
potential. The power bus should be decoupled to ground using
a 10 µF tantalum capacitor located close to the AD8328. In
addition to the 10 µF capacitor, each V
decoupled to ground with ceramic chip capacitors located close
to the pins. The bypass pin, BYP, should also be decoupled. The
PCB should have a low impedance ground plane covering all
unused portions of the board, except in areas of the board
where input and output traces are in close proximity to the

V

IN+

V

IN–

DATEN

SDATA

TXEN

SLEEP

CLK

10µF

0.1µF

165Ω

0.1µF

1kΩ

1kΩ

1kΩ

1kΩ

1kΩ

pin should be individually

CC

AD8328

10

1

2

3
4

5

6
7

8

9

GND

V

CC

GND

GND

V

IN+

V

IN–

GND

DATEN

SDATA

CLK

QSOP

GND

V

TXEN

RAMP
V

OUT+

V

OUT–

BYP

NC

SLEEP

GND

20

19

CC

18

17

16

15

14

13

0.1μF

12

11

Figure 20. Typical Application Circuit

AD8328 and the output transformer. All AD8328 ground pins
must be connected to the ground plane to ensure proper
grounding of all internal nodes.

SIGNAL INTEGRITY LAYOUT CONSIDERATIONS

Careful attention to printed circuit board layout details will
prevent problems due to board parasitics. Proper RF design
techniques are mandatory. The differential input and output
traces should be kept as short as possible. Keeping the traces
short minimizes parasitic capacitance and inductance. This is
most critical between the outputs of the AD8328 and the 2:1
output transformer. It is also critical that all differential signal
paths be symmetrical in length and width. In addition, the
input and output traces should be adequately spaced to
minimize coupling (crosstalk) through the board. Following
these guidelines optimizes the overall performance of the
AD8328 in all applications.

Rev. A | Page 11 of 20

0.1μF

0.1μF

TO DIPLEXER
Z

IN

TOKO 458PT-1087

= 75Ω

03158-020

AD8328

www.BDTIC.com/ADI

INITIAL POWER-UP

When the supply voltage is first applied to the AD8328, the gain
of the amplifier is initially set to Gain Code 1. Since power is
first applied to the amplifier, the TXEN pin should be held low
(Logic 0) to prevent forward signal transmission. After power is
applied to the amplifier, the gain can be set to the desired level
by following the procedure provided in the
a

nd Gain Adjustment section. The TXEN pin can then be

b

rought from Logic 0 to Logic 1, enabling forward signal

transmission at the desired gain level.

SPI Programming

RAMP PIN AND BYP PIN FEATURES

The RAMP pin is used to control the length of the burst on and
off transients. By default, leaving the RAMP pin unconnected
results in a transient that is fully compliant with DOCSIS 2.0
Section 6.2.21.2, Spurious Emissions During Burst On/Off
Tra ns ie nt s. DOCSIS requires that all between-burst transients
must be dissipated no faster than 2 µs; and adding capacitance
to the RAMP pin adds more time to the transient.

The BYP pin is used to decouple the output stage at midsupply.
T

ypically, for normal DOCSIS operation, the BYP pin should be
decoupled to ground with a 0.1 µF capacitor. However, in
applications that require transient on/off times faster than 2 µs,
smaller capacitors can be used, but it should be noted that the
BYP pin should always be decoupled to ground.

TRANSMIT ENABLE (TXEN) AND SLEEP

The asynchronous TXEN pin is used to place the AD8328 into
between-burst mode. In this reduced current state, the output
impedance of 75 Ω is maintained. Applying Logic 0 to the
TXEN pin deactivates the on-chip amplifier, providing a 97.8%
reduction in consumed power. For 5 V operation, the supply
current is typically reduced from 120 mA to 2.6 mA. In this
mode of operation, between-burst noise is minimized and high
input to output isolation is achieved. In addition to the TXEN

SLEEP

SLEEP

pin,

pin places

pin, the AD8328 also incorporates an asynchronous
which can be used to further reduce the supply current to
approximately 20 µA. Applying Logic 0 to the
the amplifier into
SLEEP

mode can result in a transient voltage at the output of

the amplifier.

SLEEP

mode. Transitioning into or out of

DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS

To deliver the DOCSIS required 58 dBmV of QPSK signal and
55 dBmV of 16 QAM signal, the PA is required to deliver up to
60 dBmV. This added power is required to compensate for
losses associated with the diplex filter or other passive components
that may be included in the upstream path of cable modems
or set-top boxes. It should be noted that the AD8328 was
characterized with a differential input signal.
Figure 10 show the AD8328 second and third harmonic
d

istortion performance vs. the fundamental frequency for

Figure 7 and

Rev. A | Page 12 of 20

various output power levels. These figures are useful for
determining the in-band harmonic levels from 5 MHz to
65 MHz. Harmonics higher in frequency (above 42 MHz for
DOCSIS and above 65 MHz for EuroDOCSIS) are sharply
attenuated by the low-pass filter function of the diplexer.

Another measure of signal integrity is adjacent channel power,
co

mmonly referred to as ACP. DOCSIS 2.0, Section 6.2.21.1.1
states, “Spurious emissions from a transmitted carrier may
occur in an adjacent channel that could be occupied by a carrier
of the same or different symbol rates.”

easured ACP for a 60 dBmV QPSK signal taken at the output

m
of the AD8328 evaluation board. The transmit channel width
and adjacent channel width in
sym

bol rates of 160 kSym/s. Tabl e 6 shows the ACP results for

e AD8328 driving a QPSK 60 dBmV signal for all conditions

th
in DOCSIS Table 6-9, Adjacent Channel Spurious Emissions.

Figure 9 shows the

Figure 9 correspond to the

NOISE AND DOCSIS

At minimum gain, the AD8328 output noise spectral density is

1.2 nV/√Hz measured at 10 MHz. DOCSIS Table 6-10, Spurious
Emissions in 5 MHz to 42 MHz, specifies the output noise for
various symbol rates. The calculated noise power in dBmV for
160 kSym/s is

Hz

2

nV1.2

⎞

×

⎟
⎠

⎡

⎛

⎛

⎜

⎢

log20

×

⎜

⎜

⎢

⎜

⎝

⎝

⎣

Comparing the computed noise power of −66.4 dBmV to the
+8 dB

mV signal yields −74.4 dBc, which meets the required
level set forth in DOCSIS Table 6-10. As the AD8328 gain is
increased above this minimum value, the output signal
increases at a faster rate than the noise, resulting in a signal­to-noise ratio that improves with gain. In transmit disable
mode, the output noise spectral density is 1.1 nV/√Hz, which
results in −67 dBmV when computed over 160 kSym/s. The
noise power was measured directly at the output of the
AD8328AR-EVAL board.

⎤

⎞
⎟

⎥

⎟

⎟
⎠

−=+

⎥
⎦

dBmV66.460kHz160

(1)

EVALUATION BOARD FEATURES AND OPERATION

The AD8328 evaluation board and control software can be used
to control the AD8328 upstream cable driver via the parallel
port of a PC. A standard printer cable connected to the parallel
port of the PC is used to feed all the necessary data to the AD8328
using the Windows®-based control software. This package
provides a means of controlling the gain and the power mode of
the AD8328. With this evaluation kit, the AD8328 can be evaluated
in either a single-ended or differential input configuration. See
Figure 26 for a schematic of the evaluation board.

AD8328

Z

×

×

Z

www.BDTIC.com/ADI

DIFFERENTIAL SIGNAL SOURCE

Typical applications for the AD8328 use a differential input
signal from a modulator or a DAC. See Table 7 for common

alues of R4, or calculate other input configurations using

v
Equation 2. This circuit configuration will give optimal
distortion results due to the symmetric input signals. Note
that this configuration was used to characterize the AD8328.

Z

×

k1.6

R4

IN

=

k1.6

Z

IN

(2)

Z

−

IN

V

IN+

V

IN–

Figure 21. Differential Circuit

R4

AD8328

3158-021

DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE

The default configuration of the evaluation board implements
a differential signal drive from a single-ended signal source.
This configuration uses a 1:1 balun transformer to approximate
a differential signal. Because of the nonideal nature of real
transformers, the differential signal is not purely equal and
opposite in amplitude. Although this circuit slightly sacrifices
even-order harmonic distortion due to asymmetry, it does
provide a convenient way to evaluate the AD8328 with a single­ended source.

The AD8328 evaluation board is populated with a TOKO

B-A0070 1:1 for this purpose (T1). Table 7 provides

617D

ical R4 values for common input configurations. Other input

typ
impedances can be calculated using Equation 3. See

or a schematic of the evaluation board. To use the transformer

f

Figure 26

for converting a single-ended source into a differential signal,
the input signal must be applied to V

Z

×

k1.6

R4

IN

=

k1.6

V

IN+

IN

(3)

Z

−

IN

Figure 22. Single-to-Differential Circuit

.

IN+

R4

AD8328

03158-022

SINGLE-ENDED SOURCE

Although the AD8328 was designed to have optimal DOCSIS
performance when used with a differential input signal, the
AD8328 can also be used as a single-ended receiver, or an IF
digitally controlled amplifier. However, as with the single­ended-to-differential configuration previously noted, even­order harmonic distortion is slightly degraded.

requires the removal of R2 and R3 to be shorted with R4 open,
as well as the addition of 82.5  at R1 and 39.2  at R17 for
75  termination.

nd R12 for some common input configurations. Other input

a

Table 7 shows the correct values for R11

impedance configurations can be accommodated using
Equation 4 and Equation 5.

Z

800

IN

R

=

1 (4)

17

R

=

800

IN

Z

−

IN

1

RZ

IN

(5)

1

ZR

+

IN

V

IN+

R1

R17

Figure 23. Single-Ended Circuit

AD8328

03158-023

Table 7. Common Matching Resistors

Differential Input Termination

ZIN (Ω) R2/R3 R4 (Ω) R1/R17

50 Open 51.1 Open/Open
75 Open 78.7 Open/Open
100 Open 107.0 Open/Open
150 Open 165.0 Open/Open

Single-Ended Input Termination

ZIN (Ω) R2 (Ω)/R3 (Ω) R4 (Ω) R1 (Ω)/R17 (Ω)

50 0/0 Open 53.6/25.5
75 0/0 Open 82.5/39.2

OVERSHOOT ON PC PRINTER PORTS

The data lines on some PC parallel printer ports have excessive
overshoot that can cause communication problems when
presented to the CLK pin of the AD8328. The evaluation
board was designed to accommodate a series resistor and
shunt capacitor (R2 and C5 in

nal if required.

sig

Figure 26) to filter the CLK

INSTALLING VISUAL BASIC CONTROL SOFTWARE

Install the CabDrive_28 software by running the setup.exe file
on Disk One of the AD8328 evaluation software. Follow the on­screen directions and insert Disk Two when prompted. Choose
the installation directory and then select the icon in the upper
left to complete the installation.

When operating the AD8328 in a single-ended input mode,
V

IN+

and V

should be terminated as shown in Figure 23.

IN–

On the AD8328 evaluation boards, this termination method

Rev. A | Page 13 of 20

AD8328

www.BDTIC.com/ADI

RUNNING AD8328 SOFTWARE

To load the control software, go to Start, Programs,
CABDRIVE_28 or select the AD8328.exe file from the
installed directory. Once loaded, select the proper parallel
port to communicate with the AD8328 (see Figure 24).

Figure 24. Parallel Port Selection

03158-024

TRANSMIT ENABLE AND SLEEP MODE

The Transmit Enable and Transmit Disable buttons select the
mode of operation of the AD8328 by asserting logic levels on
the asynchronous TXEN pin. The Transmit Disable button
applies Logic 0 to the TXEN pin, disabling forward transmission.
The Transmit Enable button applies Logic 1 to the TXEN pin,
enabling the AD8328 for forward transmission. Checking the

SLEEP

Enable
SLEEP

Mode box applies Logic 0 to the asynchronous

pin, setting the AD8328 for

SLEEP

mode.

MEMORY FUNCTIONS

The Memory section of the software provides a way to alternate
between two gain settings. The XM1 button stores the current
value of the GAIN SLIDER into memory, while the RM1 button
recalls the stored value, returning the gain SLIDER to the stored
level. The same applies to the XM2 and RM2 buttons.

CONTROLLING GAIN/ATTENUATION OF THE AD8328

The SLIDER controls the gain/attenuation of the AD8328,
which is displayed in dB and in V/V. The gain scales 1 dB
per LSB. The gain code from the position of the SLIDER is
displayed in decimal, binary, and hexadecimal (see

Figure 25).

03158-025

Figure 25. Control Software Interface

Rev. A | Page 14 of 20

AD8328

A

www.BDTIC.com/ADI

_A

V

IN+

V

IN–

P1 2

P1 3

P1 5

P1 6

P1 7

P1 16

R1

_A

R17

R5

1kΩ

R7

1kΩ

R9

1kΩ

R11
1kΩ

R13
1kΩ

R2

T1

TOKO
617DB-A0070

R3

TP1

R6
0Ω

C3

TP2

R8
0Ω

C4

TP3

R10

0Ω

C5

TP4

R12

0Ω

C6

TP5

R14

0Ω

C7

C1

0.1µF

R4

78.7Ω

C2A

0.1μF

10

1

2

3

4

5

6

7

8

9

GND

V

CC

GND

GND

V

IN+

V

IN–

GND

DATEN

SDATA

CLK

AD8328

QSOP

GND

V

TXEN

RAMP

V

OUT+

V

OUT–

BYP

NC

SLEEP

GND

TP9

V

TOKO

1

2

3

C13

0.1µF

TP10

TP11

TP12

CC

R15

CABLE_OA

0Ω

6

4

V

CC

R16

P1 19
P1 20
P1 21
P1 22
P1 23
P1 24
P1 25
P1 26
P1 27
P1 28
P1 29
P1 30

1

P1 33

03158-026

C8

20

19

CC

18

17

16

15

14

13

12

11

C9 0.1µF

C10 0.1µF

C11

C12 0.1µF

TP_AGND1

AGND1

10µF

458PT-1087

VCC1

TP_VCC1

Figure 26. AD8328 Evaluation Board Schematic

Rev. A | Page 15 of 20

AD8328

www.BDTIC.com/ADI

Figure 27. Primary Side

03158-027

Figure 30. Internal Ground Plane

3158-030

3158-028

Figure 28. Component Side Silkscreen

Figure 29. Internal Power Plane

Figure 31. Secondary Side

03158-029

Figure 32. Secondary Side Silkscreen

03158-031

03158-032

Rev. A | Page 16 of 20

AD8328

R

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.60

MAX

0.60

MAX

0.75

0.55

0.35

COPLANARITY

0.08

16

15

11

10

PIN 1

INDICATOR

20

1

5

6

0.30

0.23

0.18

2.25

2.10 SQ

1.95

0.25 MIN

PIN 1

INDICATO

1.00

0.85

0.80

SEATING

PLANE

12° MAX

BSC SQ

0.50
BSC

4.00

TOP

VIEW

0.80 MAX

0.65 TYP

0.20

REF

3.75

BCS SQ

0.05 MAX

0.02 NOM

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1

Figure 33. 20-Lead Frame Chip Scale Package [LFCSP_VQ]

4

mm × 4 mm Body, Very Thin Quad

(CP-20-1)

Dimensions shown in millimeters

0.345

0.341

0.337

PIN 1

0.010

0.004

COPLANARITY

0.004

20 11

1

0.065

0.049

BSC

0.012

0.008

0.025

COMPLIANT TO JEDEC STANDARDS MO-137-AD

Figure 34. 20-Lead Shrink Small Outline Package [QSOP]

(R

Dimensions shown in inches

10

0.069

0.053

Q-20)

0.158

0.154

0.150

SEATING
PLANE

0.244

0.236

0.228

0.010

0.006

8°
0°

0.050

0.016

Rev. A | Page 17 of 20

AD8328

www.BDTIC.com/ADI

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8328ARQ –40°C to +85°C 20-Lead QSOP RQ-20
AD8328ARQ-REEL –40°C to +85°C 20-Lead QSOP RQ-20
AD8328ARQZ
AD8328ARQZ-REEL
AD8328ACP –40°C to +85°C 20-Lead LFCSP_VQ CP-20-1
AD8328ACP-REEL –40°C to +85°C 20-Lead LFCSP_VQ CP-20-1
AD8328ACP-REEL7 –40°C to +85°C 20-Lead LFCSP_VQ CP-20-1
AD8328ACPZ
AD8328ACPZ-REEL
AD8328ACPZ-REEL7
AD8328ACP-EVAL Evaluation Board
AD8328ARQ-EVAL Evaluation Board

1

Z = Pb-free part.

1

1

1

1

1

–40°C to +85°C 20-Lead QSOP RQ-20
–40°C to +85°C 20-Lead QSOP RQ-20

–40°C to +85°C 20-Lead LFCSP_VQ CP-20-1
–40°C to +85°C 20-Lead LFCSP_VQ CP-20-1
–40°C to +85°C 20-Lead LFCSP_VQ CP-20-1

Rev. A | Page 18 of 20

AD8328

www.BDTIC.com/ADI

NOTES

Rev. A | Page 19 of 20

AD8328

www.BDTIC.com/ADI

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03158–0–10/05(A)

Rev. A | Page 20 of 20