Datasheet AD8326ARP-REEL, AD8326ARP-EVAL, AD8326ARP, AD8326ARE-REEL, AD8326ARE-EVAL Datasheet (Analog Devices)

High Output Power

–40

–45

–50

–55

–60

–65

–70

–75

–80

5 15 25 35 45 55 65

DISTORTION – dBc

FREQUENCY – MHz

ARP(VS = +12V)
ARE(VS = ⴞ5V)

ARP(VO = 69dBmV)

ARP(VO = 67dBmV)

ARE(VO = 65dBmV)

ARE(VO = 62dBmV)

a

FEATURES
Supports DOCSIS Standard for Reverse Path

Transmission
Gain Programmable in 0.75 dB Steps over a 53.5 dB Range
Low Distortion at 65 dBmV Output

–62 dBc SFDR at 21 MHz

–58 dBc SFDR at 65 MHz
1 dB Compression of 25 dBm at 10 MHz
Output Noise Level

–45 dBmV in 160 kHz
Maintains 75 ⍀ Output Impedance

Power-Up and Power-Down Condition
Upper Bandwidth: 100 MHz (Full Gain Range)
Single or Dual Supply Operation

APPLICATIONS
Gain-Programmable Line Driver

CATV Telephony Modems

CATV Terminal Devices
General-Purpose Digitally Controlled Variable Gain Block

Programmable CATV Line Driver

AD8326

FUNCTIONAL BLOCK DIAGRAM

V

IN+

V

IN–

ZIN (SINGLE) = 800⍀
Z

(DIFF) = 1.6k⍀

IN

DIFF OR
SINGLE
INPUT
AMP

GND

VCC (7 PINS)

VERNIER

DATEN

AD8326

DATA CLK V

ATTENUATION

CORE

DECODE

DATA LATCH

SHIFT

REGISTER

(10 PINS)

EE

8

8

8

BYP

POWER

AMP

Z

OUT

POWER-DOWN

LOGIC

TXEN

SLEEP

DIFF =

75⍀

V

V

OUT+

OUT–

GENERAL DESCRIPTION

The AD8326 is a high-output power, digitally controlled, vari­able gain amplifier optimized for coaxial line driving applications
such as data and telephony cable modems that are designed to
the MCNS-DOCSIS upstream standard. An 8-bit serial word
determines the desired output gain over a 53.5 dB range result­ing in gain changes of 0.75 dB/LSB. The AD8326 is offered in
two models, each optimized to support the desired output power
and resulting performance.

The AD8326 comprises a digitally controlled variable attenuator
of 0 dB to –54 dB, that is preceded by a low noise, fixed-gain
buffer and is followed by a low distortion high-power amplifier.
The AD8326 accepts a differential or single-ended input signal.

The output is designed to drive a 75 Ω load, such as coaxial

cable, although the AD8326 is capable of driving other loads.

When driving 67 dBm into a 75 Ω load, the AD8326ARP

provides a worst harmonic of only –59 dBc at 21 MHz and

–57 dBc at 42 MHz. When driving 65 dBmV into a 75 Ω load,

the AD8326ARE provides a worst harmonic of only –62 dBc at
21 MHz and –60 dBc at 42 MHz.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

Figure 1. Worst Harmonic Distortion vs. Frequency

The differential output of the AD8326 is compliant with DOCSIS
paragraph 4.2.10.2 for “Spurious Emissions During Burst On/Off
Transients.” In addition, this device has a sleep mode function
that reduces the quiescent current to 4 mA.

The AD8326 is packaged in a low-cost 28-lead TSSOP and a
28-lead P (power) SOIC. Both devices have an operational tem-

perature range of –40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD8326–SPECIFICA TIONS

(TA = 25ⴗC, VS = 12 V, RL = RIN = 75 ⍀, VIN = 259 mV p-p, V
transformer with an insertion loss of 0.5 dB @ 10 MHz, unless otherwise noted.)

measured through a 1:1

OUT

AD8326ARP

Parameter Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Specified AC Voltage Output = 67 dBmV, Max Gain 259 mV p-p
Noise Figure Max Gain, f = 10 MHz 16.6 dB

Input Resistance Differential Input 1600 Ω

Single-Ended Input 800 Ω

Input Capacitance 2pF

GAIN CONTROL INTERFACE

Gain Range 52.5 53.5 54.5 dB
Maximum Gain Gain Code = 71 Dec 26.5 27.5 28.5 dB
Minimum Gain Gain Code = 0 Dec –27 –26 –25 dB
Gain Scaling Factor 0.7526 dB/LSB

Gain Linearity Error f = 10 MHz, Code-to-Code ±0.2 dB

OUTPUT CHARACTERISTICS

Bandwidth (–3 dB) All Gain Codes 100 MHz
Bandwidth Roll-Off f = 65 MHz 1.2 dB
Bandwidth Peaking f = 65 MHz 0 dB
Output Noise Spectral Density Max Gain, f = 10 MHz –28 dBmV in

160 kHz

Min Gain, f = 10 MHz –45.5 dBmV in

160 kHz

Transmit Disable Mode, f = 10 MHz –65 dBmV in

160 kHz

1 dB Compression Point Max Gain, f = 10 MHz 26.5 dBm

Differential Output Impedance Transmit Enable and Transmit Disable Mode 75 ± 20% Ω

OVERALL PERFORMANCE

Worst Harmonic Distortion f = 14 MHz, V

f = 21 MHz, V
f = 42 MHz, V
f = 65 MHz, V

Adjacent Channel Power 16 QAM, V

= 67 dBmV @ Max Gain –59 dBc

OUT

= 67 dBmV @ Max Gain –59 dBc

OUT

= 67 dBmV @ Max Gain –57 dBc

OUT

= 67 dBmV @ Max Gain –55 dBc

OUT

= 67 dBmV –56 dBc

OUT

Adj Ch Wid = Tr Ch Wid = 160 KSYM/SEC

Output Settling

Due to Gain Change (T
Due to Input Step Change Max Gain, V

Signal Isolation Min Gain, TXEN = 0, 65 MHz, V

) Min to Max Gain 60 ns

GS

Max Gain, TXEN = 0, 42 MHz, V
Max Gain, TXEN = 0, 65 MHz, V

= 0 V to 0.25 V p-p 30 ns

IN

= 0.25 V p-p –85 dBc

IN

= 0.25 V p-p –31 dBc

IN

= 0.25 V p-p –28 dBc

IN

All Gains, SLEEP, 65 MHz, VIN = 0.25 V p-p –85 dBc

POWER CONTROL

Transmit Enable Response Time (t
Transmit Disable Response Time (t
Between Burst Transients

1

) Max Gain, VIN = 0 250 ns

ON

) Max Gain, VIN = 0 40 ns

OFF

Equivalent Output = 31 dBmV 5 mV p-p
Equivalent Output = 61 dBmV 60 mV p-p

POWER SUPPLY

Operating Range 11.4 12 12.6 V
Quiescent Current Transmit Enable Mode (TXEN = 1) 147 157 167 mA

Transmit Disable Mode (TXEN = 0) 38 44 50 mA
Sleep Mode 1.5 4.5 7.5 mA

OPERATING TEMPERATURE –40 +85 °C

RANGE

NOTES

1

Between Burst Transients measured at the output of diplexer.

Specifications subject to change without notice.

–2–

REV. 0

AD8326

SPECIFICA TIONS

(TA = 25ⴗC, VS = ⴞ5 V, RL = RIN = 75 ⍀, VIN = 206 V p-p, V
transformer with an insertion loss of 0.5 dB @ 10 MHz, unless otherwise noted.)

measured through a 1:1

OUT

AD8326ARE

Parameter Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Specified AC Voltage Output = 65 dBmV, Max Gain 206 mV p-p
Noise Figure Max Gain, f = 10 MHz 16.6 dB

Input Resistance Differential Input 1600 Ω

Single-Ended Input 800 Ω

Input Capacitance 2pF

GAIN CONTROL INTERFACE

Gain Range 52.5 53.5 54.5 dB
Maximum Gain Gain Code = 71 Dec 26.5 27.5 28.5 dB
Minimum Gain Gain Code = 0 Dec –27 –26 –25 dB
Gain Scaling Factor 0.7526 dB/LSB

Gain Linearity Error f = 10 MHz, Code-to-Code ±0.2 dB

OUTPUT CHARACTERISTICS

Bandwidth (–3 dB) All Gain Codes 100 MHz
Bandwidth Roll-Off f = 65 MHz 1.1 dB
Bandwidth Peaking f = 65 MHz 0 dB
Output Noise Spectral Density Max Gain, f = 10 MHz –28 dBmV in

160 kHz

Min Gain, f = 10 MHz –45.5 dBmV in

160 kHz

Transmit Disable Mode, f = 10 MHz –65 dBmV in

160 kHz

1 dB Compression Point Max Gain, f = 10 MHz 25.0 dBm

Differential Output Impedance Transmit Enable and Transmit Disable Mode 75 ± 20% Ω

OVERALL PERFORMANCE

Worst Harmonic Distortion f = 14 MHz, V

f = 21 MHz, V
f = 42 MHz, V
f = 65 MHz, V

Adjacent Channel Power 16 QAM, V

= 65 dBmV @ Max Gain –62 dBc

OUT

= 65 dBmV @ Max Gain –62 dBc

OUT

= 65 dBmV @ Max Gain –60 dBc

OUT

= 65 dBmV @ Max Gain –58 dBc

OUT

= 65 dBmV –58 dBc

OUT

Adj Ch Wid = Tr Ch Wid = 160 KSYM/SEC

Output Settling

Due to Gain Change (T
Due to Input Step Change Max Gain, V

Signal Isolation Min Gain, TXEN = 0, 65 MHz, V

) Min to Max Gain 60 ns

GS

Max Gain, TXEN = 0, 42 MHz, V
Max Gain, TXEN = 0, 65 MHz, V

= 0 V to 0.19 V p-p 30 ns

IN

= 0.19 V p-p –85 dBc

IN

= 0.19 V p-p –31 dBc

IN

= 0.19 V p-p –28 dBc

IN

All Gains, SLEEP, 65 MHz, VIN = 0.19 V p-p –85 dBc

POWER CONTROL

Transmit Enable Response Time (tON) Max Gain, VIN = 0 250 ns
Transmit Disable Response Time (t
Between Burst Transients

1

) Max Gain, VIN = 0 40 ns

OFF

Equivalent Output = 31 dBmV 5 mV p-p
Equivalent Output = 61 dBmV 60 mV p-p

POWER SUPPLY

Operating Range ±4.75 ±5.0 ±5.25 V

Quiescent Current Transmit Enable Mode (TXEN = 1) 140 150 160 mA

Transmit Disable Mode (TXEN = 0) 36 42 48 mA
Sleep Mode 1 4 7 mA

OPERATING TEMPERATURE –40 +85 °C

RANGE

NOTES

1

Between Burst Transients measured at the output of diplexer.

Specifications subject to change without notice.

REV. 0

–3–

AD8326

LOGIC INPUTS (TTL/CMOS Compatible Logic)

(DATEN, CLK, SDATA, TXEN, SLEEP, V

= 12 V: Full Temperature Range)

CC

Parameter Min Typ Max Unit

Logic “1” Voltage 2.1 5.0 V
Logic “0” Voltage 0 0.8 V
Logic “1” Current (V
Logic “0” Current (V
Logic “1” Current (V
Logic “0” Current (V
Logic “1” Current (V
Logic “0” Current (V

Specifications subject to change without notice.

TIMING REQUIREMENTS

= 5 V) CLK, SDATA, DATEN 020nA

INH

= 0 V) CLK, SDATA, DATEN –600 –100 nA

INL

= 5 V) TXEN 50 190 µA

INH

= 0 V) TXEN –250 –30 µA

INL

= 5 V) SLEEP 50 190 µA

INH

= 0 V) SLEEP –250 –30 µA

INL

(Full Temperature Range, VCC = 12 V, tR = tF = 4 ns, f

= 8 MHz unless otherwise noted.)

CLK

Parameter Min Typ Max Unit

Clock Pulsewidth (t
Clock Period (t
Setup Time SDATA vs. Clock (t
Setup Time DATEN vs. Clock (t
Hold Time SDATA vs. Clock (t
Hold Time DATEN vs. Clock (t

) 16.0 ns

WH

) 32.0 ns

C

) 5.0 ns

DS

) 15.0 ns

ES

) 5.0 ns

DH

) 3.0 ns

EH

Input Rise and Fall Times, SDATA, DATEN, Clock (tR, tF)10ns

Specifications subject to change without notice.

t

DS

SDATA

CLK

VALID DATA WORD G1

MSB. . . .LSB

t

C

t

WH

VALID DATA WORD G2

DATEN

TXEN

ANALOG

OUTPUT

t

ES

8 CLOCK CYCLES

SIGNAL AMPLITUDE (p-p)

Figure 2. Serial Interface Timing

SDATA

MSB

CLK

t

EH

GAIN TRANSFER (G1)

t

GS

VALID DATA BIT

MSB-1 MSB-2

t

DS

GAIN TRANSFER (G2)

t

OFF

t

ON

t

DH

Figure 3. SDATA Timing

–4–

REV. 0

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage V

CC

Pins 5, 9, 10, 19, 20, 23, 27 . For ARP, Max VCC = VEE + 13 V;

. . . . . . . . . . . . . . . . . . . . . . . For ARE, Max V

= VEE + 11 V

CC

Input Voltages

Pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V

Pins 1, 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V

Internal Power Dissipation

TSSOP EPAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 W

PSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.0 W

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

AD8326

Model Temperature Range Package Description ␪

JA

Package Option

AD8326ARP –40°C to +85°C 28-Lead Power SOIC with Slug 23°C/W* RP-28

AD8326ARP-REEL
AD8326ARP-EVAL Evaluation Board

AD8326ARE –40°C to +85°C 28-Lead TSSOP with Exposed Pad 39°C/W* RE-28

AD8326ARE-REEL
AD8326ARE-EVAL Evaluation Board

*Thermal Resistance measured on SEMI standard 4-layer board.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8326 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–5–

AD8326

PIN CONFIGURATION

1

DATEN

2

SDATA V

3

CLK V

4

GND V

5

V

CC

6

TXEN

SLEEP

OUT– OUT+

AD8326

7

TOP VIEW

(Not to Scale)

8

NC BYP

9

V

CC

10

V

CC

11

V

EE

12

NC NC

13

V

EE

14

NC = NO CONNECT

GND

28
27

CC

26

IN–

25

IN+

V

24

EE

V

23

CC

V

22

EE

21

V

20

CC

V

19

CC

V

18

EE

17

V

16

EE

15

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 DATEN Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic

0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta­neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch
(holds the previous gain state) and simultaneously enables the register for serial data load.

2 SDATA Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the

internal register with the MSB (Most Significant Bit) first and ignored.

3 CLK Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-

slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to

the slave. This requires the input serial data word to be valid at or before this clock transition.
4, 28 GND Common External Ground Reference
5, 9, 10, 19, V

CC

Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin.

20, 23, 27
6 TXEN Transmit Enable pin. Logic 1 powers up the part.
7 SLEEP Low Power Sleep Mode. In the Sleep mode, the AD8326’s supply current is reduced to 4 mA. A

Logic 0 powers down the part (High Z

State) and a Logic 1 powers up the part.

OUT

8, 12, 17 NC No Connection to these pins.
11, 13, 16, 18, V

EE

Common Negative External Supply Voltage. A 0.1 µF capacitor must decouple each pin.

22, 24
14 OUT– Negative Output Signal
15 OUT+ Positive Output Signal

21 BYP Internal Bypass. This pin must be externally ac-coupled (0.1 µF capacitor).

25 V

IN+

Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a

0.1 µF capacitor.

26 V

IN–

Inverting Input. DC-biased to approximately V

CC

/2. Should be ac-coupled with a 0.1 µF capacitor.

–6–

REV. 0

+1/2 V

–26

–30

–34

–38

–42

–46

–50

GAIN CONTROL – Decimal

OUTPUT NOISE – dBmV in 160 kHz

0 8 16 24 32 40 48 56 64 72

f = 10MHz
TXEN = 1
V

S

= 12V

–1/2 V

Typical Performance Characteristics–

V

CC

10␮F

0.1␮F

75⍀

IN

75⍀

IN

0.1␮F

165⍀

0.1␮F

0.1␮F

V

V

BYP

IN+

IN–

V

CC

AD8326

V

EE

V

EE

OUT+

OUT–

10␮F

0.1␮F

0.1␮F

0.1␮F

1:1

TOKO

617DB-A0070

C

L

75⍀

+

V

–

AD8326

O

TPC 1. Test Circuit

1.0
VS = 12V

= 67dBmV@ MAX GAIN

P

O

0.5

0

–0.5

GAIN ERROR – dB

–1.0

–1.5

0 9 18 27 36 45 54 63 72

GAIN CONTROL – Decimal

10MHz

5MHz

42MHz

65MHz

TPC 2. Gain Error vs. Gain Control

40

VS = 12V

= 67dBmV @ MAX GAIN

V

O

30

20

10

0

GAIN – dB

–10

–20

–30

–40

0.1 1 10 100 1000
FREQUENCY – MHz

71D

46D

23D

00D

TPC 3. AC Response

32.0

VS = 12V

GAIN – dB

30.5

29.0

27.5

26.0

24.5

23.0

21.5

= 67dBmV @ MAX GAIN

P

OUT

1

10

FREQUENCY – MHz

CL = 0pF

CL = 10pF

CL = 20pF

CL = 50pF

100

TPC 4. AC Response for Various Capacitor Loads

TPC 5. Output Referred Noise vs. Gain Control

REV. 0

–7–

AD8326

–50

VS = 12V

–55

f

= 42MHz

P

= 67dBmV @ MAX GAIN

O

–60

–65

–70

–75

DISTORTION – dBc

–80

–85

–90

0 9 18 27 36 45 54 63 72

GAIN CODE – Decimal

HD3

HD2

TPC 6. Harmonic Distortion vs. Gain Code for
AD8326-ARP

–50

VS = 12V(ARP)

–55

–60

VO = 68dBmV @ MAX GAIN

–65

–70

–75

DISTORTION – dBc

–80

–85

–90

5 15 25 35 45 55 65

VO = 65dBmV @ MAX GAIN

FREQUENCY – MHz

VO = 69dBmV @ MAX GAIN

VO = 67dBmV @ MAX GAIN

0

RBW 500Hz RF ATT 30dB

–10

VBW 5kHz
SWT 20s UNIT dBm

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 21MHz 100kHz/ SPAN 1MHz

CH PWR +12.27dBm
ACP UP –56.72dB
ACP LOW –56.71dB

TPC 9. Adjacent Channel Power for AD8326-ARP

190

180

170

160

150

IMPEDANCE – ⍀

140

130

120

110

1 10 100 1000

POWER-DOWNPOWER-UP

FREQUENCY – MHz

SLEEP

TPC 7. Second Order Harmonic Distortion vs. Frequency
for Various Output Powers

–35

VS = +12V(ARP)

–40

–45

VO = 68dBmV @ MAX GAIN

–50

–55

–60

DISTORTION – dBc

–65

VO = 65dBmV @ MAX GAIN

–70

–75

5 15 25 35 45 55 65

FREQUENCY – MHz

VO = 69dBmV @ MAX GAIN

VO = 67dBmV @ MAX GAIN

TPC 8. Third Order Harmonic Distortion vs. Frequency
for Various Output Powers

TPC 10. Input Impedance vs. Frequency (Inputs

Ω

Shunted with 165

1000

100

10

IMPEDANCE – ⍀

1

0.1 1 10 100 1000

)

SLEEP

POWER-DOWN

POWER-UP

FREQUENCY – MHz

TPC 11. Output Impedance vs. Frequency

–8–

REV. 0

AD8326

–50

VS = ⴞ5V

–55

f

= 42MHz

P

= 65dBmV @ MAX GAIN

O

–60

–65

–70

–75

DISTORTION – dBc

–80

–85

–90

0 9 18 27 36 45 54 63 72

DEC CODE

HD3

HD2

TPC 12. Harmonic Distortion vs. Gain Control for
AD8326-ARE

–50

VS = ⴞ5V(ARE)

–55

–60

–65

VO = 66dBmV @ MAX GAIN

–70

VO = 65dBmV @ MAX GAIN

0

RBW 500Hz RF ATT 30dB

–10

VBW 5kHz
SWT 20s UNIT dBm

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 21MHz 100kHz/ SPAN 1MHz

CH PWR +10.41dBm
ACP UP –58.83dB
ACP LOW –59.06dB

TPC 15. Adjacent Channel Power for AD8326-ARE

0

VS = 12V

–20

TXEN = 1

–40

–60

–75

DISTORTION – dBc

–80

VO = 62dBmV @ MAX GAIN

–85

–90

5 15 25 35 45 55 65

FREQUENCY – MHz

VO = 64dBmV @ MAX GAIN

TPC 13. Second Order Harmonic Distortion vs. Frequency
for Various Output Powers

–40

VS = ⴞ5V(ARE)

–45

–50

VO = 65dBmV @ MAX GAIN

–55

–60

–65

DISTORTION – dBc

–70

–75

–80

VO = 62dBmV @ MAX GAIN

5 15 25 35 45 55 65

FREQUENCY – MHz

VO = 66dBmV @ MAX GAIN

VO = 64dBmV @ MAX GAIN

TPC 14. Third Order Harmonic Distortion vs. Frequency
for Various Output Powers

ISOLATION – dBc

–80

TXEN = 0

–100

–120

0 10 100 1000

FREQUENCY – MHz

SLEEP

TPC 16. Signal Isolation vs. Frequency

200

VS = 12V(ARP)

180

160

140

120

100

80

SUPPLY CURRENT – mA

60

40

20

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90

TRANSMIT ENABLE

TRANSMIT DISABLE

TEMPERATURE – ⴗC

TPC 17. Quiescent Current vs. Temperature

REV. 0

–9–

AD8326

APPLICATIONS
General Applications

The AD8326 is primarily intended for use as the upstream
power amplifier (PA), also known as a line driver, in DOCSIS
(Data Over Cable Service Interface Specification) certified
cable modems, cable telephony systems, and CATV set-top
boxes. The upstream signal is either a QPSK or QAM signal
generated by a DSP, a dedicated QPSK/QAM modulator, or a
DAC. In all cases the signal must be low-pass filtered before
being applied to the PA in order to filter out-of-band noise and
higher order harmonics from the amplified signal. Due to the
varying distances between the cable modem and the headend,
the upstream PA must be capable of varying the output power
by applying gain or attenuation. The varying output power of
the AD8326 ensures that the signal from the cable modem will
have the proper level once it arrives at the headend.

The upstream
signal path also contains a transformer, a diplexer, and cable split­ters. The AD8326 has been designed to overcome losses associated
with these passive components in the upstream cable path, particu­larly in modems that support cable telephony.

AD8326ARP Applications

The AD8326ARP is in a thermally enhanced PSOP2 package,
and designed for single 12 V supply and output power applica­tions up to +69 dBmV. The AD8326ARP will

provide maximum

performance in 12 V systems.

AD8326ARE Applications

The AD8326ARE is in a TSSOP package with an exposed ther-

mal pad. It is designed for dual ±5 V or single 10 V supplies. For

applications requiring up to 65 dBmV of output power, lower
cost, smaller package, and lower power dissipation, the TSSOP
package is most appropriate.

Operational Description

The AD8326 consists of four analog functions in the transmit
enable or forward mode. The input amplifier (preamp) can be
used single-ended or differentially. If the input is used in the
differential configuration, it is imperative that the input signals be
180 degrees out of phase and of equal amplitudes. This will
ensure proper gain accuracy and harmonic performance. The
preamp stage drives a vernier stage that provides the fine tune
gain adjustment. The approximate step resolution of 0.75 dB is
implemented in this stage and provides a total of approximately

5.25 dB of accumulated attenuation. After the vernier stage, a
DAC provides the bulk of the AD8326’s attenuation (8 bits or
48 dB). The signals in the preamp and vernier gain blocks are
differential to improve the PSRR and linearity. A differential
current is fed from the DAC into the output stage, which
amplifies these currents to the appropriate levels necessary to

drive a 75 Ω load.

The output stage utilizes negative feedback to implement a

differential 75 Ω output impedance, which eliminates the need

for external matching resistors needed in typical video (or
video filter) termination requirements.

SPI Programming

The AD8326 is controlled through a serial peripheral interface
(SPI) of three digital data lines, CLK, DATEN, and SDATA.
Changing the gain requires 8 bits of data to be streamed into the
SDATA port. The sequence of loading the SDATA register
begins on the falling edge of the DATEN pin, which activates
the CLK line. With the CLK line activated, data on the SDATA
line is clocked into the serial shift register, Most Significant Bit
(MSB) first, on the rising edge of the CLK pulses. Since a 7-bit
shift register is used in the AD8326, the MSB of the 8-bit word
is a “don’t care” bit and is shifted out of the register on the eighth
clock pulse. The data is latched into the attenuator core on the
rising edge of the DATEN line. This provides control over the
changes in the output signal level. The serial interface timing for
the AD8326 is shown in Figures 2 and 3. The programmable
gain range of the AD8326 is –25.75 dB to +27.5 dB with steps
of 0.75 dB. This provides a total gain range of 53.25 dB. The
AD8326 was characterized with a TOKO transformer (TOKO
#617DB-A0070), and the stated gain values include the losses
due to the transformer.

For gain codes from 0 through 71 the gain transfer function is:

A dB dB CODE

=×

27 5 0 75 71. – (. ( – )

[]

V

where AV is the gain in dB and CODE is the decimal equivalent

of the 8-bit word. Gain codes 0 to 71 provide linear changes in
gain. Figure 4 shows the gain characteristics of the AD8326 for
all possible values in an 8-bit word. Note that maximum gain is
achieved at Code 71. From Code 72 through 127 the 5.25 dB
of attenuation from the vernier stage is being applied over every
eight codes, resulting in the saw tooth characteristic at the top
of the gain range. Because the eighth bit is shifted out of the
register, the gain characteristics for Codes 128 through 255 are
identical to Codes 0 through 127, as depicted in Figure 4.

28
21
14

7
0

–7

GAIN – dB

–14
–21
–28

0 32 64 96 128 160 192 224 256

GAIN CODE – Decimal

Figure 4. Gain Code vs. Gain

–10–

REV. 0

AD8326

V

EE

V

CC

DATEN

SDATA

CLK

TXEN

SLEEP

10␮F

10␮F

0.1␮F

0.1␮F

0.1␮F

0.1␮F

0.1␮F

10
11
12
13
14

1
2
3
4
5
6
7
8
9

DATEN

SDATA
CLK
GND1
V

CC

TXEN

SLEEP

GND
V

CC

V

CC

V

EE

GND
V

EE

V

OUT–

AD8326

28

GND

27

V

CC

26

V

IN–

25

V

IN+

24

V

EE

23

V

CC

22

V

EE

21

BYP

20

V

CC

19

V

CC

18

V

EE

17

GND

16

V

EE

15

V

OUT+

TOKO 617DB-A0070

TO DIPLEXER
Z

= 75⍀

IN

Figure 5. Typical Applications Circuit

0.1␮F

0.1␮F

0.1␮F

0.1␮F

0.1␮F

0.1␮F

0.1␮F

0.1␮F

0.1␮F

0.1␮F

0.1␮F

165⍀

V

IN–

ZIN = 150⍀

V

IN+

Input Bias, Impedance, and Termination

The VIN+ and VIN– inputs have a dc bias level of approxi­mately 1.47 V below V

/2, therefore the input signal should

CC

be ac-coupled using 0.1 µF capacitors as seen in the typical

application circuit (see Figure 5).

The differential input impedance of the AD8326 is approxi-

mately 1600 Ω, while the single-ended input is 800 Ω.

Single-Ended Inverting Input

When operating the AD8326 in a single-ended input mode VIN+
and V

– should be terminated as illustrated in Figure 6. On the

IN

AD8326 evaluation boards, this termination method requires the

removal of R12, R13, R14, R16, R17, and R18. Install a 0 Ω
jumper at R15, an 82.5 Ω resistor at R10 for a 75 Ω system, and a

39.2 Ω resistor at R11 to balance the inputs of the AD8326

evaluation board (Figure 11). Other input impedance configura­tions may be calculated using the equations in Figure 6.

ZIN = R10||800

||R10

R11 = Z

IN

–

V

IN

R10

R11

–

AD8326

+

Figure 6. Single-Ended Input Impedance

The inverting and noninverting inputs of the AD8326 must be
balanced for all input configurations.

Differential Input from Single-Ended Source

The default configuration of the evaluation board implements a
differential signal drive from a single-ended signal source. A

Toko 1:1 transformer is included on the board for this purpose
(T3). Enabling the evaluation board for single to differential

input conversion requires R15–R17 to be removed, and 0 Ω

jumpers must be installed on the placeholders for R13, R14, and

R18. For a 75 Ω input impedance, R12 should be 78.7 Ω. Refer

to Figure 11 for evaluation board schematic. In this configuration,
the input signal must be applied to V

–. Other input imped-

IN

ances may be calculated using the equation in Figure 7.

DESIRED IMPEDANCE = R12||1600

VIN–

R12

AD8326

Figure 7. Differential Signal from Single-Ended Source

Differential Signal Source

The AD8326 evaluation board is also capable of accepting a

differential input signal. This requires the installation of a 165 Ω

resistor in R12, the removal of R13–R14, R17–R18, and the

installation of 0 Ω jumpers for R15–R16. This configuration
results in a differential input impedance of 150 Ω. Other differ-

ential input impedance configurations may be calculated with
the equation in Figure 8.

DESIRED IMPEDANCE = R12||1600

VIN+

R12

VIN–

AD8326

Figure 8. Differential Input

REV. 0

–11–

AD8326

Output Bias, Impedance, and Termination

The outputs have a dc bias level of approximately VCC/2, there­fore they should be ac-coupled before being applied to the load.

The differential output impedance of the AD8326 is internally

maintained at 75 Ω, regardless of whether the amplifier is in

transmit enable mode or transmit disable mode, eliminating the
need for external back termination resistors. A 1:1 transformer
is used to couple the amplifier’s differential output to the coaxial
cable while maintaining a proper impedance match. If the out-

put signal is being evaluated on standard 50 Ω test equipment, a
minimum loss 75 Ω–50 Ω pad must be used to provide the test

circuit with proper impedance match.

Single Supply Operation

The 12 V supply should be delivered to each of the VCC pins via
a low impedance power bus to ensure that each pin is at the
same potential. The power bus should be decoupled to ground using

a 10 µF tantalum capacitor located close to the AD8326ARP.
In addition to the 10 µF capacitor, each V

pin should be

CC

individually decoupled to ground with 0.1 µF ceramic chip

capacitors located close to the pins. The pin labeled BYP (Pin

21) should also be decoupled with a 0.1 µF capacitor. The PCB

should have a low-impedance ground plane covering all unused
portions of the board, except in the area of the input and output
traces in close proximity to the AD8326 and output transformer. All
ground and V

pins of the AD8326ARP must be connected to

EE

the ground plane to ensure proper grounding of all internal nodes.
Pin 28 and the exposed pad should be connected to ground.

Dual Supply Operation

The +5 V supply power should be delivered to each of the V

CC

pins via a low impedance power bus to ensure that each pin is at
the same potential. The –5 V supply should also be delivered to
each of the V

pins with a low impedance bus. The power buses

EE

should be decoupled to ground with a 10 µF tantalum capacitor
located close to the AD8326ARE. In addition to the 10 µF capaci-

tor, all V

, VEE and BYP pins should be individually decoupled to

CC

ground with 0.1 µF ceramic chip capacitors located close to the

pins. The PCB should have a low-impedance ground plane
covering all unused portions of the board, except in the area of
the input and output traces in close proximity to the AD8326
and output transformer. All ground pins of the AD8326ARE must
be connected to the ground plane to ensure proper grounding of
all internal nodes. Pin 28 and the exposed thermal pad should
both be tied to ground.

Signal Integrity Layout Considerations

Careful attention to printed circuit board layout details will
prevent problems due to board parasitics. Proper RF design
technique is mandatory. The differential input and output traces
should be kept as short as possible. It is also critical to make
sure that all differential signal paths are symmetrical in length
and width. In addition, the input and output traces should be
kept far apart in order to minimize coupling (crosstalk) through
the board. Following these guidelines will improve the overall
performance of the AD8326 in all applications.

Thermal Layout Considerations

As integrated circuits become denser, smaller, and more power­ful, they often produce more heat. Therefore when designing PC
boards, the layout must be able to draw heat away from the higher
power devices. The AD8326ARE draws up to 1.5 W when running

at +65 dBmV with ±5 V supplies. The AD8326ARP draws a

maximum of 2 W at +67 dBmV with a +12 V supply.

The following guidelines should be used for both the AD8326ARE
and AD8326ARP.

First and foremost, the exposed thermal pad should be soldered
directly to a substantial ground plane that adequately absorbs
heat away from the AD8326 package. This is the simplest, and
most important step in thermally managing the power dissipated in
the AD8326. Increasing the area of copper beneath the AD8326
will lower the thermal resistance in the PCB and more effectively
allow air to remove the heat from the PCB, and consequently,
from the AD8326.

Secondly, thermal stitching is a method for increasing thermal
capacity of the PCB. Additionally, thermal stitching can be used
to provide a thermally efficient area onto which the AD8326
may be soldered. Thermal stitching is accomplished by using a
number of plated through holes (or vias) densely populated in
the solder pad area (but not confined to the size of the TSSOP
or PSOP2 exposed thermal pad). This technique maximizes the
copper area where the package is attached to the PCB increas­ing the thermal mass or capacity by utilizing more than one
copper plane. This method of thermal management should be
applied in close proximity to the exposed thermal pad.

Another important guideline is to utilize a multilayer PCB with
the AD8326. Lowering the PCB thermal resistance using several
layers will generally increase thermal mass resulting in cooler
junction temperatures.

Using the techniques described above and dedicating 2.9 square
inches of thermally enhanced PCB area, the AD8326 in either
package can operate at safe junction temperatures.

Figures 12-17

show the above practices in use on the AD8326ARE-EVAL board.

Initial Power-Up

When the supply is first applied to the AD8326, the gain setting
of the amplifier is indeterminate. Therefore, as power is first
applied to the amplifier, the TXEN pin should be held low
(Logic 0), preventing forward signal transmission. After power
has been applied to the amplifier, the gain can be set to the desired
level by following the procedure in the SPI Programming and
Gain Adjustment section. The TXEN pin can then be brought
from Logic 0 to Logic 1, enabling forward signal transmission at
the desired gain level.

Asynchronous Power-Down

The asynchronous TXEN pin is used to place the AD8326 into
“Between Burst” mode while maintaining a differential output

impedance of 75 Ω. Applying Logic 0 to the TXEN pin acti-

vates the on-chip reverse amplifier, providing a 72% reduction
in consumed power. For 12 V operation, the supply current is
typically reduced from 159 mA to 44 mA. In this mode of
operation, between burst noise is minimized and the amplifier
can no longer transmit in the upstream direction. In addition
to the TXEN pin, the AD8326 also incorporates an asynchro­nous SLEEP pin, which may be used to further reduce the supply current
to approximately 4 mA. Applying Logic 0 to the SLEEP pin
places the amplifier into SLEEP mode. Transitioning into or
out of SLEEP mode will result in a transient voltage at the
output of the amplifier.

–12–

REV. 0

AD8326

Distortion, Adjacent Channel Power, and DOCSIS

In order to deliver +58 dBmV of high fidelity output power
required by DOCSIS, the PA is required to deliver up to
+67 dBmV. This added power is required to compensate for
losses associated with the transformer, diplexer, directional
coupler, and splitters that may be included in the upstream
path of the cable telephony. It should be noted that the AD8326
was characterized with the TOKO 617DB-A0070 transformer.
TPC 7, TPC 8, TPC 13, and TPC 14 show the AD8326 second
and third harmonic distortion performance versus fundamental
frequency for various output power levels.

These figures are
useful for determining the in band harmonic levels from 5 MHz
to 65 MHz. Harmonics higher in frequency will be sharply
attenuated by the low-pass filter function of the diplexer.

Another measure of signal integrity is adjacent channel power,
commonly referred to as ACP. DOCSIS section 4.2.10.1.1
states, “Spurious emissions from a transmitted carrier may
occur in an adjacent channel that could be occupied by a carrier
of the same or different symbol rates.” TPC 9 shows the mea­sured ACP for a +67 dBmV 16 QAM signal taken at the output
of the AD8326

evaluation board, through a 75 Ω to 50 Ω

matching pad (5.7 dB of loss). The transmit channel width
and adjacent
rates of
the

AD8326 for all conditions in DOCSIS Table 4-7 “Adjacent

channel width in TPC 9 correspond to symbol

160 KSYM/SEC. Table I shows the ACP results for

Channel Spurious Emissions.”

Table I. Adjacent Channel Power

Adjacent Channel Symbol Rate

Transmit 160K/s 320K/s 640K/s 1280K/s 2560K/s
Symbol ACP ACP ACP ACP ACP
Rate (dBc) (dBc) (dBc) (dBc) (dBc)

160K/s –57 –59 –62 –63 –64
320K/s –57 –58 –60 –62 –64
640K/s –55 –58 –58 –60 –62
1280K/s –55 –57 –58 –58 –60
2560K/s –53 –56 –57 –57 –57

Noise and DOCSIS

At minimum gain, the AD8326 output noise spectral density is

13.3 nV/√Hz measured at 10 MHz. DOCSIS Table 4-8, “Spuri-

ous Emissions in 5 MHz to 42 MHz,” specifies the output noise
for various symbol rates. The calculated noise power in dBmV
for 160 KSYM/SECOND is:




20










13 3



×









.

Hz

nV

2



160 60 45 5

×












+=log

kHz dBmV











– .

Comparing the computed noise power of –45.5 dBmV to the
+8 dBmV signal yields –53.5 dBc, which meets the required level
set forth in DOCSIS Table 4-8. As the AD8326 gain is increased
from this minimum value, the output signal increases at a faster

rate than the noise, resulting in a signal to noise ratio that improves
with gain. In transmit disable mode, the output noise spectral

density is 1.4 nV/√Hz, which results in –65 dBmV when computed

over 160

KSYM/SECOND

.

The noise power was measured directly at the output of the
transformer. In a typical cable telephony application there will
be a 6 dB pad, or splitter, which will further attenuate the noise
by 6 dB.

Evaluation Board Features and Operation

The AD8326 evaluation boards (Part # AD8326ARE-EVAL
and AD8326ARP-EVAL) and control software can be used to
control the AD8326 upstream cable driver via the parallel port
of a PC. A standard printer cable connected between the paral­lel port and the evaluation board is used to feed all the necessary
data to the AD8326 by means of the Windows 9X-based control
software. This package provides a means of evaluating the amplifier
by providing a convenient way to program the gain/attenuation
as well as offering easy control of the asynchronous TXEN and
SLEEP pins. With this evaluation kit, the AD8326 can be evalu­ated in either a single-ended or differential input configuration.
The amplifier can also be evaluated with or without the PULSE
diplexer in the output signal path. A schematic of the evaluation
board is provided in Figure 11.

Output Transformer and Diplexer

A 1:1 transformer is needed to couple the differential outputs of
the AD8326 to the cable while maintaining a proper impedance
match. The specified transformer is available from TOKO (Part
# 617DB-A0070); however, M/A-COM part # ETC-1-1T may
also be used. The evaluation board is equipped with the TOKO
transformer, but is also designed to accept the M/A-COM trans­former. The PULSE diplexer included on the evaluation board
provides a high-order low-pass filter function, typically used in the
upstream path. To remove the diplexer from the signal path,

remove the 0 Ω chip resistors at R7 and R19, and install a 0 Ω

chip resistor at R6 so the output signal is directed away from
the diplexer and toward the CABLE port of the evaluation

board (Figure 11). The ability of the PULSE diplexer to achieve

DOCSIS compliance is neither expressed nor implied by Analog
Devices Inc. Data on the diplexer should be obtained from
PULSE. When using the diplexer, be sure to properly terminate

the cable port (75 Ω) so that the AD8326 draws minimal current.

Overshoot on PC Printer Ports

The data lines on some PC parallel printer ports have excessive
overshoot that may cause communications problems when pre­sented to the CLK pin of the AD8326. The evaluation board
was designed to accommodate a series resistor and shunt capaci­tor (R2 and C2 in Figure 11) to filter the CLK signal if required.

Installing Visual Basic Control Software

Install the “CabDrive_26” software by running “setup.exe” on
disk one of the AD8326 Evaluation Software. Follow on-screen
directions and insert disk two when prompted. Choose instal­lation directory, and then select the icon in the upper left to
complete installation.

REV. 0

–13–

AD8326

Running AD8326 Software

To load the control software, go to START, PROGRAMS,
CABDRIVE_26, or select the AD8326.exe from the installed
directory. Once loaded, select the proper parallel port to com­municate with the AD8326 (Figure 9).

Figure 9. Parallel Port Selection

Controlling Gain/Attenuation of the AD8326

The slide bar controls the gain/attenuation of the AD8326,
which is displayed in dB and in V/V. The gain scales 0.75 dB
per LSB with valid codes from 0 to 71. The gain code from the
position of the slide bar is displayed in decimal, binary, and
hexadecimal (Figure 10).

Transmit Enable and Sleep Mode

The Transmit Enable and Transmit Disable buttons select the
mode of operation of the AD8326 by asserting logic levels on
the asynchronous TXEN pin. The Transmit Disable button
applies Logic 0 to the TXEN pin, disabling forward transmis-

sion while maintaining a 75 Ω back termination. The Transmit

Enable button applies Logic 1 to the TXEN pin, enabling the
AD8326 for forward transmission. Checking the “Enable SLEEP
Mode” checkbox applies logic “0” to the asynchronous SLEEP
pin, setting the AD8326 for SLEEP mode.

Memory Functions

The MEMORY section of the software provides a way to alter­nate between two gain settings. The “X->M1” button stores
the current value of the gain slide bar into memory while the
“RM1” button recalls the stored value, returning the gain slide
bar to the stored level. The same applies to the “X->M2” and
“RM2” buttons.

Figure 10. Control Software Interface

–14–

REV. 0

AD8326

CC

V

TP15

TP18

TP17

+

TP13

TP16

C7

0.1␮F

R17

ETC1

TOKO1

DNI

R13

TP14

0.1␮F

C11

+ 0

IN

V

TP11

0⍀

0⍀

DNI

C20

OPEN

R8

621

4

621
4

CABLE_O

R9

OPEN

0⍀

R6

OPEN

3

3

C21

0.1␮F

ETC1

TOKO1

TP9

0.1␮F

R5

OPEN

HPF_O

5

CBL

9

HPP

DNI

R16

TOKO1 ETC1

0⍀

R11

DNI

C23

C12

0.1␮F

0.1␮F

0.1␮F

C13

CC

V

C14

0.1␮F

C15

CX6002

EE

V

TB1

AGND

C16

0.1␮F

0.1␮F

0.1␮F

3, 10–18

COM

LPP

1

C17

C18

AGND

TP12

0.1␮F

0.1␮F

R19

R7

TP10

T2

T1

TP8

R4

– 0

IN

V

0⍀

R18

621

T4

DNI

4

3

621

T3

DNI

R15

R10

C22

0.1␮F

C20

10␮F

R14

DNI

4

3

0⍀

R12

78.7⍀

C10

0.1␮F

C9

REV. 0

DATEN

28272625242322212019181716

Z1

TP7

15

EE

V

C19

10␮F

+

AGND

AD8326

123456789

C4

CLK

SDATA

TXEN

SLEEP

0.1␮F

1011121314

C5

C6

0.1␮F

P1 19

P1 22

P1 21

P1 20

C1

DNI

TP2

W1

R1

0⍀

W2

TP1

0.1␮F

P1 1

P1 4

P1 3

P1 2

P1 23

P1 5

P1 24

TP3 TP4

P1 6

P1 25

R2

P1 7

P1 26

P1 8

0⍀

P1 27

C2

P1 9

P1 28

DNI

P1 10

P1 29

TP5 TP6

P1 11

P1 30

R3

P1 12

P1 31

0⍀

P1 13

P1 32

P1 14

P1 33

C3

P1 15

P1 34

DNI

P1 16

P1 35

P1 17

P1 36

AGND

P1 18

Figure 11. Evaluation Board Schematic

–15–

AD8326

Figure 12. Evaluation Board Layout (Component Side)

–16–

REV. 0

AD8326

Figure 13. Evaluation Board Layout (Silkscreen Top)

REV. 0

–17–

AD8326

Figure 14. Evaluation Board Layout (Circuit Side)

–18–

REV. 0

AD8326

Figure 15. Evaluation Board Layout (Silkscreen Bottom)

REV. 0

–19–

AD8326

Figure 16. Evaluation Board Layout (Internal Ground Plane)

–20–

REV. 0

AD8326

Figure 17. Evaluation Board Layout (Internal Power Planes)

REV. 0

–21–

AD8326

AD8326 Evaluation Board Rev. B – Revised - November 22, 2000

Qty. Description Vendor Ref Description

2 10 µF 16 V. B Size Tantalum Chip Capacitor ADS# 4-7-24 C7, C19
4 0.1 µF 50 V. 1206 Size Ceramic Chip Capacitor ADS# 4-5-18 C20–23
14 0.1 µF 25 V. 603 Size Ceramic Chip Capacitor ADS# 4-12-8 C4–C6, C8–C18
90 Ω 1/8 W. 1206 Size Chip Resistor ADS# 3-18- 88 R1–R3, R7, R8, R13, R14,

R18, R19

1 78.7 Ω 1% 1/8 W. 1206 Size Chip Resistor ADS# 3-18-194 R12

2 Yellow Test Point [INPUTS] (Bisco TP104-01-04) ADS# 12-18-32 TP13, TP14
6 White Test Point [DATA] (Bisco TP104-0 -09) ADS# 12-18-42 TP1–TP6
1 Red Test Point [VCC] (Bisco TP104-01-02) ADS# 12-18-43 TP15
1 Blue Test Point [VEE] (Bisco TP104-01-06) ADS# 12-18-62 TP7
3 Black Test Point [AGND] (Bisco TP104-01-00) ADS# 12-18-44 TP16–TP18
4 End Launch SMA Connector ADS# 12-1-31 VIN–, VIN+, CABLE,

HPF
1 Centronics Type 36 Pin Right-Angle Connector ADS# 12-3-50 P1
1 3 Terminal Power Block (Green) ADS# 12-19-14 TB1
1 1:1 Transformer TOKO # 617DB – A0070 TOKO T3, T1
1 Pulse # CX 6002 Diplexer PULSE Z2
1 AD 8326ARE (TSSOP ePad) UPSTREAM Cable Driver ADI# AD8326XRE Z1
1 AD 8326ARE REV. B Evaluation PC Board ADI# AD8326XRE-EVAL EVAL PCB

4#4–40 × 1/4 Inch STAINLESS Panhead Machine Screw ADS# 30-1-1
4#4–40 × 3/4 Inch Long Aluminum Round Standoff ADS# 30-16-3
2# 2–56 × 3/8 inch STAINLESS Panhead Machine Screw ADS# 30-1-17 (p1 hardware)

2 # 2 Steel Flat Washer ADS# 30-6-6 (p1 Hardware)
2 # 2 Steel Internal Tooth Lockwasher ADS# 30-5-2 (p1 Hardware)
2 # 2 STAINLESS STEEL Hex. Machine Nut ADS# 30-7-6 (p1 Hardware)

Do not install C1–C3, R4–R6, R10, R11, R15–R17, T2, T4, TP8–TP12, W1–W2.

–22–

REV. 0

)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead PSOP

(RP-28)

0.711 (18.06)

0.701 (17.81)

AD8326

0.189 (4.80)

0.179 (4.55)

PIN 1

0.004 (0.10)

0.000 (0.00)
STANDOFF

0.119 (3.05)

0.117 (3.00)

0.115 (2.95)

0.047

(1.20)

MAX

28

28

PIN 1

0.006 (0.15)

0.000 (0.00)

15

HEAT SLUG

ON BOTTOM

0.539 (13.69)

0.529 (13.44)

0.050 (1.27)
BSC

0.019 (0.48)

0.014 (0.36)

0.299 (7.59)

0.292 (7.42)

141

0.098 (2.49)

0.090 (2.29)

SEATING
PLANE

0.410 (10.41)

0.400 (10.16)

8ⴗ
0ⴗ

0.0125 (0.32)

0.0091 (0.23)

28-Lead HTSSOP

(RE-28)

0.386 (9.80)

0.382 (9.70)

0.378 (9.60)

15

EXPOSED

PAD

ON BOTTOM

1

0.138 (3.55)

0.136 (3.50)

0.134 (3.45)

BSC

0.0118 (0.30)

0.0075 (0.19)

0.0256

(0.65)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm

0.177 (4.50)

0.173 (4.40)

0.169 (4.30)

14

0.041 (1.05)

0.039 (1.00)

0.031 (0.80)

SEATING
PLANE

0.252
(6.40)

BSC

0.0079 (0.20)

0.0035 (0.09)

0.016 (0.41)

0.010 (0.25)

8ⴗ
0ⴗ

45°

0.040 (1.27)

0.024 (0.61)

0.030 (0.75)

0.024 (0.60)

0.177 (0.45)

REV. 0

–23–

C01856–1.5–7/01(0)

–24–

PRINTED IN U.S.A.