Datasheet AD8325 Datasheet (Analog Devices)

5 V CATV Line Driver Fine Step

FUNDAMENTAL FREQUENCY – MHz

–50

5

DISTORTION – dBc

–52

–54

–56

–60

–64

15 25 35 45

55 65

–62

–58

V

OUT

= 60dBmV

@ MAX GAIN

V

OUT

= 62dBmV

@ MAX GAIN

V

OUT

= 61dBmV

@ MAX GAIN

V

OUT

= 59dBmV

@ MAX GAIN

a

FEATURES
Supports DOCSIS Standard for Reverse Path

Transmission

Gain Programmable in 0.75 dB Steps Over a 59.45 dB

Range

Low Distortion at 61 dBmV Output

–57 dBc SFDR at 21 MHz
–55 dBc SFDR at 42 MHz

Output Noise Level

–48 dBmV in 160 kHz

Maintains 75 ⍀ Output Impedance

Transmit Enable and Transmit Disable Modes
Upper Bandwidth: 100 MHz (Full Gain Range)
5 V Supply Operation
Supports SPI Interfaces

APPLICATIONS
Gain-Programmable Line Driver

DOCSIS High-Speed Data Modems

Interactive Cable Set-Top Boxes

PC Plug-in Cable Modems
General-Purpose Digitally Controlled Variable Gain Block

V

IN+

V

IN–

ZIN (SINGLE) = 800⍀
Z

(DIFF) = 1.6k⍀

IN

Output Power Control

FUNCTIONAL BLOCK DIAGRAM

VCC (7 PINS)

R1

DIFF OR
SINGLE
INPUT
AMP

R2

VERNIER

DATA CLK GND (11 PINS)

DATEN

AD8325

ATTENUATION

CORE

8

DECODE

8

DATA LATCH

8

SHIFT

REGISTER

AD8325

BYP

POWER

AMP

Z

DIFF =

OUT

75⍀

POWER-DOWN

LOGIC

TXEN

SLEEP

V

V

OUT+

OUT–

GENERAL DESCRIPTION

The AD8325 is a low-cost, digitally controlled, variable gain ampli­fier optimized for coaxial line driving applications such as cable
modems that are designed to the MCNS-DOCSIS upstream
standard. An 8-bit serial word determines the desired output gain
over a 59.45 dB range resulting in gain changes of 0.7526 dB/LSB.

The AD8325 comprises a digitally controlled variable attenuator
of 0 dB to –59.45 dB, which is preceded by a low noise, fixed
gain buffer and is followed by a low distortion high power ampli­fier. The AD8325 accepts a differential or single-ended input
signal. The output is specified for driving a 75 Ω load, such as
coaxial cable.

Distortion performance of –57 dBc is achieved with an output
level up to 61 dBmV at 21 MHz bandwidth. A key performance
and cost advantage of the AD8325 results from the ability to
maintain a constant 75 Ω output impedance during Transmit
Enable and Transmit Disable conditions. In addition, this
device has a sleep mode function that reduces the quiescent
current to 4 mA.

The AD8325 is packaged in a low-cost 28-lead TSSOP, operates
from a single 5 V supply, and has an operational temperature
range of –40°C to +85°C.

Figure 1. Worst Harmonic Distortion vs. Gain Control

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD8325–SPECIFICATIONS

(TA = 25ⴗC, VS = 5 V, RL = 75 ⍀, VIN (differential) = 31 dBmV, V

measured through

OUT

a 1:1 transformer1 with an insertion loss of 0.5 dB @ 10 MHz unless otherwise noted.)

Parameter Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Specified AC Voltage Output = 61 dBmV, Max Gain 31 dBmV
Noise Figure Max Gain, f = 10 MHz 13.8 dB
Input Resistance Single-Ended Input 800 Ω

Differential Input 1600 Ω

Input Capacitance 2pF

GAIN CONTROL INTERFACE

Gain Range 58.45 59.45 60.45 dB
Maximum Gain Gain Code = 79 Dec 29.2 30.0 30.8 dB
Minimum Gain Gain Code = 0 Dec –30.25 –29.45 –28.65 dB
Gain Scaling Factor 0.7526 dB/LSB

OUTPUT CHARACTERISTICS

Bandwidth (–3 dB) All Gain Codes 100 MHz
Bandwidth Roll-Off f = 65 MHz 1.6 dB
Bandwidth Peaking f = 65 MHz 0 dB
Output Noise Spectral Density Max Gain, f = 10 MHz –33 dBmV in

160 kHz

Min Gain, f = 10 MHz –48 dBmV in

160 kHz

Transmit Disable Mode, f = 10 MHz –68 dBmV in

160 kHz

1 dB Compression Point Max Gain, f = 10 MHz 18.5 dBm
Differential Output Impedance Transmit Enable and Transmit Disable Modes 75 ± 20% Ω

OVERALL PERFORMANCE

Second Order Harmonic Distortion f = 21 MHz, V

f = 42 MHz, V
f = 65 MHz, V

Third Order Harmonic Distortion f = 21 MHz, V

f = 42 MHz, V
f = 65 MHz, V

= 61 dBmV @ Max Gain –70 dBc

OUT

= 61 dBmV @ Max Gain –67 dBc

OUT

= 61 dBmV @ Max Gain –60 dBc

OUT

= 61 dBmV @ Max Gain –57 dBc

OUT

= 61 dBmV @ Max Gain –55 dBc

OUT

= 61 dBmV @ Max Gain –54 dBc

OUT

Adjacent Channel Power Adjacent Channel Width = Transmit Channel –53.8 dBc

Width = 160 K

SYM/SEC

Gain Linearity Error f = 10 MHz, Code to Code ±0.3 dB
Output Settling

Due to Gain Change (T
Due to Input Change Max Gain, V

) Min to Max Gain 60 ns

GS

= 31 dBmV 30 ns

IN

Isolation in Transmit Disable Mode Max Gain, TXEN = 0 V, f = 42 MHz, –33 dBc

VIN = 31 dBmV

POWER CONTROL

Transmit Enable Settling Time (TON) Max Gain, VIN = 0 V 300 ns
Transmit Disable Settling Time (T
Between Burst Transients

2

) Max Gain, VIN = 0 V 40 ns

OFF

Equivalent Output = 31 dBmV 3 mV p-p
Equivalent Output = 61 dBmV 50 mV p-p

POWER SUPPLY

Operating Range 4.75 5 5.25 V
Quiescent Current Transmit Enable Mode (TXEN = 1) 123 133 140 mA

Transmit Disable Mode (TXEN = 0) 30 35 10 mA
Sleep Mode 2 4 7 mA

OPERATING TEMPERATURE –40 +85 °C
RANGE

NOTES

1

TOKO 617DB-A0070 used for above specifications. MACOM ETC-1-IT-15 can be substituted.

2

Between Burst Transients measured at the output of a 42 MHz diplexer.

Specifications subject to change without notice.

–2–

REV. 0

AD8325

LOGIC INPUTS (TTL/CMOS-Compatible Logic)

(DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 5 V: Full Temperature Range)

Parameter Min Typ Max Unit

Logic “1” Voltage 2.1 5.0 V
Logic “0” Voltage 0 0.8 V
Logic “1” Current (V
Logic “0” Current (V
Logic “1” Current (V
Logic “0” Current (V
Logic “1” Current (V
Logic “0” Current (V

TIMING REQUIREMENTS

= 5 V) CLK, SDATA, DATEN 020nA

INH

= 0 V) CLK, SDATA, DATEN –600 –100 nA

INL

= 5 V) TXEN 50 190 µA

INH

= 0 V) TXEN –250 –30 µA

INL

= 5 V) SLEEP 50 190 µA

INH

= 0 V) SLEEP –250 –30 µA

INL

(Full Temperature Range, VCC = 5 V, TR = TF = 4 ns, f

= 8 MHz unless otherwise noted.)

CLK

Parameter Min Typ Max Unit

Clock Pulsewidth (T
Clock Period (T
Setup Time SDATA vs. Clock (T
Setup Time DATEN vs. Clock (T
Hold Time SDATA vs. Clock (T
Hold Time DATEN vs. Clock (T

) 16.0 ns

WH

) 32.0 ns

C

) 5.0 ns

DS

) 15.0 ns

ES

) 5.0 ns

DH

) 3.0 ns

EH

Input Rise and Fall Times, SDATA, DATEN, Clock (TR, TF)10ns

T

DS

SDATA

VALID DATA WORD G1

MSB. . . .LSB

T

C

T

WH

VALID DATA WORD G2

CLK

DATEN

TXEN

ANALOG

OUTPUT

T

ES

8 CLOCK

CYCLES

SIGNAL AMPLITUDE (p-p)

Figure 2. Serial Interface Timing

MSB

SDATA

CLK

T

EH

GAIN TRANSFER (G1)

T

VALID DATA BIT

MSB-1

T

DS

GAIN TRANSFER (G2)

T

OFF

GS

T

ON

MSB-2

T

DH

REV. 0

Figure 3. SDATA Timing

–3–

AD8325

TOP VIEW

(Not to Scale)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

AD8325

DATEN

GND

SDATA V

CC

CLK V

IN–

GND V

IN+

V

CC

GND

TXEN V

CC

SLEEP

GND

GND BYP

V

CC

V

CC

V

CC

V

CC

GND GND

GND GND

GND GND

OUT– OUT+

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage +V

S

PIN CONFIGURATION

Pins 5, 9, 10, 19, 20, 23, 27 . . . . . . . . . . . . . . . . . . . . . . 6 V

Input Voltages

Pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V

Pins 1, 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V

Internal Power Dissipation

TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 W

Operating Temperature Range . . . . . . . . . . . –40° C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model Temperature Range Package Description ␪

JA

Package Option

AD8325ARU –40°C to +85°C 28-Lead TSSOP 67.7°C/W* RU-28
AD8325ARU-REEL –40°C to +85°C 28-Lead TSSOP 67.7°C/W* RU-28
AD8325-EVAL Evaluation Board

*Thermal Resistance measured on SEMI standard 4-layer board.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8325 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

Pin No. Mnemonic Description

1 DATEN Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic

2 SDATA Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the

3 CLK Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-

4, 8, 11, 12, GND Common External Ground Reference.
13, 16, 17, 18,
22, 24, 28

5, 9, 10, 19, V
20, 23, 27

6 TXEN Logic “0” disables transmission. Logic “1” enables transmission.
7 SLEEP Low Power Sleep Mode. Logic 0 enables Sleep mode, where Z

14 OUT– Negative Output Signal.

15 OUT+ Positive Output Signal.
21 BYP Internal Bypass. This pin must be externally ac-coupled (0.1 µF cap).

25 V

26 V

CC

IN+

IN–

PIN FUNCTION DESCRIPTIONS

0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta­neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch
(holds the previous gain state) and simultaneously enables the register for serial data load.

internal register with the MSB (Most Significant Bit) first.

slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to
the slave. This requires the input serial data word to be valid at or before this clock transition.

Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin.

goes to 400 Ω and supply

OUT

current is reduced to 4 mA. Logic 1 enables normal operation.

Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF
capacitor.

Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor.

–4–

REV. 0

Typical Performance Characteristics–AD8325

FREQUENCY – MHz

ISOLATION – dB

–40

–100

–80

–60

0

–20

0.1 10010 10001

TXEN = 0
V

IN

= 31dBmV

MAX GAIN

MIN GAIN

34

V

= 61dBmV

@ MAX GAIN

31

OUT

CL= 0pF

CL= 10pF

V

0.1␮F

V

IN–

V

165⍀

IN

0.1␮F

AD8325

V

IN+

GND

CC

OUT–

OUT+

TOKO 617DB–A0070

TPC 1. Basic Test Circuit

0.5

f = 10MHz

0

f = 5MHz

–0.5

f = 42MHz

f = 65MHz

GAIN CONTROL – Decimal

GAIN ERROR – dB

–1.0

–1.5

–2.0

10 30 50 60

0

20 40

TPC 2. Gain Error vs. Gain Control

1:1

R

L

75⍀

70 80

GAIN – dB

28

25

0.1␮F

22

V

165⍀

IN

0.1␮F

19

V

CC

V

–

IN

+

V

GND

IN

FREQUENCY – MHz

CL= 20pF

TOKO617DB–A0070

1:1

OUT–

OUT+

101

CL= 50pF

L

TPC 4. AC Response for Various Cap Loads

–30

f = 10MHz
TXEN = 1

–34

–38

–42

–46

OUTPUT NOISE – dBmV IN 160kHz

–50

024

16 328

GAIN CONTROL – Decimal

40 48 56 64 72 80

TPC 5. Output Referred Noise vs. Gain Control

75⍀C

R

L

100

REV. 0

40

30

20

10

0

–10

GAIN – dB

–20

–30

–40

–50

0.1 100

1

TPC 3. AC Response

79D

46D

23D

00D

10 1000

FREQUENCY – MHz

TPC 6. Isolation in Transmit Disable Mode vs. Frequency

–5–

AD8325

–55

V

–60

V

–65

V

= 60dBmV @ MAX GAIN

OUT

DISTORTION – dBc

–70

–75

535

FUNDAMENTAL FREQUENCY – MHz

= 62dBmV @ MAX GAIN

OUT

= 61dBmV @ MAX GAIN

OUT

V

OUT

25 4515

= 59dBmV @ MAX GAIN

55 65

TPC 7. Second Order Harmonic Distortion vs. Frequency
for Various Output Levels

–50

V

= 62dBmV @ MAX GAIN

–52

–54

–56

V

= 61dBmV @ MAX GAIN

OUT

OUT

180

170

160

150

140

IMPEDANCE – ⍀

130

120

110

0.1␮F

Z

165⍀

IN

0.1␮F

TXEN = 0

TXEN = 1

TOKO 617DB–A0070

V

CC

V

–

IN

OUT–
OUT+

V

+

IN

GND

101

FREQUENCY – MHz

1:1

R

L

TPC 10. Input Impedance vs. Frequency

90

85

80

75

TXEN = 1

75⍀

100

–58

DISTORTION – dBc

–60

–62

V

= 59dBmV @ MAX GAIN

OUT

–64

535

25 4515

FUNDAMENTAL FREQUENCY – MHz

V

= 60dBmV @ MAX GAIN

OUT

55 65

TPC 8. Third Order Harmonic Distortion vs. Frequency for
Various Output Levels

–50

FO = 42MHz

= 61dBmV @ MAX GAIN

V

OUT

–55

–60

–65

–70

DISTORTION – dBc

–75

–80

030

20 4010

HD3

HD2

50 60

GAIN CONTROL – Dec Code

70 80

TPC 9. Harmonic Distortion vs. Gain Control

70

IMPEDANCE – ⍀

65

60

55

TXEN = 0

101

FREQUENCY – MHz

TPC 11. Output Impedance vs. Frequency

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

C11

CENTER 21MHz 75kHz/DIV SPAN 750kHz

C11

C0

CH PWR 12.3dBm
ACP UP –54.02dB
ACP LOW –53.79dB

CU1

C0

TPC 12. Adjacent Channel Power

100

CU1

–6–

REV. 0

AD8325

APPLICATIONS
General Application

The AD8325 is primarily intended for use as the upstream
power amplifier (PA) in DOCSIS (Data Over Cable Service
Interface Specifications) certified cable modems and CATV
set-top boxes. Upstream data is modulated in QPSK or QAM
format, and done with DSP or a dedicated QPSK/QAM modula­tor. The amplifier receives its input signal from the QPSK/QAM
modulator or from a DAC. In either case the signal must be
low-pass filtered before being applied to the amplifier. Because
the distance from the cable modem to the central office will vary
with each subscriber, the AD8325 must be capable of varying its
output power by applying gain or attenuation to ensure that all
signals arriving at the central office are of the same amplitude.
The upstream signal path contains components such as a trans­former and diplexer that will result in some amount of power loss.
Therefore, the amplifier must be capable of providing enough
power into a 75 Ω load to overcome these losses without sacri­ficing the integrity of the output signal.

Operational Description

The AD8325 is composed of four analog functions in the power­up or forward mode. The input amplifier (preamp) can be used
single-endedly or differentially. If the input is used in the differ­ential configuration, it is imperative that the input signals are 180
degrees out of phase and of equal amplitudes. This will ensure
proper gain accuracy and harmonic performance. The preamp
stage drives a vernier stage that provides the fine tune gain
adjustment. The 0.7526 dB step resolution is implemented in
the vernier stage and provides a total of approximately 5.25 dB of
attenuation. After the vernier stage, a DAC provides the bulk
of the AD8325’s attenuation (9 bits or 54 dB). The signals in the
preamp and vernier gain blocks are differential to improve the
PSRR and linearity. A differential current is fed from the DAC
into the output stage, which amplifies these currents to the
appropriate levels necessary to drive a 75 Ω load. The output
stage utilizes negative feedback to implement a differential
75 Ω output impedance. This eliminates the need for external
matching resistors needed in typical video (or video filter) ter­mination requirements.

SPI Programming and Gain Adjustment

Gain programming of the AD8325 is accomplished using a
serial peripheral interface (SPI) and three digital control lines,
DATEN, SDATA, and CLK. To change the gain, eight bits
of data are streamed into the serial shift register through the
SDATA port. The SDATA load sequence begins with a falling
edge on the DATEN pin, thus activating the CLK line. With the
CLK line activated, data on the SDATA line is clocked into the
serial shift register Most Significant Bit (MSB) first, on the rising
edge of each CLK pulse. Because only a 7-bit shift register is
used, the MSB of the 8-bit word is a “don’t care” bit and is shifted
out of the register on the eighth clock pulse. A rising edge on
the DATEN line latches the contents of the shift register into
the attenuator core resulting in a well controlled change in the
output signal level. The serial interface timing for the AD8325 is
shown in Figures 2 and 3. The programmable gain range of the
AD8325 is –29.45 dB to +30 dB and scales 0.7526 dB per least
significant bit (LSB). Because the AD8325 was characterized

with a transformer, the stated gain values already take into account
the losses associated with the transformer.

The gain transfer function is as follows:

= 30.0 dB – (0.7526 dB × (79 – CODE)) for 0 ≤ CODE ≤ 79

A

V

where A

is the gain in dB and CODE is the decimal equivalent

V

of the 8-bit word.

Valid gain codes are from 0 to 79. Figure 4 shows the gain char­acteristics of the AD8325 for all possible values in an 8-bit
word. Note that maximum gain is achieved at Code 79. From
Code 80 through 127, the 5.25 dB of attenuation from the ver­nier stage is being applied over every eight codes, resulting in
the sawtooth characteristic at the top of the gain range. Because
the eighth bit is a “don’t care” bit, the characteristic for codes 0
through 127 repeats from Codes 128 through 255.

30

25

20

15

10

5

0

–5

GAIN – dB

–10

–15

–20

–25

–30

32 64 96 128 160 192 224

0

GAIN CODE – Decimal

256

Figure 4. Gain vs. Gain Code

Input Bias, Impedance, and Termination

The V
V

CC

IN+

and V

inputs have a dc bias level of approximately

IN–

/2, therefore the input signal should be ac-coupled. The

differential input impedance is approximately 1600 Ω while the
single-ended input impedance is 800 Ω. If the AD8325 is being
operated in a single-ended input configuration with a desired
input impedance of 75 Ω, the V

IN+

and V

inputs should be

IN–

terminated as shown in Figure 5. If an input impedance other
than 75 Ω is desired, the values of R1 and R2 in Figure 5 can be
calculated using the following equations:

ZR

= 1 800

IN

RZR

21= 

IN

ZIN = 75⍀

–

R1 = 82.5⍀

AD8325

+

R2 = 39.2⍀

Figure 5. Single-Ended Input Termination

REV. 0

–7–

AD8325

Output Bias, Impedance, and Termination

The differential output pins V
dc level of approximately V

and V

OUT+

/2. Therefore, the outputs should be

CC

are also biased to a

OUT–

ac-coupled before being applied to the load. This is accomplished
with a 1:1 transformer as seen in the typical applications circuit
of Figure 6. The transformer also converts the output signal
from differential to single-ended, while maintaining a proper
impedance match to the line. The differential output impedance
of the AD8325 is internally maintained at 75 Ω, regardless of
whether the amplifier is in transmit enable mode (TXEN = 1)
or transmit disable mode (TXEN = 0). If the output signal is
being evaluated on standard 50 Ω test equipment, a 75 Ω to 50 Ω
pad must be used to provide the test circuit with the correct
impedance match.

Power Supply Decoupling, Grounding, and Layout
Considerations

Careful attention to printed circuit board layout details will
prevent problems due to associated board parasitics. Proper RF
design techniques are mandatory. The 5 V supply power should be
delivered to each of the V

pins via a low impedance power bus

CC

to ensure that each pin is at the same potential. The power bus
should be decoupled to ground with a 10 µF tantalum capacitor
located in close proximity to the AD8325. In addition to the
10 µF capacitor, each V

pin should be individually decoupled to

CC

ground with a 0.1 µF ceramic chip capacitor located as close to
the pin as possible. The pin labeled BYP (Pin 21) should also be
decoupled with a 0.1 µF capacitor. The PCB should have a low-
impedance ground plane covering all unused portions of the
component side of the board, except in the area of the input and
output traces (see Figure 10). It is important that all of the
AD8325’s ground pins are connected to the ground plane to
ensure proper grounding of all internal nodes. The differential

input and output traces should be kept as short and symmetrical
as possible. In addition, the input and output traces should be
kept far apart in order to minimize coupling (crosstalk) through
the board. Following these guidelines will improve the overall
performance of the AD8325 in all applications.

Initial Power-Up

When the 5 V supply is first applied to the VCC pins of the
AD8325, the gain setting of the amplifier is indeterminate.
Therefore, as power is first applied to the amplifier, the TXEN
pin should be held low (Logic 0) thus preventing forward signal
transmission. After power has been applied to the amplifier, the
gain can be set to the desired level by following the procedure in
the SPI Programming and Gain Adjustment section. The TXEN
pin can then be brought from Logic 0 to 1, enabling forward
signal transmission at the desired gain level.

Between Burst Operation

The asynchronous TXEN pin is used to place the AD8325 into
“Between Burst” mode while maintaining a differential output
impedance of 75 Ω. Applying a Logic 0 to the TXEN pin acti­vates the on-chip reverse amplifier, providing a 74% reduction
in consumed power. The supply current is reduced from approxi­mately 133 mA to approximately 35 mA. In this mode of
operation, between burst noise is minimized and the amplifier
can no longer transmit in the upstream direction. In addition to
the TXEN pin, the AD8325 also incorporates an asynchronous
SLEEP pin, which may be used to place the amplifier in a high
output impedance state and further reduce the supply current to
approximately 4 mA. Applying a Logic 0 to the SLEEP pin
places the amplifier into SLEEP mode. Transitioning into or
out of SLEEP mode will result in a transient voltage at the output
of the amplifier. Therefore, use only the TXEN pin for DOCSIS
compliant “Between Burst” operation.

TXEN

SLEEP

5V

DATEN

SDATA

CLK

10␮F
25V

0.1␮F

0.1␮F

0.1␮F

AD8325 TSSOP

DATEN

SDATA

CLK

GND1

V

CC

TXEN

SLEEP

GND2

V

1

CC

V

CC2

GND3

GND4

GND5

OUT–

GND11

V

CC6

V

IN–

V

IN+

GND10

V

CC5

GND9

BYP

V

CC4

V

CC3

GND8

GND7

GND6

OUT+

TOKO 617DB-A0070

TO DIPLEXER Z

Figure 6. Typical Applications Circuit

0.1␮F

0.1␮F

0.1␮F

0.1␮F

0.1␮F

= 75⍀

IN

0.1␮F

0.1␮F

165⍀

V

IN–

ZIN = 150⍀

V

IN+

–8–

REV. 0

AD8325

Distortion, Adjacent Channel Power, and DOCSIS

In order to deliver 58 dBmV of high fidelity output power required
by DOCSIS, the PA should be able to deliver about 61 dBmV
in order to make up for losses associated with the transformer
and diplexer. TPC 7 and TPC 8 show the AD8325 second and
third harmonic distortion performance versus fundamental
frequency for various output power levels. These figures are
useful for determining the inband harmonic levels from 5 MHz
to 65 MHz. Harmonics higher in frequency will be sharply attenu­ated by the low-pass filter function of the diplexer. Another
measure of signal integrity is adjacent channel power or ACP.
DOCSIS section 4.2.9.1.1 states, “Spurious emissions from
a transmitted carrier may occur in an adjacent channel that could
be occupied by a carrier of the same or different symbol rates.”
TPC 12 shows the measured ACP for a 16 QAM, 61 dBmV signal,
taken at the output of the AD8325 evaluation board (see Figure
12 for evaluation board schematic). The transmit channel width
and adjacent channel width in TPC 12 correspond to symbol rates
of 160 K

. Table I shows the ACP results for the AD8325

SYM/SEC

for all conditions in DOCSIS Table 4-7 “Adjacent Channel
Spurious Emissions.”

Table I. ACP Performance for All DOCSIS Conditions (All Values in dBc)

TRANSMIT
CHANNEL
SYMBOL
RATE

160 K

SYM/SEC

320 K

SYM/SEC

640 K

SYM/SEC

1280 K

SYM/SEC

2560 K

SYM/SEC

160 K

SYM/SEC

–53.8 –55.6 –61.1 –67.0

–53.1

–54.3 –53.2 –54.0 –56.3

–56.3 –54.3 –53.4 –54.1

–58.5 –56.2 –54.4 –53.5

ADJACENT CHANNEL SYMBOL RATE

320 K

–53.8 –56.0 –61.5

SYM/SEC

640 K

Evaluation Board Features and Operation

The AD8325 evaluation board (Part # AD8325-EVAL) and
control software can be used to control the AD8325 upstream
cable driver via the parallel port of a PC. A standard printer
cable connected between the parallel port and the evaluation
board is used to feed all the necessary data to the AD8325 by
means of the Windows-based, Microsoft Visual Basic control
software. This package provides a means of evaluating the
amplifier by providing a convenient way to program the gain/
attenuation as well as offering easy control of the amplifiers’
asynchronous TXEN and SLEEP pins. With this evaluation kit
the AD8325 can be evaluated with either a single-ended or differ­ential input configuration. The amplifier can also be evaluated
with or without the PULSE diplexer in the output signal path. To
remove the diplexer from the signal path, leave R6 and R8 open
and install a 0 Ω chip resistor at R7. A schematic of the evalua­tion board is provided in Figure 12.

SYM/SEC

1280 K

SYM/SEC

2560 K

SYM/SEC

–66.7

–67.6

–62.0

–56.3

–54.1

Noise and DOCSIS

At minimum gain, the AD8325’s output noise spectral density is
10 nV/√Hz measured at 10 MHz. DOCSIS Table 4-8, “Spurious
Emissions in 5 MHz to 42 MHz,” specifies the output noise for
various symbol rates. The calculated noise power in dBmV for
160 K

SYM/SECOND





20







is:

nV

Hz

2



160 60 48

×








10



log –

















kHz dBmV

+=











Comparing the computed noise power of –48 dBmV to the
8 dBmV signal yields –56 dBc, which meets the required level of
–53 dBc set forth in DOCSIS Table 4-8. As the AD8325’s gain is
increased from this minimum value, the output signal increases at a
faster rate than the noise, resulting in a signal to noise ratio that
improves with gain. In transmit disable mode, the output noise
spectral density computed over 160 K

SYM/SECOND

is 1.0 nV/√Hz

or –68 dBmV.

REV. 0

–9–

Overshoot on PC Printer Ports

The data lines on some PC parallel printer ports have excessive
overshoot that may cause communications problems when pre­sented to the CLK pin of the AD8325 (TP6 on the evaluation
board). The evaluation board was designed to accommodate a
series resistor and shunt capacitor (R2 and C5) to filter the
CLK signal if required.

Transformer and Diplexer

A 1:1 transformer is needed to couple the differential outputs of
the AD8325 to the cable while maintaining a proper impedance
match. The specified transformer is available from TOKO (Part
# 617DB-A0070); however, MA/COM part # ETC-1-1T-15
can also be used. The evaluation board is equipped with the
TOKO transformer, but is also designed to accept the MA/COM
transformer. The PULSE diplexer included on the evaluation
board provides a high-order low-pass filter function, typically
used in the upstream path. The ability of the PULSE diplexer
to achieve DOCSIS compliance is neither expressed nor implied
by Analog Devices Inc. Data on the diplexer can be obtained
from PULSE.

AD8325

Differential Inputs

The AD8325-EVAL evaluation board may be driven with a
differential signal in one of two ways. A transformer may be
used to convert a single-ended signal to differential, or a differ­ential signal source may be used. Figure 7 and the following
paragraphs describe each of these methods.

Single-Ended-to-Differential Input (Figure 7, Option 1)

A TOKO 617DB-A0070 1:1 transformer is preinstalled in the
T3 location of the evaluation board. Install 0 Ω chip resistors at
R14, R15, and R20, and leave R16 through R19 open. For
50 Ω differential input impedance, install a 51.1 Ω resistor at R13.
For 75 Ω differential input impedance, use a 78.7 Ω resistor.
In this configuration, the input signal must be applied to the

port of the evaluation board. For input impedances other

V

IN+

than 50 Ω or 75 Ω, the correct value for R13 can be calculated
using the following equation.

Desired Input Impedance = (R131600)

Differential Input (Figure 7, Option 2)

If a differential signal source is available, it may be applied
directly to both the V

IN+

and V

input ports of the evaluation

IN–

board. In this case, 0 Ω chip resistors should be installed at
locations R16 through R19, and R14, R15, and R20 should be
left open. The equation at the end of the preceding paragraph
can be used to compute the correct value for R13 for any
desired differential input impedance. For differential input
impedances of 75 Ω or 150 Ω, the value of R13 will be 78.7 Ω or
165 Ω respectively.

DIFF IN

T1

DIFFERENTIAL INPUT, OPTION 1

VIN+

VIN–

DIFFERENTIAL INPUT, OPTION 2

R13

R13

AD8325

AD8325

Installing the Visual Basic Control Software

To install the “CABDRIVE_25” evaluation board control soft­ware, close all Windows applications and then run “SETUP.EXE”
located on Disk 1 of the AD8325 Evaluation Software. Follow
the on-screen instructions and insert Disk 2 when prompted to
do so. Enter the path of the directory into which the software
will be installed and select the button in the upper left corner to
complete the installation.

Running the Software

To invoke the control software, go to START -> PROGRAMS

-> CABDRIVE_25, or select the AD8325.EXE icon from the
directory containing the software.

Controlling the Gain/Attenuation of the AD8325

The slide bar controls the AD8325’s gain/attenuation, which is
displayed in dB and in V/V. The gain scales at 0.7526 dB per
LSB with the valid codes being from decimal 0 to 79. The gain
code (i.e., position of the slide bar) is displayed in decimal, binary,
and hexadecimal (see Figure 8).

Transmit Enable, Transmit Disable, and Sleep

The “Transmit Enable” and “Transmit Disable” buttons select
the mode of operation of the AD8325 by controlling the logic
level on the asynchronous TXEN pin. The “Transmit Enable”
button applies a Logic 1 to the TXEN pin putting the AD8325
in forward transmit mode. The “Transmit Disable” button
applies a Logic 0 to the TXEN pin selecting reverse mode, where
the forward signal transmission is disabled while a back termina­tion of 75 Ω is maintained. On early revisions of the software,
the “Transmit Enable” and “Transmit Disable” buttons may be
called “Power-Up” and “Power-Down” respectively. Checking
the “Enable SLEEP Mode” box applies a Logic 0 to the asyn­chronous SLEEP pin, putting the AD8325 into SLEEP mode.

Memory Section

The “MEMORY” section of the software provides a convenient
way to alternate between two gain settings. The “X->M1” but­ton stores the current value of the gain slide bar into memory
while the “RM1” button recalls the stored value, returning the
gain slide bar to that level. The “X->M2” and “RM2” buttons
work in the same manner.

Figure 7. Differential Input Termination Options

–10–

REV. 0

EVALUATION BOARD FEATURES AND OPERATION

AD8325

REV. 0

Figure 8. Screen Display of Windows-Based Control Software

–11–

AD8325

Figure 9. Evaluation Board—Assembly (Component Side)

–12–

REV. 0

AD8325

REV. 0

Figure 10. Evaluation Board Layout (Component Side)

–13–

AD8325

Figure 11. Evaluation Board—Solder Side

–14–

REV. 0

AD8325

CC

V

TP9

TP10

TP11

TP12

C12

R19

R17

TP23

C16

10␮F

VIN–0

DNI

DNI

0.1␮F

AGND

C11

AGND

Z1

R21

R12

0.1␮F

DNI

AGND

0⍀

R15

DNI

27

28

GND

DATEN

123

AGND

6

4

34

T4 T3

AGND

25

26

CC

IN–

V

V

SDATA

CLK

456

2

2

IN+

V

GND

24

1

3

1

5

23

GND

CC

V

SEC PRI SECPRI

R13

51.1⍀

C9

0.1␮F

C10

22

CC

V

TXEN

789

R20

TOKO1

ETC1

TP24

C15

0.1␮F

20

21

BYP

GND

SLEEP

GND

VIN+0

0⍀

DNI

R18

R22

DNI

DNI

R16

R14

0⍀

R11

0.1␮F

C7

C8

0.1␮F

18

19

17

CCVCC

V

GND

CC

CC

V

GND

V

1011121314

DNI

DNI

0.1␮F

16

GND

GND

TP22

15

GNDGND

DNI

AGND

AGND

OUT+

OUT–

HPF_0

9

AGND

TSSOP28

DNI

TP21

5

CBL

HPP

LPP

1

AGND

TB1

CC

V

DEVICE = 2LUGPWR

TP13

3

COM

DNI

P1 19

P1 20

10–18

CX6002

P1 21

P1 22

CABLE_0

DNI

TP20

AGND

R8

0⍀

R7

DNI

R6

0⍀

DNI

TP19

DNI

TP18

R4

DNI

DNI

TP17

PKG_TYPE = R1206

P1 23

P1 24

P1 25

P1 26

P1 27

P1 28

DNI

R10

R9

0⍀

6

4

34

T2 T1

TP15

P1 29

P1 30

AGND

DNI = DO NOT INSTALL

1

2

TOKO1

3

1

2

5

TP16

R5

DNI

SEC PRI SECPRI

DNI

ETC1

DNI

DNI

DNI

TP14

P1 31

P1 32

P1 33

P1 34

P1 35

AGND

AGND

P1 36

REV. 0

DATEN

SDATA

CLK

TXEN

TP6

TP2

TP1

TP4

R1

0⍀

TP3

C1

C2

0.1␮F

C3

0.1␮F

0.1␮F
AGND

SLEEP

Figure 12. Evaluation Board Schematic

–15–

P1 1

C4

P1 2

DNI

TP5

P1 3

P1 4

P1 5

R2

P1 6

C5

0⍀

P1 7

1000pF

P1 8

P1 9

TP7 TP8

P1 10

P1 11

R3

P1 12

C6

0⍀

P1 13

P1 14

DNI

P1 15

P1 16

P1 18

P1 17

AGND

AD8325

EVALUATION BOARD BILL OF MATERIALS

AD8325 Evaluation Board Rev. B, Single-Ended-to-Differential Input – Revised – February 21, 2001

Qty. Description Vendor Ref Desc.

1 10 µF 25 V. ‘D’ size tantalum chip capacitor ADS # 4-7-2 C12
1 1,000 pF 50 V. 1206 ceramic chip capacitor ADS # 4-5-20 C5
2 0.1 µF 50 V. 1206 size ceramic chip capacitor ADS # 4-5-18 C15, C16
8 0.1 µF 25 V. 0603 size ceramic chip capacitor ADS # 4-12-8 C1–C3, C7–C11
11 0 Ω 5% 1/8 W. 1206 size chip resistor ADS # 3-18-88 R1–R3, R6, R8, R9, R14, R15, R20
1 51.1 Ω 1% 1/8 W. 1206 size chip resistor ADS # 3-18-99 R13
2 Yellow Test Point ADS# 12-18-32 TP23, TP24
8 White Test Point ADS# 12-18-42 TP1–TP8
1 Red Test Point ADS# 12-18-43 TP9
3 Black Test Point ADS# 12-18-44 TP10–TP12 (GND)
1 Centronics-type 36-pin Right-Angle Connector ADS# 12-3-50 P1
1 Terminal Block 2-Pos Green ED1973-ND ADS# 12-19-13 TB1
3 SMA End launch Jack (E F JOHNSON # 142-0701-801) ADS# 12-1-31 V
2 1:1 Transformer TOKO # 617DB – A0070 TOKO T1–T3
1 PULSE Diplexer* PULSE Z2
1 AD8325 (TSSOP) UPSTREAM Cable Driver ADI# AD8325XRU Z1
1 AD8325 REV. B Evaluation PC board NC Evaluation PC board
4#4–40 × 1/4 inch STAINLESS panhead machine screw ADS# 30-1-1
4#4–40 × 3/4 inch long aluminum round stand-off ADS# 30-16-3
2# 2–56 × 3/8 inch STAINLESS panhead machine screw ADS# 30-1-17 (P1 hardware)
2 # 2 steel flat washer ADS# 30-6-6 (P1 hardware)
2 # 2 steel internal tooth lockwasher ADS# 30-5-2 (P1 hardware)
2 # 2 STAINLESS STEEL hex. machine nut ADS# 30-7-6 (P1 hardware)

NOTES
*PULSE Diplexer part numbers B5008 (42 MHz), CX6002 (42 MHz), B5009 (65 MHz).
DO NOT INSTALL C4, C6, R4, R5, R7, R10–R12, R16–R19, R21, R22, T2, T4, TP13–TP22.
SMA’s TXEN, CLK, SLEEP, DATEN, SDATA, HPF_0

–, VIN+, CABLE_0

IN

C02439–2.5–4/01(0)

PIN 1

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

28

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead TSSOP

(RU-28)

0.386 (9.80)

0.378 (9.60)

15

0.177 (4.50)

0.169 (4.30)

0.256 (6.50)

0.246 (6.25)

MAX

0.0079 (0.20)

0.0035 (0.090)

0.0256 (0.65)
BSC

141

0.0433 (1.10)

0.0118 (0.30)

0.0075 (0.19)

8ⴗ
0ⴗ

0.028 (0.70)

0.020 (0.50)

PRINTED IN U.S.A.

–16–

REV. 0