3.3 V Upstream
V
FEATURES
Supports DOCSIS 2.0 and Euro-DOCSIS standards for
reverse path transmission systems
Gain programmable in 1 dB steps over a 59 dB range
Low distortion at 61 dBmV output:
–59 dBc SFDR at 21 MHz
–54 dBc SFDR at 65 MHz
Output noise level @ minimum gain 1.3 nV/√Hz
Maintains 75 Ω output impedance in TX-enable and
Transmit-disable condition
Upper bandwidth: 100 MHz (full gain range)
3.3 V supply operation
Supports SPI® interfaces
APPLICATIONS
DOCSIS 2.0 and Euro-DOCSIS cable modems
CATV set-top boxes
CATV telephony modems
Coaxial and twisted pair line drivers
Cable Line Driver
AD8324
FUNCTIONAL BLOCK DIAGRAM
BYP
DIFF =
V
OUT+
V
OUT–
RAMP
04339-0-001
IN+
DIFF
OR SINGLE
INPUT
AMP
V
IN–
ZIN(SINGLE) = 550Ω
Z
(DIFF) = 1100Ω
IN
AD8324
GND DATEN DATACLK
VERNIER
ATTENUATION
CORE
8
DECODE
8
DATA LATCH
8
SHIFT
REGISTER
OUTPUT
STAGE
Z
OUT
75Ω
POWER-
DOWN LOGIC
SLEEP
TXEN
Figure 1. Functional Block Diagram
–40
GENERAL DESCRIPTION
The AD83241 is a low cost amplifier designed for coaxial line
driving. The features and specifications make the AD8324
ideally suited for DOCSIS 2.0 and Euro-DOCSIS applications.
The gain of the AD8324 is digitally controlled. An 8-bit serial
word determines the desired output gain over a 59 dB range,
resulting in gain changes of 1 dB/LSB.
The AD8324 accepts a differential or single-ended input signal.
The output is specified for driving a 75 Ω load through a 1:1
transformer.
Distortion performance of –54 dBc is achieved with an output
level up to 61 dBmV at 65 MHz bandwidth.
This device has a sleep mode function that reduces the quiescent current to 30 µA and a full power-down function that
reduces power-down current to 2.5 mA.
The AD8324 is packaged in a low cost 20-lead LFCSP package
and a 20-lead QSOP package. The AD8324 operates from a
single 3.3 V supply.
V
= 61dBmV @ DEC 60
–50
–60
DISTORTION (dBc)
–70
–80
515
OUT
THIRD HARMONIC
25 35 45 55 65
FREQUENCY (MHz)
Figure 2. Worst Harmonic Distortion vs. Frequency
1
Patent pending.
V
= 61dBmV @ DEC 60
OUT
SECOND HARMONIC
04339-0-002
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
www.analog.com
AD8324
TABLE OF CONTENTS
Specifications..................................................................................... 3
Power Saving Features ............................................................... 12
Logic Inputs (TTL/CMOS Compatible Logic)......................... 4
Timing Requirements.................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations and Functional Descriptions ........................6
Typical Performance Characteristics............................................. 7
Applications..................................................................................... 10
General Applications.................................................................. 10
Circuit Description..................................................................... 10
Gain Programming for the AD8324........................................ 10
Input Bias, Impedance, and Termination ................................10
Output Bias, Impedance, and Termination............................. 10
Power Supply............................................................................... 11
Signal Integrity Layout Considerations................................... 11
Initial Power-Up .........................................................................11
Distortion, Adjacent Channel Power, and DOCSIS............... 12
Utilizing Diplex Filters............................................................... 12
Noise and DOCSIS..................................................................... 12
Evaluation Board Features and Operation.............................. 13
Differential Signal Source.......................................................... 13
Differential Signal from Single-Ended Source....................... 13
Single-Ended Source.................................................................. 13
Overshoot on PC Printer Ports ................................................ 14
Installing Visual Basic Control Software................................. 14
Running AD8324 Software ....................................................... 14
Controlling Gain/Attenuation of the AD8324...................... 14
Transmit Enable and Sleep Mode............................................. 14
Memory Functions..................................................................... 14
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
RAMP Pin and BYP Pin Features ............................................11
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD8324
SPECIFICATIONS
Table 1. TA = 25°C, VCC = 3.3 V, RL = RIN = 75 Ω, VIN (Differential) = 27.5 dBmV, unless otherwise noted. The AD8324 is characterized
using a 1:1 transformer
Parameter Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Specified AC Voltage Output = 61 dBmV, Max Gain 27.5 dBmV
Input Resistance Single-Ended Input 550 Ω
Differential Input 1100 Ω
Input Capacitance 2 pF
GAIN CONTROL INTERFACE
Voltage Gain Range 58 59.0 60 dB
Max Gain Gain Code = 60 Dec 32.5 33.5 34.5 dB
Min Gain Gain Code = 1 Dec –26.5 –25.5 –24.5 dB
Output Step Size
Output Step Size Temperature Coefficient TA = –40°C to +85°C ±0.004 dB/°C
OUTPUT CHARACTERISTICS
Bandwidth (–3 dB) All Gain Codes (1–60 Decimal Codes) 100 MHz
Bandwidth Roll-Off f = 65 MHz 1.7 dB
1 dB Compression Point3 Max Gain, f = 10 MHz, Output Referred 19.6 21 dBm
Min Gain, f = 10 MHz, Input Referred 2.1 3.7 dBm
Output Noise2
Max Gain f = 10 MHz 157 166 nV/√Hz
Min Gain f = 10 MHz 1.3 1.5 nV/√Hz
Transmit Disable f = 10 MHz 1.1 1.2 nV/√Hz
Noise Figure2
Max Gain f = 10 MHz 15.5 16.0 dB
Differential Output Impedance TX Enable and TX Disable 75 ± 30%4 Ω
OVERALL PERFORMANCE
Second-Order Harmonic Distortion
f = 33 MHz, V
f = 65 MHz, V
Third-Order Harmonic Distortion
f = 65 MHz, V
2, 6
ACPR
Isolation (Transmit Disable)2 Max Gain, f = 65 MHz –75 –70 dB
POWER CONTROL
TX Enable Settling Time Max Gain, VIN = 0 2.5 µs
TX Disable Settling Time Max Gain, VIN = 0 3.8 µs
Output Switching Transients3 Equivalent Output = 31 dBmV 2.5 6 mV p-p
Equivalent Output = 61 dBmV 27 71 mV p-p
Output Settling
Due to Gain Change Min to Max Gain 60 ns
Due to Input Step Change Max Gain, VIN = 27.5 dBmV 30 ns
POWER SUPPLY
Operating Range 3.13 3.3 3.47 V
Quiescent Current Max Gain 195 207 235 mA
Min Gain 25 39 50 mA
Transmit Disable (TXEN = 0) 1 2.5 4 mA
OPERATING TEMPERATURE RANGE LFCSP –40 +85 °C
QSOP –25 +70 °C
1
at the device output.
2
0.6 1.0 1.4 dB/LSB
5, 3
5, 3
= 61 dBmV @ Max Gain –66 –60 dBc
OUT
= 61 dBmV @ Max Gain –58 –53 dBc
OUT
f = 21 MHz, V
= 61 dBmV @ Max Gain –59 –57.5 dBc
OUT
= 61 dBmV @ Max Gain –54 –52.5 dBc
OUT
–61 –58 dBc
SLEEP
Mode (Power-Down)
30 500 µA
Rev. 0 | Page 3 of 16
AD8324
A
G
A
1
TOKO 458PT-1556 used for above specifications. Typical insertion loss of 0.5 dB @ 10 MHz.
2
Guaranteed by design and characterization to ±6 sigma for TA = 25°C.
3
Guaranteed by design and characterization to ±3 sigma for TA = 25°C.
4
Measured through a 1:1 transformer.
5
Specification is worst case over all gain codes.
6
VIN = 27.5 dBmV, QPSK modulation, 160 kSPS symbol rate.
LOGIC INPUTS (TTL/CMOS COMPATIBLE LOGIC)
Table 2.
DATEN
, CLK, SDATA, TXEN,
Parameter Min Typ Max Unit
Logic 1 Voltage 2.1
Logic 0 Voltage 0
Logic 1 Current (V
Logic 0 Current (V
Logic 1 Current (V
Logic 0 Current (V
Logic 1 Current (V
Logic 0 Current (V
= 3.3 V), CLK, SDATA,
INH
= 0 V), CLK, SDATA,
INL
= 3.3 V), TXEN 50
INH
= 0 V), TXEN −250
INL
= 3.3 V),
INH
= 0 V),
INL
SLEEP
SLEEP
TIMING REQUIREMENTS
Table 3. VCC = 3.3 V, tR = tF = 4 ns, f
Parameter Min Typ Max Unit
Clock Pulse Width (tWH) 16.0
Clock Period (tC) 32.0
Setup Time SDATA vs. Clock (tDS) 5.0
t
DS
DATEN
DATEN
vs. Clock (tES)
vs. Clock (tEH)
VALID DATA WORD G1
MSB . . . LSB
t
C
t
VUH
Setup Time
Hold Time SDATA vs. Clock (tDH) 5.0
Hold Time
Input Rise and Fall Times, SDATA,
SDATA
CLK
SLEEP
, VCC = 3.3 V, unless otherwise noted
DATEN
DATEN
= 8 MHz, unless otherwise noted
CLK
DATEN
, Clock (tR, tF)
VALID DATA WORD G2
3.3 V
0.8 V
20 nA
−100 nA
190 µA
−30 µA
190 µA
−30 µA
ns
ns
ns
ns
ns
ns
0
−600
50
−250
15.0
3.0
10 ns
VALID DATA BIT
SDAT
MSB MSB-1 MSB-2
DATEN
TXEN
NALO
OUTPUT
t
ES
8 CLOCK CYCLES
SIGNAL AMPLITUDE (p-p)
t
EH
GAIN TRANSFER (G1) GAIN TRANSFER (G2)
t
OFF
t
GS
t
CN
04339-0-0030
CLK
t
DS
Figure 4. SDATA Timng
t
DH
04339-0-004
Figure 3. Serial Interface Ti ming
Rev. 0 | Page 4 of 16
AD8324
ABSOLUTE MAXIMUM RATINGS
Table 4. AD8324 Stress Ratings
Parameter Rating
Supply Voltage VCC 3.63 V
Input Voltage
VIN+, VIN– 1.5 V p-p
DATEN
, SDATA, CLK,
Internal Power Dissipation
QSOP, LFCSP 776 mW
Operating Temperature Range
LFCSP –40°C to +85°C
QSOP –25°C to +70°C
Storage Temperature Range –65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
SLEEP
, TXEN
–0.5 V to +3.63 V
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 5 of 16
AD8324
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
GND
GND
V
IN+
V
IN–
GND
CC
GND
V
1
2
AD8324
3
TOP VIEW
(Not to Scale)
4
5
678910
DATEN
SDATA
GND
CLK
VCCTXEN
161720 19 18
GND
SLEEP
1
GND
2
V
CC
3
15
RAMP
V
14
OUT+
V
13
OUT–
12
BYP
11
NC
04339-0-006
GND
GND
V
V
GND
DATEN
SDATA
CLK
IN+
IN–
4
AD8324
5
TOP VIEW
(Not to Scale)
6
7
8
9
10
NC = NO CONNECT
20
19
18
17
16
15
14
13
12
11
Figure 5. 20-Lead LFCSP Figure 6. 20-Lead QSOP
Table 5. Pin Function Descriptions
Pin No. Pin No.
20-Lead
LFCSP
1, 2, 5, 9,
18, 19
17, 20 2, 19 V
3 5 V
20-Lead
QSOP Mnemonic Description
1, 3, 4, 7,
GND Common External Ground Reference.
11, 20
CC
IN+
Common Positive External Supply Voltage.
Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF
capacitor.
4 6 V
6 8
Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor.
IN–
DATEN
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A
Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and
simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data
latch (holds the previous and simultaneously enables the register for serial data load).
7 9 SDATA
Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the internal
register with the MSB (most significant bit) first.
8 10 CLK
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-
slave shift register. Logic 0-to-1 transition latches the data bit, and a 1-to-0 transfers the data bit
to the slave. This requires the input serial data-word to be valid at or before this clock transition.
10 12
SLEEP
Low Power Sleep Mode. In the sleep mode, the AD8324’s supply current is reduced to 30 µA. A
Logic 0 powers down the part (high Z
state), and a Logic 1 powers up the part.
OUT
12 14 BYP Internal Bypass. This pin must be externally decoupled (0.1 µF capacitor).
13 15 V
14 16 V
Negative Output Signal. Must be biased to VCC. See Figure 23.
OUT–
Positive Output Signal. Must be biased to VCC. See Figure 23.
OUT+
15 17 RAMP External RAMP Capacitor (Optional).
16 18 TXEN Logic 0 disables forward transmission. Logic 1 enables forward transmission.
GND
V
CC
TXEN
RAMP
V
OUT+
V
OUT–
BYP
NC
SLEEP
GND
04339-0-005
Rev. 0 | Page 6 of 16
AD8324
TYPICAL PERFORMANCE CHARACTERISTICS
–40
–50
–60
V
= 62dBmV @ DEC 60
OUT
V
= 61dBmV @ DEC 60
OUT
–40
–50
–60
V
= 62dBmV @ DEC 60
OUT
V
= 61dBmV @ DEC 60
OUT
V
= 60dBmV @ DEC 60
OUT
DISTORTION (dBc)
–70
V
= 60dBmV @ DEC 60
OUT
–80
515
25 35 45 55 65
FREQUENCY (MHz)
Figure 7. Second-Order Harmonic Distortion vs. Frequency
for Various Output Powers
–40
V
= 61dBmV @ DEC 60
OUT
–50
TA = –40°C
DISTORTION (dBc)
–60
–70
–80
TA = +25°C
TA = +85°C
15 25 35 45 55 65
5
FREQUENCY (MHz)
Figure 8. LFSCP Second-Order Harmonic Distortion
vs. Frequency vs. Temperature
–40
V
= 61dBmV @ DEC 60
OUT
–50
04339-0-007
04339-0-008
DISTORTION (dBc)
–70
–80
515
25 35 45 55 65
FREQUENCY (MHz)
Figure 10. Third-Order Harmonic Distortion vs. Frequency
for Various Output Powers
–40
V
= 61dBmV @ DEC 60
OUT
TA = +25°C
TA = –40°C
–50
–60
DISTORTION (dBc)
–70
–80
515
TA = +85°C
25 35 45 55 65
FREQUENCY (MHz)
Figure 11. LFCSP Third-Order Harmonic Distortion
vs. Frequency vs. Temperature
–40
V
= 61dBmV @ DEC 60
OUT
TA = +25°C
–50
TA = +70°C
04339-0-010
04339-0-011
TA = +25°C
TA = +70°C
DISTORTION (dBc)
–60
–70
–80
TA = –25°C
5
15 25 35 45 55 65
FREQUENCY (MHz)
Figure 9. QSOP Second-Order Harmonic Distortion
vs. Frequency vs. Temperature
04339-0-009
Rev. 0 | Page 7 of 16
–60
DISTORTION (dBc)
–70
–80
515
25 35 45 55 65
FREQUENCY (MHz)
TA = –25°C
Figure 12. QSOP Third-Order Harmonic Distor tion
vs. Frequency vs. Temperature
04339-0-012
AD8324
0
–10
–20
–30
–40
–50
(dBm)
OUT
–60
P
–70
–80
–90
–100
CENTER 21 MHz
40
30
DEC60
20
DEC54
DEC48
10
DEC42
DEC36
0
DEC30
GAIN (dB)
–10
DEC24
DEC18
–20
DEC12
–30
–40
0.1
1.4
1.3
1.2
C0
CL1
CL1
100 kHz/DIV SPAN 1 MHz
Figure 13. Adjacent Channel Power
DEC 1 TO DEC 6
1 10 100 1000
FREQUENCY (MHz)
Figure 14. AC Response
f
= 10MHz
CU1
C0
CH PWR
WORST ACP
CU1
12dBm
–61dBc
04339-0-013
04339-0-014
60
V
= 57dBmV/TONE
OUT
50
@ MAX GAIN
40
30
20
10
(dBmV)
0
OUT
V
–10
–20
–30
–40
41.6 41.7
41.8 41.9 42.0 42.1 42.2 42.3 42.4 42.5
FREQUENCY (MHz)
Figure 16. Two-Tone Intermodulation Distortion
0
TXEN = 0
–10
VIN = 27.5dBmV
–20
–30
–40
–50
–60
ISOLATION (dB)
–70
–80
MAX GAIN
–90
–100
0
MIN GAIN
10
FREQUENCY (MHz)
100 1000
Figure 17. Isolation in Transmit Disable Mode vs. Frequency
2.0
1.5
1.0
04339-0-016
04339-0-017
1.1
1.0
0.9
OUTPUT STEP SIZE (dB)
0.8
0.7
0.6
0 6 12 18 24 30 36 42 48 54 60
GAIN CONTROL (Decimal Code)
Figure 15. Output Step Size vs. Gain Control
04339-0-015
Rev. 0 | Page 8 of 16
0.5
0
–0.5
GAIN ERROR (dB)
–1.0
–1.5
–2.0
0 6 12 2418 30 36 42 48 54 60
GAIN CONTROL (Decimal Code)
f
= 5MHz
f
= 10MHz
f
= 42MHz
f
= 65MHz
Figure 18. Gain Error vs. Gain Control
04339-0-018
AD8324
180
f
= 10MHz
160
TXEN = 1
140
120
100
80
60
40
20
OUTPUT REFERRED VOLTAGE NOISE (nV/ Hz)
0
0 6 12 30 36 42 48 54 602418
GAIN CONTROL (Decimal Code)
Figure 19. Output Referred Voltage Noise vs. Gain Control
210
TA = 25°C
190
170
150
130
110
90
70
QUIESCENT SUPPLY CURRENT (mA)
50
30
0
6 12 3036424854602418
GAIN CONTROL (Decimal Code)
Figure 20. Supply Current vs. Gain Control
04339-0-019
04339-0-020
1/2 V
110
100
90
80
70
60
BETWEEN BURSTS TRANSIENTS (mV p-p)
50
40
30
20
10
0
DOCSIS 2.0 BETWEEN BURST
TRANSIENT SPECIFICATION
0
6 12 3036424854602418
GAIN CONTROL (Decimal Code)
Figure 21. Between Burst Transient vs. Gain Control
3.3V
0.1µF
18.7Ω
39.5Ω
18.7Ω
1/2 V
IN
IN
V
IN+
V
IN–
0.1µF
V
CC
AD8324
GNDBYP
OUT+
OUT–
Figure 22. Typical Characterization Circuit
10µF
AD8324
0.1µF
1:1
75Ω
04339-0-021
R
L
04339-0-022
Rev. 0 | Page 9 of 16
AD8324
APPLICATIONS
GENERAL APPLICATIONS
The AD8324 is primarily intended for use as the upstream
power amplifier (PA) in DOCSIS (data over cable service
interface specification) certified cable modems and CATV settop boxes. The upstream signal is either a QPSK or QAM signal
generated by a DSP, a dedicated QPSK/QAM modulator, or a
DAC. In all cases, the signal must be low-pass filtered before
being applied to the PA in order to filter out-of-band noise and
higher order harmonics from the amplified signal.
Due to the varying distances between the cable modem and the
head-end, the upstream PA must be capable of varying the
output power by applying gain or attenuation. The ability to
vary the output power of the AD8324 ensures that the signal
from the cable modem will have the proper level once it arrives
at the head-end. The upstream signal path commonly includes a
diplexer and cable splitters. The AD8324 has been designed to
overcome losses associated with these passive components in
the upstream cable path.
CIRCUIT DESCRIPTION
The AD8324 is composed of three analog functions in the
transmit-enable mode. The input amplifier (preamp) can be
used in a single-ended or differential configuration. If the input
is used in the differential configuration, the input signals should
be 180 degrees out of phase and of equal amplitude. A vernier is
used in the input stage for controlling the fine 1 dB gain steps.
This stage then drives a DAC, which provides the bulk of the
AD8324’s attenuation. The signals in the preamp and DAC
blocks are differential to improve the PSRR and linearity. A
differential current is fed from the DAC into the output stage.
The output stage maintains 75 Ω differential output impedance
in all power modes.
GAIN PROGRAMMING FOR THE AD8324
The AD8324 features a serial peripheral interface (SPI) for
programming the gain code settings. The SPI interface consists
of three digital data lines: CLK,
DATEN
programmed. The SDATA pin accepts the serial data stream for
programming the AD8324 gain code. The CLK pin accepts the
clock signal to latch in the data from the SDATA line.
The AD8324 utilizes a 6-bit shift register for clocking in the
data. The shift register is designed to be programmed MSB first.
The timing interface for programming the AD8324 can be seen
in Table 2, Table 3, Figure 3, and Figure 4. While the
is held low, the serial bits on the SDATA line are shifted into the
register on the rising edge of the CLK pin. For existing software
pin should be held low while the AD8324 is being
DATEN
, and SDATA. The
DATEN
pin
that uses 8-bits to program the cable driver, the 2 MSBs will be
ignored. This allows the AD8324 to be compatible with some
existing system designs.
The AD8324 recognizes gain codes 1 through 60 (all gain codes
are in decimal, unless otherwise noted). When the AD8324 is
programmed with 61 to 63, it will internally default to max gain
(gain code 60). If the programmed gain code is above 63, the
AD8324 will recognize only the 6 LSBs. For example, gain code
75 (01001011 binary) will be interpreted as gain code 11
(001011 binary) since the 2 MSBs are ignored.
The programming range of the AD8324 is from –25.5 dB (gain
code 1) to +33.5 dB (gain code 60). The 60 dB gain range is
linear with a 1 dB change in a 1 LSB change in gain code.
Figure 15 illustrates the gain step size of the AD8324 versus gain
code. The AD8324 was characterized with a differential input
signal and a TOKO 458PT-1457 1:1 transformer at the output.
INPUT BIAS, IMPEDANCE, AND TERMINATION
The V
the input signal should be ac-coupled as seen in the typical
application circuit (Figure 23). The differential input impedance
of the AD8324 is approximately 1.1 kΩ, while the single-ended
input is 550 Ω. The high input impedance of the AD8324 allows
flexibility in termination and properly matching filter networks.
The AD8324 will exhibit optimum performance when driven
with a pure differential signal.
IN+
and V
inputs have a dc bias level of VCC/2; therefore
IN–
OUTPUT BIAS, IMPEDANCE, AND TERMINATION.
The output stage of the AD8324 requires a bias of 3.3 V. The
3.3 V power supply should be connected to the center tap of the
output transformer. Also, the V
center tap of the transformer should be decoupled as seen in the
typical application circuit (Figure 23).
The output impedance of the AD8324 is 75 Ω, regardless of
whether the amplifier is in transmit enable, transmit disable, or
sleep mode. This, when combined with a 1:1 voltage ratio transformer, eliminates the need for external back termination resistors. If the output signal is being evaluated using standard 50 Ω
test equipment, a minimum loss 75 Ω to 50 Ω pad must be used
to provide the test circuit with the proper impedance match.
The AD8324 evaluation board provides a convenient means to
implement a matching attenuator. Soldering a 43.3 Ω resistor in
the R15 placeholder and an 86.6 Ω resistor in the R16 placeholder will allow testing on a 50 Ω system. When using a
matching attenuator, it should be noted that there will be 5.7 dB
of power loss (7.5 dB voltage) through the network.
that is being applied to the
CC
Rev. 0 | Page 10 of 16
AD8324
Z
= 150Ω
IN
V
IN+
V
IN–
DATEN
SDATA
CLK
TXEN
SLEEP
V
CC
0.1µF
174Ω
0.1µF
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
10µF
1
2
3
4
5
6
7
8
9
10
AD8324-JRQ
GND
V
CC
GND
GND
V
IN+
V
IN–
GND
DATEN
SDATA
CLK
GND
V
TXEN
RAMP
V
OUT+
V
OUT–
BYP
NC
SLEEP
GND
20
19
CC
18
0.1µF
17
16
15
14
13
0.1µF
12
11
1:1
TOKO 458PT-1556
TO DIPLEXER
= 75Ω
Z
IN
04339-0-023
Figure 23. Typical Application Circuit
Tabl e 6. Ad j ace n t Ch a nn e l Power
Adjacent Channel Symbol Rate (kSym/s)
Channel Symbol Rate (kSym/s) 160 320 640 1280 2560 5120
160 –63 –64 –68 –71 –72 –66
320 –63 –64 –66 –70 –72 –67
640 –64 –64 –65 –67 –71 –67
1280 –67 –65 –65 –66 –68 –67
2560 –70 –67 –66 –66 –67 –65
5120 –72 –70 –67 –67 –64 –64
POWER SUPPLY
The 3.3 V supply should be delivered to each of the VCC pins via
a low impedance power bus. This ensures that each pin is at the
same potential. The power bus should be decoupled to ground
using a 10 µF tantalum capacitor located close to the AD8324.
In addition to the 10 µF capacitor, V
pins should be decoupled
CC
to ground with ceramic chip capacitors located close to the pins.
The bypass pin, labeled BYP, should also be decoupled. The PCB
should have a low impedance ground plane covering all unused
portions of the board, except in areas of the board where input
and output traces are in close proximity to the AD8324 and the
output transformer. All AD8324 ground pins must be connected
to the ground plane to ensure proper grounding of all internal
nodes.
SIGNAL INTEGRITY LAYOUT CONSIDERATIONS
Careful attention to printed circuit board layout details will
prevent problems due to board parasitics. Proper RF design
techniques are mandatory. The differential input and output
traces should be kept as short as possible. Keeping the traces
short will minimize parasitic capacitance and inductance, which
is most critical between the outputs of the AD8324 and the 1:1
output transformer. It is also critical that all differential signal
paths be symmetrical in length and width. In addition, the input
and output traces should be adequately spaced to minimize
coupling (crosstalk) through the board. Following these guidelines will optimize the overall performance of the AD8324 in all
applications.
INITIAL POWER-UP
When the supply voltage is first applied to the AD8324, the gain
of the amplifier is initially set to gain code 1. As power is first
applied to the amplifier, the TXEN pin should be held low
(Logic 0) to prevent forward signal transmission. After power
has been applied to the amplifier, the gain can be set to the
desired level by following the procedure provided in the Gain
Programming for the AD8324 section. The TXEN pin can then
be brought from Logic 0 to Logic 1, enabling forward signal
transmission at the desired gain level.
RAMP PIN AND BYP PIN FEATURES
The RAMP pin (Pin 15) is used to control the length of the
burst on and off transients. By default, leaving the RAMP pin
unconnected will result in a transient that is fully compliant
with DOCSIS 2.0 Section 6.2.21.2, Spurious Emissions During
Burst On/Off Transients. DOCSIS requires that all between
burst transients must be dissipated no faster than 2 µs. Adding
capacitance to the RAMP pin will slow the dissipation even
more.
Rev. 0 | Page 11 of 16
AD8324
The BYP pin is used to decouple the output stage to ground.
Typically, for normal DOCSIS operation, the BYP pin should be
decoupled to ground with a 0.1 µF capacitor. However, in
applications that may require transient on/off times faster than
2 µs, smaller capacitors may be used, but it should be noted that
the BYP pin should always be decoupled to ground.
POWER SAVING FEATURES
The AD8324 incorporates three distinct methods of reducing
power consumption: transmit disable and sleep modes for
between-burst and shutdown modes, as well as gain dependent
quiescent current for transmit enable mode.
Another measure of signal integrity is adjacent channel power,
commonly referred to as ACP. DOCSIS 2.0, section 6.2.21.1.1
states, “Spurious emissions from a transmitted carrier may
occur in an adjacent channel that could be occupied by a carrier
of the same or different symbol rates.” Figure 13 shows the
typical ACP for a 61 dBmV (approximately 12 dBm) QPSK
signal taken at the output of the AD8324 evaluation board. The
transmit channel width and adjacent channel width in Figure 13
correspond to the symbol rates of 160 kSym/s. Table 6 shows
the ACP results for the AD8324 driving a QPSK, 61 dBmV
signal for all conditions in DOCSIS Table 6-9, Adjacent Channel
Spurious Emissions.
The asynchronous TXEN pin is used to place the AD8324 into
between-burst mode. In this reduced current state, the 75 Ω
output impedance is maintained. Applying Logic 0 to the TXEN
pin deactivates the on-chip amplifier, providing a 98.8% reduction in consumed power. For 3.3 V operation, the supply current
is typically reduced from 207 mA to 2.5 mA. In this mode of
operation, between-burst noise is minimized and high input to
output isolation is achieved. In addition to the TXEN pin, the
SLEEP
AD8324 also incorporates an asynchronous
may be used to further reduce the supply current to approximately 30 µA. Applying Logic 0 to the
SLEEP
amplifier into
mode may result in a transient voltage at the output of the
amplifier.
In addition to the sleep and transmit disable functions, the
AD8324 provides yet another means of reducing system power
consumption. While in the transmit enable state, the AD8324
incorporates supply current scaling, which allows for lower
power consumption at lower gain codes. Figure 20 shows the
typical relationship between supply current and gain code.
mode. Transitioning into or out of
SLEEP
pin, which
pin places the
SLEEP
DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS
To deliver the DOCSIS required 58 dBmV of QPSK signal and
55 dBmV of 16 QAM signal, the PA is required to deliver up to
61 dBmV. This added power is required to compensate for
losses associated with the diplex filter or other passive components that may be included in the upstream path of cable
modems or set-top boxes. It should be noted that the AD8324
was characterized with a differential input signal. Figures 7 to 10
show the AD8324 second and third harmonic distortion performance versus the fundamental frequency for various output
power levels. These figures are useful for determining the inband harmonic levels from 5 MHz to 65 MHz. Harmonics
higher in frequency (above 42 MHz for DOCSIS and above
65 MHz for Euro-DOCSIS) will be sharply attenuated by the
low-pass filter function of the diplexer.
UTILIZING DIPLEX FILTERS
The AD8324 was designed to drive 61 dBmV without any
external filtering and still meet DOCSIS spurious emissions and
distortion requirements. However, in most upstream CATV
applications, a diplex filter is used to separate the upstream and
downstream signal paths from one another. The diplex filter
does have insertion loss that the upstream driver needs to overcome, but it also provides a low-pass filter. The addition of this
low-pass filter to the signal chain can greatly attenuate second
harmonic products of channels above 21 MHz and third
harmonic products of channels at or above 14 MHz up for
diplexers with a 42 MHz upstream cutoff. Similar performance
gains can be achieved using European-specified diplexers to
filter second harmonics for channels above 33 MHz and third
harmonics for channels above 22 MHz (65 MHz upstream
cutoff). This filtering allows the AD8324 to drive up to
63 dBmV of QPSK (this level can vary by application and
modulation type).
NOISE AND DOCSIS
At minimum gain, the AD8324 output noise spectral density is
1.3 nV/√Hz measured at 10 MHz. DOCSIS Table 6-10, Spurious
Emissions in 5 MHz to 42 MHz, specifies the output noise for
various symbol rates. The calculated noise power in dBmV for
160 kSym/s is
2
20 × log [√(1.3 nV/√Hz)
Comparing the computed noise power of –65.7 dBmV to the
+8 dBmV signal yields –73.7 dBc, which meets the required
level set forth in DOCSIS Table 6-10. As the AD8324 gain is
increased above this minimum value, the output signal
increases at a faster rate than the noise, resulting in a signal-tonoise ratio that improves with gain. In transmit disable mode,
the output noise spectral density is 1.1 nV/√Hz, which results in
–67 dBmV when computed over 160 kSym/s. The noise power
was measured directly at the AD8324AR-EVAL’s output.
× 160 kHz] + 60 = –65.7 dBmV
Rev. 0 | Page 12 of 16
AD8324
Z
EVALUATION BOARD FEATURES AND OPERATION
The AD8324 evaluation board and control software can be used
to control the AD8324 upstream cable driver via the parallel
port of a personal computer. A standard printer cable connected
to the parallel port of the PC is used to feed all the necessary
data to the AD8324 using the Windows® based control software.
This package provides a means of controlling the gain and the
power mode of the AD8324. With this evaluation kit, the
AD8324 can be evaluated in either a single-ended or differential
input configuration. A schematic of the evaluation board is
provided in Figure 29.
DIFFERENTIAL SIGNAL SOURCE
Typical applications for the AD8324 use a differential input
signal from a modulator or a DAC. Refer to Table 7 for common
values of R4, or calculate other input configurations using the
equation in Figure 24. This circuit configuration will give
optimal distortion results due to the symmetric input signals. It
should be noted that this is the configuration that was used to
characterize the AD8324.
ZIN× 1100Ω
R4 =
1100Ω – Z
IN
V
IN+
IN
V
IN–
Figure 24. Differential Circuit
R4
AD8324
04339-0-024
DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE
The default configuration of the evaluation board implements a
differential signal drive from a single-ended signal source. This
configuration uses a 1:1 balun transformer to approximate a
differential signal. Because of the non-ideal nature of real
transformers, the differential signal is not purely equal and
opposite in amplitude. Although this circuit slightly sacrifices
even order harmonic distortion due to asymmetry, it does
provide a convenient way to evaluate the AD8324 with a singleended source. The AD8324 evaluation board is populated with a
TOKO 617DB-A0070 1:1 for this purpose (T1).
Table 7 provides typical R4 values for common input
configurations. R16 must be removed, and R2 and R3 should be
shorted. Other input impedances may be calculated using the
equation in Figure 25. Refer to Figure 29 for an evaluation
board schematic. To use the transformer for converting a single
ended source into a differential signal, the input signal must be
applied to V
IN+
.
ZIN× 1100Ω
R4 =
1100Ω – Z
IN
V
IN+
Z
IN
Figure 25. Single-to-Differential Circuit
R4
AD8324
04339-0-025
SINGLE-ENDED SOURCE
Although the AD8324 was designed to have optimal DOCSIS
performance when used with a differential input signal, the
AD8324 may also be used as a single-ended receiver, or as an IF
digitally controlled amplifier. However, as with the single-ended
to differential configuration noted previously, even order
harmonic distortion will be slightly degraded.
When operating the AD8324 in a single-ended input mode,
terminate the part as illustrated in Figure 26. On the AD8324
evaluation boards, this termination method requires the
removal and shorting of R2 and R3, the removal of R4, as well
as the addition of 86.6 Ω at R1 and 40.2 Ω at R17 for 75 Ω
termination. Table 7 shows the correct values for R11 and R12
for some common input configurations. Other input impedance
configurations may be accommodated using the equations in
Figure 26.
× 550
Z
IN
R1 =
550 – Z
V
IN+
Z
IN
R1
Figure 26. Single-Ended Circuit
R17
R17 =
IN
Table 7. Common Matching Resistors
Differential Input Termination
ZIN (Ω) R2/R3 (Ω) R4 (Ω) R1/R17 (Ω)
50 Open 52.3 Open/Open
75 Open 80.6 Open/Open
100 Open 110 Open/Open
150 Open 174 Open/Open
Single-Ended Input Termination
ZIN (Ω) R2/R3 (Ω) R4 (Ω) R1/R17 (Ω)
50 0/0 Open 54.9/26.1
75 0/0 Open 86.6/40.2
× R1
Z
IN
R1 – Z
AD8324
IN
04339-0-026
Rev. 0 | Page 13 of 16
AD8324
OVERSHOOT ON PC PRINTER PORTS
The data lines on some PC parallel printer ports have excessive
overshoot, which may cause communications problems when
presented to the CLK pin of the AD8324. The evaluation board
was designed to accommodate a series resistor and shunt
capacitor (R9 and C5 in Figure 29) to filter the CLK signal if
required. For parallel ports with logic levels above 3.3 V, R9 and
C5 may be used as an attenuator.
INSTALLING VISUAL BASIC CONTROL SOFTWARE
Install the CabDrive_24 software by running the setup.exe file
on disk one of the AD8324 evaluation software. Follow the onscreen directions and insert disk two when prompted. Choose
the installation directory and then select the icon in the upper
left to complete the installation.
RUNNING AD8324 SOFTWARE
To load the control software, go to START, PROGRAMS,
CABDRIVE_24 or select the AD8324.exe file from the installed
directory. Once loaded, select the proper parallel port to
communicate with the AD8324 (Figure 27).
CONTROLLING GAIN/ATTENUATION OF THE AD8324
The slide bar controls the gain/attenuation of the AD8324,
which is displayed in dB and in V/V. The gain scales 1 dB per
LSB. The gain code from the position of the slide bar is
displayed in decimal, binary, and hexadecimal (Figure 28).
04339-0-028
Figure 28. Control Software Interface
TRANSMIT ENABLE AND SLEEP MODE
The Transmit Enable and Transmit Disable buttons select the
mode of operation of the AD8324 by asserting logic levels on
the asynchronous TXEN pin. The Transmit Disable button
applies Logic 0 to the TXEN pin, disabling forward transmission. The Transmit Enable button applies Logic 1 to the TXEN
pin, enabling the AD8324 for forward transmission. Checking
04339-0-027
Figure 27. Parallel Port Selection
the Enable SLEEP Mode checkbox applies Logic 0 to the asynchronous
SLEEP
pin, setting the AD8324 for
SLEEP
mode.
MEMORY FUNCTIONS
The Memory section of the software provides a way to alternate
between two gain settings. The X–>M1 button stores the
current value of the gain slide bar into memory, while the RM1
button recalls the stored value, returning the gain slide bar to
the stored level. The same applies to the X–>M2 and RM2
buttons.
Rev. 0 | Page 14 of 16
AD8324
R4A
C1A
0.1µF
C2A
0.1µF
TP9A
VCC1
DUT1
AD8324
1
GND GND
2
V
CC
3
GND TXEN
4
GND RAMP
5
V
IN+
6
V
IN–
7
GND BYP
8
DATAEN N
9
SDATA SLEEP
10
CLK GND
V
V
V
OUT+
OUT–
VCC1
C13A
0.1µF
C8A
10µF
TP10A
TP11A
TP12A
TP_VCC1
T2A
1
2
3
TOKOB5F
VCC1
R15A
6
4
0Ω
CABLE_0A
R16A
OPEN
P1
19
P1
20
P1
21
P1
22
P1
23
P1
24
P1
25
P1
26
P1
27
P1
28
P1
29
P1
30
P1
31
04339-0-029
C9A
OPEN
20
19
CC
18
17
16
15
14
13
C
12
11
C10A
0.1µF
C11A
OPEN
C12A
0.1µF
AGND1
TP_AGND1
VIN+_A
VIN–_A
P1
P1
P1
P1
P1
P1
R2A
OPEN
T1A
1
R6A
0Ω
C3A
OPEN
R8A
0Ω
C4A
OPEN
R10A
0Ω
C5A
OPEN
R12A
0Ω
C6A
OPEN
R14A
0Ω
C7A
OPEN
3
4
TOKO1
R3A
OPEN
2
73.4Ω
6
R1A
OPEN
R17A
OPEN
TP1A
R5A
1kΩ
2
TP2A
R7A
1kΩ
3
TP3A
R9A
1kΩ
5
TP4A
R11A
1kΩ
6
TP5A
R13A
1kΩ
7
16
Figure 29. AD8324 Evaluation Board Schematic
Rev. 0 | Page 15 of 16
AD8324
C
Y
OUTLINE DIMENSIONS
INDICATOR
SEATING
PIN 1
1.00
0.85
0.80
PLANE
12° MAX
BSC SQ
VIEW
0.50
BSC
4.0
TOP
0.80 MAX
0.65 TYP
0.20
REF
3.75
BSC SQ
0.05 MAX
0.02 NOM
0.60
MAX
0.60
MAX
0.75
0.55
0.35
COPLANARITY
0.08
16
15
11
10
BOTTOM
VIEW
0.30
0.23
0.18
20
1
2.25
2.10 SQ
1.95
5
6
0.25MIN
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 30. 20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body (CP-20)
Dimensions shown in millimeters
0.341
BSC
PIN 1
0.010
0.004
OPLANARIT
0.004
20 11
1
0.065
0.049
0.025
BSC
COMPLIANT TO JEDEC STANDARDS MO-137AD
0.012
0.008
0.069
0.053
10
SEATING
PLANE
0.154
BSC
0.236
BSC
0.010
0.006
8°
0°
0.050
0.016
Figure 31. 20-Lead Shrink Small Outline Package [QSOP] (RQ-20)
Dimensions shown in inches
ORDERING GUIDE
Model Temperature Range Package Description θJA (°C/W) Package Option
AD8324JRQ –25°C to +70°C 20-Lead QSOP 83.21 RQ-20
AD8324JRQ-REEL –25°C to +70°C 20-Lead QSOP 83.21 RQ-20
AD8324JRQ-REEL7 –25°C to +70°C 20-Lead QSOP 83.21 RQ-20
AD8324JRQ-EVAL
AD8324ACP –40°C to +85°C 20-Lead LFCSP 30.42 CP-20
AD8324ACP-REEL7 –40°C to +85°C 20-Lead LFCSP 30.42 CP-20
AD8324ACP-EVAL
1
Thermal resistance measured on SEMI standard 4-layer board.
2
Thermal resistance measured on SEMI standard 4-layer board, paddle soldered to board.
Evaluation Board
Evaluation Board
© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C04339–0–10/03(0)
Rev. 0 | Page 16 of 16
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