Datasheet AD8315 Datasheet (ANALOG DEVICES)

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C

FEATURES

Complete RF detector/controller function
>50 dB range at 0.9 GHz (−49 dBm to +2 dBm, re 50 Ω)
Accurate scaling from 0.1 GHz to 2.5 GHz
Temperature-stable linear-in-dB response
Log slope of 23 mV/dB, intercept at −60 dBm at 0.9 GHz
True integration function in control loop
Low power: 20 mW at 2.7 V, 38 mW at 5 V
Power-down to 10.8 μW

APPLICATIONS

Single, dual, and triple band mobile handset (GSM, DCS, EDGE)
Transmitter power control

GENERAL DESCRIPTION

The AD8315 is a complete low cost subsystem for the precise
control of RF power amplifiers operating in the frequency range

0.1 GHz to 2.5 GHz and over a typical dynamic range of 50 dB.
It is intended for use in cellular handsets and other battery­operated wireless devices. The log amp technique provides a
much wider measurement range and better accuracy than
controllers using diode detectors. In particular, its temperature
stability is excellent over a specified range of −30°C to +85°C.

50 dB GSM PA Controller

AD8315

Its high sensitivity allows control at low signal levels, thus
reducing the amount of power that needs to be coupled to
the detector.

For convenience, the signal is internally ac-coupled. This
high-pass coupling, with a corner at approximately 0.016 GHz,
determines the lowest operating frequency. Therefore, the
source can be dc grounded.

The AD8315 provides a voltage output, VAPC, that has the
voltage range and current drive to directly connect to most
handset power amplifiers’ gain control pin. VAPC can swing
from 250 mV above ground to within 200 mV below the supply
voltage. Load currents of up to 6 mA can be supported.

The setpoint control input is applied to the VSET pin and has
an operating range of 0.25 V to 1.4 V. The associated circuit
determines the slope and intercept of the linear-in-dB
measurement system; these are nominally 23 mV/dB and

−60 dBm for a 50 Ω termination (−73 dBV) at 0.9 GHz.
Further simplifying the application of the AD8315, the input
resistance of the setpoint interface is over 100 MΩ, and the bias
current is typically 0.5 µA.

The AD8315 is available in MSOP and LFCSP packages and
consumes 8.5 mA from a 2.7 V to 5.5 V supply. When powered
down, the sleep current is 4 µA.

FUNCTIONAL BLOCK DIAGRAM

VPOS

ENBL

DET

RFIN

OMM

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

10dB

LOW NOISE

GAIN BIAS

DET

OFFSET
COMP’N

10dB

LOW NOISE

BAND GAP

REFERENCE

DET DET DET

10dB 10dB

INTERCEPT

POSITIONING

Figure 1.

OUTPUT
ENABLE

DELAY

V-I

VAP C

FLTR

VSET

23mV/dB
250mV TO

1.4V = 50dB

01520-001

×1.35

HI-Z

LOW NOISE (25nV/√Hz)
RAIL-TO-RAIL BUFFER

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD8315

TABLE OF CONTENTS

Features .............................................................................................. 1

Practical Loop ............................................................................. 15

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 12

Basic Theory................................................................................ 12

Controller-Mode Log Amps ..................................................... 13

Control Loop Dynamics............................................................ 13

REVISION HISTORY

6/06—Rev. B to Rev. C

Updated Format..................................................................Universal

Changes to Ordering Guide.......................................................... 23

1/03—Rev. 0 to Rev. B

Edits to Product Description Section ............................................ 1

Edit to Functional Block Diagram ................................................. 1

Edits to Specifications...................................................................... 2

Edits to Absolute Maximum Ratings ............................................. 3

Ordering Guide Updated................................................................. 3

TPC 9 Replaced with New Figure .................................................. 5

Edits to TPC 27................................................................................. 8

Edit to Figure 1.................................................................................. 9

Edit to Figure 3................................................................................ 10

Edit to Equation 9........................................................................... 10

Edit to Equation 10......................................................................... 10

A Note About Power Equivalency ........................................... 16

Basic Connections...................................................................... 16

Range on VSET and RFIN ........................................................ 17

Transi e n t Resp o n se .................................................................... 17

Mobile Handset Power Control Example ............................... 18

Enable and Power-On................................................................ 19

Input Coupling Options ............................................................ 19

Using the Chip Scale Package................................................... 20

Evaluation Board ........................................................................ 20

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 23

Edit to Equation 11......................................................................... 10

Edits to Example section ............................................................... 10

Edit to Basic Connections Section ............................................... 12

Edits to Input Coupling Options Section.................................... 14

Table III Becomes Table II............................................................. 15

Table II Recommended Components Deleted ........................... 15

Using the Chip-Scale Package Section Added............................ 15

Edits to Evaluation Board Section................................................ 15

Figure 12 Title Edited..................................................................... 16

Figure 13 Title Edited..................................................................... 16

8-Lead Chip Scale Package (CP-8) Added .................................. 17

Updated Outline Dimensions....................................................... 17

10/99—Revision 0: Initial Version

Rev. C | Page 2 of 24

AD8315

SPECIFICATIONS

VS = 2.7 V, T = 25°C, 52.3 Ω termination on RFIN, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

OVERALL FUNCTION

Frequency Range
Input Voltage Range ±1 dB log conformance, 0.1 GHz −57 −11 dBV

Equivalent dBm Range −44 +2 dBm
Logarithmic Slope
Logarithmic Intercept

Equivalent dBm Level −66 −57 −51 dBm

RF INPUT INTERFACE Pin RFIN

Input Resistance
Input Capacitance

OUTPUT Pin VAPC

Minimum Output Voltage V
ENBL low 0.02 V
Maximum Output Voltage RL ≥ 800 Ω 2.45 2.6 V
vs. Temperature
General Limit 2.7 V ≤ V
Output Current Drive Source/Sink 5/200 mA/μA
Output Buffer Noise 25 nV√Hz
Output Noise RF input = 2 GHz, 0 dBm, f
Small Signal Bandwidth 0.2 V to 2.6 V swing 30 MHz
Slew Rate 10% to 90%, 1.2 V step (V
Response Time FLTR = open, see Figure 26 150 ns

SETPOINT INTERFACE Pin VSET

Nominal Input Range Corresponding to central 50 dB 0.25 1.4 V
Logarithmic Scale Factor 43.5 dB/V
Input Resistance 100 kΩ
Slew Rate 16 V/μs

ENABLE INTERFACE Pin ENBL

Logic Level to Enable Power 1.8 V
Input Current when Enable

High
Logic Level to Disable Power 0.8 V
Enable Time

Disable Time

Power-On/Enable Time

1

2

2

3

3

4

To meet all specifications 0.1 2.5 GHz

0.1 GH 21.5 24 25.5 mV/dB

0.1 GHz −79 −70 −64 dBV

0.1 GHz 2.8 kΩ

0.1 GHz 0.9 pF

≤ 200 mV, ENBL high 0.25 0.27 0.3 V

SET

85°C, V

= 3 V, I

POS

≤ 5.5 V, RL = ∞ V

POS

= 6 mA 2.54 V

OUT

= 100 kHz, C

NOISE

), open loop

SET

= 220 pF 130 nV/√Hz

FLT

5

− 0.1 V

POS

13 V/μs

V

POS

20 μA

Time from ENBL high to V

≤ 200 mV, refer to Figure 23

V

SET

Time from ENBL low to V

≤ 200 mV, refer to Figure 23

V

SET

within 1% of final value,

APC

within 1% of final value,

APC

Time from VPOS/ENBL high to V
V

≤ 200 mV, refer to Figure 28

SET

Time from VPOS/ENBL low to V

≤ 200 mV, refer to Figure 28

V

SET

within 1% of final value,

APC

within 1% of final value,

APC

4 5 μs

8 9 μs

2 3 μs

100 200 ns

Rev. C | Page 3 of 24

AD8315

Parameter Conditions Min Typ Max Unit

POWER INTERFACE Pin VPOS

Supply Voltage 2.7 5.5 V
Quiescent Current ENBL high 8.5 10.7 mA

Over Temperature −30°C ≤ TA ≤ +85°C 12.9 mA

Disable Current

Over Temperature −30°C ≤ TA ≤ +85°C 13 μA

1

Operation down to 0.02 GHz is possible.

2

Mean and standard deviation specifications are available in Table 2

3

See Figure 11 for plot of input impedance vs. frequency.

4

This parameter is guaranteed but not tested in production. Limit is −3 sigma from the mean.

5

Response time in a closed-loop system depends on the filter capacitor (C

6

This parameter is guaranteed but not tested in production. Maximum specified limit on this parameter is the 6 sigma value.

Table 2. Typical Specifications at Selected Frequencies at 25°C (Mean and Sigma)

Frequency (GHz) Mean Sigma Mean Sigma Mean Sigma Mean Sigma

0.1 23.8 0.3 −70.1 1.8 −57.7 1.3 −10.6 0.8

0.9 23.2 0.4 −72.6 1.8 −61.0 1.3 −11.2 0.8

1.9 22.2 0.3 −73.8 1.6 −62.9 0.9 −18.5 1.7

2.5 22.3 0.4 −75.6 1.5 −64.0 1.1 −20.0 1.7

6

ENBL low 4 10 μA

) used and the response of the variable gain element.

FLT

±1 dB Dynamic Range

Slope (mV/dB) Intercept (dBV)

Low Point (dBV) High Point (dBV)

Rev. C | Page 4 of 24

AD8315

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage VPOS 5.5 V
Temporary Overvoltage VPOS

(100 cycles, 2 sec duration, ENBL Low) 6.3 V

VAPC, VSET, ENBL 0 V, V
RFIN 17 dBm

Equivalent Voltage 1.6 V rms

Internal Power Dissipation 60 mW
θJA (MSOP) 200°C/W
θJA (LFCSP, Paddle Soldered) 80°C/W
θJA (LFCSP, Paddle Not Soldered) 200°C/W
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec)

MSOP 300°C
LFCSP 240°C

POS

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. C | Page 5 of 24

AD8315

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

RFIN

2

ENBL

3

VSET

(Not to Scale)

4

FLTR

NC = NO CONNECT

AD8315

TOP VIEW

8

7

6

5

VPOS

VAP C

NC

COMM

01520-002

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 RFIN RF Input.
2 ENBL Connect to VPOS for Normal Operation Connect Pin to Ground for Disable Mode.
3 VSET Setpoint Input. Nominal input range 0.25 V to 1.4 V.
4 FLTR Integrator Capacitor. Connect between FLTR and COMM.
5 COMM Device Common (Ground).
6 NC No Connection.
7 VAPC Output. Control voltage for gain control element.
8 VPOS Positive Supply Voltage: 2.7 V to 5.5 V.

Rev. C | Page 6 of 24

AD8315

R
R

TYPICAL PERFORMANCE CHARACTERISTICS

10

0

–10

–20

–30

0.1GHz

–40

0.9GHz

–50

RF INPUT AMPLITUDE (dBV)

–60

–70

–80

0.2

1.9GHz

0.4 0.6 0.8 1.0 1.2 1.4
V

SET

2.5GHz

(V)

Figure 3. Input Amplitude vs. V

10

0

(+3dBm)

RF INPUT

(–47dBm)

–10

–20

–30

–40

AMPLITUDE (d BV)

–50

–60

–70

0.1

+85°C

+25°C

0.3 0.5 0.7 0.9 1.1 1.3 1.5

–30°C

ERROR AT +85°C AND –30°C
BASED ON DEVIATIO N FROM
SLOPE AND INTE RCEPT AT +25°C

(V)

V

SET

Figure 4. Input Amplitude and Log Conformance vs. V

10

0

(+3dBm)

RF INPUT

(–47dBm)

–10

–20

–30

–40

AMPLIT UDE (dBV)

–50

–60

–70

0.1

0.3 0. 5 0.7 0.9 1.1 1.3 1.5

–30°C

+85°C

+25°C

ERROR AT +85°C AND –30° C
BASED ON DEVIAT ION FRO M
SLOPE AND I NTERCEPT AT +25°C

V

(V)

SET

SET

+25°C

–30°C

+25°C

–30°C

+85°C

at 0.1 GHz

SET

+85°C

23

13

3

–7

–17

–27

–37

–47

–57

–67

4

3

2

1

0

–1

–2

–3

–4

RF INPU T AMPL ITUDE (dBm)

1520-003

4

3

2

1

0

ERROR (dB)

–1

–2

–3

–4

01520-004

ERROR (dB)

01520-005

4

3

2

0.1GHz

1.9GHz

1

0

OR (dB)

E

–1

–2

–3

–4

0.2

V

(V)

SET

Figure 6. Log Conformance vs. V

10

0

(+3dBm)

RF INPUT

(–47dBm)

–10

–20

–30

–40

AMPLITUDE ( dBV)

–50

+25°C

–60

+85°C

–70

0.1

0.30.50.70.91.11.31.5

+85°C

–30°C

+25°C

ERROR AT +85°C AND –30° C
BASED ON DEVIATI ON FROM
SLOPE AND INTERCEPT AT +25°C

–30°C

(V)

V

SET

Figure 7. Input Amplitude and Log Conformance vs. V

10

0

(+3dBm)

–10

–30°C

+85°C

ERROR AT +85°C AND –30°C
BASED ON DEVIATION F ROM
SLOPE AND INTERCEPT AT +25°C

(V)

V

SET

RF INPUT

(–47dBm)

–20

–30

–40

AMPLITUDE (dBV)

–50

–60

–70

+25°C

+25°C

–30°C

+85°C

0.1

0.3 0.5 0.7 0.9 1.1 1.3 1.5

2.5GHz

SET

0.9GHz

at 1.9 GHz

SET

1.60.4 0.6 0.8 1.0 1.2 1.4

01520-006

4

3

2

1

0

–1

–2

–3

–4

4

3

2

1

0

ERROR (dB)

–1

–2

–3

–4

ERROR (dB)

01520-007

01520-008

Figure 5. Input Amplitude and Log Conformance vs. V

at 0.9 GHz

SET

Figure 8. Input Amplitude and Log Conformance vs. V

at 2.5 GHz

SET

Rev. C | Page 7 of 24

AD8315

(

m

4

3

2

1

0

ERROR (dB)

–1

–2

–3

–4

–80 –50 –40 –30 –20 –10

+85°C

ERROR AT +85°C AND –30° C
BASED ON DEVIATION FROM
SLOPE AND INT ERCEPT AT +25°C

–60

RF INPUT AMPL ITUDE (dBV)

Figure 9. Distribution of Error at Temperature After Ambient Normalization vs.

–30°C

0–70

(+3dBm)(–47dBm)

01520-009

Figure 12. Distribution of Error at Temperature After Ambient Normalization vs.

Input Amplitude, 3 Sigma to Either Side of Mean, 0.1 GHz

4

3

2

1

0

ERROR (dB)

–1

–2

ERROR AT +85°C AND –30°C

–3

BASED ON DEVIAT ION FROM
SLOPE AND INTERCEPT AT +25°C

–4

–80 –50 –40 –30 –20 –10

–70

RF INPUT AMPL ITUDE (dBV)

Figure 10. Distribution of Error at Temperature After Ambient Normalization vs.

+85°C

–30°C

0–60

(+3dBm)(–47dBm)

01520-010

Figure 13. Distribution of Error at Temperature After Ambient Normalization vs.

Input Amplitude, 3 Sigma to Either Side of Mean, 0.9 GHz

3000

2700

2400

2100

1800

X (LFCSP)

1500

1200

RESISTANCE (Ω)

900

600

300

0

02

FREQUENCY
(GHz )

0.1

0.9

1.9

2.5

X (MSOP)

R (LFCSP)

R (MSOP)

0.5 1.0 1.5 2. 0
FREQUENCY (GHz)

MSOP

R –

2900 –

700 –
130 –
170 –

jXΩ
j1900
j240
j80
j70

CHIP SCAL E (L FCSP)

R –

2700 –

730 –
460 –
440 –

R

0

–200

–400

jXΩ

–600

j1500
j220

–800

j130
j110

–1000

–1200

X

REACTANCE (Ω)

–1400

–1600

–1800

–2000

.5

1520-011

4

3

2

1

0

ERROR (dB)

–1

–2

–3

–4

–80 –50 –40 –30 –20 –10

Input Amplitude, 3 Sigma to Either Side of Mean, 1.9 GHz

4

3

2

1

0

ERROR (dB)

–1

–2

–3

–4

–80 –50 –40 –30 –20 –10

Input Amplitude, 3 Sigma to Either Side of Mean, 2.5 GHz

10

8

A)

6

4

SUPPLY CURRENT

2

0

1.3

Figure 11. Input Impedance

–30°C

ERROR AT +85°C AND –30°C
BASED ON DEVIAT ION FROM
SLOPE AND I NTERCEPT AT +25°C

–70

ERROR AT +85°C AND –30°C
BASED ON DEVIAT ION FROM
SLOPE AND INTERCEPT AT +25°C

–70

RF INPUT AMPLITUDE (d BV)

–30°C

RF INPUT AMPLITUDE (d BV)

DECREASING

V

ENBL

1.4 1.5 1.6 1.7

V

ENBL

(V)

Figure 14. Supply Current vs. V

+85°C

+85°C

INCREASING
V

ENBL

ENBL

0–60

(+3dBm)(–47dBm)

(+3dBm)(–47dBm)

01520-012

0–60

01520-013

01520-014

Rev. C | Page 8 of 24

AD8315

–

√

25

24

23

22

SLOPE (mV/dB)

21

20

0

0.5 1.0 1. 5 2. 0 2.5

–30°C

FREQUENCY (GHz)

+85°C

+25°C

Figure 15. Slope vs. Frequency; −30°C, +25°C, and +85°C

24

23

SLOPE (mV/dB)

22

0.1GHz

0.9GHz

1.9GHz

01520-015

–66

–68

–70

–72

+25°C

–74

INTERCEPT (d BV)

–76

–78

–80

0

+85°C

–30°C

0.5 1.0 1.5 2.0 2.5

FREQUENCY (GHz)

Figure 18. Intercept vs. Frequency; −30°C, +25°C, and +85°C

68

–70

–72

–74

INTERCEPT ( dBV)

–76

0.1GHz

0.9GHz

1.9GHz

01520-018

–10

AMPLITUDE (dB)

–15

–20

–25

–30

–35

–40

2.5GHz

21

2.5

3.0 3.5 4.0 4.5 5. 0 5.5

V

(V)

S

01520-016

Figure 16. Slope vs. Supply Voltage

–78

–80

2.5

3.0 3.5 4.0 4.5 5.0 5.5

Figure 19. Intercept vs. Supply Voltage

45
40
35
30
25
20
15
10

5
0

–5

= 220pF

C

FLT

100 1k 10k 100k 1M 10M

10

FREQUENCY (Hz)

C

= 0pF

FLT

0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130

PHASE (Degrees)

01520-017

Figure 17. AC Response from VSET to VAPC

10000

Hz)

1000

100

NOISE SPECTRAL DENSITY (nV/

–23dBV

10

100

1k 10k 100k 1M 10M

Figure 20. VAPC

2.5GHz

VS (V)

= 220pF, RF INPUT = 2GHz

C

FLT

RF INPUT

–51dBV

–48dBV

–33dBV

–43dBV

–13dBV

–53dBV AND

–63dBV

FREQUENCY (Hz )

Noise Spectral Density

1520-019

01520-020

Rev. C | Page 9 of 24

AD8315

3.5

2.8

3.3

3.1

(V)

2.9

APC

V

2.7

2.5

2.3

2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5

2.7

Figure 21. Maximum V

GND

GND

RF OUT

220pF

10MHz REF
OUTPUT

1

RFIN

2

ENBL

3

VSET

4

NC = NO CONNECT

R AND S

SMT03

SIGNAL

GENERATOR

52.3Ω

Figure 23. Test Setup for ENBL Response Time

0mA

6mA

SUPPLY VOLTAGE (V)

Voltage vs. Supply Voltage by Load Current

APC

AVERAGE = 16 SAMPLES

200mV PER VERTICAL

DIVISION

V

APC

1V PER

VERTICAL

DIVISION

Figure 22. ENBL Response Time

TIMEBASE

STANFORD DS345

0.1µF

AD8315

8

VPOS

7

6

5

TEK P6205

FET PROBE

VAPC

NC

COMMFLTR

2mA

4mA

2µs PER
HORIZONTAL
DIVISION

V

ENBL

PULSE

GENERATOR

PULSE OUT

2.7V

TEK P6205

FET PROBE

TRIG
OUT

TEK TDS694C

SCOPE

TRIG

2.7

(V)

2.6

APC

V

2.5

SHADING INDICATES

±3 SIGMA

2.4

1520-021

2.7

Figure 24. Maximum V

2.8 3.0
SUPPLY VOLTAGE (V)

Voltage vs. Supply Voltage with 4 mA Load Current

APC

2.9

01520-024

V

APC

GND

RF

INPUT

GND

1520-022

Figure 25. V

Response Time, Full-Scale Amplitude Change, Open-Loop

APC

AVERAGE = 16 SAMPLES

1V PER

VERTICAL

DIVISION

PULSED RF

0.1GHz, –13dBV

100ns PER
HORIZONTAL
DIVISIO N

1520-025

R AND S SMT 03

SIGNAL

GENERATOR

PULSE

MODULATION

MODE

SPLITTER

–3dB

52.3Ω

01520-023

10MHz REF
OUTPUT

PULSE MODE IN OUT

RF OUT

RF

–3dB

1

RFIN

2

2.7V

0.3V

ENBL

3

VSET

4

NC

NC = NO CONNECT

AD8315

VPOS

VAP C

COMMFLTR

NC

EXT TRIG

8

7

6

5

PICOSECOND

PULSE LABS

GENERATOR

0.1µF

TEK P6205

FET PROBE

PULSE

2.7V

PULSE OUT

TEK TDS694C

SCOPE

TRIG
OUT

TRIG

1520-026

Figure 26. Test Setup for VAPC Response Time

Rev. C | Page 10 of 24

AD8315

GND

AVERAGE = 16 SAMPLES

V

200mV PER

V

APC

VERTI CAL

DIVISION

APC

GND

500mV PER

VERTICAL

DIVISION

2µs PER
HORIZONTAL
DIVISIO N

01520-027

GND

V

V

AND

ENBL

1V PER

S

VERTICAL

DIVISION

Figure 27. Power-On and Power-Off Response with VSET Grounded

R AND S

SMT03

SIGNAL

GENERATOR

RF OUT

52.3Ω

220pF

10MHz REF
OUTPUT

AD8315

1

2

3

4

NC = NO CONNECT

RFIN

ENBL

VSET

VPOS

VAP C

NC

COMMFLTR

8

7

6

5

EXT TRIG

TEK P6205

FET PROBE

TEK P6205

FET PROBE

STANFORD DS345

PULSE

GENERATOR

AD811

732Ω

PULSE OUT

49.9Ω

TRIG

TEK TDS694C

SCOPE

TRIG
OUT

Figure 28. Test Setup for Power-On and Power-Off Response with VSET Grounded

GND

1V PER

VERTICAL

DIVISIO N

V

S

AVERAGE = 16 SAMPLES

2µs PER
HORIZONT AL
DIVISION

1520-029

Figure 29. Power-On and Power-Off Response with VSET and ENBL Grounded

49.9Ω

TRIG

TEK TDS694C

SCOPE

TRIG
OUT

01520-030

R AND S

SMT03

SIGNAL

GENERATOR

52.3Ω

220pF

01520-028

10MHz REF
OUTPUT

RF OUT

1

RFIN

2

ENBL

3

4

NC = NO CONNECT

AD8315

VSET

VPOS

VAP C

COMMFLTR

NC

8

7

6

5

EXT TRIG

TEK P6205

FET PROBE

TEK P6205

FET PROBE

STANFORD DS345

PULSE

GENERATOR

AD811

732Ω

PULSE OUT

Figure 30. Test Setup for Power-On and Power-Off Response with VSET

and ENBL Grounded

Rev. C | Page 11 of 24

AD8315

A

THEORY OF OPERATION

The AD8315 is a wideband logarithmic amplifier (log amp)
similar in design to the

AD8313 and AD8314. However, it is

strictly optimized for use in power control applications rather
than as a measurement device.

Figure 31 shows the main
features in block schematic form. The output (Pin 7, VAPC) is
intended to be applied directly to the automatic power-control
(APC) pin of a power amplifier module.

BASIC THEORY

Logarithmic amplifiers provide a type of compression in which
a signal having a large range of amplitudes is converted to one
of smaller range. The use of the logarithmic function uniquely
results in the output representing the decibel value of the input.
The fundamental mathematical form is:

V

VV

SLP

OUT

Here

V

is the input voltage, VZ is called the intercept (voltage)

IN

because when V

IN

and thus the result is zero, and V
which is the amount by which the output changes for a certain
change in the ratio (V
used, denoted by the function log
decade, and since a decade corresponds to 20 dB,
represents the volts/dB. For the AD8315, a nominal (low
frequency) slope of 24 mV/dB was chosen, and the intercept
was placed at the equivalent of −70 dBV for a sine wave input
(316 µV rms). This corresponds to a power level of −57 dBm

IN

log= (1)

10

V

Z

= VZ the argument of the logarithm is unity

is called the slope (voltage),

SLP

). When BASE-10 logarithms are

IN/VZ

, V

represents the volts/

10

SLP

V

/20

SLP

V

(PRECISE SLOPE

CONTROL)

LOW NOISE

BAND GAP

REFERENCE

DET DET DET

10dB 10dB

Figure 31. Block Schematic

RFIN

COMM

(PADDLE)

VPOS

ENBL

DET

10dB

(WEAK GM STAGE)

(PRECISE GAI N

CONTRO L)

LOW NOISE

GAIN BIAS

DET

10dB

OFFSET
COMP’N

Z

INTERCEPT

POSITIONING

when the net resistive part of the input impedance of the log
amp is 50 Ω. However, both the slope and the intercept are
dependent on frequency (see

Figure 15 and Figure 18).

Keeping in mind that log amps do not respond to power but
only to voltages and that the calibration of the intercept is
waveform dependent and is only quoted for a sine wave signal,
the equivalent power response can be written as

V

= VDB (PIN − PZ) (2)

OUT

where:

P

, the input power, and PZ, the equivalent intercept, are both

IN

expressed in dBm (thus, the quantity in parentheses is simply a
number of decibels).

V

is the slope expressed as so many mV/dB.

DB

For a log amp having a slope V

of 24 mV/dB and an intercept

DB

at −57 dBm, the output voltage for an input power of –30 dBm
is 0.024 [−30 − (−57)] = 0.648 V.

Further details about the structure and function of log amps can
be found in data sheets for other log amps produced by Analog
Devices, Inc. Refer to the

AD640 data sheet and AD8307 data

sheet, both of which include a detailed discussion of the basic
principles of operation and explain why the intercept depends
on waveform, an important consideration when complex
modulation is imposed on an RF carrier.

TES

(ELIMIN

GLITCH)

OUTPUT
ENABLE

DELAY

(CURRENT-MODE SIGNAL)

LOW NOISE (25nV/√Hz)
RAIL-TO-RAI L BUFFER

(CURRENT-

NULLING

MODE)

(CURRENT-MODE

FEEDBACK)

(SMALL INTERNAL
FILTER CAPACITOR
FOR GHz RIPPLE)

HI-Z

×1.35

V-I

VAP C

FLTR

VSET

23mV/dB
250mV TO

1.4V = 50dB

1520-031

Rev. C | Page 12 of 24

AD8315

V

The intercept need not correspond to a physically realizable
part of the signal range for the log amp. Therefore, the specified
intercept is −70 dBV, at 0.1 GHz, whereas the smallest input for
accurate measurement (a +1 dB error, see

Tabl e 2) at this
frequency is higher, being about −58 dBV. At 2.5 GHz, the
+1 dB error point shifts to −64 dBV. This positioning of the
intercept is deliberate and ensures that the V

voltage is within

SET

the capabilities of certain DACs, whose outputs cannot swing
below 200 mV.

Figure 32 shows the 100 MHz response of the
AD8315; the vertical axis does not represent the output (at pin
VAPC) but the value required at the power control pin, VSET,
to null the control loop.

1.5

1.0

SET

V

0.5

0.288V @ –58dBV

0

100µV
–80dBV
–67dBm

–70dBV

1mV

–60dBV

–47dBm

IDEAL

V

Figure 32. Basic Calibration of the AD8315 at 0.1 GHz

E

P

O

L

S

10mV
–40dBV
–27dBm

, dBVIN, P

IN

1.416V @ –11dBV

B

d

/

V

m

4

2

=

ACTUAL

100mV

–20dBV

–7dBm

IN

1V (RMS)

0dBV

+13dBm (RE 50Ω)

01520-032

CONTROLLER-MODE LOG AMPS

The AD8315 combines the two key functions required for the
measurement and control of the power level over a moderately
wide dynamic range. First, it provides the amplification needed
to respond to small signals in a chain of four amplifier/limiter
cells (see
and a bandwidth of approximately 3.5 GHz. At the output of
each of these amplifier stages is a full-wave rectifier, essentially a
square law detector cell that converts the RF signal voltages to a
fluctuating current having an average value that increases with
signal level. A further passive detector stage is added before the
first stage. These five detectors are separated by 10 dB, spanning
some 50 dB of dynamic range. Their outputs are each in the
form of a differential current, making summation a simple
matter. It is readily shown that the summed output can closely
approximate a logarithmic function. The overall accuracy at the
extremes of this total range, viewed as the deviation from an
ideal logarithmic response, that is, the log conformance error,
can be judged by referring to
across the central 40 dB are moderate. Other performance
curves show how conformance to an ideal logarithmic function
varies with supply voltage, temperature, and frequency.

Figure 31), each having a small signal gain of 10 dB

Figure 6, which shows that errors

In a device intended for measurement applications, this current
would then be converted to an equivalent voltage, to provide the
log (V

) function shown in Equation 1. However, the design of

IN

the AD8315 differs from standard practice in that its output
needs to be a low noise control voltage for an RF power amplifier
not a direct measure of the input level. Furthermore, it is highly
desirable that this voltage be proportional to the time integral of
the error between the actual input V

and the dc voltage V

IN

SET

(applied to Pin 3, VSET) that defines the setpoint, that is, a
target value for the power level, typically generated by a DAC.

This is achieved by converting the difference between the sum
of the detector outputs (still in current form) and an internally
generated current proportional to V

to a single-sided,

SET

current-mode signal. This, in turn, is converted to a voltage (at
Pin 4, FLTR, the low-pass filter capacitor node) to provide a
close approximation to an exact integration of the error between
the power present in the termination at the input of the AD8315
and the setpoint voltage. Finally, the voltage developed across
the ground-referenced filter capacitor C

is buffered by a

FLT

special low noise amplifier of low voltage gain (×1.35) and
presented at Pin 7 (VAPC) for use as the control voltage for the
RF power amplifier. This buffer can provide rail-to-rail swings
and can drive a substantial load current, including large
capacitors. Note that the RF power amplifier is assumed to have
a positive slope with RF power increasing monotonically with
an increasing APC control voltage.

CONTROL LOOP DYNAMICS

To understand how the AD8315 behaves in a complete control
loop, an expression for the current in the integration capacitor
as a function of the input V
be developed (see

SET

3

V

SET

RFIN

1

V

IN

Figure 33).

SETPOINT

INTERFACE

LOGARIT HMIC

RF DETE CTIO N

SUBSYSTEM

I

= I

log10 (VIN/VZ)

DET

SLP

Figure 33. Behavioral Model of the AD8315

and the setpoint voltage V

IN

I

= V

SET

/4.15kΩ

SET

FLTR

×1.35

I

ERR

4

C

FLT

I

DET

VAPC

7

SET

must

01520-033

Rev. C | Page 13 of 24

AD8315

(

)

(

)

−

(

()(

)

()()(

)

=∞=

First, the summed detector currents are written as a function of
the input

I

= I

DET

log10 (VIN/VZ) (3)

SLP

where:

I

is the partially filtered demodulated signal, whose

DET

exact average value is extracted through the subsequent
integration step.

I

is the current-mode slope and has a value of 115 µA per

SLP

decade (that is, 5.75 µA/dB).

V

is the input in V rms.

IN

V

is the effective intercept voltage, which, as previously noted,

Z

is dependent on waveform but is 316 µV rms (−70 dBV) for a
sine wave input.

Now the current generated by the setpoint interface is simply

I

= V

SET(4)

The difference between this current and I
loop filter capacitor C
on this capacitor, V

/415 kΩ (4)

SET

is applied to the

DET

. It follows that the voltage appearing

FLT

, is the time integral of the difference

FLT

current:

V

(s) = (I

FLT

SET

=

The control output V

SET

− I

)/sC

DET

sC

APC

(5)

FLT

SLP

FLT

logk4.15 −

VVIV

10

IN

Z

(6)

is slightly greater than this, because the
gain of the output buffer is ×1.35. In addition, an offset voltage
is deliberately introduced in this stage; this is inconsequential
because the integration function implicitly allows for an
arbitrary constant to be added to the form of Equation 6. The
polarity is such that V
value of V
practice, the V

greater than the equivalent value of VIN. In

SET

APC

rises to its maximum value for any

APC

output rails to the positive supply under this
condition unless the control loop through the power amplifier
is present. In other words, the AD8315 seeks to drive the RF
power to its maximum value whenever it falls below the
setpoint. The use of exact integration results in a final error that
is theoretically 0, and the logarithmic detection law would
ideally result in a constant response time following a step
change of either the setpoint or the power level, if the power­amplifier control function were likewise linear in dB. However,
this latter condition is rarely true, and it follows that in practice,
the loop response time depends on the power level, and this
effect can strongly influence the design of the control loop.

Equation 6 can be restated as

log

SLP

SET

()

sV

=

where

APC

V

is the volts-per-decade slope from Equation 1,

SLP

sT

having a value of 480 mV/decade, and
constant for the integration, being equal to 4.15 kΩ × C

VVVV

10

IN

Z

(7)

T is an effective time

/1.35;

FLT

the resistor value comes from the setpoint interface scaling
Equation 4 and the factor 1.35 arises because of the voltage gain
of the buffer. Therefore, the integration time constant can be
written as

T = 3.07 C

in µs, when C is expressed in nF (8)

FLT

To simplify our understanding of the control loop dynamics,
begin by assuming that the power amplifier gain function is
actually linear in dB, and for the moment, use voltages to
express the signals at the power amplifier input and output.
Let the RF output voltage be V

and let its input be VCW.

PA

Furthermore, to characterize the gain control function, this
form is used

)

VV

GBCAPC

VGV 10=

CWOPA

(9)

where:

G

is the gain of the power amplifier when V

O

V

is the gain scaling.

GBC

APC

= 0.

While few amplifiers conform so conveniently to this law, it
provides a clearer starting point for understanding the more
complex situation that arises when the gain control law is less ideal.

This idealized control loop is shown in

Figure 34. With some
manipulation, it is found that the characteristic equation of this
system is

APC

()

sV

SET

=

−

1

10

+

sT

O

VVkGVVVV

CWOGBCSLPGBC

Z

(10)

log

where:

k is the coupling factor from the output of the power amplifier

to the input of the AD8315 (for example, ×0.1 for a 20 dB coupler).

T

is a modified time constant (V

O

GBC/VSLP

)T.

This is quite easy to interpret. First, it shows that a system of
this sort exhibits a simple single-pole response, for any power
level, with the customary exponential time domain form for
either increasing or decreasing step polarities in the demand
level V
final value of the control voltage V

or the carrier input VCW. Second, it reveals that the

SET

is determined by several

APC

fixed factors:

APC

SET

logτ −

10

VVkGVVVV

Z

(11)

CWOSLPGBC

Rev. C | Page 14 of 24

AD8315

Example

Assume that the gain magnitude of the power amplifier runs
from a minimum value of ×0.316 (−10 dB) at V
(40 dB) at V

= 1 V. Using a coupling factor of k = 0.0316 (that is, a

V

GBC

= 2.5 V. Applying Equation 9, GO = 0.316 and

APC

= 0 to ×100

APC

30 dB directional coupler) and recalling that the nominal value

is 480 mV and VZ = 316 µV for the AD8315, first calculate

of V

SLP

the range of values needed for V

to control an output range of

SET

+33 dBm to −17 dBm. This can be found by noting that, in the
steady state, the numerator of Equation 7 must be 0, that is:

= V

V

SET

log10 (kVPA/VZ) (12)

SLP

DIRECTI ONAL COUPL ER

VIN= kV

RF

V

SET

RESPONSE-SHAPING

OF OVERALL CONTROL-

LOOP (EX TERNAL CAP)

Figure 34. Idealized Control Loop for Analysis

V

RF

AD8315

C

RF PA

V

FLT

V

CW

RF DRIVE: UP
TO 2.5GHz

APC

01520-034

where V
the power amplifier output. For 33 dBm, V

is expanded to kVPA, the fractional voltage sample of

IN

= 10 V rms, which

PA

evaluates to

(max) = 0.48 log10 (316 mV/316 µV) = 1.44 V (13)

V

SET

For a delivered power of −17 dBm, V

(min) = 0.48 log10 (1 mV/316 µV) = 0.24 V (14)

V

SET

= 31.6 mV rms

PA

Check that the power range is 50 dB, which should correspond
to a voltage change in V

of 50 dB × 24 mV/dB = 1.2 V,

SET

which agrees.

Now, the value of V

is of interest, although it is a dependent

APC

parameter, inside the loop. It depends on the characteristics of
the power amplifier, and the value of the carrier amplitude V
Using the control values previously derived, that is, G
and V

−7 dBm (so V

= 1 V, and assuming the applied power is fixed at

GBC

= 100 mV rms), the following is true using

CW

= 0.316

O

CW

Equation 11

(max) = (V

V

APC

SETVGBC

)/V

− log10 kGOVCW/V

SLP

Z

= (1.44 × 1)/0.48 − log10(0.0316 × 0.316 × 0.1/316 µV)

= 3.0 − 0.5 = 2.5 V (15)

(min) = (V

V

APC

SETVGBC

)/V

− log10 kGOVCW/V

SLP

Z

= (0.24 × 1)/0.48 − log10(0.0316 × 0.316 × 0.1/316 µV)

= 0.5 − 0.5 = 0 (16)

both of which results are consistent with the assumptions made
about the amplifier control function. Note that the second term
is independent of the delivered power and a fixed function of
the drive power.

Finally, using the loop time constant for these parameters and
an illustrative value of 2 nF for the filter capacitor C

TO = (V

GBC/VSLP

) T

FLT

= (1/0.48)3.07 µs × 2 (nF) = 12.8 µs (17)

PRACTICAL LOOP

At present time, power amplifiers, or VGAs preceding such
amplifiers, do not provide an exponential gain characteristic. It
follows that the loop dynamics (the effective time constant)
varies with the setpoint because the exponential function is
unique in providing constant dynamics. The procedure must
therefore be as follows. Beginning with the curve usually provided
for the power output vs. the APC voltage, draw a tangent at the

at V

1

Figure 35).

.

APC

= V1 and

APC

.

point on this curve where the slope is highest (see
Using this line, calculate the effective minimum value of the
variable V
constant. Note that the minimum in V

and use it in Equation 17 to determine the time

GBC

corresponds to the

GBC

maximum rate of change in the output power vs. V

For example, suppose it is found that, for a given drive power,
the amplifier generates an output power of P

at V

P

2

= V2. Then, it is readily shown that

APC

= 20 (V2 − V1)/(P2 − P1) (18)

V

GBC

This should be used to calculate the filter capacitance. The
response time at high and low power levels (on the shoulders
of the curve shown in

Figure 35) is slower. Note also that it is
sometimes useful to add a 0 in the closed-loop response by
placing a resistor in series with C
this, see the

Transient Response section.

. For more information on

FLT

Rev. C | Page 15 of 24

AD8315

V

33

23

13

(dBm)

RF

P

3

–7

0

0.5 1 .0 1.5 2.0 2.5

V1, P

1

V

APC

(V)

, P

2

2

01520-035

Figure 35. Typical Power-Control Curve

A NOTE ABOUT POWER EQUIVALENCY

In using the AD8315, it must be understood that log amps do
not fundamentally respond to power. It is for this reason that
dBV (decibels above 1 V rms) are used rather than the commonly
used metric of dBm. The dBV scaling is fixed, independent of
termination impedance, while the corresponding power level is
not. For example, 224 mV rms is always −13 dBV (with one
further condition of an assumed sinusoidal waveform; see the

AD640 data sheet for more information about the effect of

waveform on logarithmic intercept), and this corresponds to a
power of 0 dBm when the net impedance at the input is 50 Ω.
When this impedance is altered to 200 Ω, however, the same
voltage corresponds to a power level that is four times smaller

2

/R) or −6 dBm. A dBV level can be converted to dBm in

(P = V
the special case of a 50 Ω system and a sinusoidal signal by
simply adding 13 dB (0 dBV is then, and only then, equivalent
to 13 dBm).

Therefore, the external termination added ahead of the AD8315
determines the effective power scaling. This often takes the
form of a simple resistor (52.3 Ω provides a net 50 Ω input), but
more elaborate matching networks can be used. The choice of
impedance determines the logarithmic intercept, that is, the
input power for which the V
baseline if that relationship were continuous for all values of

. This is never the case for a practical log amp; the intercept

V

IN

(so many dBV) refers to the value obtained by the minimum
error straight line fit to the actual graph of V
generally, V

). Where the modulation is complex, as in CDMA,

IN

the calibration of the power response needs to be adjusted; the
intercept remains stable for any given arbitrary waveform.
When a true power (waveform independent) response is
needed, a mean-responding detector, such as the
should be considered.

vs. PIN function would cross the

SET

vs. PIN (more

SET

AD8361,

The logarithmic slope, V

in Equation 1, which is the amount

SLP

by which the setpoint voltage needs to be changed for each
decibel of input change (voltage or power), is, in principle,
independent of waveform or termination impedance. In
practice, it usually falls off somewhat at higher frequencies,
due to the declining gain of the amplifier stages and other
effects in the detector cells (see

Figure 15).

BASIC CONNECTIONS

Figure 36 shows the basic connections for operating the
AD8315, and
application. The AD8315 is typically used in the RF power
control loop of a mobile handset.

A supply voltage of 2.7 V to 5.5 V is required for the AD8315.
The supply to the VPOS pin should be decoupled with a low
inductance 0.1 µF surface-mount ceramic capacitor, close to the
device. The AD8315 has an internal input coupling capacitor.
This negates the need for external ac coupling. This capacitor,
along with the low frequency input impedance of the device of
approximately 2.8 kΩ, sets the minimum usable input frequency to
around 0.016 GHz. A broadband 50 Ω input match is achieved
in this example by connecting a 52.3 Ω resistor between RFIN
and ground. A plot of input impedance vs. frequency is shown

Figure 11. Other coupling methods are also possible (see

in
Input Coupling Options section).

DIRECTIONAL

ATTENUATOR

Figure 37 shows a block diagram of a typical

RFIN

+V

S

V

SET

COUPLER

C

FLT

52.3Ω

R1

52.3Ω

AD8315

1

RFIN

2

ENBL

3

VSET

COMMFLTR

NC = NO CO NNECT

Figure 36. Basic Connections

AD8315

RFIN

Figure 37. Typical Application

VPOS

VAPC

NC

POWER

VAPC

FLTR

0.1µF

8

7

6

54

AMP

GAIN
CONTROL
VOLTAGE

VSET

C

FLT

C1

+V

S

(2.7V TO 5 .5V)

+V

APC

DAC

RFIN

01520-036

01520-037

Rev. C | Page 16 of 24

AD8315

In a power control loop, the AD8315 provides both the detector
and controller functions. A sample of the power amplifier’s (PA)
output power is coupled to the RF input of the AD8315, usually
via a directional coupler. In dual-mode applications, where
there are two PAs and two directional couplers, the outputs of
the directional couplers can be passively combined (both PAs
will never be turned on simultaneously) before being applied to
the AD8315.

A setpoint voltage is applied to VSET from the controlling
source (generally, this is a DAC). Any imbalance between the
RF input level and the level corresponding to the setpoint
voltage is corrected by the AD8315’s VAPC output that drives
the gain control terminal of the PA. This restores a balance
between the actual power level sensed at the input of the
AD8315 and the value determined by the setpoint. This
assumes that the gain control sense of the variable gain
element is positive, that is, an increasing voltage from
VAPC tends to increase gain.

V

can swing from 250 mV to within 100 mV of the supply

APC

rail and can source up to 6 mA. If the control input of the PA
needs to source current, a suitable load resistor can be connected
between VAPC and COMM. The output swing and current
sourcing capability of VAPC is shown in

Figure 21.

RANGE ON VSET AND RFIN

The relationship between the RF input level and the setpoint
voltage follows from the nominal transfer function of the device

Figure 4, Figure 5, Figure 7, and Figure 8). At 0.9 GHz, for

(see
example, a voltage of 1 V on VSET indicates a demand for

−30 dBV (−17 dBm, re 50 Ω) at RFIN. The corresponding power
level at the output of the power amplifier is greater than this
amount due to the attenuation through the directional coupler.

For setpoint voltages of less than approximately 250 mV, V
remains unconditionally at its minimum level of approximately
250 mV. This feature can be used to prevent any spurious
emissions during power-up and power-down phases.

APC

Above 250 mV, V
corresponding to a dynamic range of 50 dB. This results in a
slope of 23 mV/dB or approximately 43.5 dB/V.

TRANSIENT RESPONSE

The time domain response of power amplifier control loops,
using any kind of controller, is only partially determined by the
choice of filter, which, in the case of the AD8315, has a true
integrator form 1/sT, as shown in Equation 7, with a time
constant given by Equation 8. The large signal step response is
also strongly dependent on the form of the gain-control law.
Nevertheless, some simple rules can be applied. When the filter
capacitor C
response, but the incremental bandwidth of this loop still varies
as V
as shown in
where the slope of the tangent drawn on this curve is greatest,
that is, for power outputs near the center of the PA’s range, and
is much reduced at both the minimum and the maximum
power levels, where the slope of the gain control curve is lowest
due to its S-shaped form.

Using smaller values of C
increases in inverse proportion to its value. Eventually, however,
a secondary effect appears due to the inherent phase lag in the
power amplifier’s control path, some of which can be due to
parasitic or deliberately added capacitance at the VAPC pin.
This results in the characteristic poles in the ac loop equation
moving off the real axis and thus becoming complex (and
somewhat resonant). This is a classic aspect of control loop
design. The lowest permissible value of C
experimentally for a particular amplifier. For GSM and DCS
power amplifiers, C

In many cases, some improvement in the worst-case response
time can be achieved by including a small resistance in series
with C
transfer function, that serves to cancel some of the higher order
poles in the overall loop. A combination of main capacitor C
shunted by a second capacitor and resistor in series is also
useful in minimizing the settling time of the loop.

FLT

traverses the nonlinear gain-control function of the PA,

APC

; this generates an additional 0 in the closed-loop

FLT

has a linear control range up to 1.4 V,

SET

is very large, it dominates the time domain

Figure 35. This bandwidth is highest at the point

, the loop bandwidth generally

FLT

needs to be determined

FLT

typically ranges from 150 pF to 300 pF.

FLT

FLT

Rev. C | Page 17 of 24

AD8315

V

1000pF

TO

ANTENNA

8-BIT

RAMP DAC

0V TO 2.5 5V

LDC15D190A0007A

7

8

5

AT T N

20dB

1

R2

600Ω

R3
1kΩ

1

R2, R3 OPTIO NAL,

SEE TEXT

2

ENABLE

0V/2.7V

1

6

52.3Ω

150pF

1.5kΩ

1

4

3

R1

P

OUT

35dBm MAX

49.9Ω

P

OUT

32dBm MAX

AD8315

1

RFIN

2

ENBL

3

VSET

4

NC = NO CONNECT

COMMFLTR

Figure 38. Dual-Mode (GSM/DCS) PA Control Example

3.5

4.7µF 4.7µF

1000pF

BAND

SELECT

0V/2V

GSM

VCTL

PF08107B

VAPC

DCS

0.1µF

+V

VPOS

VAP C

NC

8

7

6

5

2.7V

S

500Ω

(OPTIO NAL,

SEE TEXT)

P

IN

3dBm

P

IN

3dBm

GSM

DCS

01520-038

MOBILE HANDSET POWER CONTROL EXAMPLE

Figure 38 shows a complete power amplifier control circuit for a
dual-mode handset. The PF08107B (Hitachi), a dual mode
(GSM, DCS) PA, is driven by a nominal power level of 3 dBm.
The PA has a single gain control line; the band to be used is
selected by applying either 0 V or 2 V to the PA’s VCTL input.

Some of the output power from the PA is coupled off using a
dual-band directional coupler (Murata LDC15D190A0007A).
This has a coupling factor of approximately 19 dB for the GSM
band and 14 dB for DCS and an insertion loss of 0.38 dB and

0.45 dB, respectively. Because the PF08107B transmits a maximum
power level of 35 dBm for GSM and 32 dBm for DCS, additional
attenuation of 20 dB is required before the coupled signal is
applied to the AD8315. This results in peak input levels to the
AD8315 of −4 dBm (GSM) and −2 dBm (DCS). While the
AD8315 gives a linear response for input levels up to 2 dBm,
for highly temperature-stable performance at maximum PA
output power, the maximum input level should be limited to
approximately −2 dBm (see
however, reduce the sensitivity of the circuit at the low end.

Figure 5 and Figure 7). This does,

The operational setpoint voltage, in the range 250 mV to 1.4 V,
is applied to the VSET pin of the AD8315. This is typically
supplied by a DAC. The AD8315’s VAPC output drives the
level control pin of the power amplifier directly. V

reaches a

APC

maximum value of approximately 2.5 V on a 2.7 V supply while
delivering the 3 mA required by the level control input of the
PA. This is more than sufficient to exercise the gain control
range of the PA.

During initialization and completion of the transmit sequence,
V

should be held at its minimum level of 250 mV by keeping

APC

below 200 mV.

V

SET

In this example, V

is supplied by an 8-bit DAC that has an

SET

output range from 0 V to 2.55 V or 10 mV per bit. This sets the
control resolution of VSET to 0.4 dB/bit (0.04 dB/mV times
10 mV). If finer resolution is required, the DAC’s output voltage
can be scaled using two resistors, as shown in

Figure 38. This
converts the DAC’s maximum voltage of 2.55 V down to 1.6 V
and increases the control resolution to 0.25 dB/bit.

A filter capacitor (C
choice of C

depends to a large degree on the gain control

FLT

) must be used to stabilize the loop. The

FLT

dynamics of the power amplifier, something that is frequently
poorly characterized, so some trial and error can be necessary.

In this example, a 150 pF capacitor is used and a 1.5 kΩ series
resistor is included. This adds a zero to the control loop and

Rev. C | Page 18 of 24

AD8315

increases the phase margin, which helps to make the step response
of the circuit more stable when the PA output power is low and
the slope of the PA’s power control function is the steepest.

In both situations, the voltage on VSET should be kept below
200 mV during power-on and power-off to prevent any
unwanted transients on VAPC.

A smaller filter capacitor can be used by inserting a series
resistor between VAPC and the control input of the PA. A
series resistor works with the input impedance of the PA to
create a resistor divider and reduces the loop gain. The size of
the resistor divider ratio depends upon the available output
swing of V

and the required control voltage on the PA.

APC

This technique can also be used to limit the control voltage in
situations where the PA cannot deliver the power level being
demanded by VAPC. Overdrive of the control input of some
PAs causes increased distortion. It should be noted, however,
that if the control loop opens (that is, V

goes to its maximum

APC

value in an effort to balance the loop), the quiescent current of
the AD8315 increases somewhat, particularly at supply voltages
greater than 3 V.

Figure 39 shows the relationship between V
power (P

) at 0.9 GHz . The overall gain control function is

OUT

and output

SET

linear in dB for a dynamic range of over 40 dB. Note that for

voltages below 300 mV, the output power drops off steeply

V

SET

drops toward its minimum level of 250 mV.

as V

APC

40

30

20

10

0

(dBm)

OUT

P

–10

–20

–30

–30°C

+25°C

+85°C

+25°C

–30°C

+85°C

4

3

2

1

0

ERROR (dB)

–1

–2

–3

INPUT COUPLING OPTIONS

The internal 5 pF coupling capacitor of the AD8315, along with
the low frequency input impedance of 2.8 kΩ, give a high-pass
input corner frequency of approximately 16 MHz. This sets the
minimum operating frequency.
show three options for input coupling. A broadband resistive
match can be implemented by connecting a shunt resistor to
ground at RFIN (see

Figure 40). This 52.3 Ω resistor (other
values can also be used to select different overall input impedances)
combines with the input impedance of the AD8315 to give a
broadband input impedance of 50 Ω. While the input resistance
and capacitance (C

and RIN) of the AD8315 varies from device

IN

to device by approximately ±20%, and over frequency (see
Figure 11), the dominance of the external shunt resistor means
that the variation in the overall input impedance is close to the
tolerance of the external resistor. This method of matching is
most useful in wideband applications or in multiband systems
where there is more than one operating frequency.

A reactive match can also be implemented as shown in
Figure 41. This is not recommended at low frequencies as
device tolerances dramatically vary the quality of the match
because of the large input resistance. For low frequencies,
Figure 40 or Figure 42 is recommended.

In

Figure 41, the matching components are drawn as generic
reactances. Depending on the frequency, the input impedance
and the availability of standard value components, either a
capacitor or an inductor is used. As in the previous case, the
input impedance at a particular frequency is plotted on a Smith
Chart and matching components are chosen (shunt or series L,
shunt or series C) to move the impedance to the center of the chart.

Figure 40, Figure 41, and Figure 42

–40

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4

Figure 39. P

OUT

V

(V)

SET

vs. V

at 0.9 GHz for Dual-Mode Handset

SET

1.6

–4

01520-039

Power Amplifier Application, −30°C, +25°C, and +85°C

ENABLE AND POWER-ON

The AD8315 can be disabled by pulling the ENBL pin to
ground. This reduces the supply current from its nominal level
of 7.4 mA to 4 µA. The logic threshold for turning on the device
is at 1.5 V with 2.7 V supply voltage. A plot of the enable glitch
is shown in
disabled by pulling the supply voltage to ground. To minimize
glitch in this mode, ENBL and VPOS should be tied together. If
VPOS is applied before the device is enabled, a narrow 750 mV
glitch results (see

Figure 22. Alternatively, the device can be completely

Figure 29).

Rev. C | Page 19 of 24

AD8315

C

C

RFIN

R

SHUNT

52.3V

R

C

IN

IN

1520-040

Figure 40. Broadband Resistive Input Coupling Option

AD8315

C

RFIN

C

R

C

IN

IN

01520-041

X1

X2

Figure 41. Narrow-Band Reactive Input Coupling Option

AD8315

V

ANTENNA

AD8315

C

STRIPLINE

PA

R

RFIN

ATTN

C

R

C

IN

IN

1520-042

Figure 42. Series Attention Input Coupling Option

Figure 42 shows a third method for coupling the input
signal into the AD8315. A series resistor, connected to the RF
source, combines with the input impedance of the AD8315 to
resistively divide the input signal being applied to the input.
This has the advantage of very little power being tapped off in
RF power transmission applications.

USING THE CHIP SCALE PACKAGE

On the underside of the chip scale package, there is an exposed
paddle. This paddle is internally connected to the chip’s ground.
There is no thermal requirement to solder the paddle down to
the printed circuit board’s ground plane. However, soldering
down the paddle has been shown to increase the stability over
frequency of the AD8315 ACP’s response at low input power
levels (that is, at around −45 dBm) in the DCS and PCS bands.

EVALUATION BOARD

Figure 43 shows the schematic of the AD8315 MSOP evaluation
board. The layout and silkscreen of the component side are
shown in
available for the LFCSP package (see the
exact part numbers). Apart from the slightly smaller device
footprint, the LFCSP evaluation board is identical to the MSOP
board. The board is powered by a single supply in the 2.7 V to

5.5 V range. The power supply is decoupled by a single 0.1 µF
capacitor.

Tabl e 5 details the various configuration options of the
evaluation board.

RFIN

SET

Figure 44 and Figure 45. An evaluation board is also

Ordering Guide for

R2

52.3Ω

R1

J1

0Ω

V

POS

SW1

J2

C4

(OPEN)

LK1

0.1µF

AD8315

1

RFIN

2

ENBL

3

VSET

4

FLTR

NC = NO CONNECT

V

POS

C3

0.1µF

C5

R7

16.2kΩ

COMM

VPOS

VAPC

NC

0.1µF

8

7

6

5

R8
10kΩ

C1

TP2

R3
0Ω

(OPEN)

LK2

TP1

R4

V

POS

C2
(OPEN)

J2

VAPC

AD8031

R6

17.8kΩ

R5

10kΩ

Figure 43. Evaluation Board Schematic (MSOP)

Table 5. Evaluation Board Configuration Options

Component Function Default Condition

TP1, TP2 Supply and Ground Vector Pins. Not Applicable
SW1

Device Enable. When in Position A, the ENBL pin is connected to VPOS and the AD8315 is

SW1 = A

in operating mode. In Position B, the ENBL pin is grounded putting the device in power-down mode.

R1, R2

Input Interface. The 52.3 Ω resistor in Position R2 combines with the AD8315’s internal input
impedance to give a broadband input impedance of around 50 Ω. A reactive match can be

R2 = 52.3 Ω (Size 0603)
R1 = 0 Ω (Size 0402)

implemented by replacing R2 with an inductor and R1 (0 Ω) with a capacitor. Note that the
AD8315’s RF input is internally ac-coupled.

R3, R4, C2

Output Interface. R4 and C2 can be used to check the response of VAPC to capacitive and resistive
loading. R3/R4 can be used to reduce the slope of VAPC.

R4 = C2 = Open (Size 0603)

R3 = 0 Ω (Size 0603)
C1 Power Supply Decoupling. The nominal supply decoupling consists of a 0.1 μF capacitor. C1 = 0.1 μF (Size 0603)
C4

Filter Capacitor. The response time of VAPC can be modified by placing a capacitor between

C4 = Open (Size 0603)

FLTR (Pin 4) and ground.

LK1, LK2

Measurement Mode. A quasimeasurement mode can be implemented by installing LK1 and LK2

LK1, LK2 = Installed

(connecting an inverted VAPC to VSET) to yield the nominal relationship between RFIN and VSET.
In this mode, a large capacitor (0.01 μF or greater) must be installed in C4.

01520-043

Rev. C | Page 20 of 24

AD8315

For operation in controller mode, both jumpers, LK1 and LK2,
should be removed. The setpoint voltage is applied to VSET,
RFIN is connected to the RF source (PA output or directional
coupler), and VAPC is connected to the gain control pin of the
PA. When used in controller mode, a capacitor must be installed in
C4 for loop stability. For GSM/DCS handset power amplifiers,
this capacitor should typically range from 150 pF to 300 pF.

A quasimeasurement mode (where the AD8315 delivers an
output voltage that is proportional to the log of the input signal)
can be implemented, to establish the relationship between VSET
and RFIN, by installing the two jumpers, LK1 and LK2. This
mimics an AGC loop. To establish the transfer function of the

01520-044

Figure 44. Layout of Component Side (MSOP)

EVALUATION BOARD REV A

PWUP

GND

A

TP2

B

PWDN

LK1

J3

VSET

RFIN

J1

SW1

Figure 45. Silkscreen of Component Side (MSOP)

AD8315

VPOS

TP1

R3

C1

R2

Z1

R1
C4

R5

A1

R6

C5

R7

C3

08 - 006794 REV A
COMPONENT SIDE

VAPC

J2

C2

R4

R8

LK2

01520-045

log amp, the RF input should be swept while the voltage on
VSET is measured, that is, the SMA connector labeled VSET
now acts as an output. This is the simplest method to validate
operation of the evaluation board. When operated in this mode,
a large capacitor (0.01 µF or greater) must be installed in C4
(filter capacitor) to ensure loop stability.

Rev. C | Page 21 of 24

AD8315

OUTLINE DIMENSIONS

3.20

3.00

2.80

8

5

4

SEATING
PLANE

5.15

4.90

4.65

1.10 MAX

0.23

0.08

8°
0°

0.80

0.60

0.40

3.20

3.00

2.80

PIN 1

0.95

0.85

0.75

0.15

0.00

COPLANARITY

1

0.65 BSC

0.38

0.22

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 46. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

1.89

1.74

1.59

58

BOTTOM VIEW

EXPOSEDPAD

4 1

0.25

0.20

0.15

0.15

0.10

0.05

0.55

0.40

0.30

PIN 1

INDICATOR

1.00

0.85

0.80

SEATING

PLANE

3.25

3.00

1.95

1.75

1.55

12° MAX

2.75

TOP VIEW

2.95

2.75

2.55

0.30

0.23

0.18

0.80 MAX

0.65 TYP

2.25

2.00

1.75

0.20 REF

0.60

0.45

0.30

0.50 BSC

0.05 MAX

0.02 NOM

Figure 47. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]

2 mm × 3 mm Body, Very Thin, Dual Lead

(CP-8-1)

Dimensions shown in millimeters

Rev. C | Page 22 of 24

AD8315

ORDERING GUIDE

Model Temperature Range Package Description Package Option Ordering Quantity Branding

AD8315ARM −30°C to +85°C 8-Lead MSOP, Tube RM-8 50 J7A
AD8315ARM-REEL −30°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 3,000 J7A
AD8315ARM-REEL7 −30°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 1,000 J7A
AD8315ARMZ
AD8315ARMZ-RL
AD8315-EVAL MSOP Evaluation Board
AD8315ACP-REEL −30°C to +85°C 8-Lead LFCSP_VD, 13" Tape and Reel CP-8-1 10,000 J7
AD8315ACP-REEL7 −30°C to +85°C 8-Lead LFCSP_VD, 7" Tape and Reel CP-8-1 3,000 J7
AD8315ACPZ-REEL1−30°C to +85°C 8-Lead LFCSP_VD, 13" Tape and Reel CP-8-1 10,000 0J
AD8315ACPZ-REEL71−30°C to +85°C 8-Lead LFCSP_VD, 7" Tape and Reel CP-8-1 3,000 0J
AD8315ACP-EVAL LFCSP_VD Evaluation Board
AD8315CSURF Die, Surf Tape DIE 5,000
AD8315ACHIPS Die, Waffle Pack DIE 325

1

Z = Pb-free part.

1

−30°C to +85°C 8-Lead MSOP, Tube RM-8 50 Q0S

1

−30°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 3,000 Q0S

Rev. C | Page 23 of 24

AD8315

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01520-0-6/06(C)

Rev. C | Page 24 of 24