Datasheet AD8315 Datasheet (Analog Devices)

50 dB GSM PA Controller

AD8315

FEATURES
Complete RF Detector/Controller Function
>50 dB Range at 0.9 GHz (–49 dBm to +2 dBm re 50 )
Accurate Scaling from 0.1 GHz to 2.5 GHz
Temperature-Stable Linear-in-dB Response
Log Slope of 23 mV/dB, Intercept at –60 dBm at 0.9 GHz
True Integration Function in Control Loop
Low Power: 20 mW at 2.7 V, 38 mW at 5 V
Power Down to 10.8 W

APPLICATIONS
Single, Dual, and Triple Band Mobile Handset

(GSM, DCS, EDGE)

Transmitter Power Control

PRODUCT DESCRIPTION

The AD8315 is a complete low cost subsystem for the precise
control of RF power amplifiers operating in the frequency range

0.1 GHz–2.5 GHz and over a typical dynamic range of 50 dB. It is
intended for use in cellular handsets and other battery-operated
wireless devices. The log amp technique provides a much wider
measurement range and better accuracy than controllers using
diode detectors. In particular, its temperature stability is excellent
over a specified range of –30∞C to +85∞C.

Its high sensitivity allows control at low signal levels, thus reduc­ing the amount of power that needs to be coupled to the detector.

For convenience, the signal is internally ac-coupled. This
high-pass coupling, with a corner at approximately 0.016 GHz,
determines the lowest operating frequency. Thus, the source
may be dc grounded.

The AD8315 provides a voltage output, VAPC, that has the
voltage range and current drive to directly connect to most hand­set power amplifiers’ gain control pin. VAPC can swing from 250
mV above ground to within 200 mV below the supply voltage.
Load currents of up to 6 mA can be supported.

The setpoint control input is applied to pin VSET and has an
operating range of 0.25 V–1.4 V. The associated circuit deter­mines the slope and intercept of the linear-in-dB measurement
system; these are nominally 23 mV/dB and –60 dBm for a 50 W
termination (–73 dBV) at 0.9 GHz. Further simplifying the
application of the AD8315, the input resistance of the setpoint
interface is over 100 MW, and the bias current is typically 0.5 mA.

The AD8315 is available in MSOP and lead frame chip scale
(LFCSP) packages and consumes 8.5 mA from a 2.7 V to 5.5 V
supply. When powered down, the sleep current is 4 mA.

FUNCTIONAL BLOCK DIAGRAM

RFIN

COMM

VPOS

ENBL

LOW NOISE

GAIN BIAS

OFFSET
COMP’N

LOW NOISE

BAND GAP

REFERENCE

10dB10dB10dB

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

OUTPUT
ENABLE

DELAY

VA PC

1.35

DETDETDETDETDET

10dB

INTERCEPT

POSITIONING

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

HI-Z

LOW NOISE (25nV/ Hz)
RAIL-TO-RAIL BUFFER

FLTR

VSET

V-I

23mV/dB
250mV to

1.4V = 50dB

AD8315–SPECIFICATIONS

(VS = 2.7 V, T = 25C, 52.3  termination on RFIN, unless otherwise noted.)

Parameter Conditions Min Typ Max Unit

OVERALL FUNCTION

Frequency Range

1

To Meet All Specifications 0.1 2.5 GHz

Input Voltage Range ± 1 dB Log Conformance, 0.1 GHz –57 –11 dBV

Equivalent dBm Range –44 +2 dBm
Logarithmic Slope
Logarithmic Intercept

2

2

0.1 GHz 21.5 24 25.5 mV/dB

0.1 GHz –79 –70 –64 dBV

Equivalent dBm Level –66 –57 –51 dBm

RF INPUT INTERFACE Pin RFIN

Input Resistance
Input Capacitance

3

3

0.1 GHz 2.8 kW

0.1 GHz 0.9 pF

OUTPUT Pin VAPC

Minimum Output Voltage VSET £ 200 mV, ENBL High 0.25 0.27 0.3 V

ENBL Low 0.02 V
Maximum Output Voltage R
vs. Temperature

4

General Limit 2.7 V £ VPOS £ 5.5 V, R

≥ 800 W 2.45 2.6 V

L

85∞C, V

POS

=3 V, I

=6 mA 2.54 V

OUT

= • VPOS – 0.1 V

L

Output Current Drive Source/Sink 5/200 mA/mA
Output Buffer Noise 25 nV÷ Hz
Output Noise RF Input = 2 GHz, 0 dBm, f

= 220 pF

C

FLT

Small Signal Bandwidth 0.2 V to 2.6 V Swing 30 MHz
Slew Rate 10%–90%, 1.2 V Step (V

SET

= 100 kHz, 130 nV/÷Hz

NOISE

), Open Loop

5

13 V/ms

Response Time FLTR = Open, Refer to TPC 24 150 ns

SETPOINT INTERFACE Pin VSET

Nominal Input Range Corresponding to Central 50 dB 0.25 1.4 V
Logarithmic Scale Factor 43.5 dB/V
Input Resistance 100 kW
Slew Rate 16 V/ms

ENABLE INTERFACE Pin ENBL

Logic Level to Enable Power 1.8 V

POS

V

Input Current when Enable High 20 mA
Logic Level to Disable Power 0.8 V
Enable Time Time from ENBL High to V

Final Value, V

£ 200 mV, Refer to TPC 21

SET

Disable Time Time from ENBL Low to V

Final Value, V

£ 200 mV, Refer to TPC 21

SET

Power-On/Enable Time Time from VPOS/ENBL High to V

1% of Final Value, V

£ 200 mV, Refer to

SET

within 1% of 4 5 ms

APC

within 1% of 8 9 ms

APC

within 2 3 ms

APC

TPC 26

Time from VPOS/ENBL Low to V

1% of Final Value, V

£ 200 mV, Refer to

SET

within 100 200 ns

APC

TPC 26

POWER INTERFACE Pin VPOS

Supply Voltage 2.7 5.5 V
Quiescent Current ENBL High 8.5 10.7 mA

Over Temperature –30∞C £ T

Disable Current

6

ENBL Low 4 10 mA

£ +85∞C12.9mA

A

Over Temperature –30∞C £ TA £ +85∞C13mA

NOTES

1

Operation down to 0.02 GHz is possible.

2

Mean and Standard Deviation specifications are available in Table I.

3

See TPC 9 for plot of Input Impedance vs. Frequency.

4

This parameter is guaranteed but not tested in production. Limit is –3 sigma from the mean.

5

Response time in a closed-loop system will depend upon the filter capacitor (C

6

This parameter is guaranteed but not tested in production. Maximum specified limit on this parameter is the +6 sigma value.

Specifications subject to change without notice.

) used and the response of the variable gain element.

FLT

–2–

REV. B

AD8315

Table I. Typical Specifications at Selected Frequencies at 25C (Mean and Sigma)

1 dB Dynamic Range

Slope – mV/dB Intercept – dBV Low Point – dBV High Point – dBV

Frequency – GHz Mean Sigma Mean Sigma Mean Sigma Mean Sigma

0.1 23.8 0.3 –70.1 1.8 –57.7 1.3 –10.6 0.8

0.9 23.2 0.4 –72.6 1.8 –61.0 1.3 –11.2 0.8

1.9 22.2 0.3 –73.8 1.6 –62.9 0.9 –18.5 1.7

2.5 22.3 0.4 –75.6 1.5 –64.0 1.1 –20.0 1.7

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage VPOS . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5 V

Temporary Overvoltage VPOS

(100 cycles, 2 seconds duration, ENBL Low) . . . . . . .6.3 V

VAPC, VSET, ENBL . . . . . . . . . . . . . . . . . . . . . . 0 V, VPOS

RFIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 dBm

Equivalent Voltage . . . . . . . . . . . . . . . . . . . . . . . . 1.6 V rms

Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 60 mW

(MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200∞C/W

q

JA

q

(LFCSP, Paddle Soldered) . . . . . . . . . . . . . . . . . . 80∞C/W

JA

(LFCSP, Paddle not Soldered) . . . . . . . . . . . . . 200∞C/W

q

JA

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125∞C

Operating Temperature Range . . . . . . . . . . . –40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

Lead Temperature Range (Soldering 60 sec)

MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300∞C

LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240∞C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

PIN CONFIGURATION

1

RFIN

2

ENBL

3

VSET

(Not to Scale)

4

NC = NO CONNECT

AD8315

TOP VIEW

8

7

6

5

VPOS

VAPC

NC

COMMFLTR

PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Function

1 RFIN RF Input
2 ENBL Connect to VPOS for Normal Operation

Connect pin to ground for Disable Mode

3 VSET Setpoint Input. Nominal input range

0.25 V to 1.4 V.

4 FLTR Integrator Capacitor. Connect between

FLTR and COMM.
5 COMM Device Common (Ground)
6NCNo Connection
7 VAPC Output. Control voltage for gain control

element.
8 VPOS Positive Supply Voltage: 2.7 V to 5.5 V

ORDERING GUIDE

Model Temperature Range Package Descriptions Package Option Branding Information

AD8315ARM –30∞C to +85∞CTube, 8-Lead MSOP RM-8 J7A
AD8315ARM-REEL 13" Tape and Reel
AD8315ARM-REEL7 7" Tape and Reel
AD8315-EVAL MSOP Evaluation Board
AD8315ACP-REEL –30∞C to +85∞C 13" Tape and Reel, CP-8 J7A

8-Lead LFCSP
AD8315ACP-REEL7 7" Tape and Reel
AD8315ACP-EVAL LFCSP Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although

WARNING!

the AD8315 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. B

–3–

ESD SENSITIVE DEVICE

AD8315

–Typical Performance Characteristics

1

0

–10

–20

–30

–40

0.9GHz

–50

RF INPUT AMPLITUDE – dBV

–60

–70

–80

0.2

10

0

(+3dBm)

–10

–20

–30

RF INPUT

–40

AMPLITUDE – dBV

–50

(–47dBm)

–60

–70

0.1

0.4 0.6 0.8 1.0 1.2 1.4

TPC 1. Input Amplitude vs. V

+25C

0.3 0.5 0.7 0.9 1.1 1.3 1.5

1.9GHz

0.1GHz

2.5GHz

V

– V

SET

SET

–30C

+25C

+85C

–30C

ERROR AT +85C AND –30C
BASED ON DEVIATION FROM
SLOPE AND INTERCEPT AT +25C

V

– V

SET

+85C

TPC 2. Input Amplitude and Log Conformance vs. V

0.1 GHz

23

13

3

–7

–17

–27

–37

–47

RF INPUT AMPLITUDE – dBm

–57

–67

4

3

2

1

0

ERROR – dB

–1

–2

(–47dBm)

TPC 5. Input Amplitude and Log Conformance vs. V

SET

–3

–4

at

1.9 GHz

ERROR – dB

(+3dBm)

–10

–20

–30

RF INPUT

–40

AMPLITUDE – dBV

–50

–60

–70

4

3

2

1

0

–1

–2

–3

–4

0.2

0.1GHz

0.4 0.6 0.8 1.0 1.2 1.4 1.6
V

– V

SET

TPC 4. Log Conformance vs. V

10

0

+85C

+25C

+85C

0.1

–30C

0.3 0.5 0.7 0.9 1.1 1.3 1.5

–30C

+25C

ERROR AT +85C AND –30C
BASED ON DEVIATION FROM
SLOPE AND INTERCEPT AT +25C

V

– V

SET

1.9GHz

2.5GHz

SET

0.9GHz

4

3

2

1

0

–1

–2

–3

–4

SET

ERROR – dB

at

(+3dBm)

RF INPUT

(–47dBm)

10

0

–10

–20

–30

–40

AMPLITUDE – dBV

–50

–60

–70

0.3 0.5 0.7 0.9 1.1 1.3 1.5

0.1

–30C

+25C

–30C

+85C

+25C

ERROR AT +85C AND –30C
BASED ON DEVIATION FROM
SLOPE AND INTERCEPT AT +25C

V

– V

SET

+85C

TPC 3. Input Amplitude and Log Conformance vs. V

0.9 GHz

SET

4

3

2

1

0

ERROR – dB

–1

–2

–3

–4

at

10

0

(+3dBm)

–10

–30C

+85C

ERROR AT +85C AND –30C
BASED ON DEVIATION FROM
SLOPE AND INTERCEPT AT +25C

V

– V

SET

RF INPUT

(–47dBm)

–20

–30

–40

AMPLITUDE – dBV

–50

+25C

–60

–70

0.1

0.3 0.5 0.7 0.9 1.1 1.3 1.5

+25C

–30C+85C

TPC 6. Input Amplitude and Log Conformance vs. V

2.5 GHz

–4–

4

3

2

1

0

ERROR – dB

–1

–2

–3

–4

at

SET

REV. B

AD8315

(

)(

)

(

)(

)

(

)(

)

4

3

2

1

0

ERROR – dB

–1

–2

–3

–4

–80 0–70

+85C

ERROR AT +85C AND –30C
BASED ON DEVIATION FROM
SLOPE AND INTERCEPT AT +25C

–60

RF INPUT AMPLITUDE – dBV

–47dBm

–50 –40 –30 –20 –10

–30C

+3dBm

TPC 7. Distribution of Error at Temperature after Ambient
Normalization vs. Input Amplitude, 3 Sigma to Either Side
of Mean, 0.1 GHz

4

3

2

30C

4

3

2

1

0

ERROR – dB

–1

–2

ERROR AT +85C AND –30C

–3

BASED ON DEVIATION FROM
SLOPE AND INTERCEPT AT +25C

–4

–80 0–70

–30C

+85C

–50 –40 –30 –20 –10

–60

RF INPUT AMPLITUDE – dBV

–47dBm

+3dBm

TPC 10. Distribution of Error at Temperature after Ambient
Normalization vs. Input Amplitude, 3 Sigma to Either Side of
Mean, 1.9 GHz

4

3

2

–30C

1

0

ERROR – dB

–1

–2

ERROR AT +85C AND –30C

–3

BASED ON DEVIATION FROM
SLOPE AND INTERCEPT AT +25C

–4

–80 0–70

85C

–60

–50 –40 –30 –20 –10

RF INPUT AMPLITUDE – dBV

(+3dBm)(–47dBm)

TPC 8. Distribution of Error at Temperature after Ambient
Normalization vs. Input Amplitude, 3 Sigma to Either Side
of Mean, 0.9 GHz

jX
j1500
j220
j130
j110

0

–200

–400

–600

–800

–1000

–1200

X

–1400

–1600

–1800

–2000

3000

2700

2400

2100

1800

X (LFCSP)

1500

1200

RESISTANCE – 

900

600

300

0

0 2.50.5 1 1.5 2

X (MSOP)

FREQUENCY
(GHz)

0.1

0.9

1.9

2.5

FREQUENCY – GHz

2900 –

R (LFCSP)

R (MSOP)

R –

700 –
130 –
170 –

Chip Scale (LFCSP)

MSOP

jX
j1900
j240
j80
j70

R –

2700 –

730 –
460 –
440 –

R

TPC 9. Input Impedance

1

0

ERROR – dB

–1

–2

ERROR AT +85C AND –30C

–3

BASED ON DEVIATION FROM
SLOPE AND INTERCEPT AT +25C

–4

–80 0–70

–50 –40 –30 –20 –10

–60

RF INPUT AMPLITUDE – dBV

–47dBm

+85C

+3dBm

TPC 11. Distribution of Error at Temperature after Ambient
Normalization vs. Input Amplitude, 3 Sigma to Either Side of
Mean, 2.5 GHz

10

8



REACTANCE –

6

4

DECREASING

SUPPLY CURRENT – mA

2

0

1.3

V

ENBL

1.4 1.5 1.6 1.7
V

ENBL

TPC 12. Supply Current vs. V

– V

INCREASING
V

ENBL

ENBL

REV. B

–5–

AD8315

g

25

24

23

22

SLOPE – mV/dB

21

20

0

–30 C

0.5 1.0 1.5 2.0 2.5
FREQUENCY – GHz

+85 C

+25 C

TPC 13. Slope vs. Frequency; –30∞C, +25∞C, and +85∞C

24

23

SLOPE – mV/dB

22

0.1GHz

0.9GHz

1.9GHz

–66

–68

+85 C

–70

–72

+25 C

–74

INTERCEPT – dBV

–76

–78

–80

0





–30 C



0.5 1.0 1.5 2.0 2.5
FREQUENCY – GHz

TPC 16. Intercept vs. Frequency; –30∞C, +25∞C, and +85∞C

–68

–70

–72

–74

INTERCEPT – dBV

–76

0.1GHz

0.9GHz

1.9GHz

2.5GHz

21

3.0 3.5 4.0 4.5 5.0 5.5

2.5
VS – V

TPC 14. Slope vs. Supply Voltage

45
40
35
30
25
20
15
10

5
0

–5

–10

AMPLITUDE – dB

–15
–20
–25
–30
–35
–40

10

100 1k 10k 100k 1M 10M

C

= 220pF

FLT

FREQUENCY – Hz

C

= 0pF

FLT

TPC 15. AC Response from VSET to VAPC

0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130

rees

PHASE – De

–78

–80

3.0 3.5 4.0 4.5 5.55.0

2.5

2.5GHz

VS – V

TPC 17. Intercept vs. Supply Voltage

10000

1000

100

NOISE SPECTRAL DENSITY – nV/ Hz

10

100

TPC 18. V

C

= 220PF, RF INPUT = 2GHz

FLT

RF INPUT

–51dBV

–48dBV

–33dBV

–43dBV

–23dBV

–13dBV

–53dBV AND

–63dBV

1k 10k 100k 1M 10M

FREQUENCY – Hz

Noise Spectral Density

APC

–6–

REV. B

3.5

SUPPLY VOLTAGE – V

2.8

2.7

V

APC

– V

2.7

2.6

2.5

2.4

2.8 3.0

SHADING INDICATES

3 SIGMA

2.9

AD8315

3.3

3.1

– V

2.9

APC

V

2.7

2.5

2.3

2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5

2.7

TPC 19. Maximum V
Load Current

V

GND

GND

APC

2mA

0mA

4mA

6mA

SUPPLY VOLTAGE – V

Voltage vs. Supply Voltage by

APC

AVERAGE = 16 SAMPLES

200mV PER VERTICAL

DIVISION

2 s PER
HORIZONTAL

1V PER

VERTICAL

DIVISION

DIVISION

V

ENBL

TPC 22. Maximum V
4 mA Load Current

V

APC

GND

RF

INPUT

GND

Voltage vs. Supply Voltage with

APC

AVERAGE = 16 SAMPLES

1V PER

VERTICAL

DIVISION

PULSED RF

0.1GHz, –13dBV

100ns PER
HORIZONTAL
DIVISION

TPC 20. ENBL Response Time

RF OUT

10MHz REF
OUTPUT

AD8315

1

2

3

4

NC = NO CONNECT

RFIN

ENBL

VSET

VPOS

VAPC

COMMFLTR

TIMEBASE

8

7

6

NC

5

STANFORD DS345

PULSE

GENERATOR

2.7V

0.1F

TEK P6205

FET PROBE

PULSE OUT

TEK P6205

FET PROBE

R AND S

SMT03

SIGNAL

GENERATOR

52.3

220pF

TPC 21. Test Setup for ENBL Response Time

TRIG
OUT

TEK TDS694C

SCOPE

TRIG

TPC 23. V

Response Time, Full-Scale Amplitude

APC

Change, Open-Loop

R AND S SMT03

SIGNAL

GENERATOR

PULSE

MODULATION

MODE

RF

SPLITTER

–3dB

52.3

10MHz REF
OUTPUT

PULSE MODE IN OUT

RF OUT

–3dB

AD8315

1

RFIN

2

2.7V

0.3V

ENBL

3

VSET

4

NC

NC = NO CONNECT

VPOS

VA PC

COMMFLTR

NC

EXT TRIG

8

7

6

5

PICOSECOND

0.1 F

TEK P6205

FET PROBE

TPC 24. Test Setup for VAPC Response Time

PULSE LABS

PULSE

GENERATOR

PULSE OUT

2.7V

TRIG
OUT

TEK TDS694C

SCOPE

TRIG

REV. B

–7–

AD8315

AVERAGE = 16 SAMPLES

GND

GND

V

V

APC

V

AND

ENBL

S

200mV PER

VERTICAL

DIVISION

1V PER

VERTICAL

DIVISION

2 s PER
HORIZONTAL
DIVISION

TPC 25. Power-On and -Off Response with
V

Grounded

SET

R AND S

SMT03

SIGNAL

GENERATOR

52.3

220pF

10MHz REF
OUTPUT

RF OUT

1

RFIN

2

ENBL

3

VSET

4

NC = NO CONNECT

AD8315

VPOS

VA PC

COMMFLTR

NC

8

7

6

5

EXT TRIG

TEK P6205

FET PROBE

TEK P6205

FET PROBE

STANFORD DS345

PULSE

GENERATOR

AD811

732

PULSE OUT

49.9

TRIG

TEK TDS694C

SCOPE

TRIG
OUT

500mV PER

VERTICAL

DIVISION

1V PER

VERTICAL

DIVISION

AVERAGE = 16 SAMPLES

2s PER
HORIZONTAL
DIVISION

GND

GND

V

APC

V

S

TPC 27. Power-On and -Off Response with V
ENBL Grounded

R AND S

SMT03

SIGNAL

GENERATOR



52.3

220pF

10MHz REF
OUTPUT

RF OUT

1

2

3

4

NC = NO CONNECT

AD8315

RFIN

ENBL

VSET

VPOS

VA PC

COMMFLTR

NC

8

7

6

5

EXT TRIG

TEK P6205

FET PROBE

TEK P6205

FET PROBE

STANFORD DS345

PULSE

GENERATOR

AD811

732

PULSE OUT

49.9

TEK TDS694C

and

SET

TRIG

SCOPE

TRIG
OUT

TPC 26. Test Setup for Power-On and -Off Response with
VSET Grounded

GENERAL DESCRIPTION AND THEORY

The AD8315 is a wideband logarithmic amplifier (log amp)
similar in design to the AD8313 and AD8314. However, it is
strictly optimized for use in power control applications rather
than as a measurement device. Figure 1 shows the main features
in block schematic form. The output (Pin 7, VAPC) is intended
to be applied directly to the automatic power-control (APC) pin
of a power amplifier module.

Basic Theory

Logarithmic amplifiers provide a type of compression in which a
signal having a large range of amplitudes is converted to one of
smaller range. The use of the logarithmic function uniquely results
in the output representing the decibel value of the input. The
fundamental mathematical form is:

V

VV

= log

OUT SLP

Here V
because when V

is the input voltage, VZ is called the intercept (voltage)

IN

IN

and thus the result is zero, and V

IN

10

V

Z

(1)

= VZ the argument of the logarithm is unity

is called the slope (voltage),

SLP

which is the amount by which the output changes for a certain
change in the ratio (V
denoted by the function log
and since a decade corresponds to 20 dB, V

). When BASE-10 logarithms are used,

IN/VZ

, V

represents the “volts/decade,”

10

SLP

/20 represents the

SLP

“volts/dB.” For the AD8315, a nominal (low frequency) slope

–8–

TPC 28. Test Setup for Power-On and -Off Response with
VSET and ENBL Grounded

of 24 mV/dB was chosen, and the intercept VZ was placed at the
equivalent of –70 dBV for a sine wave input (316 mV rms). This
corresponds to a power level of –57 dBm when the net resistive
part of the input impedance of the log amp is 50 W. However,
both the slope and the intercept are dependent on frequency (see
TPC 13 and TPC 16).

Keeping in mind that log amps do not respond to power but
only to voltages and that the calibration of the intercept is
waveform dependent and is only quoted for a sine wave signal,
the equivalent power response can be written as:

VVPP

= (–)

OUT DB IN Z

where the input power P

and the equivalent intercept PZ are

IN

(2)

both expressed in dBm (thus, the quantity in parentheses is
simply a number of decibels), and V
so many mV/dB. For a log amp having a slope V

is the slope expressed as

DB

of 24 mV/dB

DB

and an intercept at –57 dBm, the output voltage for an input
power of –30 dBm is 0.024 [–30 – (–57)] = 0.648 V.

Further details about the structure and function of log amps can
be found in data sheets for other log amps produced by Analog
Devices. Refer to data sheets for the AD640 and AD8307, both
of which include a detailed discussion of the basic principles of
operation and explain why the intercept depends on waveform,
an important consideration when complex modulation is
imposed on an RF carrier.

REV. B

AD8315

RFIN

COMM

(PADDLE)

VPOS

ENBL

(PRECISE GAIN

CONTROL)

LOW NOISE

GAIN BIAS

OFFSET
COMP’N

(WEAK GM STAGE)

(PRECISE SLOPE

CONTROL)

LOW NOISE

BAND GAP

REFERENCE

10dB10dB10dB

INTERCEPT

POSITIONING

Figure 1. Block Schematic

The intercept need not correspond to a physically realizable part
of the signal range for the log amp. Thus, the specified intercept
is –70 dBV, at 0.1 GHz, whereas the smallest input for accurate
measurement (a +1 dB error, see Table I) at this frequency is
higher, being about –58 dBV. At 2.5 GHz, the +1 dB error point
shifts to –64 dBV. This positioning of the intercept is deliberate
and ensures that the V

voltage is within the capabilities of cer-

SET

tain DACs, whose outputs cannot swing below 200 mV. Figure 2
shows the 100 MHz response of the AD8315; the vertical axis
represents not the output (at pin VAPC) but the value required
at the power control pin VSET to null the control loop. This
will be explained next.

1.5

1.0

SET

V

0.5

0

100V

–80dBV

–67dBm

–70dBV

0.288V @ –58dBV

IDEAL

1mV
–60dBV
–47dBm

V

P

O

L

S

10mV

–40dBV

–27dBm

, dBVIN, P

IN

1.416V @ –11dBV

B

/d

V

m

= 24

E

ACTUAL

IN

100mV
–20dBV
–7dBm

1V (RMS)

0dBV

+13dBm (RE 50)

Figure 2. Basic Calibration of the AD8315 at 0.1 GHz

Controller-Mode Log Amps

The AD8315 combines the two key functions required for the
measurement and control of the power level over a moderately
wide dynamic range. First, it provides the amplification needed to
respond to small signals in a chain of four amplifier/limiter cells
(see Figure 1), each having a small signal gain of 10 dB and a
bandwidth of approximately 3.5 GHz. At the output of each of
these amplifier stages is a full-wave rectifier, essentially a square-

(ELIMINATES

GLITCH)

OUTPUT
ENABLE

DELAY

(CURRENT-MODE SIGNAL)

DETDETDETDETDET

10dB

(CURRENT-

NULLING

MODE)

HI-Z

LOW NOISE (25nV/ Hz)
RAIL-TO-RAIL BUFFER

(CURRENT-MODE

FEEDBACK)

(SMALL INTERNAL
FILTER CAPACITOR
FOR GHz RIPPLE)

1.35

V- I

VA PC

FLTR

VSET

23mV/dB
250mV to

1.4V = 50dB

law detector cell that converts the RF signal voltages to a fluctu­ating current having an average value that increases with signal
level. A further passive detector stage is added before the first
stage. These five detectors are separated by 10 dB, spanning
some 50 dB of dynamic range. Their outputs are each in the
form of a differential current, making summation a simple mat­ter. It is readily shown that the summed output can closely
approximate a logarithmic function. The overall accuracy at the
extremes of this total range, viewed as the deviation from an
ideal logarithmic response, that is, the log conformance error, can
be judged by reference to TPC 4, which shows that errors across
the central 40 dB are moderate. Other performance curves show
how conformance to an ideal logarithmic function varies with
supply voltage, temperature, and frequency.

In a device intended for measurement applications, this current
would then be converted to an equivalent voltage, to provide the

) function shown in Equation 1. However, the design of the

log(V

IN

AD8315 differs from standard practice in that its output needs
to be a low noise control voltage for an RF power amplifier, not
a direct measure of the input level. Further, it is highly desirable
that this voltage be proportional to the time-integral of the error
between the actual input V

and a dc voltage V

IN

(applied to

SET

Pin 3, VSET) which defines the setpoint, that is, a target value
for the power level, typically generated by a D/A converter.

This is achieved by converting the difference between the sum of
the detector outputs (still in current form) and an internally gener­ated current proportional to V

to a single-sided current-mode

SET

signal. This, in turn, is converted to a voltage (at Pin 4, FLTR, the
low-pass filter capacitor node), to provide a close approximation
to an exact integration of the error between the power present in
the termination at the input of the AD8315 and the setpoint
voltage. Finally, the voltage developed across the ground-referenced
filter capacitor C

is buffered by a special low noise amplifier

FLT

of low voltage gain (¥1.35) and presented at Pin 7 (VAPC) for
use as the control voltage for the RF power amplifier. This buffer
can provide “rail-to-rail” swings and can drive a substantial load
current, including large capacitors. Note: The RF power is assumed
to increase monotonically with an increasingly positive delivered
by the amplifier under control of the AD8315 voltage on its
APC control pin.

REV. B

–9–

AD8315

Control Loop Dynamics

In order to understand how the AD8315 behaves in a complete
control loop, an expression for the current in the integration
capacitor as a function of the input V

must be developed. Refer to Figure 3.

V

SET

V

SET

3

RFIN

1

V

SET

V

IN

SETPOINT

INTERFACE

LOGARITHMIC

RF DETECTION

SUBSYSTEM

I

= I

DET

SLP

I

SET

I

DET

LOG10 (VIN/VZ)

and the setpoint voltage

IN

= V

/4.15k

SET

FLTR

I

ERR

4

1.35

C

FLT

VAPC

7

Figure 3. Behavioral Model of the AD8315

First, the summed detector currents are written as a function of
the input:

II VV

= log ( / )

DET SLP IN Z

where I

is the partially filtered demodulated signal, whose

DET

10

(3)

exact average value will be extracted through the subsequent
integration step; I
of 115 mA per decade (that is, 5.75 mA/dB); V
volts-rms; and V

is the current-mode slope and has a value

SLP

is the effective intercept voltage, which, as

Z

is the input in

IN

previously noted, is dependent on waveform but is 316 mV rms
(–70 dBV) for a sine wave input. Now the current generated by
the setpoint interface is simply:

IV k

=W/.415

SET SET

The difference between this current and I
loop filter capacitor C
this capacitor, V

VsI I sC

FLT SET DET FLT

SET SLP IN Z

=

FLT

() ( – )/=

/. – log ( / )415

The control output V

. It follows that the voltage appearing on

FLT

, is the time integral of the difference current:

WVkI VV

sC

is slightly greater than this, since the

APC

10

FLT

DET

is applied to the

(4)

(5)

(6)

gain of the output buffer is ¥1.35. Also, an offset voltage is
deliberately introduced in this stage; this is inconsequential
since the integration function implicitly allows for an arbitrary
constant to be added to the form of Equation 6. The polarity is
such that V

greater than the equivalent value of VIN. In practice, the

V

SET

V

output will rail to the positive supply under this condition

APC

will rise to its maximum value for any value of

APC

unless the control loop through the power amplifier is present.
In other words, the AD8315 seeks to drive the RF power to its
maximum value whenever it falls below the setpoint. The use
of exact integration results in a final error that is theoretically
zero, and the logarithmic detection law would ideally result in a
constant response time following a step change of either the
setpoint or the power level, if the power-amplifier control
function were likewise linear-in-dB. This latter condition is
rarely true, however, and it follows that in practice, the loop
response time will depend on the power level, and this effect can
strongly influence the design of the control loop.

Equation 6 can be restated as:

Vs

()

=

APC

VV VV

SET SLP IN Z

-

log ( / )

10

sT

(7)

–10–

where V

is the volts-per-decade slope from Equation 1, having

SLP

a value of 480 mV/decade, and T is an effective time constant for
the integration, being equal to 4.15 kW ¥ C

/1.35; the resistor

FLT

value comes from the setpoint interface scaling Equation 4 and
the factor 1.35 arises because of the voltage gain of the buffer.
So the integration time constant can be written as:

TCin s when C is in nF

= 307.,m expressed

FLT

(8)

To simplify our understanding of the control loop dynamics,
begin by assuming that the power amplifier gain function actu­ally is linear-in-dB. Also use voltages to express the signals at
the power amplifier input and output, for the moment. Let the
RF output voltage be V

and its input be VCW. Further, to

PA

characterize the gain control function, this form is used:

(/)

VV

VGV

= 10

PA O CW

where G
V

GBC

is the gain of the power amplifier when V

O

is the gain-scaling. While few amplifiers will conform so

APC GBC

APC

(9)

= 0 and

conveniently to this law, it provides a clearer starting point for
understanding the more complex situation that arises when the
gain control law is less ideal.

This idealized control loop is shown in Figure 4. With some
manipulation, it is found that the characteristic equation of this
system is:

Vs

()

APC

()/–log /

SET GBC SLP GBC O CW Z

=

sT

+101

()

O

(10)

VV V V kGV V

where k is the coupling factor from the output of the power
amplifier to the input of the AD8315 (e.g., ¥ 0.1 for a “20 dB
coupler”), and T

is a modified time constant (V

O

GBC/VSLP

)T.

This is quite easy to interpret. First, it shows that a system of
this sort will exhibit a simple single-pole response, for any power
level, with the customary exponential time domain form for
either increasing or decreasing step polarities in the demand
level V
final value of the control voltage V

or the carrier input VCW. Second, it reveals that the

SET

will be determined by

APC

several fixed factors:

Vt VV V kGVV

=•

=

()

APC SET GBC SLP O CW Z

() ( )

/–log /

10

(11)

Example

Assume that the gain magnitude of the power amplifier runs
from a minimum value of ¥0.316 (–10 dB) at V
(40 dB) at V

V

= 1 V. Using a coupling factor of k = 0.0316 (that is, a

GBC

= 2.5 V. Applying Equation 9, GO = 0.316 and

APC

= 0 to ¥100

APC

30 dB directional coupler) and recalling that the nominal value of

is 480 mV and VZ = 316 ␮V for the AD8315, first calculate

V

SLP

the range of values needed for V

to control an output range

SET

of 33 dBm to –17 dBm. This can be found by noting that, in
the steady state, the numerator of Equation 7 must be zero,
that is:

VV kVV

= log ( / )

SET SLP PA Z

when V

is expanded to kVPA, the fractional voltage sample of

IN

10

the power amplifier output. Now, for +33 dBm, V

= 10 V rms,

PA

(12)

this evaluates to:

VmVVV

().log ( / ) .max ==048 316 316 1 44

SET

10

For a delivered power of –17 dBm, V

VmVVV

().log ( / ) .min ==048 1 316 024

SET

10

m

= 31.6 mV rms:

PA

m

(13)

(14)

REV. B

AD8315

Check: The power range is 50 dB, which should correspond
to a voltage change in V

of 50 dB ¥ 24 mV/dB = 1.2 V,

SET

which agrees.

Now, the value of V

is of interest, although it is a dependent

APC

parameter, inside the loop. It depends on the characteristics of
the power amplifier, and the value of the carrier amplitude V
Using the control values derived above, that is, G

= 1 V, and assuming the applied power is fixed at –7 dBm

V

GBC

= 0.316 and

O

CW

.

(so VCW = 100 mV rms), the following is true using Equation 11:

VVVVkGVV

()( )/ –log /

max =

APC SET GBC SLP O CW Z

(. )/ . –log(. . ./ )

=¥ ¥ ¥

144104800316 0 316 0 1 316

.–. .

==

VVVVkGVV

APC SET GBC SLP O CW Z

30 05 25

()( )/ –log /

min =

(. )/ . –log (. . . / )

=¥ ¥ ¥

024104800316 0 316 0 1 316

.–.

==

05 05

zero

10

V

10

V

10

10

m

(15)

V

m

(16)

both of which results are consistent with the assumptions made
about the amplifier control function. Note that the second term
is independent of the delivered power and a fixed function of
the drive power.

DIRECTIONAL COUPLER

V

= kV

IN

RF

V

SET

RESPONSE-SHAPING

OF OVERALL CONTROL-

LOOP (EXTERNAL CAP)

V

RF

AD8315

RF PA

C

FLT

V

RF DRIVE: UP
TO 2.5GHz

V

APC

CW

Figure 4. Idealized Control Loop for Analysis

Finally, using the loop time constant for these parameters and
an illustrative value of 2 nF for the filter capacitor C

TVVT

=

(/)

OGBCSLP

=¥=

(/ . ) . ( ) .1048 3072 128mm

snF s

FLT

:

(17)

Practical Loop

At the present time, power amplifiers, or VGAs preceding such
amplifiers, do not provide an exponential gain characteristic. It
follows that the loop dynamics (the effective time constant) will
vary with the setpoint, since the exponential function is unique
in providing constant dynamics. The procedure must, therefore,
be as follows. Beginning with the curve usually provided for the
power output versus the APC voltage, draw a tangent at the
point on this curve where the slope is highest (see Figure 5).
Using this line, calculate the effective minimum value of the
variable V
constant. Note that the minimum in V
maximum rate of change in the output power versus V

and use it in Equation 17 to determine the time

GBC

corresponds to the

GBC

APC

.

For example, suppose it is found that, for a given drive power,
the amplifier generates an output power of P

at V

P

2

VVVPP

GBC

= V2. Then, it is readily shown that:

APC

= 20

(–)/(–)

21 2 1

at V

1

= V1 and

APC

(18)

This should be used to calculate the filter capacitance. The
response time at high and low power levels (on the “shoulders”

REV. B

–11–

of the curve shown in Figure 5) will be slower. Note also that it
is sometimes useful to add a zero in the closed-loop response by
placing a resistor in series with C

. For more about these

FLT

matters, refer to the Applications section.

V2, P

33

23

13

– dBm

RF

P

3

–7

0

0.5 1.0 1.5 2.0 2.5

V1, P

1

V

– V

APC

2

Figure 5. Typical Power-Control Curve

A Note About Power Equivalency

In using the AD8315, it must be understood that log amps do not
fundamentally respond to power. It is for this reason that dBV
(decibels above 1 V rms) are used rather than the commonly used
metric of dBm. The dBV scaling is fixed, independent of termi­nation impedance, while the corresponding power level is not.
For example, 224 mV rms is always –13 dBV (with one further
condition of an assumed sinusoidal waveform; see the AD640
data sheet for more information about the effect of waveform on
logarithmic intercept), and this corresponds to a power of 0 dBm
when the net impedance at the input is 50 W. When this impedance
is altered to 200 W, however, the same voltage corresponds to a
power level that is four times smaller (P = V

2

/R) or –6 dBm. A

dBV level may be converted to dBm in the special case of a 50 W
system and a sinusoidal signal by simply adding 13 dB (0 dBV
is then, and only then, equivalent to 13 dBm).

Therefore, the external termination added ahead of the AD8315
determines the effective power scaling. This will often take the
form of a simple resistor (52.3 W will provide a net 50 W input),
but more elaborate matching networks may be used. The choice
of impedance determines the logarithmic intercept, that is, the
input power for which the V

versus PIN function would

SET

cross the baseline if that relationship were continuous for all
values of V

. This is never the case for a practical log amp; the

IN

intercept (so many dBV) refers to the value obtained by the
minimum error straight line fit to the actual graph of V

(more generally, VIN). Where the modulation is complex, as

P

IN

SET

versus

in CDMA, the calibration of the power response needs to be
adjusted; the intercept will remain stable for any given arbitrary
waveform. When a true power (waveform independent) response is
needed, a mean-responding detector, such as the AD8361,
should be considered.

The logarithmic slope, V

in Equation 1, which is the amount

SLP

by which the setpoint voltage needs to be changed for each decibel
of input change (voltage or power), is, in principle, independent
of waveform or termination impedance. In practice, it usually
falls off somewhat at higher frequencies, due to the declining
gain of the amplifier stages and other effects in the detector
cells (see TPC 13).

AD8315

Basic Connections

Figure 6 shows the basic connections for operating the AD8315,
and Figure 7 shows a block diagram of a typical application.
The AD8315 is typically used in the RF power control loop of a
mobile handset.

A supply voltage of 2.7 V to 5.5 V is required for the AD8315.
The supply to the VPOS pin should be decoupled with a low
inductance 0.1 mF surface-mount ceramic capacitor, close to the
device. The AD8315 has an internal input coupling capacitor.
This negates the need for external ac-coupling. This capacitor,
along with the low frequency input impedance of the device of
approximately 2.8 kW, sets the minimum usable input frequency
to around 0.016 GHz. A broadband 50 W input match is achieved
in this example by connecting a 52.3 W resistor between RFIN
and ground. A plot of input impedance versus frequency is
shown in TPC 9. Other coupling methods are also possible (see
Input Coupling Options section).

NC

0.1F

8

7

6

C1

+V

S

(2.7V TO 5.5V)

+V

APC

RFIN

+V

V

SET

R1

52.3

S

C

FLT

AD8315

1

2

3

45

NC = NO CONNECT

RFIN

ENBL

VSET

VPOS

VAPC

COMMFLTR

Figure 6. Basic Connections

DIRECTIONAL

COUPLER

ATTENUATOR

52.3

RFIN

POWER

AMP

GAIN
CONTROL
VOLTAGE

VAPC

AD8315

FLTR

C

VSET

FLT

RFIN

DAC

Figure 7. Typical Application

In a power control loop, the AD8315 provides both the detector and
controller functions. A sample of the power amplifier’s (PA) output
power is coupled to the RF input of the AD8315, usually via a
directional coupler. In dual mode applications, where there are
two PAs and two directional couplers, the outputs of the directional
couplers can be passively combined (both PAs will never be turned
on simultaneously) before being applied to the AD8315.

A setpoint voltage is applied to VSET from the controlling
source (generally this will be a DAC). Any imbalance between
the RF input level and the level corresponding to the setpoint
voltage will be corrected by the AD8315’s VAPC output that
drives the gain control terminal of the PA. This restores a balance
between the actual power level sensed at the input of the AD8315
and the value determined by the setpoint. This assumes that the gain
control sense of the variable gain element is positive, that is, an
increasing voltage from VAPC will tend to increase gain.

can swing from 250 mV to within 100 mV of the supply

V

APC

rail and can source up to 6 mA. If the control input of the PA
needs to source current, a suitable load resistor can be con­nected between VAPC and COMM. The output swing and
current sourcing capability of VAPC is shown in TPC 19.

Range on VSET and RFIN

The relationship between the RF input level and the setpoint
voltage follows from the nominal transfer function of the device
(see TPCs 2, 3, 5, and 6). At 0.9 GHz, for example, a voltage of
1 V on VSET indicates a demand for –30 dBV (–17 dBm re 50 W)
at RFIN. The corresponding power level at the output of the
power amplifier will be greater than this amount due to the
attenuation through the directional coupler.

For setpoint voltages of less than approximately 250 mV, V

APC

will remain unconditionally at its minimum level of approximately
250 mV. This feature can be used to prevent any spurious emissions
during power-up and power-down phases.

Above 250 mV, V

will have a linear control range up to 1.4 V,

SET

corresponding to a dynamic range of 50 dB. This results in a
slope of 23 mV/dB or approximately 43.5 dB/V.

Transient Response

The time domain response of power amplifier control loops,
using any kind of controller, is only partially determined by the
choice of filter which, in the case of the AD8315, has a true
integrator form 1/sT as shown in Equation 7, with a time con­stant given by Equation 8. The large signal step response is
also strongly dependent on the form of the gain-control law.
Nevertheless, some simple rules can be applied. When the filter
capacitor C

is very large, it will dominate the time domain

FLT

response, but the incremental bandwidth of this loop will still
vary as V

traverses the nonlinear gain-control function of the

APC

PA, as sketched in Figure 5. This bandwidth will be highest at
the point where the slope of the tangent drawn on this curve is
greatest—that is, for power outputs near the center of the PA’s
range—and will be much reduced at both the minimum and
the maximum power levels, where the slope of the gain control
curve is lowest, due to its S-shaped form.

Using smaller values of C

, the loop bandwidth will generally

FLT

increase, in inverse proportion to its value. Eventually, however,
a secondary effect will appear, due to the inherent phase lag in
the power amplifier’s control path, some of which may be due to
parasitic or deliberately added capacitance at the VAPC pin.
This results in the characteristic poles in the ac loop equation
moving off the real axis and thus becoming complex (and some­what resonant). This is a classic aspect of control loop design.
The lowest permissible value of C

needs to be determined

FLT

experimentally for a particular amplifier. For GSM and DCS
power amplifiers, C

will typically range from 150 pF to 300 pF.

FLT

In many cases, some improvement in the worst-case response
time can be achieved by including a small resistance in series
with C

; this generates an additional zero in the closed-loop

FLT

transfer function, that will serve to cancel some of the higher
order poles in the overall loop. A combination of main capacitor

shunted by a second capacitor and resistor in series will

C

FLT

also be useful in minimizing the settling time of the loop.

Mobile Handset Power Control Example

Figure 8 shows a complete power amplifier control circuit for a
dual mode handset. The PF08107B (Hitachi), a dual mode
(GSM, DCS) PA, is driven by a nominal power level of 3 dBm.

–12–

REV. B

3.5V

4.7F 4.7F

AD8315

TO

ANTENNA

8-BIT

RAMP DAC

0V–2.55V

BAND

SELECT

0V/2V

VCTL

VAPC

0.1F

8

7

6

5

1000pF

(OPTIONAL,

SEE TEXT)

+V

S

2.7V

500

LDC15D190A0007A

7

8

5

ATTN

20dB

R2*

600

R3*

1k

*R2, R3 OPTIONAL,

*SEE TEXT

2

ENABLE

0V/2.7V

6

52.3

150pF

1.5k

1

49.9

4

3

R1

1

2

3

4

NC = NO CONNECT

GSM

P

OUT

35dBm MAX

P

DCS

OUT

32dBm MAX

AD8315

RFIN

ENBL

VSET

1000pF

PF08107B

VPOS

VA PC

NC

COMMFLTR

Figure 8. Dual Mode (GSM/DCS) PA Control Example

PIN GSM
3dBm

DCS

P

IN

3dBm

The PA has a single gain control line; the band to be used is
selected by applying either 0 V or 2 V to the PA’s VCTL input.

Some of the output power from the PA is coupled off using a
dual-band directional coupler (Murata part number
LDC15D190A0007A). This has a coupling factor of approxi­mately 19 dB for the GSM band and 14 dB for DCS and an
insertion loss of 0.38 dB and 0.45 dB, respectively. Because the
PF08107B transmits a maximum power level of +35 dBm for
GSM and +32 dBm for DCS, additional attenuation of 20 dB is
required before the coupled signal is applied to the AD8315.
This results in peak input levels to the AD8315 of –4 dBm
(GSM) and –2 dBm (DCS). While the AD8315 gives a linear
response for input levels up to +2 dBm, for highly temperature­stable performance at maximum PA output power, the maxi­mum input level should be limited to approximately –2 dBm
(see TPC 3 and TPC 5). This does, however, reduce the sensi­tivity of the circuit at the low end.

The operational setpoint voltage, in the range 250 mV to 1.4 V, is
applied to the VSET Pin of the AD8315. This will typically be
supplied by a digital-to-analog converter (DAC). The AD8315’s
VAPC output drives the level control pin of the power amplifier
directly. V

reaches a maximum value of approximately 2.5 V

APC

on a 2.7 V supply while delivering the 3 mA required by the level
control input of the PA. This is more than sufficient to exercise
the gain control range of the PA.

During initialization and completion of the transmit sequence,
VAPC should be held at its minimum level of 250 mV by keeping
VSET below 200 mV.

In this example, V

is supplied by an 8-bit DAC that has an

SET

output range from 0 V to 2.55 V or 10 mV per bit. This sets the
control resolution of VSET to 0.4 dB/bit (0.04 dB/mV times
10 mV). If finer resolution is required, the DAC’s output voltage
can be scaled using two resistors as shown. This converts the
DAC’s maximum voltage of 2.55 V down to 1.6 V and increases
the control resolution to 0.25 dB/bit.

A filter capacitor (C
choice of C

will depend to a large degree on the gain control

FLT

) must be used to stabilize the loop. The

FLT

dynamics of the power amplifier, something that is frequently
poorly characterized, so some trial and error may be necessary.

In this example, a 150 pF capacitor is used and a 1.5 kW series
resistor is included. This adds a zero to the control loop and
increases the phase margin, which helps to make the step response
of the circuit more stable when the PA output power is low and
the slope of the PA’s power control function is the steepest.

A smaller filter capacitor can be used by inserting a series
resistor between VAPC and the control input of the PA.
A series resistor will work with the input impedance of the
PA to create a resistor divider and will reduce the loop gain. The
size of the resistor divider ratio depends upon the available
output swing of V

and the required control voltage on the PA.

APC

This technique can also be used to limit the control voltage in
situations where the PA cannot deliver the power level being
demanded by VAPC. Overdrive of the control input of some
PAs causes increased distortion. It should be noted, however,
that if the control loop opens (i.e., VAPC goes to its maxi­mum value in an effort to balance the loop), the quiescent current
of the AD8315 will increase somewhat, particularly at supply
voltages greater than 3 V.

REV. B

–13–

AD8315

Figure 9 shows the relationship between V
power (P

) at 0.9 GHz . The overall gain control function is

OUT

linear in dB for a dynamic range of over 40 dB. Note that for V

and output

SET

SET

voltages below 300 mV, the output power drops off steeply as
VAPC drops toward its minimum level of 250 mV.

1.6

4

3

2

1

0

–1

–2

–3

–4

ERROR – dB

40

30

20

10

0

– dBm

OUT

P

–10

–20

–30

–40

0

Figure 9. P

+85 C

+25 C

+25 C

–30 C

–30 C

0.2 0.4 0.6 0.8 1.0 1.2 1.4

vs. V

OUT

SET

V

– V

SET

at 0.9 GHz for Dual Mode Handset

+85 C

Power Amplifier Application; –30∞C, +25∞C, and +85∞C

Enable and Power-On

The AD8315 may be disabled by pulling the ENBL pin to ground.
This reduces the supply current from its nominal level of 7.4 mA
to 4 mA. The logic threshold for turning on the device is at 1.5 V
with 2.7 V supply voltage. A plot of the enable glitch is shown in
TPC 20. Alternatively, the device can be completely disabled by
pulling the supply voltage to ground. To minimize glitch in this
mode, ENBL and VPOS should be tied together. If VPOS is
applied before the device is enabled, a narrow 750 mV glitch will
result (see TPC 27).

In both situations, the voltage on VSET should be kept below
200 mV during power-on and power-off to prevent any unwanted
transients on VAPC.

Input Coupling Options

The internal 5 pF coupling capacitor of the AD8315, along with
the low frequency input impedance of 2.8 kW, give a high-pass
input corner frequency of approximately 16 MHz. This sets the
minimum operating frequency. Figure 10 shows three options for
input coupling. A broadband resistive match can be implemented
by connecting a shunt resistor to ground at RFIN (Figure 10a).
This 52.3 W resistor (other values can also be used to select differ­ent overall input impedances) combines with the input impedance
of the AD8315 to give a broadband input impedance of 50 W.
While the input resistance and capacitance (C

and RIN) of the

IN

AD8315 will vary from device to device by approximately ±20%,
and over frequency (TPC 9), the dominance of the external shunt
resistor means that the variation in the overall input impedance
will be close to the tolerance of the external resistor. This method
of matching is most useful in wideband applications or in multi­band systems where there is more than one operating frequency.

A reactive match can also be implemented as shown in Figure 10b.
This is not recommended at low frequencies as device tolerances
will dramatically vary the quality of the match because of the large
input resistance. For low frequencies, Option 10a or Option 10c
is recommended.

In Figure 10b, the matching components are drawn as generic
reactances. Depending on the frequency, the input impedance
and the availability of standard value components, either a capacitor
or an inductor will be used. As in the previous case, the input
impedance at a particular frequency is plotted on a Smith Chart
and matching components are chosen (shunt or series L, shunt or
series C) to move the impedance to the center of the chart.

AD8315

C

C

RFIN

R

SHUNT

52.3

R

C

IN

IN

a. Broadband Resistive

AD8315

C

RFIN

C

R

C

IN

IN

X1

X2

b. Narrow Band Reactive

ANTENNA

AD8315

C

C

STRIPLINE

PA

R

ATTN

RFIN

R

C

IN

IN

c. Series Attenuation

Figure 10. Input Coupling Options

Figure 10c shows a third method for coupling the input signal
into the AD8315. A series resistor, connected to the RF source,
combines with the input impedance of the AD8315 to resistively
divide the input signal being applied to the input. This has the
advantage of very little power being “tapped off” in RF power
transmission applications.

–14–

REV. B

AD8315

Using the Chip Scale Package

On the underside of the chip scale package, there is an exposed
paddle. This paddle is internally connected to the chip’s ground.
There is no thermal requirement to solder the paddle down to the
printed circuit board’s ground plane. However, soldering down
the paddle has been shown to increase the stability over frequency
of the AD8315 ACP’s response at low input power levels (i.e., at
around –45 dBm) in the DCS and PCS bands

.

Evaluation Board

Figure 11 shows the schematic of the AD8315 MSOP evaluation
board. The layout and silkscreen of the component side are
shown in Figures 12 and 13. An evaluation board is also available
for the LFCSP package (for exact part numbers, see Ordering
Guide). Apart from the slightly smaller device footprint, the
LFCSP evaluation board is identical to the MSOP board. The
board is powered by a single supply in the range, 2.7 V to 5.5 V.
The power supply is decoupled by a single 0.1 ␮F capacitor.
Table II details the various configuration options of the
evaluation board.

RFIN

VSET

R2

52.3

R1

J1

0

VPOS

SW1

J3

C4

(OPEN)

0.1F

AD8315

1

RFIN

2

ENBL

3

VSET

4

FLTR

NC = NO CONNECT

V

POS

C3

0.1F

C5

16.2k

AD8031

R5

10k

R7

VPOS

VAPC

COMM

NC

0.1F

8

7

6

5

R8
10k

R6

17.8k

C1

TP2

TP1

R3
0

R4

(OPEN)C2(OPEN)

LK2LK1

V

POS

Figure 11. Evaluation Board Schematic

Table II. Evaluation Board Configuration Options

Component Function Default Condition

TP1, TP2 Supply and Ground Vector Pins Not Applicable
SW1 Device Enable: When in Position A, the ENBL pin is connected to VPOS and SW1 = A

the AD8315 is in operating mode. In Position B, the ENBL pin is grounded
putting the device in power-down mode.

R1, R2 Input Interface: The 52.3 W resistor in Position R2 combines with the R2 = 52.3 W (Size 0603)

AD8315’s internal input impedance to give a broadband input impedance R1 = 0 W (Size 0402)
of around 50 W. A reactive match can be implemented by replacing R2 with
an inductor and R1 (0 W) with a capacitor. Note that the AD8315’s RF input
is internally ac-coupled.

R3, R4, C2 Output Interface: R4 and C2 can be used to check the response of V

capacitive and resistive loading. R3/R4 can be used to reduce the slope of V

to R4 = C2 = Open (Size 0603)

APC

.R3 = 0 W (Size 0603)

APC

C1 Power Supply Decoupling: The nominal supply decoupling consists of a C1 = 0.1 mF (Size 0603)

0.1 mF capacitor.

C4 Filter Capacitor: The response time of V

can be modified by placing a C4 = Open (Size 0603)

APC

capacitor between FLTR (Pin 4) and ground.

LK1, LK2 Measurement Mode: A quasi-measurement mode can be implemented by LK1, LK2 = Installed

installing LK1 and LK2 (connecting an inverted V
nominal relationship between RFIN and V

. In this mode, a large capacitor

SET

APC

to V

) to yield the

SET

(0.01 mF or greater) must be installed in C4.

J2

VAPC

REV. B

–15–

AD8315

Figure 12. Layout of Component Side (MSOP)

For operation in controller mode, both jumpers, LK1 and LK2,
should be removed. The setpoint voltage is applied to V

SET

,
RFIN is connected to the RF source (PA output or directional
coupler), and V

is connected to the gain control pin of the

APC

PA. When used in controller mode, a capacitor must be installed in

for loop stability. For GSM/DCS handset power amplifiers,

C

4

this capacitor should typically range from 150 pF to 300 pF.

A quasi-measurement mode (where the AD8315 delivers an
output voltage that is proportional to the log of the input signal)
can be implemented, to establish the relationship between V

SET

and RFIN, by installing the two jumpers, LK1 and LK2. This
mimics an AGC loop. To establish the transfer function of the
log amp, the RF input should be swept while the voltage on

is measured, that is, the SMA connector labeled VSET

V

SET

now acts as an output. This is the simplest method to validate
operation of the evaluation board. When operated in this mode,
a large capacitor (0.01 mF or greater) must be installed in C4
(filter capacitor) to ensure loop stability.

Figure 13. Silkscreen of Component Side (MSOP)

–16–

REV. B

OUTLINE DIMENSIONS

8-Lead microSOIC Package [MSOP]

(RM-8)

Dimensions shown in millimeters

3.00
BSC

AD8315

PIN 1

INDICATOR

1.00

0.90

0.80

SEATING

85

3.00
BSC

1

PIN 1

0.65 BSC

0.15

0.00

0.38

0.22

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187AA

4

SEATING
PLANE

4.90

BSC

1.10 MAX

0.23

0.08

8
0

8-Lead Lead Frame Chip Scale Package [LFCSP]

2 mm  3 mm Body

(CP-8)

Dimensions shown in millimeters

1.89

1.74

1.59

58

BOTTOM VIEW

4

1.95

1.75

1.55

PLANE

3.25

3.00

2.75

2.25

2.00

1.75

2.95

2.75

2.55

12

0

0.30

0.23

0.18

NOTES

1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS.

2. PADDLE IS COPPER PLATED WITH LEAD FINISH.

0.60

0.45

0.30

0.50 BSC

1.00 MAX

0.65 NOM

0.05

0.02

0.00

0.20 REF

0.80

0.40

0.55

0.40

0.30

0.15

1

0.10

0.05

0.25

0.20

0.15

REV. B

–17–

AD8315

Revision History

Location Page

1/03—Data Sheet changed from REV. 0 to REV. B.

Edits to PRODUCT DESCRIPTION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edit to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

ORDERING GUIDE updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

TPC 9 replaced with new figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edits to TPC 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Edit to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Edit to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Edit to Equation 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Edit to Equation 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Edit to Equation 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Edits to Example section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Edit to Basic Connections section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Edits to Input Coupling Options section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table III becomes Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table II Recommended Components deleted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Using the Chip-Scale Package section added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Edits to Evaluation Board section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 12 title edited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 13 title edited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8-Lead Chip Scale Package (CP-8) added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

–18–

REV. B

–19–

C01520-0-1/03(B)

–20–

PRINTED IN U.S.A.