Page 1
X1
X2
Y1
Y2
V
P
OUT
NC
V
N
AD830
NC = NO CONNECT
1
2
3
4
8
7
6
5
A=1
V→1
V→1
High Speed, Video
9
–6
–21
100k 1G10M1M10k
–3
0
3
6
–18
–15
–12
–9
FREQUENCY – Hz
GAIN – dB
100M
VS = ±5V
RL = 150Ω
CL = 4.7pF
CL = 15pF
CL = 33pF
a
FEATURES
Differential Amplification
Wide Common-Mode Voltage Range: +12.8 V, –12 V
Differential Voltage Range: 62 V
High CMRR: 60 dB @ 4 MHz
Built-in Differential Clipping Level: 62.3 V
Fast Dynamic Performance
85 MHz Unity Gain Bandwidth
35 ns Settling Time to 0.1%
360 V/ms Slew Rate
Symmetrical Dynamic Response
Excellent Video Specifications
Differential Gain Error: 0.06%
Differential Phase Error: 0.088
15 MHz (0.1 dB) Bandwidth
Flexible Operation
High Output Drive of 650 mA min
Specified with Both 65 V and 615 V Supplies
Low Distortion: THD = –72 dB @ 4 MHz
Excellent DC Performance: 3 mV max Input Offset
Voltage
APPLICATIONS
Differential Line Receiver
High Speed Level Shifter
High Speed In-Amp
Differential to Single Ended Conversion
Resistorless Summation and Subtraction
High Speed A/D Driver
PRODUCT DESCRIPTION
The AD830 is a wideband, differencing amplifier designed for
use at video frequencies but also useful in many other applications. It accurately amplifies a fully differential signal at the
110
Difference Amplifier
AD830
CONNECTION DIAGRAM
8-Pin Plastic Mini-DIP (N),
Cerdip (Q) and SOIC (R) Packages
input and produces an output voltage referred to a user-chosen
level. The undesired common-mode signal is rejected, even at
high frequencies. High impedance inputs ease interfacing to finite source impedances and thus preserve the excellent
common-mode rejection. In many respects, it offers significant
improvements over discrete difference amplifier approaches, in
particular in high frequency common-mode rejection.
The wide common-mode and differential-voltage range of the
AD830 make it particularly useful and flexible in level shifting
applications, but at lower power dissipation than discrete solutions. Low distortion is preserved over the many possible differential and common-mode voltages at the input and output.
Good gain flatness and excellent differential gain of 0.06% and
phase of 0.08° make the AD830 suitable for many video system
applications. Furthermore, the AD830 is suited for general purpose signal processing from dc to 10 MHz.
100
90
80
70
CMRR – dB
60
50
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
40
30
1k
Common-Mode Rejection Ratio vs. Frequency
FREQUENCY – Hz
VS = ±15V
VS = ±5V
1M100k10k
10M
Closed-Loop Gain vs. Frequency, Gain = +1
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
Page 2
AD830–SPECIFICA TIONS
(VS = 615 V, R
= 150 V, C
LOAD
= 5 pF, TA = +258C unless otherwise noted)
LOAD
AD830J/A AD830S
1
Parameter Conditions Min Typ Max Min Typ Max Units
DYNAMIC CHARACTERISTICS
3 dB Small Signal Bandwidth Gain = 1, V
0.1 dB Gain Flatness Frequency Gain = 1, V
= 100 mV rms 75 85 75 85 MHz
OUT
= 100 mV rms 11 15 11 15 MHz
OUT
Differential Gain Error 0 to +0.7 V, Frequency = 4.5 MHz 0.06 0.09 0.06 0.09 %
Differential Phase Error 0 to +0.7 V, Frequency = 4.5 MHz 0.08 0.12 0.08 0.12 Degrees
Slew Rate 2 V Step, R
4 V Step, R
3 dB Large Signal Bandwidth Gain = 1, V
Settling Time, Gain = 1 V
V
OUT
OUT
= 500 Ω 360 360 V/µs
L
= 500 Ω 350 350 V/µs
L
= 1 V rms 38 45 38 45 MHz
OUT
= 2 V Step, to 0.1% 25 25 ns
= 4 V Step, to 0.1% 35 35 ns
Harmonic Distortion 2 V p-p, Frequency = 1 MHz –82 –82 dBc
2 V p-p, Frequency = 4 MHz –72 –72 dBc
Input Voltage Noise Frequency = 10 kHz 27 27 nV/√
Input Current Noise 1.4 1.4 pA/√Hz
DC PERFORMANCE
Offset Voltage Gain = 1 ±1.5 ±3 ±1.5 ±3mV
Gain = 1, T
MIN–TMAX
±5 ±7mV
Open Loop Gain DC 64 69 64 69 dB
Gain Error R
= 1 kΩ, G = ±1 ±0.1 ±0.6 ±0.1 ±0.6 %
L
Peak Nonlinearity, RL= 1 kΩ, –1 V ≤ X ≤ +1 V 0.01 0.03 0.01 0.03 % FS
Gain = 1 –1.5 V ≤ X ≤ +1.5 V 0.035 0.07 0.035 0.07 % FS
–2 V ≤ X ≤ +2 V 0.15 0.4 0.15 0.4 % FS
Input Bias Current V
Input Offset Current VIN = 0 V, T
= 0 V, +25°C to T
IN
V
= 0 V, T
IN
MIN
MIN–TMAX
MAX
510 510µA
713 817µA
0.1 1 0.1 1 µA
INPUT CHARACTERISTICS
Differential Voltage Range V
Differential Clipping Level
2
Common-Mode Voltage Range V
= 0 ±2.0 ±2.0 V
CM
Pins 1 and 2 Inputs Only ±2.1 ±2.3 ±2.1 ±2.3 V
= ±1 V –12.0 +12.8 –12.0 +12.8 V
DM
CMRR DC, Pins 1, 2, ±10 V 90 100 90 100 dB
DC, Pins 1, 2, ±10 V, T
MIN–TMAX
88 86 dB
Frequency = 4 MHz 55 60 55 60 dB
Input Resistance 370 370 kΩ
Input Capacitance 2 2 pF
Hz
OUTPUT CHARACTERISTICS
Output Voltage Swing R
≥ 1 kΩ±12 +13.8, –13.8 ±12 +13.8, –13.8 V
L
RL ≥ 1 kΩ, ±16.5 V
S
±13 +15.3, –14.7 ±13 +15.3, –14.7 V
Short Circuit Current Short to Ground ±80 ±80 mA
Output Current RL = 150 Ω±50 ±50 mA
POWER SUPPLIES
Operating Range ±4 ±16.5 ±4 ±16.5 V
Quiescent Current T
MIN–TMAX
14.5 17 14.5 17 mA
+ PSRR (to VP) DC, G = 1 86 86 dB
– PSRR (to V
PSRR DC, G = 1, ±5 to ±15 V
PSRR DC, G = 1, ±5 to ±15 V
NOTES
1
See Standard Military Drawing 5962-9313001MPA for specifications.
2
Clipping level function on X channel only.
Specifications subject to change without notice.
) DC, G = 1 68 68 dB
N
S
,
T
MIN–TMAX
S
66 71 66 71 dB
62 68 60 68 dB
–2–
REV. A
Page 3
AD830
(VS = 65 V, R
Parameter Conditions Min Typ Max Min Typ Max Units
DYNAMIC CHARACTERISTICS
3 dB Small Signal Bandwidth Gain = 1, V
0.1 dB Gain Flatness Frequency Gain = 1, V
Differential Gain Error 0 to +0.7 V, Frequency = 4.5 MHz,
Differential Phase Error 0 to +0.7 V, Frequency = 4.5 MHz,
Slew Rate, Gain = 1 2 V Step, R
3 dB Large Signal Bandwidth Gain = 1, V
Settling Time V
Harmonic Distortion 2 V p-p, Frequency = 1 MHz –69 –69 dBc
Input Voltage Noise Frequency = 10 kHz 27 27 nV/√
Input Current Noise 1.4 1.4 pA/√Hz
DC PERFORMANCE
Offset Voltage Gain = 1 ±1.5 ±3 ±1.5 ±3mV
Open Loop Gain DC 60 65 60 65 dB
Unity Gain Accuracy R
Peak Nonlinearity, RL= 1 kΩ –1 V ≤ X ≤ +1 V 0.01 0.03 0.01 0.03 % FS
Input Bias Current V
Input Offset Current VIN = 0 V, T
INPUT CHARACTERISTICS
Differential Voltage Range V
Differential Clipping Level
Common-Mode Voltage Range V
CMRR DC, Pins 1, 2, +4 V to –2 V 90 100 90 100 dB
Input Resistance 370 370 kΩ
Input Capacitance 2 2 pF
OUTPUT CHARACTERISTICS
Output Voltage Swing R
Short Circuit Current Short to Ground –55, +70 –55, +70 mA
Output Current ±40 ±40 mA
= 150 V, C
LOAD
= 5 pF, TA = +258C unless otherwise noted)
LOAD
= 100 mV rms 35 40 35 40 MHz
OUT
= 100 mV rms 5 6.5 5 6.5 MHz
OUT
G = +2 0.14 0.18 0.14 0.18 %
G = +2 0.32 0.4 0.32 0.4 Degrees
= 500 Ω 210 210 V/µs
L
4 V Step, RL = 500 Ω 240 240 V/µs
= 1 V rms 30 36 30 36 MHz
OUT
= 2 V Step, to 0.1% 35 35 ns
OUT
V
= 4 V Step, to 0.1% 48 48 ns
OUT
2 V p-p, Frequency = 4 MHz –56 –56 dBc
Gain = 1, T
= 1 kΩ±0.1 ±0.6 ±0.1 ±0.6 %
L
MIN–TMAX
–1.5 V ≤ X ≤ +1.5 V 0.045 0.07 0.045 0.07 % FS
–2 V ≤ X ≤ +2 V 0.23 0.4 0.23 0.4 % FS
= 0 V, +25°C to T
IN
V
= 0 V, T
IN
= 0 ±2.0 ±2.0 V
2
CM
Pins 1 and 2 Inputs Only ±2.0 ±2.2 ±2.0 ±2.2 V
= ±1 V –2.0 +2.9 –2.0 +2.9 V
DM
MIN
MIN–TMAX
MAX
DC, Pins 1, 2, +4 V to –2 V,
T
MIN–TMAX
Frequency = 4 MHz 55 60 55 60 dB
≥ 150 Ω±3.2 ±3.5 ±3.2 ±3.5 V
L
RL ≥ 150 Ω, ±4 V
S
AD830J/A AD830S
1
±4 ±5mV
510 510µA
713 817µA
0.1 1 0.1 1 µA
88 86 dB
±2.2 +2.7, –2.4 ±2.2 +2.7, –2.4 V
Hz
POWER SUPPLIES
Operating Range ±4 ±16.5 ±4 ±16.5 V
Quiescent Current T
+ PSRR (to V
) DC, G = 1, Offset 86 86 dB
P
MIN–TMAX
13.5 16 13.5 16 mA
– PSRR (to VN) DC, G = 1, Offset 68 68 dB
PSRR (Dual Supply) DC, G = 1, ±5 to ±15 V
S
66 71 66 71 dB
PSRR (Dual Supply) DC, G = 1, ±5 to ±15 VS,
T
MIN–TMAX
NOTES
1
See Standard Military Drawing 5962-9313001MPA for specifications.
2
Clipping level function on X channel only.
Specifications subject to change without notice.
REV. A
62 68 60 68 dB
–3–
Page 4
AD830
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18 V
Internal Power Dissipation
2
. . . . . . . Observe Derating Curves
1
Output Short Circuit Duration . . . . Observe Derating Curves
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . .±V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . .±V
S
S
Storage Temperature Range (Q) . . . . . . . . . –65°C to +150°C
Storage Temperature Range (N) . . . . . . . . . –65°C to +125°C
Storage Temperature Range (R) . . . . . . . . . –65°C to +125°C
Operating Temperature Range
AD830J . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C
AD830A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD830S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range (Soldering 60 seconds) . . . +300 °C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
8-Pin Plastic Package: θJA = 90°C/Watt
8-Pin SOIC Package: θJA = 155°C/Watt
8-Pin Cerdip Package: θJA = 110°C/Watt
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD830 is limited by the associated rise in junction temperature.
For the plastic packages, the maximum safe junction temperature is 145°C. For the cerdip, the maximum junction temperature is 175°C. If these maximums are exceeded momentarily,
proper circuit operation will be restored as soon as the die temperature is reduced. Leaving the AD830 in the “overheated”
condition for an extended period can result in permanent damage to the device. To ensure proper operation, it is important to
observe the recommended derating curves.
While the AD830 output is internally short circuit protected,
this may not be sufficient to guarantee that the maximum junction temperature is not exceeded under all conditions. If the
output is shorted to a supply rail for an extended period, then
the amplifier may be permanently destroyed.
ESD SUSCEPTIBILITY
ESD (electrostatic discharge) sensitive device. Electrostatic
charges as high as 4000 volts, which readily accumulate on the
human body and on test equipment, can discharge without detection. Although the AD830 features proprietary ESD protection circuitry, permanent damage may still occur on these
devices if they are subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid any performance degradation or loss of functionality.
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD830AN –40°C to +85°C 8-Pin Plastic Mini-DIP N-8
AD830JR 0°C to +70°C 8-Pin SOIC R-8
5962-9313001MPA* –55°C to +125°C 8-Pin Cerdip Q-8
*See Standard Military Drawing for specifications.
2.5
2.0
1.5
1.0
0.5
TOTAL POWER DISSIPATION – Watts
0
–50
8-PIN SOIC
–30
AMBIENT TEMPERATURE – °C
8-PIN MINI-DIP
TJ MAX = 145°C
70503010–10
90
3.0
2.8
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
TOTAL POWER DISSIPATION – Watts
0.4
0.2
–60
8-PIN CERDIP
–40
AMBIENT TEMPERATURE – °C
TJ MAX = 175°C
100 120806040200–20
140
Maximum Power Dissipation vs. Temperature,
Mini-DlP and SOIC Packages
–4–
Maximum Power Dissipation vs. Temperature,
Cerdip Package
REV. A
Page 5
Typical Characteristics–
FREQUENCY – Hz
3
–12
–27
100k 100M10M1M10k
–9
–6
–3
0
–24
–21
–18
–15
GAIN – dB
±15V
±5V
1G
±10V
RL = 150Ω
CL = 4.7pF
JUNCTION TEMPERATURE – °C
INPUT OFFSET VOLTAGE – mV
3
–4
140
–1
–3
–40
–2
–60
2
0
1
120100806040200–20
±5V
S
±15V
S
±10V
S
AD830
110
100
90
80
70
CMRR – dB
60
50
40
30
1k
FREQUENCY – Hz
VS = ±5V
1M100k10k
VS = ±15V
10M
Figure 1. Common-Mode Rejection Ratio vs. Frequency
–50
V
= 2V p-p
OUT
RL = 150Ω
GAIN = +1
–60
–70
±5V SUPPLIES
2ND HARMONIC
3RD HARMONIC
100
90
TO VP @ ±5V
80
TO VN @ ±15V
70
60
TO VN @ ±5V
50
PSRR – dB
40
30
20
10
1k
TO VP @ ±15V
FREQUENCY – Hz
1M100k10k
10M
Figure 4. Power Supply Rejection Ratio vs. Frequency
–80
HARMONIC DISTORTION – dBc
–90
Figure 2. Harmonic Distortion vs. Frequency
9
8
7
6
5
INPUT CURRENT – µA
4
REV. A
3
Figure 3. Input Bias Current vs. Temperature
–40
–60
±15V SUPPLIES
2ND HARMONIC
3RD HARMONIC
10k 10M1M100k1k
FREQUENCY – Hz
JUNCTION TEMPERATURE – °C
Figure 5. Closed-Loop Gain vs. Frequency G = +1
140
120806040 100200–20
Figure 6. Input Offset Voltage vs. Temperature
–5–
Page 6
AD830
0.20
15
0.06
0.02
6
0.04
5
0.12
0.08
0.10
0.14
0.16
0.18
1413121110987
SUPPLY VOLTAGE – ±Volts
DIFFERENTIAL GAIN – %
DIFFERENTIAL PHASE – Degrees
GAIN
PHASE
0.40
0.12
0.04
0.08
0.24
0.16
0.20
0.28
0.32
0.36
GAIN = +2
R
L
= 150Ω
FREQ = 4.5MHz
JUNCTION TEMPERATURE – °C
QUIESCENT SUPPLY CURRENT– mA
15.00
12.25
140
13.00
12.50
–40
12.75
–60
13.75
13.25
13.50
14.00
14.25
14.50
14.75
120100806040200–20
±16.5V
S
±5V
S
0.10
0.09
0.08
0.07
0.06
0.05
0.04
DIFFERENTIAL GAIN – %
0.03
0.02
0.01
PHASE
GAIN
SUPPLY VOLTAGE – ±Volts
GAIN = +2
R
= 500Ω
L
FREQ = 4.5MHz
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
DIFFERENTIAL PHASE – Degrees
0.01
1565
1413121110987
Figure 7. Differential Gain and Phase vs. Supply Voltage,
= 500
R
L
Ω
–40
–50
–60
–70
–80
HARMONIC DISTORTION – dB
–90
–100
0.25
0.50
PEAK AMPLITUDE – Volts
HD3 (±5V)
100kHz
HD2 (±5V)
100kHz
HD3 (±15V)
100kHz
HD2 (±15V)
100kHz
1.751.251.000.75 1.50
2.00
Figure 8. Harmonic Distortion vs. Peak Amplitude,
Frequency = 100 kHz
Figure 10. Differential Gain and Phase vs. Supply Voltage,
= 150
R
L
Ω
–40
–50
–60
–70
–80
HARMONIC DISTORTION – dB
–90
–100
HD3 (±5V)
4MHz
0.25
HD2 (±5V)
4MHz
0.50
HD3 (±15V)
4MHz
PEAK AMPLITUDE – Volts
HD2 (±15V)
4MHz
1.751.251.000.75 1.50
2.00
Figure 11. Harmonic Distortion vs. Peak Amplitude,
Frequency = 4 MHz
50
40
30
20
INPUT VOLTAGE NOISE – nV/√Hz
10
100
Figure 9. Noise Spectral Density
1k
FREQUENCY – Hz
100k 1M10k
10M
Figure 12. Supply Current vs. Junction Temperature
–6–
REV. A
Page 7
Typical Characteristics–
V
1
V
P
OUT
V
N
V
OUT
= 2V
1
RESISTOR LESS GAIN OF 2
1
2
4
3
8
7
5
6
AD830
C
A=1
G
M
G
M
V
OUT
= V
1
GAIN OF 1
V
1
V
P
OUT
V
N
1
2
4
3
8
7
5
6
AD830
C
A=1
G
M
G
M
V
OUT
= V
1
OP-AMP CONNECTION
V
1
V
P
OUT
V
N
1
2
4
3
8
7
5
6
AD830
C
A=1
G
M
G
M
(a)
(b)
(c)
10
90
100
0%
1V
20
ns
V
S
= ± 15V
VS = ± 5V
AD830
3
0
RL = 150Ω
–3
CL = 0pF
–6
–9
–12
–15
–18
UNITY GAIN CONNECTION
–21
–24
–27
1M 1G100M10M100k
±15V
±5V
FREQUENCY – Hz
9
6
3
0
–3
–6
–9
–12
–15
–18
–21
Figure 13. Closed-Loop Gain vs. Frequency for the
Three Common Connections of Figure 16
100mV
VS = ± 5V
100
90
GAIN OF 2 CONNECTION
Figure 15. Closed-Loop Gain vs. Frequency vs.
C
REV. A
VS = ± 15V
10
0%
ns
20
Figure 14. Small Signal Pulse Response,
= 150 Ω, CL = 4.7 pF, G = +1
R
L
9
6
3
0
–3
–6
GAIN – dB
–9
–12
–15
–18
–21
, G = +1. VS = ±5 V
L
VS = ±5V
RL = 150Ω
CL = 4.7pF
CL = 33pF
CL = 15pF
100k 1G10M1M10k
100M
FREQUENCY – Hz
–7–
Figure 16. Connection Diagrams
Figure 17. Large Signal Pulse Response,
R
= 150 Ω, CL = 4.7 pF, G = +1
L
9
VS = +15V
6
3
0
–3
–6
GAIN – dB
–9
–12
–15
–18
–21
RL = 150Ω
100k 100M10M1M10k
FREQUENCY – Hz
CL = 33pF
CL = 15pF
CL = 4.7pF
1G
Figure 18. Closed-Loop Gain vs. Frequency, vs.
, G = +1. VS = ±15 V
C
L
Page 8
AD830
A=1
V
→ I
V→ I
V
OUT
V
2
V
1
V
OUT
= V1 – V
2
I
Y
I
X
TRADITIONAL DIFFERENTIAL AMPLIFICATION
In the past, when differential amplification was needed to reject
common-mode signals superimposed with a desired signal; most
often the solution used was the classic op amp based difference
amplifier shown in Figure 19. The basic function V
= V1–V2 is
O
simply achieved, but the overall performance is poor and the circuit possesses many serious problems that make it difficult to realize a robust design with moderate to high levels of
performance.
R
V
2
V
1
1
R
3
R
4
R
2
ONLY IF R
DOES
VOUT
V
OUT
= R2 = R3 = R
1
= V1 – V
4
2
Figure 19. Op Amp Based Difference Amplifier
PROBLEMS WITH THE OP AMP BASED APPROACH
• Low Common-Mode Rejection Ratio (CMRR)
• Low Impedance Inputs
• CMRR Highly Sensitive to the Value of Source R
• Different Input Impedance for the + and – Input
• Poor High Frequency CMRR
• Requires Very Highly Matched Resistors R
to Achieve
1–R4
High CMRR
• Halves the Bandwidth of the Op Amp
• High Power Dissipation in the Resistors for Large CommonMode Voltage
AD830 FOR DIFFERENTIAL AMPLIFICATION
The AD830 amplifier was specifically developed to solve the
listed problems with the discrete difference amplifier approach.
Its topology, discussed in detail in a later section, by design acts
as a difference amplifier. The circuit of Figure 20 shows how
simply the AD830 is configured to produce the difference of two
signals V
and V2, in which the applied differential signal is
1
exactly reproduced at the output relative to a separate output
common. Any common-mode voltage present at the input is
removed by the AD830.
Figure 20. AD830 as a Difference Amplifier
ADVANTAGEOUS PROPERTIES OF THE AD830
• High Common-Mode Rejection Ratio (CMRR)
• High Impedance Inputs
• Symmetrical Dynamic Response for +1 and –1 Gain
• Low Sensitivity to the Value of Source R
• Equal Input Impedance for the + and – Input
• Excellent High Frequency CMRR
• No Halving of the Bandwidth
• Constant Power Distortion vs. Common-Mode Voltage
• Highly Matched Resistors Not Needed
–8–
REV. A
Page 9
UNDERSTANDING THE AD830 TOPOLOGY
A=1
V
OUT
V
X2
V
X1
V
X1
– VX2 = V
Y
2
– V
Y1
FOR V
Y2
= V
OUT
V
OUT
= (V
X1
– V
X2
+ VY1)
I
Y
I
X
V
Y2
V
Y1
G
M
G
M
1
1 + S(C
C /GM
)
C
C
The AD830 represents Analog Devices’ first amplifier product
to embody a powerful alternative amplifier topology. Referred to
as active feedback, the topology used in the AD830 provides inherent advantages in the handling of differential signals, differing system commons, level shifting and low distortion, high
frequency amplification. In addition, it makes possible the
implementation of many functions not realizable with single op
amp circuits or is superior to op amp based equivalent circuits.
With this in mind, it is important to understand the internal
structure of the AD830.
The topology, reduced to its elemental form, is shown below in
Figure 21. Nonideal effects such as nonlinearity, bias currents
and limited full scale are omitted from this model for simplicity,
but are discussed later. The key feature of this topology is the
use of two, identical voltage-to-current converters, G
, that
M
make up input and feedback signal interfaces. They are labeled
with inputs V
and VY, respectively. These voltage to current
X
converters possess fully differential inputs, high linearity, high
input impedance and wide voltage range operation. This enables
the part to handle large amplitude differential signals; they also
provide high common-mode rejection, low distortion and negligible loading on the source. The label, G
, is meant to convey
M
that the transconductance is a large signal quantity, unlike in the
front-end of most op amps. The two G
I
and IY, sum together at a high impedance node which is char-
X
stage current outputs
M
acterized by an equivalent resistance and capacitance connected
to an “ac common.” A unity voltage gain stage follows the high
impedance node to provide buffering from loads. Relative to
either input, the open loop gain, A
transconductance, G
G
3 RP. The unity gain frequency ω0 dB for the open loop gain
M
, working into the resistance, RP; AOL =
M
is established by the transconductance, G
capacitance, C
; ω0 dB = GM/CC. The open loop description of
C
, is set by the
OL
, working into the
M
the AD830 is shown below for completeness.
V
X1
G
V
X2
V
Y1
V
Y2
M
I
X
I
Z
I
Y
G
M
C
C
A=1 V
R
P
I
= (V
X
X1
I
= (V
Y
Y1
IZ = IX + IY
A
=
OLS
OUT
– VX2) G
– V
) G
Y2
G
M RP
1 + S (C
M
M
C RP
)
AD830
Figure 22. Closed-Loop Connection
Precise amplification is accomplished through closed-loop operation of this topology. Voltage feedback is implemented via
the Y G
–Y input for negative feedback as shown in Figure 22. An input
signal is applied across the X G
or single-ended referred to common. It produces a current signal which is summed at the high impedance node with the output current from the Y G
sum to a small error current necessary to develop the output
voltage at the high impedance node. The error current is usually
negligible, so the null condition essentially forces the Y G
output stage current to exactly equal the X GM output current.
Since the two transconductances are identical, the differential
voltage across the Y inputs equals the negative of the differential
voltage across the X input; V
V
Y2–VY1
easily analyze any function possible to synthesize with the
AD830, including any feedback situation.
The bandwidth of the circuit is defined by the G
capacitor C
single pole response, excluding the output amplifier and loading
effects. It is important to note that the bandwidth and general dy-
namic behavior is symmetrical (identical) for the noninverting and
the inverting connections of the AD830. In addition, the input im-
pedance and CMRR are the same for either connections. This is
very advantageous and unlike in a voltage or current feedback
amplifier, where there is a distinct difference in performance between the inverting and noninverting gain. The practical importance of this cannot be overemphasized and is a key feature
offered by the AD830 amplifier topology.
stage in which where the output is connected to the
M
stage, either fully differentially
M
stage. Negative feedback nulls this
M
M
= –VX or more precisely
Y
= VX1–VX2. This simple relation provides the basis to
and the
. The highly linear GM stages give the amplifier a
C
M
REV. A
Figure 21. Topology Diagram
–9–
Page 10
AD830
10
90
100
0%
1V 1V
15
0
20
3
0
6
9
12
161284
SUPPLY VOLTAGE – Volts
MAXIMUM OUTPUT SWING – ±Volts
V
P
VN
INTERFACING THE INPUT
Common-Mode Voltage Range
The common-mode range of the AD830 is defined by the amplitude of the differential input signal and the supply voltage.
The general definition of common-mode voltage, V
, is usu-
CM
ally applied to a symmetrical differential signal centered about a
particular voltage as illustrated by the diagram in Figure 23.
This is the meaning implied here for common-mode voltage.
The internal circuitry establishes the maximum allowable voltage on the input or feedback pins for a given supply voltage.
This constraint and the differential input voltage sets the
common-mode voltage limit. Figure 24 shows a curve of the
common-mode voltage range vs. differential voltage for three
supply voltage settings.
V
MAX
V
V
PEAK
CM
Figure 23. Common-Mode Definition
15
12
–V
CM
9
+V
CM
±15V = V
S
+V
CM
±10V = V
S
Differential Voltage Range
The maximum applied differential voltage is limited by the clipping range of the input stages. This is nominally set at 2.4 volts
magnitude and depicted in the crossplot (X-Y) photo of Figure
25. The useful linear range of the input stages is set at 2 volts,
but is actually a function of the distortion required for a particular application. The distortion increases for larger differential
input voltages. A plot of relative distortion versus input differential voltage is shown in Figures 8 and 11 in the Typical Characteristics section. The distortion characteristics could impose a
secondary limit to the differential input voltage for high accuracy applications.
Figure 25. Clipping Behavior
6
3
COMMON-MODE VOLTAGE – ±Volts
0
0
DIFFERENTIAL INPUT VOLTAGE – V
–V
CM
+V
CM
±5V = V
S
–V
CM
1.61.20.80.4
PEAK
2.0
Figure 24. Input Common-Mode Voltage Range vs.
Differential Input Voltage
Figure 26. Maximum Output Swing vs. Supply
–10–
REV. A
Page 11
AD830
5
8
4
1
2
3
7
6
A=1
AD830
G
M
C
G
M
+
–
INPUT
SIGNAL
+V
S
0.1µF
R
S
36.5Ω
V
OUT
R
S
C
1
100pF
R
1
1kΩ
R
1
0.1µF
–V
S
* OPTIONAL
FEEDBACK
NETWORK
Z
CM
V
CM
Choice of Polarity
The sign of the gain is easily selected by choosing the polarity of
the connections to the + and – inputs of the X G
stage. Swap-
M
ping between inverting and noninverting gain is possible simply
by reversing the input connections. The response of the amplifier is identical in either connection, except for the sign change.
The bandwidth, high impedance, transient behavior, etc., of the
AD830, is symmetrical for both polarities of gain. This is very
advantageous and unlike an op amp.
Input Impedance
The relatively high input impedance of the AD830, for a differential receiver amplifier, permits connections to modest impedance sources without much loading or loss of common-mode
rejection. The nominal input resistance is 300 kΩ. The real limit
to the upper value of the source resistance is in its effect on
common-mode rejection and bandwidth. If the source resistance
is in only one input, then the low frequency common-mode rejection will be lowered to ≈ R
1
f =
2π
× RS×C
capacitance pole
Furthermore, the high frequency common-mode rejection will
. The source resistance/input
IN/RS
IN
limits the bandwidth.
be additionally lowered by the difference in the frequency response caused by the R
3 CIN pole. Therefore, to maintain
S
the peak output differential voltage can be easily derived from
the maximum output swing as V
OCM
= V
MAX–VPEAK
.
Output Current
The absolute peak output current is set by the short circuit current limiting, typically greater that 60 mA. The maximum drive
capability is rated at 50 mA, but without a guarantee of distortion performance. Best distortion performance is obtained by
keeping the output current ≤20 mA. Attempting to drive large
voltages into low valued resistances (e.g., 10 V into 150 Ω) will
cause an apparent lowering of the limit for output signal swing,
but is just the current limiting behavior.
Driving Cap Loads
The AD830 is capable of driving modest sized capacitive loads
while maintaining its rated performance. Several curves of bandwidth versus capacitive load are given in Figures 15 and 18. The
AD830 was designed primarily as a low distortion video speed
amplifier, but with a tradeoff, giving up very large capacitive
load driving capability. If very large capacitive loads must be
driven, then the network shown in Figure 27 should be used to
insure stable operation. If the loss of gain caused by the resistor
R
in series with the load is objectionable, then the optional
S
feedback network shown may be added to restore the lost gain.
good low and high frequency common-mode rejection, it is recommended that the source resistances of the + and – inputs be
matched and of modest value (≤10 kΩ).
Handling Bias Currents
The bias currents are typically 4 µA flowing into each pin of the
G
stages of the AD830. Since all applications possess some fi-
M
nite source resistance, the bias current through this resistor will
create a voltage drop (I
pedance of the AD830 permits modest values of R
3 RS). The relatively high input im-
BIAS
, typically
S
≤10 kΩ. If the source resistance is in only one terminal, then an
objectional offset voltage may result (e.g., 4 µA 3 5 kΩ =
20 mV). Placement of an equal value resistor in series with the
other input will cancel the offset to first order. However, due to
mismatches in the resistances, a residual offset will remain and
likely be greater than bias current (offset current) mismatches.
Applying Feedback
The AD830 is intended for use with gain from 1 to 100. Gains
greater than one are simply set by a pair of resistors connected
as shown in the difference amplifier (Figure 35) with gain >1.
The value of the bottom resistor R
1 kΩ to insure that the pole formed by C
nection of R
and R2 is sufficiently high in frequency so that it
1
, should be kept less than
2
and the parallel con-
IN
does not introduce excessive phase shift around the loop and destabilizes the amplifier. A compensating resistor, equal to the
parallel combination of R
with the other Y G
common-mode rejection and to lower the offset voltage induced
by the input bias current.
Output Common Mode
The output swing of the AD830 is defined by the differential in-
stage input to preserve the high frequency
M
put voltage, the gain and the output common. Depending on
the anticipated signal span, the output common (or ground)
may be set anywhere between the allowable peak output voltage
in a manner similar to that described for input voltage common
mode. A plot of the peak output voltage versus supply is shown
in Figure 26. A prediction of the common-mode range versus
and R2, should be placed in series
1
Figure 27. Circuit for Driving Large Capacitive Loads
3
0
–3
–6
–9
–12
–15
–18
–21
–24
CLOSED-LOOP AMPLITUDE RESPONSE – dB
–27
100k 100M10M1M10k
FREQUENCY – Hz
±15V
±5V
Figure 28. Closed-Loop Response vs. Frequency with
100 pF Load and Series Resistor Compensation
REV. A
–11–
Page 12
AD830
5
8
4
1
2
3
7
6
A=1
AD830
G
M
C
+
–
V
P
+
–
+
–
V
OUT
V
OCM
V
ICM
V
IN
V
OUT
= (VIN – V
ICM
) + V
OCM
G
M
SUPPLIES, BYPASSING AND GROUNDING (FIGURE 29)
The AD830 is capable of operating over a wide range of supply
voltages, both single and dual supplies. The coupling may be dc
or ac provided the input and output voltages stay within the
specified common-mode voltage limits. For dual supplies, the
device works from ±4 V to ±16.5 V. Single supply operation is
possible over +8 V to +33 V. It is also possible to operate the
part with split supply voltages (e.g., +24 V, –5 V) for special
applications such as level shifting. The primary constraint is that
the total potential between the two supplies does not exceed
33 V.
Inclusion of power supply bypassing capacitors is necessary to
achieve stable behavior and the specified performance. It is especially important when driving low resistance loads. At a minimum, connect a 0.1 µF ceramic capacitor at the supply lead of
the AD830 package. In addition, for the best by passing, we recommend connecting a 0.01 µF ceramic capacitor and 4.7 µF
tantalum capacitor to the supply lead going to the AD830.
V
AND
V
V
P
N
0.1µF
LOAD
GND
LEAD
AND
V
P
N
0.01µF
4.7µF
LOAD
GND
LEAD
(a) (b)
Figure 29. Supply Decoupling Options
The AD830 is designed by its functionality to be capable of
rejecting noise and dissimilar potentials in the ground lines.
Therefore, proper care is necessary to realize the benefits of the
differential amplification of the part. Separation of the input and
output grounds is crucial in rejection of the common mode
noise at the inputs and eliminating any ground drops on the input signal line. For example, connecting the ground of a coaxial
cable to the AD830 output common (board ground) could degrade the CMR and also introduce power-down loading on
cable grounds. However, it is also necessary as in any electronic
system, to provide a return path for bias currents back to their
original power supply. This is accomplished by providing a connection between the differing grounds through a modest impedance labeled Z
(e.g., 100 Ω).
CM
Single Supply Operation
The AD830 is capable of operating in single power supply applications down to a voltage of +8 V, with the generalized connection shown in Figure 30. There is a constraint on the
common-mode voltage at the input and output which establishes the range for these voltages. Direct coupling may be used
for input and output voltages which lie in these ranges. Any gain
network applied needs to be referred to the output common
connection or have an appropriate offset voltage. In situations
where the signal lies at a common voltage outside the common
mode range of the AD830 direct coupling will not work, so ac
coupling should be used. A tested application included later in
this data sheet (Figure 42), shows how to easily accomplish coupling to the AD830. For single supply operation where direct
coupling is desired the input and output common-mode curves
(Figures 31 and 32) should be used.
Figure 30. General Single Supply Connection
30
28
24
20
16
12
8
4
COMMON MODE VOLTAGE LIMITS – ±Volts
0
TO GND
0
DIFFERENTIAL INPUT VOLTAGE – V
VP = +30V
1.61.20.80.4
PEAK
VP = +15V
VP = +10V
2.0
Figure 31. Input Common-Mode Range for Single Supply
28
TO V
24
20
16
12
8
MAXIMUM OUTPUT SWING – ±Volts
4
0
10
SUPPLY VOLTAGE – Volts
P
TO GND
26221814
30
Figure 32. Output Swing Limit for Single Supply
–12–
REV. A
Page 13
AD830
Differential Line Receiver
The AD830 was specifically designed to perform as a differential line receiver. The circuit in Figure 33 shows how simple it is
to configure the AD830 for this function. The signal from system “A” is received differentially relative to A’s common, and
that voltage is exactly reproduced relative to the common in system B. The common-mode rejection versus frequency, shown in
Figure 1, is excellent, typically 100 dB at low frequencies. The
high input impedance permits the AD830 to operate as a bridging amplifier across low impedance terminations with negligible
loading. The differential gain and phase specifications are very
good as shown in Figure 7 for 500 Ω and Figure 10 for 150 Ω.
The input and output common should be separated to achieve
the full CMR performance of the AD830 as a differential amplifier. However, a common return path is necessary between systems A and B.
V
P
AD830
A=1
C
Z
CM
V
INPUT
SIGNAL
V
COMMON IN
SYSTEM A
V
CM
1
1
2
G
M
2
36
G
M
0.1µF
8
V
7
OUT
0.1µF
45
V
N
= V
– V
V
OUT
2
1
COMMON IN
SYSTEM B
Figure 33. Differential Line Receiver
Wide Range Level Shifter
The wide common-mode range and accuracy of the AD830 allows easy level shifting of differential signals referred to an input
common-mode voltage to any new voltage defined at the output. The inputs may be referenced to levels as high as 10 V at
the inputs with a ±2 V swing about 10 V. In the circuit of Figure 34, the output voltage, V
, is defined by the simple equa-
OUT
tion shown below. The excellent linearity and low distortion are
preserved over the full input and output common-mode range.
The voltage sources need not be of low impedance, since the
high input resistance and modest input bias current of the
AD830 V-to-I converters permit the use of resistive voltage dividers as reference voltages.
V
P
V
1
INPUT
SIGNAL
V
2
INPUT
COMMON
1
G
M
2
3
G
M
AD830
A=1
C
45
V
= V1 – V2 + V
OUT
3
0.1µF
8
V
7
OUT
6
0.1µF
V
N
V
OUTPUT
COMMON
3
Difference Amplifier with Gain > 1
The AD830 can provide instrumentation amplifier style differential amplification at gains greater than 1. The input signal is
connected differentially and the gain is set via feedback resistors
as shown in Figure 35. The gain, G = (R
+ R1)/R2. The AD830
2
can provide either inverting or noninverting differential amplification. The polarity of the gain is established by the polarity of
the connection at the input. Feedback resistors R
ally be R
≤ 1 kΩ to maintain closed-loop stability and also keep
2
should gener-
2
bias current induced offsets low. Highest CMRR and lowest dc
offsets are preserved by including a compensating resistor in
series with Pin 3. The gain may be as high as 100.
V
P
1
V
V
CM
1
INPUT
SIGNAL
V
2
Z
CM
R
R
2
1
G
M
2
36
G
M
AD830
A=1
C
4
V
= (V1 – V2) (1+R1 /R2)
OUT
0.1µF
8
V
7
OUT
0.1µF
5
V
N
R1
R2
Figure 35. Gain of G Differential Amplifier, G > 1
Offsetting the Output with Gain
Some applications, such as A/D drivers, require that the signal
be amplified and also offset, typically to accommodate the input
range of the device. The AD830 can offset the output signal
very simply through Pin 3 even with gain > 1. The voltage applied to Pin 3 must be attenuated by an appropriate factor so
that V
3 G = desired offset. In Figure 36, a resistive divider
3
from a voltage reference is used to produce the attenuated offset
voltage.
V
P
V
1
V
CM
1
INPUT
SIGNAL
V
2
Z
CM
R1 R
2
G
M
2
3
G
M
AD830
A=1
C
0.1µF
8
V
7
OUT
6
0.1µF
45
V
REF
R
1
N
R
2
R
3
V
3
R
4
V
= (V1 – V2) (1+R1 /R2)
OUT
V
Figure 36. Offsetting the Output with Differential Gain > 1
Figure 34. Differential Amplification with Level Shifting
REV. A
–13–
Page 14
AD830
Loop Through or Line Bridging Amplifier (Figure 37)
The AD830 is ideally suited for use as a video line bridging amplifier. The video signal is tapped from the conductor of the
cable relative to its shield. The high input impedance of the
AD830 provides negligible loading on the cable. More significantly, the benign loading is maintained while the AD830 is
powered-down. Coupled with its good video load driving performance, the AD830 is well suited to video cable monitoring
applications.
V
P
0.1µF
8
V
75Ω
V
0.1µF
N
OUT
75Ω
499Ω
499Ω
7
C
M
M
AD830
A=1
C
OPTIONAL C
1
G
R
G
2
249Ω
36
G
45
Figure 37. Cable Tap Amplifier
Resistorless Summing
Direct, two input, resistorless summing is easily realized from
the general unity gain mode. By grounding V
two inputs to V
applied voltages V
V
. A diagram of this simple, but potent application is shown
3
and VY1, the output is the exact sum of the
X1
and V3, relative to common; V
1
and applying the
X2
= V1 +
OUT
below in Figure 38. The AD830 summing circuit possesses several virtues not present in the classic op amp based summing
circuits. It has high impedance inputs, no resistors, very precise
summing, high reverse isolation and noninverting gain. Achieving this function and performance with op amps requires significantly more components.
V
P
M
M
V
OUT
AD830
= V1 + V
8
A=1
C
7
3
OUT
V
N
1
V
1
V
3
G
2
36
G
45
Figure 38. Resistorless Summing Amplifier
23 Gain Bandwidth Line Driver
A gain of two, without the use of resistors, is possible with the
AD830. This is accomplished by grounding V
, tying the two
X2
inputs V
and VY1 together and applying the input, VIN, to this
X1
wired connection. The output is exactly twice the applied voltage, V
; V
IN
= 2 3 VIN. Figure 39 below shows the connec-
OUT
tions for this highly useful application. The most notable
characteristic of this alternative gain of two is that there is no
loss of bandwidth as in a voltage feedback op amp based gain of
+2 where the bandwidth is halved, therefore, the gain bandwidth is doubled. Also, this circuit is accurate without the need
for any precise valued resistors, as in the op amp equivalents,
and it possess excellent differential gain and phase performance
as shown in Figures 40 and 41.
V
P
1
V
IN
G
2
36
G
45
AD830
M
A=1
M
C
0.1µF
8
V
75Ω
V
OUT
75Ω
0.1µF
N
7
Figure 39. Full Bandwidth Line Driver (G = +2)
.10
.09
.08
.07
.06
.05
.04
DIFFERENTIAL GAIN – %
.03
.02
.01
5
GAIN
6
PHASE
SUPPLY VOLTAGE – ±Volts
GAIN = +2
= 150Ω
R
L
FREQ = 3.58MHz
0 TO 0.7V
.20
.18
.16
.14
.12
.10
.08
.06
.04
DIFFERENTIAL PHASE – Degrees
.02
15
1413121110987
Figure 40. Differential Gain and Phase for the Circuit of
Figure 39
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
AMPLITUDE RESPONSE – dB
–0.6
–0.7
–0.8
RL = 150Ω
GAIN = +2
100k 100M10M1M10k
VS = ±5V
FREQUENCY – Hz
VS = ±15V
VS = ±10V
Figure 41. 0.1 dB Gain Flatness for the Circuit of Figure 39
–14–
REV. A
Page 15
AD830
1
–0.4
–0.9
10 100 10M1M100k10k1k
–0.3
–0.2
–0.1
0
–0.8
–0.7
–0.6
–0.5
AMPLITUDE RESPONSE – dB
FREQUENCY – Hz
AC COUPLED LINE RECEIVER
The AD830 is configurable as an ac coupled differential amplifier on a single or bipolar supply voltages. All that is needed is
inclusion of a few noncritical passive components as illustrated
below in Figure 42. A simple resistive network at the X G
M
input establishes a common-mode bias. Here, the common
mode is centered at 6 volts, but in principle can be any voltage
within the common-mode limits of the AD830. The 10 kΩ resistors to each input bias the X G
stage with sufficiently high
M
impedance to keep the input coupling corner frequency low, but
not too large so that residual bias current induced offset voltage
INPUT
SIGNAL
Z
CM
10µF
R
T
10µF
10kΩ
+V
S
10kΩ
10kΩ
10kΩ
2kΩ*
*OPTIONAL TUNING FOR
IMPROVING VERY LOW
FREQUENCY CMR.
1
G
M
2
3
G
M
4
becomes troublesome. For dual supply operation, the 10 kΩ
resistors may go directly to ground. The output common is conveniently set by a Zener diode for a low impedance reference to
preserve the high frequency CMR. However, a simple resistive
divider will work fine and good high frequency CMR can be
maintained by placing a compensating resistor in series with the
+Y input. The excellent CMRR response of the circuit is shown
in Figure 43. A plot of the 0.1 dB flatness from 10 Hz is also
shown. With the use of 10 µF capacitors, the CMR is >90 dB
down to a few tens of hertz. This level of performance is almost
impossible to achieve with discrete solutions.
+12V
AD830
A=1
C
0.1µF
8
V
7
6
5
1N4736
OUT
1000µF
+12V
4.7kΩ
6.8V
75Ω
75Ω
COAX
CABLE
75Ω
Figure 42. AC Coupled Line Receiver
120
100
80
60
40
COMMON-MODE REJECTION – dB
20
WITH CIRCUIT TRIMMED
USING EXTERNAL 2kΩ
POTENTIOMETER
WITHOUT EXTERNAL
2kΩ POTENTIOMETER
10 100 100M10M1M100k10k1k
FREQUENCY – Hz
Figure 43. Common-Mode Rejection vs. Frequency for
Line Receiver
REV. A
Figure 44. Amplitude Response vs. Frequency for Line
Receiver
–15–
Page 16
AD830
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Cerdip (Q) Package
0.005 (0.13) MIN
0.055 (1.4) MAX
0.200 (5.08)
0.125 (3.18)
PIN 1
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.200
(5.08)
MAX
PIN 1
0.023 (0.58)
0.014 (0.36)
8
1
0.405 (10.29) MAX
0.100
(2.54)
BSC
5
4
0.070 (1.78)
0.030 (0.76)
0.310 (7.87)
0.220 (5.59)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
SEATING
PLANE
Plastic Mini-DIP (N) Package
58
0.280 (7.11)
0.240 (6.10)
0.100
(2.54)
BSC
4
0.070 (1.77)
0.045 (1.15)
0.060 (1.52)
0.015 (0.38)
0.130
(3.30)
MIN
SEATING
PLANE
1
0.430 (10.92)
0.348 (8.84)
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
15
°
0
°
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
C1735–24–10/92
8-Pin SOIC (R) Package
0.198 (5.00)
0.188 (4.75)
8
1
0.050
(1.27)
TYP
0.010 (0.25)
0.004 (0.10)
All brand or product names mentioned are trademarks or registered trademarks of their respective holders.
5
0.158 (4.00)
0.150 (3.80)
4
0.018 (0.46)
0.014 (0.36)
0.102 (2.59)
0.094 (2.39)
0.244 (6.200)
0.228 (5.80)
0.015 (0.38)
0.007 (0.18)
0.205 (5.20)
0.181 (4.60)
0.045 (1.15)
0.020 (0.50)
PRINTED IN U.S.A.
–16–
REV. A
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