Page 1
+3 Volt, Serial Input
a
FEATURES
Complete 12-Bit DAC
No External Components
Single +3 Volt Operation
0.5 mV/Bit with 2.0475 V Full Scale
6 s Output Voltage Settling Time
Low Power: 3.6 mW
Compact SO-8 1.5 mm Height Package
APPLICATIONS
Portable Communications
Digitally Controlled Calibration
Servo Controls
PC Peripherals
GENERAL DESCRIPTION
The AD8300 is a complete 12-bit, voltage-output digital-toanalog converter designed to operate from a single +3 volt supply. Built using a CBCMOS process, this monolithic DAC
offers the user low cost, and ease-of-use in single-supply +3 volt
systems. Operation is guaranteed over the supply voltage range
of +2.7 V to +5.5 V making this device ideal for battery operated applications.
The 2.0475 V full-scale voltage output is laser trimmed to
maintain accuracy over the operating temperature range of the
device. The binary input data format provides an easy-to-use
one-half-millivolt-per-bit software programmability. The voltage
outputs are capable of sourcing 5 mA.
Complete 12-Bit DAC
AD8300
FUNCTIONAL BLOCK DIAGRAM
12-BIT
CLR
LD
CS
CLK
SDI
REF
EN
DAC
12
DAC
REGISTER
12
SERIAL
REGISTER
AD8300
A double buffered serial data interface offers high speed, threewire, DSP and microcontroller compatible inputs using data in
(SDI), clock (CLK) and load strobe (LD) pins. A chip select
(CS) pin simplifies connection of multiple DAC packages by
enabling the clock input when active low. Additionally, a CLR
input sets the output to zero scale at power on or upon user
demand.
The AD8300 is specified over the extended industrial (–40°C to
+85°C) temperature range. AD8300s are available in plastic
DIP, and low profile 1.5 mm height SO-8 surface mount packages.
V
OUT
V
DD
GND
3.0
DVFS 1 LSB
2.8
DATA = FFF
TA = +258C
2.6
PROPER OPERATION
2.4
WHEN VDD SUPPLY
VOLTAGE ABOVE
2.2
MINIMUM SUPPLY VOLTAGE – Volts
2.0
0.01 100.1 1.0
OUTPUT LOAD CURRENT – mA
H
CURVE
Figure 1. Minimum Supply Voltage vs. Load
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
1.00
V
= +2.7V
0.75
0.50
0.25
0.00
–0.25
–0.50
INL LINEARITY ERROR – LSB
–0.75
–1.00
0 40961024 2048
DD
T
= –408C, +258C, +1258C
A
= –408C
= +258C
= +1258C
DIGITAL INPUT CODE – Decimal
3072
Figure 2. Linearity Error vs. Digital Code and Temperature
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
Page 2
AD8300–SPECIFICATIONS
+3 V OPERATION
(@ V
= +5 V ⴞ 10%, –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted)
DD
Parameter Symbol Condition Min Typ Max Units
STATIC PERFORMANCE
Resolution N [Note 1] 12 Bits
Relative Accuracy INL –2 ±1/2 +2 LSB
Differential Nonlinearity
Zero-Scale Error V
Full-Scale Voltage
Full-Scale Tempco TCV
2
3
DNL Monotonic –1 ±1/2 +1 LSB
ZSE
V
FS
FS
Data = 000
Data = FFF
H
H
[Notes 3, 4] 16 ppm/°C
+1/2 +3 mV
2.039 2.0475 2.056 Volts
ANALOG OUTPUT
Output Current (Source) I
Output Current (Sink) I
Load Regulation L
Output Resistance to GND R
Capacitive Load C
OUT
OUT
REG
OUT
L
Data = 800
Data = 800
R
= 200 Ω to ∞, Data = 800
L
Data = 000
No Oscillation
H
H
H
, ∆V
, ∆V
4
= 5 LSB 5 mA
OUT
= 5 LSB 2 mA
OUT
H
1.5 5 LSB
30 Ω
500 pF
LOGIC INPUTS
Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance C
INTERFACE TIMING
SPECIFICATIONS
4, 5
Clock Width High t
Clock Width Low t
Load Pulsewidth t
Data Setup t
Data Hold t
Clear Pulsewidth t
Load Setup t
Load Hold t
Select t
Deselect t
AC CHARACTERISTICS
4
Voltage Output Settling Time t
IL
IH
IL
IL
CH
CL
LDW
DS
DH
CLRW
LD1
LD2
CSS
CSH
S
To ±0.2% of Full Scale 7 µs
To ±1 LSB of Final Value
Output Slew Rate SR Data = 000
to FFFH to 000
H
2.1 V
40 ns
40 ns
50 ns
15 ns
15 ns
40 ns
15 ns
40 ns
40 ns
40 ns
6
H
14 µs
2.0 V/µs
0.6 V
10 µA
10 pF
DAC Glitch 15 nV/s
Digital Feedthrough 15 nV/s
SUPPLY CHARACTERISTICS
Power Supply Range VDD
Positive Supply Current I
Power Dissipation P
DD
DISS
RANGE
DNL < ±1 LSB 2.7 5.5 V
VDD = 3 V, VIL = 0 V, Data = 000
V
= 3.6 V, VIH = 2.3 V, Data = FFF
DD
VDD = 3 V, VIL = 0 V, Data = 000
H
H
H
1.2 1.7 mA
1.9 3.0 mA
3.6 5.1 mW
Power Supply Sensitivity PSS ∆VDD = ±5% 0.001 0.005 %/%
NOTES
1
LSB = 0.5 mV for 0 V to +2.0475 V output range.
2
The first two codes (000H, 001H) are excluded from the linearity error measurement.
3
Includes internal voltage reference error.
4
These parameters are guaranteed by design and not subject to production testing.
5
All input control signals are specified with tR = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in
this 6 LSB region.
Specifications subject to change without notice.
–2–
REV. A
Page 3
AD8300
+5 V OPERATION
(@ V
= +5 V ⴞ 10%, –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted)
DD
Parameter Symbol Condition Min Typ Max Units
STATIC PERFORMANCE
Resolution N [Note 1] 12 Bits
Relative Accuracy INL –2 ±1/2 +2 LSB
Differential Nonlinearity
Zero-Scale Error V
Full-Scale Voltage
Full-Scale Tempco TCV
2
3
DNL Monotonic –1 ±1/2 +1 LSB
ZSE
V
FS
FS
Data = 000
Data = FFF
H
H
[Notes 3, 4] 16 ppm/°C
+1/2 +3 mV
2.039 2.0475 2.056 Volts
ANALOG OUTPUT
Output Current (Source) I
Output Current (Sink) I
Load Regulation L
Output Resistance to GND R
Capacitive Load C
OUT
OUT
REG
OUT
L
Data = 800
Data = 800
R
= 200 Ω to ∞, Data = 800
L
Data = 000
No Oscillation
H
H
H
, ∆V
, ∆V
4
= 5 LSB 5 mA
OUT
= 5 LSB 2 mA
OUT
H
1.5 5 LSB
30 Ω
500 pF
LOGIC INPUTS
Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance C
INTERFACE TIMING
SPECIFICATIONS
4, 5
Clock Width High t
Clock Width Low t
Load Pulsewidth t
Data Setup t
Data Hold t
Clear Pulsewidth t
Load Setup t
Load Hold t
Select t
Deselect t
AC CHARACTERISTICS
4
Voltage Output Settling Time t
IL
IH
IL
IL
CH
CL
LDW
DS
DH
CLWR
LD1
LD2
CSS
CSH
S
To ±0.2% of Full Scale 6 µs
To ±1 LSB of Final Value
Output Slew Rate SR Data = 000
to FFFH to 000
H
2.4 V
30 ns
30 ns
30 ns
15 ns
15 ns
30 ns
15 ns
30 ns
30 ns
30 ns
6
H
13 µs
2.2 V/µs
0.8 V
10 µA
10 pF
DAC Glitch 15 nV/s
Digital Feedthrough 15 nV/s
SUPPLY CHARACTERISTICS
Power Supply Range VDD
Positive Supply Current I
Power Dissipation P
DD
DISS
RANGE
DNL < ±1 LSB 2.7 5.5 V
VDD = 5 V, VIL = 0 V, Data = 000
V
= 5.5 V, VIH = 2.3 V, Data = FFF
DD
VDD = 5 V, VIL = 0 V, Data = 000
H
H
H
1.2 1.7 mA
2.8 4.0 mA
6 5.1 mW
Power Supply Sensitivity PSS ∆VDD = ±10% 0.001 0.006 %/%
NOTES
1
1 LSB = 0.5 mV for 0 V to +2.0475 V output range.
2
The first two codes (000H, 001H) are excluded from the linearity error measurement.
3
Includes internal voltage reference error.
4
These parameters are guaranteed by design and not subject to production testing.
5
All input control signals are specified with tR = tF = 2 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in
this 6 LSB region.
Specifications subject to change without notice.
REV. A –3–
Page 4
AD8300
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
V
to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
OUT
Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
I
OUT
Package Power Dissipation . . . . . . . . . . . . . (T
Thermal Resistance θ
JA
Max – T
J
)/θ
A
JA
8-Lead Plastic DIP Package (N-8) . . . . . . . . . . . . . 103°C/W
8-Lead SOIC Package (SO-8) . . . . . . . . . . . . . . . . 158°C/W
Maximum Junction Temperature (T
Max) . . . . . . . . . . 150°C
J
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Package Package
Model INL Temp Description Options
AD8300AN ±2 XIND 8-Lead P-DIP N-8
AD8300AR ±2 XIND 8-Lead SOIC SO-8
NOTES
XIND = –40°C to +85°C.
The AD8300 contains 630 transistors. The die size measures 72 mil × 65 mil.
PIN CONFIGURATIONS
SO-8 Plastic DIP
1
4
8
5
V
CS
CLK
SDI
DD
1
2
AD8300
TOP VIEW
3
(Not to Scale)
4
8
V
OUT
7
GND
6
CLR
5
LD
PIN DESCRIPTIONS
Pin # Name Function
1V
DD
Positive power supply input. Specified range
of operation +2.7 V to +5.5 V.
2 CS Chip Select, active low input. Disables shift
register loading when high. Does not affect
LD operation.
3 CLK Clock input, positive edge clocks data into
shift register.
4 SDI Serial Data Input, input data loads directly
into the shift register, MSB first.
5 LD Load DAC register strobes, active low.
Transfers shift register data to DAC register.
See Truth Table I for operation. Asynchronous active low input.
6 CLR Resets DAC register to zero condition.
Asynchronous active low input.
7 GND Analog and Digital Ground.
8V
OUT
DAC voltage output, 2.0475 V full scale
with 0.5 mV per bit. An internal temperature stabilized reference maintains a fixed
full-scale voltage independent of time, temperature and power supply variations.
SDI
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CLK
t
CSS
t
CS
t
LD1
LD
SDI
t
DStDH
t
CLK
LD
CLR
FS
V
OUT
ZS
CL
t
CH
t
LDW
t
S
61LSB
ERROR BAND
Figure 3. Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8300 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
CSH
t
t
LD2
CLRW
t
S
–4–
REV. A
Page 5
Typical Performance Characteristics–
AD8300
80
60
40
20
0
–20
–40
OUTPUT CURRENT – mA
–60
–80
BROADBAND NOISE – 200mV/DIV
POSITIVE
CURRENT
VDD = +3V
VDD = +5V
02
OUTPUT VOLTAGE – Volts
Figure 4. I
TIME = 100ms/DIV
LIMIT
DATA = 800
RL TIED TO +1.024V
NEGATIVE
CURRENT
LIMIT
1
vs. V
OUT
VDD = +5V
VDD = +3V
H
OUT
Figure 7. Broadband Noise
2.5
TA = –40 TO +858C
2.0
1.5
1.0
0.5
LOGIC THRESHOLD VOLTAGE
0
01 645
V
SUPPLY VOLTAGE – Volts
DD
Figure 5. Logic Input Threshold
Voltage vs. V
50
45
40
35
30
VDD = +3V 610%
25
20
15
TA = +258C
10
DATA = FFF
POWER SUPPLY REJECTION – dB
5
0
10 100 1M10k 100k
Figure 8. Power Supply Rejection
vs. Frequency
23
DD
V
= +5V 610%
DD
H
1k
FREQUENCY – Hz
HORIZONTAL = 1ms/DIV
Figure 6. Detail Settling Time
HORIZONTAL = 20ms/DIV
Figure 9. Large Signal Settling Time
3.5
3.0
2.5
VDD = +3V
2.0
1.5
1.0
SUPPLY CURRENT – mA
0.5
0
01 534
VDD = +5V
TA = +258C
DATA = FFF
2
LOGIC VOLTAGE – Volts
H
Figure 10. Supply Current vs. Logic
Input Voltage
CODE 800H TO 7FF
H
Figure 11. Midscale Transition
Performance
0.5ms/DIV
Figure 12. Digital Feedthrough vs.
Time
REV. A
–5–
Page 6
AD8300
60
50
40
30
FREQUENCY
20
10
0
–1 0 623145
TOTAL UNADJUSTED ERROR – mV
TUE = SINL+ZS+FS
ss = 300 UNITS
= +3V
V
DD
= +258C
T
A
Figure 13. Total Unadjusted
Error Histogram
1.5
NO LOAD
1.0
ss = 300 UNITS
NORMALIZED TO +258C
0.5
VDD = +5.5V
0
DRIFT – mV
OUT
–0.5
V
–1.0
–1.5
–55 –35 1255 25 45 65 85 105–15
VDD = +2.7V
TEMPERATURE – 8C
Figure 16. Full-Scale Voltage Drift
vs. Temperature
1.5
NO LOAD
1.0
0.5
0
DRIFT – mV
OUT
–0.5
V
–1.0
–1.5
–55 –35 1255 25 45 65 85 105–15
ss = 300 UNITS
NORMALIZED TO +258C
VDD = +2.7V
TEMPERATURE – 8C
VDD = +5V
Figure 14. Zero-Scale Voltage Drift
vs. Temperature
10
V
= +3V
DD
DATA = FFF
1
0.1
NOISE DENSITY – mV/Hz
0.01
1 100k10 100 1k 10k
FREQUENCY – Hz
H
Figure 17. Output Voltage Noise
Density vs. Frequency
3.0
V
= +5.5V
DD
2.6
V
= +5.0V
DD
2.2
V
= +4.5V
DD
1.8
V
= +2.7, 3.0, 3.3V
SUPPLY CURRENT – mA
1.4
DD
I
1.0
DD
DATA = FFF
VIH = +2.4V
= 0V
V
IL
–60 –20 14020 60 100
TEMPERATURE – 8C
Figure 15. Supply Current vs.
Temperature
70
60
V
= +3V
DD
DATA FFF
H
TA = –40 TO +858C
50
40
30
FREQUENCY
20
10
0
–50 –40 40–20 –10
–30
TEMPERATURE COEFFICIENT – ppm/8C
0203010
Figure 18. Full-Scale Output
Tempco Histogram
H
2.4
2.0
1.6
1.2
0.8
0.4
NOMINAL VOLTAGE CHANGE – mV
0
0 100
HOURS OF OPERATION AT +1508C
VDD = +2.7V
ss = 135 UNITS
FULL SCALE (DATA = FFFH)
ZERO SCALE (DATA = 000H)
200 300 500
400
Figure 19. Long Term Drift
Accelerated by Burn-In
–6–
600
REV. A
Page 7
AD8300
Table I. Control Logic Truth Table
CS CLK CLR LD Serial Shift Register Function DAC Register Function
H X H H No Effect Latched
L L H H No Effect Latched
L H H H No Effect Latched
L ↑ H H Shift-Register-Data Advanced One Bit Latched
↑ L H H No Effect Latched
HX H ↓ No Effect Updated with Current Shift Register Contents
H X H L No Effect Transparent
H X L X No Effect Loaded with All Zeros
HX ↑ H No Effect Latched All Zeros
NOTES
1. ↑ = Positive Logic Transition; ↓ = Negative Logic Transition; X = Don’t Care.
2. Do not clock in serial data while LD is LOW.
3. Data loads MSB first.
OPERATION
The AD8300 is a complete ready to use 12-bit digital-to-analog
converter. Only one +3 V power supply is necessary for operation. It contains a 12-bit laser-trimmed digital-to-analog
converter, a curvature-corrected bandgap reference, rail-to-rail
output op amp, serial-input register, and DAC register. The
serial data interface consists of a serial-data-input (SDI) clock
(CLK), and load strobe pins (LD) with an active low CS strobe.
In addition an asynchronous CLR pin will set all DAC register
bits to zero causing the V
to become zero volts. This func-
OUT
tion is useful for power on reset or system failure recovery to a
known state.
D/A CONVERTER SECTION
The internal DAC is a 12-bit device with an output that swings
from GND potential to 0.4 volt generated from the internal bandgap voltage, see Figure 20. It uses a laser-trimmed segmented
R-2R ladder which is switched by N-channel MOSFETs. The
output voltage of the DAC has a constant resistance independent of digital input code. The DAC output is internally connected to the rail-to-rail output op amp.
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power consumption precision amplifier. This low power amplifier contains
a differential PNP pair input stage that provides low offset voltage and low noise, as well as the ability to amplify the zero-scale
DAC output voltages. The rail-to-rail amplifier is configured
with a gain of approximately five in order to set the 2.0475 volt
full-scale output (0.5 mV/LSB). See Figure 20 for an equivalent
circuit schematic of the analog section.
REF
0.4V
1.2V
12-BIT DAC
0.4V
FS
V
OUT
2.047V
FS
R2
R1
BANDGAP
Figure 20. Equivalent AD8300 Schematic of Analog Portion
The op amp has a 2 µs typical settling time to 0.4% of full scale.
There are slight differences in settling time for negative slewing
signals versus positive. Also negative transition settling time to
within the last 6 LSB of zero volts has an extended settling time.
See the oscilloscope photos in the typical performances section
of this data sheet.
OUTPUT SECTION
The rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply. Figure 21 shows an equivalent output schematic
of the rail-to-rail amplifier with its N-channel pull-down FETs
that will pull an output load directly to GND. The output
sourcing current is provided by a P-channel pull-up device that
can source current to GND terminated loads.
V
P-CH
N-CH
DD
V
OUT
AGND
Figure 21. Equivalent Analog Output Circuit
The rail-to-rail output stage achieves the minimum operating
supply voltage capability shown in Figure 2. The N-channel
output pull-down MOSFET shown in Figure 21 has a 35 Ω on
resistance which sets the sink current capability near ground. In
addition to resistive load driving capability, the amplifier has
also been carefully designed and characterized for up to 500 pF
capacitive load driving capability.
REFERENCE SECTION
The internal curvature-corrected bandgap voltage reference is
laser trimmed for both initial accuracy and low temperature
coefficient. Figure 18 provides a histogram of total output performance of full-scale vs. temperature which is dominated by
the reference performance.
POWER SUPPLY
The very low power consumption of the AD8300 is a direct
result of a circuit design optimizing use of a CBCMOS process.
By using the low power characteristics of the CMOS for the
logic, and the low noise, tight matching of the complementary
bipolar transistors, good analog accuracy is achieved.
For power-consumption sensitive applications it is important to
note that the internal power consumption of the AD8300 is
strongly dependent on the actual logic input voltage levels
present on the SDI, CLK, CS, LD, and CLR pins. Since these
inputs are standard CMOS logic structures, they contribute
static power dissipation dependent on the actual driving logic
REV. A
–7–
Page 8
AD8300
VOH and VOL voltage levels. Consequently, for optimum dissipation use of CMOS logic versus TTL provides minimal dissipation in the static state. A V
= 0 V on the logic input pins
INL
provides the lowest standby dissipation of 1.2 mA with a +3.3 V
power supply.
As with any analog system, it is recommended that the AD8300
power supply be bypassed on the same PC card that contains
the chip. Figure 8 shows the power supply rejection versus frequency performance. This should be taken into account when
using higher frequency switched-mode power supplies with
ripple frequencies of 100 kHz and higher.
One advantage of the rail-to-rail output amplifiers used in the
AD8300 is the wide range of usable supply voltage. The part is
fully specified and tested over temperature for operation from
+2.7 V to +5.5 V. If reduced linearity and source current capability near full scale can be tolerated, operation of the AD8300
is possible down to +2.1 volts. The minimum operating supply
voltage versus load current plot in Figure 2 provides information
for operation below V
= +2.7 V.
DD
TIMING AND CONTROL
The AD8300 has a separate serial-input register from the 12-bit
DAC register that allows preloading of a new data value MSB
first into the serial register without disturbing the present DAC
output voltage value. Data can only be loaded when the CS pin
is active low. After the new value is fully loaded in the serialinput register, it can be asynchronously transferred to the DAC
register by strobing the LD pin. The DAC register uses a level
sensitive LD strobe that should be returned high before any new
data is loaded into the serial-input register. At any time the
contents of the DAC resister can be reset to zero by strobing the
CLR pin which causes the DAC output voltage to go to zero
volts. All of the timing requirements are detailed in Figure 3
along with Table I. Control Logic Truth Table.
All digital inputs are protected with a Zener type ESD protection
structure (Figure 22) that allows logic input voltages to exceed
the V
supply voltage. This feature can be useful if the user is
DD
loading one or more of the digital inputs with a 5 V CMOS logic
input voltage level while operating the AD8300 on a +3.3 V
power supply. If this mode of interface is used, make sure that
of the +5 V CMOS meets the VIL input requirement of
the V
OL
the AD8300 operating at 3 V. See Figure 5 for the effect on
digital logic input threshold versus operating V
V
DD
LOGIC
IN
GND
supply voltage.
DD
Table II. Unipolar Code Table
Hexadecimal Decimal
Number in Number in Analog Output
DAC Register DAC Register Voltage (V)
FFF 4095 +2.0475
801 2049 +1.0245
800 2048 +1.0240
7FF 2047 +1.0235
000 0 +0.0000
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC (SO-8)
0.1 968 (5.00)
0.1 890 (4.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.0098 (0.25)
0.0040 (0.10)
SEATING
85
0.0500 (1.27)
PLANE
0.2440 (6.20)
0.2284 (5.80)
41
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0075 (0.19)
0.0196 (0.50)
0.0099 (0.25)
88
0.0500 (1.27)
08
0.0160 (0.41)
3 458
8-Lead Plastic DIP (N-8)
0.430 (10.92)
0.348 (8.84)
PIN 1
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
8
0.100 (2.54)
5
0.280 (7.11)
14
BSC
0.240 (6.10)
(0.381)
0.070 (1.77)
0.045 (1.15)
0.015
TYP
0.130
(3.30)
MIN
SEATING
PLANE
0.325 (8.25)
0.300 (7.62)
158
08
0.195 ( 4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
C1968a–0–5/99
Figure 22. Equivalent Digital Input ESD Protection
Unipolar Output Operation
This is the basic mode of operation for the AD8300. The
AD8300 has been designed to drive loads as low as 400 Ω in
parallel with 500 pF. The code table for this operation is shown
in Table II.
APPLICATIONS INFORMATION
See DAC8512 data sheet for additional application circuit ideas.
–8–
PRINTED IN U.S.A.
REV. A
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