Datasheet AD829SQ-883B, AD829SQ, AD829SE-883B, AD829SCHIPS, AD829JR-REEL7 Datasheet (Analog Devices)

High-Speed, Low-Noise

a

FEATURES
High Speed

120 MHz Bandwidth, Gain = –1
230 V/␮s Slew Rate
90 ns Settling Time to 0.1%

Ideal for Video Applications

0.02% Differential Gain

0.04ⴗ Differential Phase

Low Noise

1.7 nV/√Hz Input Voltage Noise

1.5 pA/√Hz Input Current Noise

Excellent DC Precision

1 mV max Input Offset Voltage (Over Temp)

0.3 ␮V/ⴗC Input Offset Drift

Flexible Operation

Specified for ⴞ5 V to ⴞ15 V Operation
ⴞ3 V Output Swing into a 150 ⍀ Load
External Compensation for Gains 1 to 20
5 mA Supply Current

Available in Tape and Reel in Accordance with

EIA-481A Standard

PRODUCT DESCRIPTION

The AD829 is a low noise (1.7 nV/√Hz), high speed op amp
with custom compensation that provides the user with gains
from ±1 to ± 20 while maintaining a bandwidth greater than
50 MHz. The AD829’s 0.04° differential phase and 0.02%
differential gain performance at 3.58 MHz and 4.43 MHz,
driving reverse-terminated 50 Ω or 75 Ω cables, makes it ideally
suited for professional video applications. The AD829 achieves
its 230 V/µs uncompensated slew rate and 750 MHz gain band-
width product while requiring only 5 mA of current from the
power supplies.

The AD829’s external compensation pin gives it exceptional
versatility. For example, compensation can be selected to opti­mize the bandwidth for a given load and power supply voltage.
As a gain-of-two line driver, the –3 dB bandwidth can be in­creased to 95 MHz at the expense of 1 dB of peaking. In addi­tion, the AD829’s output can also be clamped at its external
compensation pin.

The AD829 has excellent dc performance. It offers a minimum
open-loop gain of 30 V/mV into loads as low as 500 Ω, low
input voltage noise of 1.7 nV/√Hz, and a low input offset volt­age of 1 mV maximum. Common-mode rejection and power
supply rejection ratios are both 120 dB.

The AD829 is also useful in multichannel, high speed data
conversion where its fast (90 ns to 0.1%) settling time is of
importance. In such applications, the AD829 serves as an input
buffer for 8-to-10-bit A/D converters and as an output I/V con­verter for high speed D/A converters.

REV. E

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Video Op Amp

AD829

CONNECTION DIAGRAMS

8-Lead Plastic Mini-DIP (N),

Cerdip (Q) and SOIC (R) Packages

–V

–IN

+IN

S

1

AD829

2

3

TOP VIEW

4

(Not to Scale)

OFFSET NULL

20-Lead LCC Pinout

NC

OFFSET

NULL

4

NC

5

–IN

NC

+IN

NC

NC = NO CONNECT

The AD829 provides many of the same advantages that a trans­impedance amplifier offers, while operating as a traditional

6
7
8

9 10111213

AD829

TOP VIEW

(Not to Scale)

NC

–V

voltage feedback amplifier. A bandwidth greater than 50 MHz
can be maintained for a range of gains by changing the external
compensation capacitor. The AD829 and the transimpedance
amplifier are both unity gain stable and provide similar voltage
noise performance (1.7 nV/√Hz). However, the current noise of
the AD829 (1.5 pA/√Hz) is less than 10% of the noise of trans­impedance amps. Furthermore, the inputs of the AD829 are
symmetrical.

PRODUCT HIGHLIGHTS

1. Input voltage noise of 2 nV/√Hz, current noise of 1.5 pA/
√Hz and 50 MHz bandwidth, for gains of 1 to 20, make the

AD829 an ideal preamp.

2. Differential phase error of 0.04° and a 0.02% differential
gain error, at the 3.58 MHz NTSC and 4.43 MHz PAL and
SECAM color subcarrier frequencies, make it an outstanding
video performer for driving reverse-terminated 50 Ω and
75 Ω cables to ±1 V (at their terminated end).

3. The AD829 can drive heavy capacitive loads.

4. Performance is fully specified for operation from ±5 V to
±15 V supplies.

5. Available in plastic, cerdip, and small outline packages.
Chips and MIL-STD-883B parts are also available.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

8

OFFSET NULL
+V

7

6

OUTPUT
C

5

NC

OFFSET

NULL

NC

20 19123

18
17
16
15
14

COMP

NC

NC

C

S

COMP

NC
+V
NC
OUTPUT

NC

AD829–SPECIFICATIONS

(@ TA = +25ⴗC and VS = ⴞ15 V dc, unless otherwise noted)

Model Conditions V

S

Min Typ Max Min Typ Max Units

INPUT OFFSET VOLTAGE ±5 V, ± 15 V 0.2 1 0.1 0.5 mV

AD829J/AR AD829AQ/S

to T

T

MIN

MAX

1 0.5 mV

Offset Voltage Drift ±5 V, ± 15 V 0.3 0.3 µV/°C

INPUT BIAS CURRENT ±5 V, ± 15 V 3.3 7 3.3 7 µA

T

MIN

to T

MAX

8.2/9.5 9.5 µA

INPUT OFFSET CURRENT ±5 V, ± 15 V 50 500 50 500 nA

T

MIN

to T

MAX

500 500 nA

Offset Current Drift ±5 V, ± 15 V 0.5 0.5 nA/°C

OPEN-LOOP GAIN V

= ±2.5 V ±5 V

O

R

= 500 Ω 30 65 30 65 V/mV

LOAD

T

to T

MIN

MAX

= 150 Ω 40 40 V/mV

R

LOAD

V

= ±10 V ±15 V

OUT

R

= 1 kΩ 50 100 50 100 V/mV

LOAD

to T

T

MIN

R

MAX

= 500 Ω 85 85 V/mV

LOAD

20 20 V/mV

20 20 V/mV

DYNAMIC PERFORMANCE

Gain Bandwidth Product ±5 V 600 600 MHz

Full Power Bandwidth

1, 2

VO = 2 V p-p
R

= 500 Ω±5 V 25 25 MHz

LOAD

±15 V 750 750 MHz

VO = 20 V p-p
R

= 1 kΩ±15 V 3.6 3.6 MHz

Slew Rate

2

LOAD

R

= 500 Ω±5 V 150 150 V/µs

LOAD

R

= 1 kΩ±15 V 230 230 V/µs

LOAD

Settling Time to 0.1% AV = –19

–2.5 V to +2.5 V ±5 V 65 65 ns

Phase Margin

DIFFERENTIAL GAIN ERROR

DIFFERENTIAL PHASE ERROR

2

3

3

10 V Step ±15 V 90 90 ns
C

= 10 pF ±15 V

LOAD

R

= 1 kΩ 60 60 Degrees

LOAD

R

= 100 Ω±15 V

LOAD

C

= 30 pF 0.02 0.02 %

COMP

R

= 100 Ω±15 V

LOAD

C

= 30 pF 0.04 0.04 Degrees

COMP

COMMON-MODE REJECTION VCM = ±2.5 V ±5 V 100 120 100 120 dB

VCM = ±12 V ±15 V 100 120 100 120 dB
T

MIN

to T

MAX

96 96 dB

POWER SUPPLY REJECTION VS = ±4.5 V to ± 18 V 98 120 98 120 dB

T

MIN

to T

MAX

94 94 dB

INPUT VOLTAGE NOISE f = 1 kHz ±15 V 1.7 2 1.7 2 nV/√

INPUT CURRENT NOISE f = 1 kHz ± 15 V 1.5 1.5 pA/√

INPUT COMMON-MODE

VOLTAGE RANGE ±5 V +4.3 +4.3 V

–3.8 –3.8 V

±15 V +14.3 +14.3 V

–13.8 –13.8 V

OUTPUT VOLTAGE SWING R

= 500 Ω±5 V 3.0 3.6 3.0 3.6 ± V

LOAD

R

= 150 Ω±5 V 2.5 3.0 2.5 3.0 ± V

LOAD

R

50 Ω±5 V 1.4 1.4 ± V

LOAD =

R

= 1 kΩ±15 V 12 13.3 12 13.3 ± V

LOAD

R

= 500 Ω±15 V 10 12.2 10 12.2 ± V

LOAD

Short Circuit Current ±5 V, ± 15 V 32 32 mA

INPUT CHARACTERISTICS

Input Resistance (Differential) 13 13 kΩ
Input Capacitance (Differential)

4

55pF

Input Capacitance (Common Mode) 1.5 1.5 pF

CLOSED-LOOP OUTPUT

RESISTANCE AV = +1, f = 1 kHz 2 2 mΩ

Hz
Hz

–2–

REV. E

AD829

Model Conditions V

POWER SUPPLY

Operating Range ±4.5 ± 18 ± 4.5 ± 18 V
Quiescent Current ±5 V 5 6.5 5 6.5 mA

TRANSISTOR COUNT Number of Transistors 46 46

NOTES

1

Full Power Bandwidth = Slew Rate/2 π V

2

Tested at Gain = +20, C

3

3.58 MHz (NTSC) and 4.43 MHz (PAL & SECAM).

4

Differential input capacitance consists of 1.5 pF package capacitance plus 3.5 pF from the input differential pair.

Specifications subject to change without notice.

COMP

= 0 pF.

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

Internal Power Dissipations

T

to T

MIN

MAX

T

to T

MIN

MAX

.

PEAK

1

2

S

±15 V 5.3 6.8 5.3 6.8 mA

AD829J/AR AD829AQ/S

Min Typ Max Min Typ Max Units

8.0 8.2/8.7 mA

8.3/8.5 8.5/9.0 mA

METALIZATION PHOTO

Contact factory for latest dimensions.

Dimensions shown in inches and (mm).

Plastic (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Watts

Small Outline (R) . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 Watts

Cerdip (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Watts

LCC (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 Watts

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±V

S

Differential Input Voltage3 . . . . . . . . . . . . . . . . . . . . ±6 Volts

Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite

Storage Temperature Range (Q, E) . . . . . . . –65°C to +150°C

Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C

Operating Temperature Range

AD829J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

AD829A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

AD829S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . .+300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Maximum internal power dissipation is specified so that TJ does not exceed

+175°C at an ambient temperature of +25°C.
Thermal characteristics:

8-lead plastic package: θJA = 100°C/watt (derate at 8.7 mW/°C)
8-lead cerdip package: θJA = 110°C/watt (derate at 8.7 mW/°C)
20-lead LCC package: θJA = 150°C/watt
8-lead small outline package: θJA = 155°C/watt (derate at 6 mW/°C).

3

If the differential voltage exceeds 6 volts, external series protection resistors should

be added to limit the input current.

ESD SUSCEPTIBILITY

ESD (electrostatic discharge) sensitive device. Electrostatic
charges as high as 4000 volts, which readily accumulate on the
human body and on test equipment, can discharge without
detection. Although the AD829 features proprietary ESD pro­tection circuitry, permanent damage may still occur on these
devices if they are subjected to high energy electrostatic dis­charges. Therefore, proper ESD precautions are recommended
to avoid any performance degradation or loss of functionality.

ORDERING GUIDE

REV. E

Model Temperature Range Package Description Package Option*

AD829JN 0°C to +70°C 8-Lead Plastic Mini-DIP N-8
AD829AR –40°C to +85°C 8-Lead Plastic SOIC SO-8
AD829JR 0°C to +70°C 8-Lead Plastic SOIC SO-8
AD829AR-REEL7 –40°C to +85°C Tape and Reel 7"
AD829AR-REEL –40°C to +85°C Tape and Reel 13"
AD829JR-REEL7 0°C to +70°C Tape and Reel 7"
AD829JR-REEL 0°C to +70°C Tape and Reel 13"
AD829AQ –40°C to +85°C 8-Lead Cerdip Q-8
AD829SQ –55°C to +125°C 8-Lead Cerdip Q-8
AD829SQ/883B –55°C to +125°C 8-Lead Cerdip Q-8
5962-9312901MPA –55°C to +125°C 8-Lead Cerdip Q-8
AD829SE/883B –55°C to +125°C 20-Lead LCC E-20A
5962-9312901M2A –55°C to +125°C 20-Lead LCC E-20A
AD829JCHIPS 0°C to +70°CDie
AD829SCHIPS –55°C to +125°CDie

*E = Leadless Chip Carrier (Ceramic); N = Plastic DIP; Q = Cerdip; SO = Small Outline IC (SOIC).

–3–

AD829–Typical Performance Characteristics

OUTPUT VOLTAGE SWING – Volts p–p

30

25

20

15

10

5

0

10 100

1k 10k

LOAD RESISTANCE – ⍀

ⴞ5 VOLT
SUPPLIES

ⴞ15 VOLT
SUPPLIES

20

15

+V

OUT

10

–V

OUT

5

INPUT COMMON-MODE RANGE – Volts

0

02051015

SUPPLY VOLTAGE – ⴞVolts

Figure 1. Input Common-Mode
Range vs. Supply Voltage

6.0

5.5

5.0

4.5

QUIESCENT CURRENT – mA

20

15

10

VOLTAGE – Volts

5

MAGNITUDE OF THE OUTPUT

0

02051015

SUPPLY VOLTAGE – ⴞVolts

+V

OUT

–V

OUT

R

= 1k⍀

LOAD

Figure 2. Output Voltage Swing

vs. Supply Voltage

5–

A

␮

–

4

VS = ⴞ5V, ⴞ15V

–

3

INPUT BIAS CURRENT –

Figure 3. Output Voltage Swing

vs. Resistive Load

100

10

1

0.1

0.01

AV = +20
C

COMP

= 0pF

AV = +1
C

COMP

= 68pF

4.0
02051015

SUPPLY VOLTAGE – ⴞVolts

Figure 4. Quiescent Current vs.
Supply Voltage

7

QUIESCENT CURRENT – mA

6

5

4

3

60– 20– 0 20 40 60 80 100 14040–

VS = ⴞ15V

VS = ⴞ5V

120

TEMPERATURE – ⴗC

Figure 7. Quiescent Current vs.
Temperature

2–

60– 20– 0 20406080100 140

40–

TEMPERATURE – ⴗC

120

Figure 5. Input Bias Current vs.
Temperature

40

NEGATIVE

CURRENT LIMIT

POSITIVE

CURRENT LIMIT

VS = ⴞ5V

AMBIENT TEMPERATURE – ⴗC

120

SHORT CIRCUIT CURRENT LIMIT – mA

35

30

25

20

15

60– 20– 0 20 40 60 80 100 14040–

Figure 8. Short Circuit Current
Limit vs. Temperature

0.001

CLOSED - LOOP OUTPUT IMPEDANCE – ⍀

1k 10k 100k 1M 10M 100M

FREQUENCY – Hz

Figure 6. Closed-Loop Output
Impedance vs. Frequency

65

VS = ±15V

= +20

A

V

= 0pF

C

60– 20– 0 20 40 60 80 100 14040–

COMP

120

TEMPERATURE – ⴗC

–3 dB BANDWIDTH – MHz

60

55

50

45

Figure 9. –3 dB Bandwidth vs.
Temperature

REV. E–4–

AD829

PHASE

+100

+80

+60

+40

+20

0

–20

120

100

80

60

40

OPEN-LOOP GAIN – dB

20

0
100 1k 10k 100k 1M 10M 100M

GAIN
ⴞ5V

Supplies
500⍀ Load

FREQUENCY – Hz

C

COMP

GAIN
ⴞ15V

Supplies
1k⍀ Load

= 0pF

Figure 10. Open-Loop Gain & Phase
Margin vs. Frequency

120

100

80

60

CMRR – dB

C

= 0pF

40

20

COMP

1k 10k 100k 1M 10M 100M

FREQUENCY – Hz

Figure 13. Common-Mode Rejection
Ratio vs. Frequency

105

PHASE – Degrees

100

95

90

85

OPEN-LOOP GAIN – dB

80

75

10 100

VS = ⴞ15V

VS = ⴞ5V

1k

LOAD RESISTANCE – ⍀

Figure 11. Open-Loop Gain vs.
Resistive Load

30

25

20

15

VS = ±5V

= 500⍀

R

L

10

A

= +20

V

C

5

OUTPUT VOLTAGE – Volts p–p

COMP

0

1

VS = ±15V

= 1k⍀

R

L

= +20

A

V

C

= 0pF

COMP

= 0pF

INPUT FREQUENCY – MHz

10 100

Figure 14. Large Signal Frequency
Response

10k

120

+

SUPPLY

100

80

SUPPLY–

60

PSRR – dB

40

C

= 0pF

COMP

20

1k 10k 100k 1M 10M 100M

FREQUENCY – Hz

Figure 12. Power Supply Rejection
Ratio (PSRR) vs. Frequency

10

8

6

4

2

0

2–

4–

6–

OUTPUT SWING FROM 0 TO ⴞV

8–

–10

0 20406080100120 160

0.1%

1%

1%

0.1%

SETTLING TIME – ns

ERROR
A

= –19

V

C

COMP

= 0pF

140

Figure 15. Output Swing & Error vs.
Settling Time

–70

–75

–80

–85

–90

THD – dB

–95

–100

–105

–110

100 300 1k 3k 10k 30k 100k

VIN = 3V RMS

= –1

A

V

= 30pF

C

COMP

C

= 100pF

LOAD

RL = 500⍀

RL = 2k⍀

FREQUENCY – Hz

Figure 16. Total Harmonic Dis­tortion (THD) vs. Frequency

REV. E

–20

VIN = 2.24V RMS

= –1

A

–30

V

= 250⍀

R

L

= 0

C

LOAD

= 30pF

C

COMP

–40

THD – dB

–50

–60

–70

0 500k 1M 1.5M 2M

3rd HARMONIC

2nd HARMONIC

FREQUENCY – Hz

Figure 17. 2nd & 3rd Harmonic
Distortion vs. Frequency

–5–

5

4

3

2

1

INPUT VOLTAGE NOISE – nV/ Hz

0

10 100 1k 10k 100k

FREQUENCY – Hz

1M 10M

Figure 18. Input Voltage Noise
Spectral Density

AD829–Typical Performance Characteristics

+V

S

0.1␮F

C

COMP

(EXTERNAL)

–V

S

0.1␮F

OFFSET

NULL

ADJUST

20k⍀

AD829

400

60– 20– 0 20 40 60 80 100 14040–

AV = +20
SLEW RATE 10 – 90%

VS = ⴞ15V

VS = ⴞ5V

TEMPERATURE – ⴗC

RISE

FALL

RISE

FALL

120

350

300

250

200

SLEW RATE – Volts / ␮s

150

100

Figure 19. Slew Rate vs. Temperature

50⍀

HP8130A

5ns RISE TIME

CABLE

DIFF GAIN

0.043ⴗ

0.05

0.04

DIFFERENTIAL PHASE – Degrees

0.03
ⴞ5 ⴞ10 ⴞ15

SUPPLY VOLTAGE – Volts

DIFF PHASE

Figure 20. Differential Gain & Phase
vs. Supply

C

COMP

0.1␮F

50⍀

+15V

AD829

15pF

0.1␮F

5pF

50⍀

300⍀

0.03

0.02

0.01

DIFFERENTIAL GAIN – Percent

Figure 21. Offset Null and External
Shunt Compensation Connections

50⍀

CABLE

TEKTRONIX
TYPE 7A24
PREAMP

50⍀

Figure 22a. Follower Connection. Gain = +2

Figure 22b. Gain-of-2 Follower
Large Signal Pulse Response

–15V

300⍀

Figure 22c. Gain-of-2 Follower
Small Signal Pulse Response

REV. E–6–

AD829

HP8130A

5ns RISE TIME

50⍀

CABLE

45⍀

5⍀

100⍀

C

COMP

+15V

AD829

–15V

= 0pF

0.1␮F

0.1␮F

Figure 23a. Follower Connection. Gain = +20

1pF

2k⍀

105⍀

FET PROBE

TEKTRONIX

TYPE 7A24

PREAMP

Figure 23b. Gain-of-20 Follower
Large Signal Pulse Response

HP8130A

5ns RISE TIME

5pF

300⍀

+15V

0.1␮F

0.1␮F

C

15pF

COMP

50⍀

50⍀

CABLE

50⍀

CABLE

300⍀

50⍀

AD829

–15V

Figure 24a. Unity Gain Inverter Connection

Figure 23c. Gain-of-20 Follower
Small Signal Pulse Response

TEKTRONIX
TYPE 7A24
PREAMP

50⍀

Figure 24b. Unity Gain Inverter
Large Signal Pulse Response

REV. E

Figure 24c. Unity Gain Inverter
Small Signal Pulse Response

–7–

AD829

THEORY OF OPERATION

The AD829 is fabricated on Analog Devices’ proprietary comple­mentary bipolar (CB) process which provides PNP and NPN
transistors with similar f
the AD829 input stage consists of an NPN differential pair in
which each transistor operates at 600 µA collector current. This
gives the input devices a high transconductance and hence gives
the AD829 a low noise figure of 2 nV/

The input stage drives a folded cascode which consists of a fast
pair of PNP transistors. These PNPs then drive a current mirror
which provides a differential-input to single-ended-output con­version. The high speed PNPs are also used in the current­amplifying output stage which provides high current gain of
40,000. Even under conditions of heavy loading, the high f
of the NPN & PNPs, produced using the CB process, permit
cascading two stages of emitter followers while still maintaining
60° of phase margin at closed-loop bandwidths greater than
50 MHz.

Two stages of complementary emitter followers also effectively
buffer the high impedance compensation node (at the C
pin) from the output so that the AD829 can maintain a high dc
open-loop gain, even into low load impedances: 92 dB into a
150 Ω load, 100 dB into a 1 kΩ load. Laser trimming and
PTAT biasing assure low offset voltage and low offset voltage
drift enabling the user to eliminate ac coupling in many
applications.

For added flexibility, the AD829 provides access to the internal
frequency compensation node. This allows the user to customize
frequency response characteristics for a particular application.

Unity gain stability requires a compensation capacitance of
68 pF (Pin 5 to ground) which will yield a small signal band­width of 66 MHz and slew rate of 16 V/µs. The slew rate and
gain bandwidth product will vary inversely with compensation
capacitance. Table I and the graph of Figure 28 show the opti­mum compensation capacitance and the resulting slew rate for a
desired noise gain. For gains between 1 and 20, C
chosen to keep the small signal bandwidth relatively constant.
The minimum gain which will still provide stability also de­pends on the value of external compensation capacitance.

An RC network in the output stage (Figure 25) completely
removes the effect of capacitive loading when the amplifier is
compensated for closed-loop gains of 10 or higher. At low fre­quencies, and with low capacitive loads, the gain from the com­pensation node to the output is very close to unity. In this case,
C is bootstrapped and does not contribute to the compensation
capacitance of the device. As the capacitive load is increased, a
pole is formed with the output impedance of the output stage–
this reduces the gain, and subsequently, C is incompletely boot­strapped. Therefore, some fraction of C contributes to the
compensation capacitance, and the unity gain bandwidth falls.
As the load capacitance is further increased, the bandwidth
continues to fall, and the amplifier remains stable.

Externally Compensating the AD829

The AD829 is stable with no external compensation for noise
gains greater than 20. For lower gains, there are two methods of
frequency compensating the amplifier to achieve closed-loop
stability; these are the shunt and current feedback compensation
methods.

s of 600 MHz. As shown in Figure 25,

T

√

Hz @ 1 kHz.

s

T

COMP

can be

COMP

+V

S

15⍀

IN+

1.2mA

IN–

OFFSET NULL

C

COMP

C

12.5pF

R

500⍀

15⍀

OUTPUT

–V

S

Figure 25. AD829 Simplified Schematic

Shunt Compensation

Figures 26 and 27 show that the first method, shunt compensa­tion, has an external compensation capacitor, C

, connected

COMP

between the compensation pin and ground. This external
capacitor is tied in parallel with approximately 3 pF of inter­nal capacitance at the compensation node. In addition, a
small capacitance, C

, in parallel with resistor R2, compen-

LEAD

sates for the capacitance at the amplifier’s inverting input.

R2

C

LEAD

+V

S

0.1␮F

0.1␮F

C

COMP

1k⍀

V

OUT

50⍀

COAX

CABLE

V

IN

50⍀

R1

AD829

–V

S

Figure 26. Inverting Amplifier Connection Using External
Shunt Compensation

+V

S

C

0.1␮F

0.1␮F

COMP

V

OUT

R2

1k⍀

C

LEAD

R1

50⍀

CABLE

V

IN

50⍀

AD829

–V

S

Figure 27. Noninverting Amplifier Connection Using
External Shunt Compensation

–8–

REV. E

Table I. Component Selection for Shunt Compensation

Slew –3 dB

Follower Inverter R1 R2 C

C

L

COMP

Rate Small Signal

Gain Gain ⍀⍀pF pF V/␮s Bandwidth – MHz

1 Open 100 0 68 16 66
2 –1 1k 1k 5 25 38 71
5 –4 511 2.0k 1 7 90 76
10 –9 226 2.05k 0 3 130 65
20 –19 105 2k 0 0 230 55
25 –24 105 2.49 0 0 230 39
100 –99 20 2k 0 0 230 7.5

AD829

Table I gives recommended C

COMP

and C

values along with

LEAD

the corresponding slew rates and bandwidth. The capacitor
values given were selected to provide a small signal frequency
response with less than 1 dB of peaking and less than 10% over­shoot. For this table, supply voltages of ±15 volts should be
used. Figure 28 is a graphical extension of the table which
shows the slew rate/gain trade-off for lower closed-loop gains,
when using the shunt compensation scheme.

100

C

COMP

– pF

10

COMP

C

1

1 10010

Figure 28. Value of C

SLEW RATE

VS = ⴞ15V

NOISE GAIN

& Slew Rate vs. Noise Gain

COMP

1k

100

SLEW RATE = V/␮s

10

Current Feedback Compensation

Bipolar nondegenerated amplifiers which are single pole and
internally compensated have their bandwidths defined as:

fT=

2 π r

1

eCCOMP

=

2 π

kT

I

C

COMP

q

where:
f

is the unity gain bandwidth of the amplifier

T

I is the collector current of the input transistor

is the compensation capacitance

C

COMP

r

is the inverse of the transconductance of the input transistors

e

kT/q is approximately equal to 26 mV @ 27°C.
Since both f

and slew rate are functions of the same variables,

T

the dynamic behavior of an amplifier is limited. Since:

then:

Slew Rate

f

T

= 4 π

kT

q

This shows that the slew rate will be only 0.314 V/µs for every
MHz of bandwidth. The only way to increase slew rate is to
increase the f

and that is difficult, due to process limitations.

T

Unfortunately, an amplifier with a bandwidth of 10 MHz can
only slew at 3.1 V/µs, which is barely enough to provide a full
power bandwidth of 50 kHz.

The AD829 is especially suited to a new form of compensation
which allows for the enhancement of both the full power band­width and slew rate of the amplifier. The voltage gain from the
inverting input pin to the compensation pin is large; therefore, if
a capacitance is inserted between these pins, the amplifier’s
bandwidth becomes a function of its feedback resistor and this
capacitance. The slew rate of the amplifier is now a function of
its internal bias (2I) and this compensation capacitance.

Since the closed-loop bandwidth is a function of R

and C

F

COMP

(Figure 29), it is independent of the amplifier closed-loop gain,
as shown in Figure 31. To preserve stability, the time constant

and C

of R

F

65 MHz. For example, with C

needs to provide a bandwidth of less than

COMP

= 15 pF and RF = 1 kΩ, the

COMP

small signal bandwidth of the AD829 is 10 MHz, while Figure
30 shows that the slew rate is in excess of 60 V/µs. As can be
seen in Figure 31, the closed-loop bandwidth is constant for
gains of –1 to –4, a property of current feedback amplifiers.

R

F

C

COMP

0.1␮F
+V

AD829

–V

S

S

V

OUT

R

0.1␮F

1k⍀

L

50⍀

COAX

CABLE

V

IN

*RECOMMENDED VALUE

OF C
<7pF

7pF

50⍀

COMP

R1

C1*

FOR C

0pF
15pF

IN4148

1

C

SHOULD NEVER EXCEED

COMP

15pF FOR THIS CONNECTION

REV. E

Slew Rate =

C

2I

COMP

Figure 29. Inverting Amplifier Connection Using Current
Feedback Compensation

–9–

AD829

Figure 30. Large Signal Pulse Response of Inverting
Amplifier Using Current Feedback Compensation.

= 15 pF, C1 = 15 pF, RF = 1 kΩ, R1 = 1 k

C

COMP

15

GAIN = –4

12

9

GAIN = –2

6

–3dB @ 9.6MHz

3

GAIN = –1

0

–3dB @ 10.2MHz

VIN = –30dBM

= ⴞ15V

V

S

R

= 1k⍀

L

= 1k⍀

R

F

= 15pF

C

COMP

= 15pF

C

1

100k 100M

1M 10M

FREQUENCY – Hz

CLOSED-LOOP GAIN – dB

–3

–6

–9

–12

–15

–3dB @ 8.2MHz

Ω

Figure 31. Closed-Loop Gain vs. Frequency for the Circuit
of Figure 29

Figure 32 is an oscilloscope photo of the pulse response of a
unity gain inverter which has been configured to provide a small
signal bandwidth of 53 MHz and a subsequent slew rate of
180 V/µs; resistor R

= 3 kΩ, capacitor C

F

= 1 pF. Figure 33

COMP

shows the excellent pulse response as a unity gain inverter, this
time using component values of: R

= 1 kΩ and C

F

COMP

= 4 pF.

Figures 34 and 35 show the closed-loop frequency response of
the AD829 for different closed-loop gains and for different
supply voltages.

If a noninverting amplifier configuration using current feedback
compensation is desired, the circuit of Figure 36 is recom­mended. This circuit doubles the slew rate compared to the
shunt compensated noninverting amplifier of Figure 27 at the
expense of gain flatness. Nonetheless, this circuit delivers 95 MHz
bandwidth with ±1 dB flatness into a back terminated cable,
with a differential gain error of only 0.01%, and a differential
phase error of only 0.015° at 4.43 MHz.

Figure 32. Large Signal Pulse Response of the Inverting
Amplifier Using Current Feedback Compensation.
C

= 1 pF, RF = 3 kΩ, R1 = 3 k

COMP

Ω

Figure 33. Small Signal Pulse Response of Inverting
Amplifier Using Current Feedback Compensation.
C

= 4 pF, RF = 1 kΩ, R1 = 1 k

COMP

15

GAIN = –4

12

9

GAIN = –2

6

3

GAIN = –1

0

–3

VS = ⴞ15V

CLOSED-LOOP GAIN – dB

–12

–15

–6

–9

= 1k⍀

R

L

= 1k⍀

R

F

= –30dBM

V

IN

1M 10M

Ω

C

= 2pF

COMP

C

= 3pF

COMP

C

= 4pF

COMP

FREQUENCY – Hz

100M

Figure 34. Closed-Loop Frequency Response for the
Inverting Amplifier Using Current Feedback Compensation

–10–

REV. E

–17

50⍀

50⍀

COAX

CABLE

0.1␮F

3pF
C

COMP

0.1␮F

AD829

V

OUT

+15V

V

IN

–15V

50⍀

50⍀

COAX

CABLE

50⍀

2k⍀

2k⍀

–20

–23

–26

–29

–32

–35

OUTPUT LEVEL – dB

–38

–41

–44

–47

1M 10M

VIN = –20dBM

= 1k⍀

R

L

R

= 1k⍀

F

GAIN = –1

= 4pF

C

COMP

FREQUENCY – Hz

ⴞ5V

ⴞ15V

100M

Figure 35. Closed-Loop Frequency Response vs. Supply
for the Inverting Amplifier Using Current Feedback
Compensation

A Low Error Video Line Driver

The buffer circuit shown in Figure 37 will drive a back-termi­nated 75 Ω video line to standard video levels (1 V p-p) with

0.1 dB gain flatness to 30 MHz with only 0.04° and 0.02%
differential phase and gain at the 4.43 MHz PAL color
subcarrier frequency. This level of performance, which meets
the requirements for high definition video displays and test
equipment, is achieved using only 5 mA quiescent current.

A High Gain, Video Bandwidth Three Op Amp In Amp

Figure 38 shows a three op amp instrumentation amplifier cir­cuit which provides a gain of 100 at video bandwidths. At a
circuit gain of 100 the small signal bandwidth equals 18 MHz
into an FET probe. Small signal bandwidth equals 6.6 MHz
with a 50 Ω load. 0.1% settling time is 300 ns.

3pF

+V

IN

(G = 20)

A1

2–8pF

SETTLING TIME

AC CMR ADJUST

AD829

Figure 36. Noninverting Amplifier Connection Using
Current Feedback Compensation

+15V

0.1␮F

75⍀

V

IN

30pF

C

COMP

AD829

–15V

0.1␮F

75⍀

Figure 37. A Video Line Driver with a Flatness over
Frequency Adjustment

The input amplifiers operate at a gain of 20, while the output
op amp runs at a gain of 5. In this circuit the main bandwidth
limitation is the gain/ bandwidth product of the output ampli­fier. Extra care needs to be taken while breadboarding this cir­cuit, since even a couple of extra picofarads of stray capacitance
at the compensation pins of A1 and A2 will degrade circuit
bandwidth.

75⍀

300⍀

300⍀

COAX

CABLE

OPTIONAL
2 – 7pF
FLATNESS
TRIM

75⍀

V

OUT

970⍀

DC CMR
ADJUST

50⍀

A3

1k⍀

AD848

(G = 5)

4000⍀

(

R

2k⍀

+15V

10␮F

COMM

+ 1(5

G

–15V

10␮F

INPUT

FREQUENCY

100 Hz
1 MHz
10 MHz

0.1␮F

0.1␮F

+V

–V

CMRR

64.6dB

44.7dB

23.9dB

S

S

1␮F

1␮F

0.1␮F

0.1␮F

PIN 7

EACH
AMPLIFIER

PIN 4

–11–

AD829

2k⍀

210⍀

1pF

R

G

1pF

2k⍀

200⍀

200⍀

3pF

AD829

A2

+V

IN

(G = 20)

3pF

Figure 38. A High Gain, Video Bandwidth Three Op Amp In Amp Circuit

CIRCUIT GAIN =

REV. E

AD829

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Cerdip (Q) Package

PIN 1

0.165±0.01

(4.19±0.25)

0.125

(3.18)

MIN

0.018±0.003
(0.46±0.08)

0.005 (0.13) MIN

PIN 1

0.200

(5.08)

MAX

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

Plastic Mini-DIP (N) Package

8

1

0.39 (9.91) MAX

0.10

(2.54)

BSC

5

4

0.033
(0.84)
NOM

0.25

(6.35)

0.035±0.01
(0.89±0.25)

0.18±0.03
(4.57±0.76)

SEATING
PLANE

0.31

(7.87)

0.30 (7.62)
REF

0.011±0.003

(0.28±0.08)

15°

0°

0.055 (1.40) MAX

8

1

0.405 (10.29) MAX

0.100
(2.54)

BSC

5

4

0.070 (1.78)

0.030 (0.76)

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MIN

SEATING
PLANE

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

15

0

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.0098 (0.25)

0.0040 (0.10)
SEATING

°

°

8-Lead SOIC (R) Package

0.1968 (5.00)

0.1890 (4.80)

85

0.0500 (1.27)

PLANE

0.2440 (6.20)

0.2284 (5.80)

41

BSC

0.0192 (0.49)

0.0138 (0.35)

0.0688 (1.75)

0.0532 (1.35)

0.0098 (0.25)

0.0075 (0.19)

0.0196 (0.50)

0.0099 (0.25)

8ⴗ

0.0500 (1.27)

0ⴗ

0.0160 (0.41)

C1443c–0–5/00 (rev. E) 00880

ⴛ 45ⴗ

20-Lead LCC (E-20A) Package

0.200 (5.08)

0.075

(1.91)

REF

19

18

14

13

BSC

20

1

BOTTOM

VIEW

0.150 (3.81)

0.100 (2.54) BSC

0.015 (0.38)

3

MIN

4

0.050 (1.27)

8

BSC

9

45° TYP

BSC

0.028 (0.71)

0.022 (0.56)

0.358 (9.09)

0.342 (8.69)
SQ

0.100 (2.54)

0.064 (1.63)

0.358
(9.09)

MAX

SQ

0.088 (2.24)

0.054 (1.37)

0.095 (2.41)

0.075 (1.90)

0.011 (0.28)

0.007 (0.18)
R TYP

0.075 (1.91)

REF

0.055 (1.40)

0.045 (1.14)

All brand or product names mentioned are trademarks or registered trademarks of their respective holders.

–12–

PRINTED IN U.S.A.

REV. E