Datasheet AD824AR-3V, AD824AR-16, AD824AR-14-3V, AD824AR-14, AD824AR Datasheet (Analog Devices)

Single Supply, Rail-to-Rail

1

2

14

13

5

6

7

10

9

8

3

4

12

11

TOP VIEW

AD824

OUT A

–IN A

+IN A

V+

+IN B

–IN B

OUT B

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

a

FEATURES
Single Supply Operation: 3 V to 30 V
Very Low Input Bias Current: 2 pA
Wide Input Voltage Range
Rail-to-Rail Output Swing
Low Supply Current: 500 A/Amp
Wide Bandwidth: 2 MHz
Slew Rate: 2 V/s
No Phase Reversal

APPLICATIONS
Photo Diode Preamplifier
Battery Powered Instrumentation
Power Supply Control and Protection
Medical Instrumentation
Remote Sensors
Low Voltage Strain Gage Amplifiers
DAC Output Amplifier

GENERAL DESCRIPTION

The AD824 is a quad, FET input, single supply amplifier, fea­turing rail-to-rail outputs. The combination of FET inputs and
rail-to-rail outputs makes the AD824 useful in a wide variety of
low voltage applications where low input current is a primary
consideration.

The AD824 is guaranteed to operate from a 3 V single supply
up to ±15 V dual supplies.

Fabricated on ADI’s complementary bipolar process, the AD824
has a unique input stage that allows the input voltage to safely
extend beyond the negative supply and to the positive supply
without any phase inversion or latchup. The output voltage
swings to within 15 mV of the supplies. Capacitive loads to
350 pF can be handled without oscillation.

The FET input combined with laser trimming provides an input
that has extremely low bias currents with guaranteed offsets
below 300 µV. This enables high accuracy designs even with
high source impedances. Precision is combined with low
noise, making the AD824 ideal for use in battery powered
medical equipment.

Low Power, FET-Input Op Amp

AD824

PIN CONFIGURATIONS

14-Lead Epoxy DIP

(N Suffix)

16-Lead Epoxy SO

(R Suffix)

OUT A

1

–IN A

2

+IN A

3

V+

4

AD824

5

+IN B

–IN B

6

OUT B

7

8

NC

NC = NO CONNECT

Applications for the AD824 include portable medical equipment,
photo diode preamplifiers and high impedance transducer
amplifiers.

The ability of the output to swing rail-to-rail enables designers
to build multistage filters in single supply systems and maintain
high signal-to-noise ratios.

The AD824 is specified over the extended industrial (–40°C to
+85°C) temperature range and is available in 14-pin DIP and
narrow 14-lead and 16-lead SO packages.

14-Lead Epoxy SO

(R Suffix)

1

OUT A

2

–IN A

3

+IN A

V+

+IN B

–IN B

OUT B

4

5

6

7

16

15

14

13

12

11

10

9

AD824

TOP VIEW

(Not to Scale)

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

NC

14

13

12

11

10

9

8

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

AD824–SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

(@ VS = 5.0 V, VCM = 0 V, V

= 0.2 V, TA = 25C unless otherwise noted)

OUT

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage AD824A V

Input Bias Current I

Input Offset Current I

B

OS

OS

T

to T

MIN

T

MIN

T

MIN

to T

to T

MAX

MAX

MAX

0.1 1.0 mV

1.5 mV
212pA
300 4000 pA
210pA
300 pA

Input Voltage Range –0.2 3.0 V
Common-Mode Rejection Ratio CMRR V

Input Impedance 10
Large Signal Voltage Gain A

VO

= 0 V to 2 V 66 80 dB

CM

= 0 V to 3 V 60 74 dB

V

CM

T

MIN

to T

MAX

60 dB

13

储3.3 Ω储pF

VO = 0.2 V to 4.0 V
R

= 2 kΩ 20 40 V/mV

L

R

= 10 kΩ 50 100 V/mV

L

= 100 kΩ 250 1000 V/mV

R

L

T

MIN

to T

= 100 kΩ 180 400 V/mV

MAX, RL

Offset Voltage Drift ∆VOS/∆T2µV/°C

OUTPUT CHARACTERISTICS

Output Voltage High V

Output Voltage Low V

Short Circuit Limit I

Open-Loop Impedance Z

OH

OL

SC

OUT

I

= 20 µA 4.975 4.988 V

SOURCE

to T

T

MIN

I

SOURCE

T

MIN

I

SINK

T

MIN

I

SINK

T

MIN

MAX

= 2.5 mA 4.80 4.85 V

to T

MAX

= 20 µA1525mV

to T

MAX

= 2.5 mA 120 150 mV

to T

MAX

4.97 4.985 V

4.75 4.82 V

20 30 mV

140 200 mV

Sink/Source ±12 mA

to T

T

MIN

MAX

±10 mA

f = 1 MHz, AV = 1 100 Ω

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 2.7 V to 12 V 70 80 dB

T

Supply Current/Amplifier I

SY

to T

MIN

T

MIN

to T

MAX

MAX

66 dB

500 600 µA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 10 kΩ, AV = 1 2 V/µs
Full-Power Bandwidth BW
Settling Time t

S

P

1% Distortion, VO = 4 V p-p 150 kHz
V

= 0.2 V to 4.5 V, to 0.01% 2.5 µs

OUT

Gain Bandwidth Product GBP 2 MHz
Phase Margin φo No Load 50 Degrees
Channel Separation CS f = 1 kHz, RL = 2 kΩ –123 dB

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 2 µV p-p
Voltage Noise Density e
Current Noise Density i

n

n

f = 1 kHz 16 nV/√Hz
f = 1 kHz 0.8 fA/√Hz

Total Harmonic Distortion THD f = 10 kHz, RL = 0, AV = +1 0.005 %

–2–

REV. B

AD824

ELECTRICAL SPECIFICATIONS

(@ VS = 15.0 V, V

= 0 V, TA = 25C unless otherwise noted)

OUT

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage AD824A V

Input Bias Current I

Input Offset Current I

OS

B

I

B

OS

to T

T

MIN

MAX

VCM = 0 V 4 35 pA
T

to T

MIN

MAX

VCM = –10 V 25 pA

T

to T

MIN

MAX

0.5 2.5 mV

0.6 4.0 mV

500 4000 pA

320 pA

500 pA
Input Voltage Range –15 13 V
Common-Mode Rejection Ratio CMRR V

Input Impedance 10
Large Signal Voltage Gain A

VO

= –15 V to 13 V 70 80 dB

CM

T

MIN

to T

MAX

66 dB

13

储3.3 Ω储pF

Vo = –10 V to +10 V;
R

= 2 kΩ 12 50 V/mV

L

= 10 kΩ 50 200 V/mV

R

L

R

= 100 kΩ 300 2000 V/mV

L

T

MIN

to T

= 100 kΩ 200 1000 V/mV

MAX, RL

Offset Voltage Drift ∆VOS/∆T2µV/°C

OUTPUT CHARACTERISTICS

Output Voltage High V

Output Voltage Low V

Short Circuit Limit I
Open-Loop Impedance Z

OH

OL

SC

OUT

I

= 20 µA 14.975 14.988 V

SOURCE

T

to T

MIN

I

SOURCE

T

MIN

I

SINK

T

MIN

I

SINK

T

MIN

Sink/Source, T

MAX

= 2.5 mA 14.80 14.85 V

to T

MAX

= 20 µA –14.985 –14.975 V

to T

MAX

= 2.5 mA –14.88 –14.85 V

to T

MAX

MIN

to T

MAX

14.970 14.985 V

14.75 14.82 V

–14.98 –14.97 V

–14.86 –14.8 V

±8 ± 20 mA

f = 1 MHz, AV = 1 100 Ω

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 2.7 V to 15 V 70 80 dB

T

Supply Current/Amplifier I

SY

to T

MIN

MAX

VO = 0 V 560 625 µA
T

to T

MIN

MAX

68 dB

675 µA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 10 kΩ, AV = 1 2 V/µs
Full-Power Bandwidth BW
Settling Time t

S

P

1% Distortion, VO = 20 V p-p 33 kHz
V

= 0 V to 10 V, to 0.01% 6 µs

OUT

Gain Bandwidth Product GBP 2 MHz
Phase Margin φo 50 Degrees
Channel Separation CS f = 1 kHz, RL =2 kΩ –123 dB

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 2 µV p-p
Voltage Noise Density e
Current Noise Density i

n

n

Total Harmonic Distortion THD f =10 kHz, V

f = 1 kHz 16 nV/√Hz
f = 1 kHz 1.1 fA/√Hz

= 3 V rms,

O

RL = 10 kΩ 0.005 %

REV. B

–3–

AD824–SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

(@ VS = 3.0 V, VCM = 0 V, V

= 0.2 V, TA = 25C unless otherwise noted)

OUT

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage AD824A -3 V V

Input Bias Current I

Input Offset Current I

B

OS

OS

T

to T

MIN

T

MIN

T

MIN

to T

to T

MAX

MAX

MAX

0.2 1.0 mV

1.5 mV
212pA
250 4000 pA
210pA
250 pA

Input Voltage Range 0 1 V
Common-Mode Rejection Ratio CMRR V

Input Impedance 10
Large Signal Voltage Gain A

VO

= 0 V to 1 V 58 74 dB

CM

T

MIN

to T

MAX

56 dB

13

储3.3 Ω储pF

VO = 0.2 V to 2.0 V
R

= 2 kΩ 10 20 V/mV

L

= 10 kΩ 30 65 V/mV

R

L

R

= 100 kΩ 180 500 V/mV

L

T

MIN

to T

= 100 kΩ 90 250 V/mV

MAX, RL

Offset Voltage Drift ∆VOS/∆T2µV/°C

OUTPUT CHARACTERISTICS

Output Voltage High V

Output Voltage Low V

Short Circuit Limit I

Open-Loop Impedance Z

I

OH

OL

SC

SC

OUT

I

= 20 µA 2.975 2.988 V

SOURCE

T

to T

MIN

I

SOURCE

T

MIN

I

SINK

T

MIN

I

SINK

T

MIN

MAX

= 2.5 mA 2.8 2.85 V

to T

MAX

= 20 µA1525mV

to T

MAX

= 2.5 mA 120 150 mV

to T

MAX

2.97 2.985 V

2.75 2.82 V

20 30 mV

140 200 mV

Sink/Source ±8mA
Sink/Source, T

MIN

to T

MAX

±6mA

f = 1 MHz, AV = 1 100 Ω

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 2.7 V to 12 V, 70 dB

Supply Current/Amplifier I

SY

to T

T

MIN

MAX

VO = 0.2 V, T

MIN

to T

MAX

66 dB

500 600 µA

DYNAMIC PERFORMANCE

Slew Rate SR RL =10 kΩ, AV = 1 2 V/µs
Full-Power Bandwidth BW
Settling Time t

S

P

1% Distortion, VO = 2 V p-p 300 kHz
V

= 0.2 V to 2.5 V, to 0.01% 2 µs

OUT

Gain Bandwidth Product GBP 2 MHz
Phase Margin φo 50 Degrees
Channel Separation CS f = 1 kHz, RL = 2 kΩ –123 dB

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 2 µV p-p
Voltage Noise Density e
Current Noise Density i

n

n

f = 1 kHz 16 nV/√Hz

0.8 fA/√Hz

Total Harmonic Distortion THD f = 10 kHz, RL = 0, AV = +1 0.01 %

–4–

REV. B

AD824

R1 R2

+IN

J1 J2

R13

–IN

R15

Q4

Q5

Q6

R9

I5

V

CC

C3

Q7

C2

Q22

Q19

Q21 Q27

Q18 Q29

Q20

Q23

R7

C4

V

OUT

Q24 Q25

Q31

Q28

R17

Q26

C1

I4I3I2I1

R12 R14

Q2

Q8

Q3

V

EE

I6

WAFER TEST LIMITS

(@ VS = 5.0 V, VCM = 0 V, TA = 25C unless otherwise noted)

Parameter Symbol Conditions Limit Unit

Offset Voltage V
Input Bias Current I
Input Offset Current I
Input Voltage Range V

OS

B

OS

CM

Common-Mode Rejection Ratio CMRR V

= 0 V to 2 V 66 dB min

CM

1.0 mV max
12 pA max
20 pA
–0.2 to 3.0 V min

Power Supply Rejection Ratio PSRR V = + 2.7 V to +12 V 70 µV/V
Large Signal Voltage Gain A
Output Voltage High V
Output Voltage Low V
Supply Current/Amplifier I

NOTE
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for
standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

ABSOLUTE MAXIMUM RATINGS

1

VO

OH

OL

SY

RL = 2 kΩ 15 V/mV min
I

= 20 µA 4.975 V min

SOURCE

I

= 20 µA25 mV max

SINK

VO = 0 V, RL = ∞ 600 µA max

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . –V

– 0.2 V to +V

S

S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 30 V

Output Short Circuit Duration to GND . . . . . . . . . Indefinite

Storage Temperature Range

N, R Package . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range

AD824A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Junction Temperature Range

N, R Package . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C

Package Type θ

2

JA

θ

JC

Units

14-Pin Plastic DIP (N) 76 33 °C/W
14-Pin SOIC (R) 120 36 °C/W
16-Pin SOIC (R) 92 27 °C/W

NOTES

1

Absolute maximum ratings apply to packaged parts unless otherwise noted.

2

θJA is specified for the worst case conditions, i.e., θ

for P-DIP packages; θJA is specified for device soldered in circuit board for SOIC
package.

is specified for device in socket

JA

Figure 1. Simplified Schematic of 1/4 AD824

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD824AN* –40°C to +85°C 14-Pin Plastic DIP N-14
AD824AR –40°C to +85°C 14-Pin SOIC R-14
AD824AR-3V –40°C to +85°C 14-Pin SOIC R-14
AD824AR-14 –40°C to +85°C 14-Pin SOIC R-14
AD824AR-14-3V –40°C to +85°C 14-Pin SOIC R-14

AD824AR-16 –40°C to +85°C 16-Pin SOIC R-16

*Not for new designs. Obsolete April 2002.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD824 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. B

–5–

WARNING!

ESD SENSITIVE DEVICE

AD824

–Typical Performance Characteristics

1µs50mV

VS = 15V
NO LOAD

45

90

135

180

80

60

40

GAIN – dB

20

0

100 10M1k 10k 100k 1M

100

90

10

0%

TPC 1. Open-Loop Gain/Phase and Small Signal
Response, V

= ±15 V, No Load

S

PHASE – Degrees

1µs50mV

VS = 5V
NO LOAD

45

90

135

180

80

60

40

GAIN – dB

20

0

100 10M1k 10k 100k 1M

100

90

10

0%

TPC 3. Open-Loop Gain/Phase and Small Signal
Response, V

= 5 V, No Load

S

PHASE – Degrees

80

60

40

GAIN – dB

20

0

100 10M1k 10k 100k 1M

100

90

10

0%

1µs50mV

VS = 15V

= 100pF

C

L

45

90

135

180

PHASE – Degrees

GAIN – dB

–20

60

40

20

0

100

90

10

0%

VS = 5V

= 220pF

C

L

45

90

135

180

PHASE – Degrees

10M1k 10k 100k 1M

1µs50mV

TPC 2. Open-Loop Gain/Phase and Small Signal
Response, V

= ±15 V, CL = 100 pF

S

–6–

TPC 4. Open-Loop Gain/Phase and Small Signal
Response, V

= 5 V, CL = 220 pF

S

REV. B

AD824

1µs50mV

VS = 3V
NO LOAD

45

90

135

180

10M1k 10k 100k 1M

GAIN – dB

–20

60

40

20

0

100

90

10

0%

TPC 5. Open-Loop Gain/Phase and Small Signal
Response, V

= 3 V, No Load

S

PHASE – Degrees

t

100

90

10

0%

t

10.810

100

90

10

0%

TPC 7. Slew Rate, RL = 10k

9.950

2µs5V

2µs5V

µs

µs

GAIN – dB

–20

= 3V

60

40

20

0

V

S

CL = 220pF

45

90

135

180

PHASE – Degrees

100

90

V

OUT

10

0%

5V

100µs

TPC 8. Phase Reversal with Inputs Exceeding Supply by 1 V

10M1k 10k 100k 1M

0.8

0.7

0.6

100

90

10

0%

1µs50mV

0.5

0.4

0.3

0.2

OUTPUT TO RAIL – Volts

0.1

0

1 10m5 10 50 100 500 1m 5m

LOAD CURRENT – A

SOURCE

SINK

TPC 6. Open-Loop Gain/Phase and Small Signal
Response, V

= 3 V, CL = 220 pF

S

REV. B

TPC 9. Output Voltage to Supply Rail vs. Sink and Source
Load Currents

–7–

AD824

–TYPICAL PERFORMANCE CHARACTERISTICS

14

COUNT = 60

12

60

40

20

NOISE DENSITY – nV/ Hz

5 10 15 20

3V VS 15V

FREQUENCY – kHz

TPC 10. Voltage Noise Density

0.1

RL = 0
A

0.010

THD+N – %

0.001

0.0001
20 100 1k 10k 20k

VS = +3

VS = +5

VS = 15

FREQUENCY – Hz

V

= +1

10

8

6

4

NUMBER OF UNITS

2

0
–2.5 2.5–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0

OFFSET VOLTAGE DRIFT

TPC 13. TC VOS Distribution, –55°C to +125°C, VS = 5, 0

150

125

100

75

50

25

0

INPUT OFFSET CURRENT – pA

–25

–60 140–40 –20 0 20 40 60 80 100 120

TEMPERATURE – C

VS = 5, 0

TPC 11. Total Harmonic Distortion

280

240

200

160

120

NUMBER OF UNITS

80

40

0

–0.5 0.5–0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4

OFFSET VOLTAGE – mV

COUNT = 860

TPC 12. Input Offset Distribution, VS = 5, 0

TPC 14. Input Offset Current vs. Temperature

100k

VS = 5, 0

10k

1k

100

10

INPUT BIAS CURRENT – pA

1

20 14040 60 80 100 120

TEMPERATURE – C

TPC 15. Input Bias Current vs. Temperature

–8–

REV. B

120

FREQUENCY – Hz

1k

INPUT VOLTAGE NOISE – nV/√Hz

100

1

1 100k10 100 1k 10k

10

100

80

60

40

20

COMMON-MODE REJECTION – dB

0

10 10M100 1k 10k 100k 1M

FREQUENCY – Hz

AD824

TPC 16. Common-Mode Rejection vs. Frequency

–40

–60

–80

THD – dB

–100

–120

100 100k1k 10k

FREQUENCY – Hz

TPC 17. THD vs. Frequency, 3 V rms

100

80

100

80

TPC 19. Input Voltage Noise Spectral Density vs.
Frequency

120

100

80

60

40

20

POWER SUPPLY REJECTION – dB

0

10 10M100

1k 10k 100k 1M

FREQUENCY – Hz

TPC 20. Power Supply Rejection vs. Frequency

30

25

60

40

20

OPEN-LOOP GAIN – dB

0

–20

10 10M100

TPC 18. Open-Loop Gain and Phase vs. Frequency

REV. B

15V

3, 0V

1k 10k 100k 1M

FREQUENCY – Hz

60

40

20

0

–20

PHASE MARGIN – Degrees

–9–

20

15

10

OUTPUT VOLTAGE – Volts

5

0

1k 1M3k

10k 30k 100k 300k

INPUT FREQUENCY – Hz

TPC 21. Large Signal Frequency Response

AD824

–80

–90

–100

–110

CROSSTALK – dB

–120

–130

–140

10 100

1k 10k 100k

FREQUENCY – Hz

TPC 22. Crosstalk vs. Frequency

10k

1k

100

10

1

OUTPUT IMPEDANCE –

.1

1 TO 4

1 TO 2

1 TO 3

100

90

10

0%

TPC 25. Large Signal Response

2750

2500

2250

2000

1750

1500

SUPPLY CURRENT – µA

1250

5µs5V

VS = 15V

VS = 3, 0

.01

10 10M100

1k 10k 100k 1M

FREQUENCY – Hz

TPC 23. Output Impedance vs. Frequency, Gain = +1

500ns20mV

100

90

10

0%

TPC 24. Small Signal Response, Unity Gain Follower,

储

100 pF Load

10k

1000

–60 140–40

–20 0 20 40 60 80 100 120

TEMPERATURE – C

TPC 26. Supply Current vs. Temperature

1000

VS = 15V
V

= 3, 0

S

100

V

– V

OL

S

10

OUTPUT SATURATION VOLTAGE – mV

0

0.01 10.00.10 1.0

VS – V

OH

LOAD CURRENT – mA

TPC 27. Output Saturation Voltage

–10–

REV. B

AD824

APPLICATION NOTES

INPUT CHARACTERISTICS

In the AD824, n-channel JFETs are used to provide a low
offset, low noise, high impedance input stage. Minimum input
common-mode voltage extends from 0.2 V below –V
than +V

. Driving the input voltage closer to the positive rail will

S

to 1 V less

S

cause a loss of amplifier bandwidth.

The AD824 does not exhibit phase reversal for input voltages
up to and including +V
AD824 voltage follower to a 0 V to 5 V (+V

. Figure 2a shows the response of an

S

) square wave input.

S

The input and output are superimposed. The output tracks the
input up to +V

without phase reversal. The reduced bandwidth

S

above a 4 V input causes the rounding of the output wave form.
For input voltages greater than +V

, a resistor in series with

S

the AD824’s noninverting input will prevent phase reversal at
the expense of greater input voltage noise. This is illustrated in
Figure 2b.

2µs1V

100

90

10

GND

0%

1V

(a)

10µs1V

+V

GND

1V

100

90

S

10

0%

1V

(b)

R

V

IN

Figure 2. (a) Response with RP = 0; V

+5V

P

V

OUT

from 0 to +V

IN

S

(b) VIN = 0 to + VS + 200 m V

= 0 to + V

V

OUT

RP = 49.9 k

S

Ω

Since the input stage uses n-channel JFETs, input current
during normal operation is positive; the current flows out from
the input terminals. If the input voltage is driven more positive
than +V

– 0.4 V, the input current will reverse direction as

S

internal device junctions become forward biased. This is
illustrated in TPC 8.

A current-limiting resistor should be used in series with the
input of the AD824 if there is a possibility of the input voltage
exceeding the positive supply by more than 300 mV or if an
input voltage will be applied to the AD824 when ± V

= 0. The

S

amplifier will be damaged if left in that condition for more than
10 seconds. A 1 kΩ resistor allows the amplifier to withstand up
to 10 V of continuous overvoltage and increases the input volt­age noise by a negligible amount.

Input voltages less than –V

are a completely different story.

S

The amplifier can safely withstand input voltages 20 V below
the minus supply voltage as long as the total voltage from the
positive supply to the input terminal is less than 36 V. In addition,
the input stage typically maintains picoamp level input currents
across that input voltage range.

OUTPUT CHARACTERISTICS

The AD824’s unique bipolar rail-to-rail output stage swings
within 15 mV of the positive and negative supply voltages. The
AD824’s approximate output saturation resistance is 100 Ω for
both sourcing and sinking. This can be used to estimate output
saturation voltage when driving heavier current loads. For
instance, the saturation voltage will be 0.5 V from either supply
with a 5 mA current load.

For load resistances over 20 kΩ, the AD824’s input error
voltage is virtually unchanged until the output voltage is driven
to 180 mV of either supply.

If the AD824’s output is overdriven so as to saturate either of
the output devices, the amplifier will recover within 2 µs of its
input returning to the amplifier’s linear operating region.

Direct capacitive loads will interact with the amplifier’s effective
output impedance to form an additional pole in the amplifier’s
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. Worst case is when the amplifier is
used as a unity gain follower. TPC 4 and 6 show the AD824’s
pulse response as a unity gain follower driving 220 pF. Configu­rations with less loop gain, and as a result less loop bandwidth,
will be much less sensitive to capacitance load effects. Noise
gain is the inverse of the feedback attenuation factor provided
by the feedback network in use.

Figure 3 shows a method for extending capacitance load drive
capability for a unity gain follower. With these component val­ues, the circuit will drive 5,000 pF with a 10% overshoot.

+V

S

0.01F

8

V

IN

1/4

AD824

4

–V

20k

0.01F

S

20pF

100

V

OUT

C

L

Figure 3. Extending Unity Gain Follower Capacitive Load
Capability Beyond 350 pF

REV. B

–11–

AD824

APPLICATIONS
Single Supply Voltage-to-Frequency Converter

The circuit shown in Figure 4 uses the AD824 to drive a low
power timer, which produces a stable pulse of width t

. The

1

positive going output pulse is integrated by R1-C1 and used as
one input to the AD824, which is connected as a differential
integrator. The other input (nonloading) is the unknown voltage,
VIN. The AD824 output drives the timer trigger input, closing
the overall feedback loop.

10V

C5

0.1F

3

0V TO 2.5V
FULL SCALE

REF02

2

V

6

5

4

499k, 1%

R1

499k, 1%

0.01F, 2%

U4

= 5V

REF

CMOS

**

R

R2

SCALE

10k

74HCO4

4

0.01F, 2%

U1

1/4

U3B U3A

32 1

C1

AD824B

C2

NOTES

= VIN/(VREF  t1), t1 = 1.1  R3  C6

f

OUT

= 25kHz fS AS SHOWN.

* = 1% METAL FILM, <50ppm/C TC

** = 10%, 20T FILM, <100ppm/C TC

t

= 33s FOR f

1

OUT

U2
CMOS 555

THR

6

TR

2

DIS

7

48

RV+

GND

1

R3*

116k

C6

390pF

5%

(NPO )

= 20kHz @ VIN = 2.0V

OUT

CV

0.1F

C3

0.1F

C4

OUT2

OUT1

3

5

Figure 4. Single Supply Voltage-to-Frequency Converter

Typical AD824 bias currents of 2 pA allow megaohm-range
source impedances with negligible dc errors. Linearity errors on
the order of 0.01% full scale can be achieved with this circuit.
This performance is obtained with a 5 V single supply, which
delivers less than 3 mA to the entire circuit.

Single Supply Programmable Gain Instrumentation Amplifier

The AD824 can be configured as a single supply instrumenta­tion amplifier that is able to operate from single supplies down
to 3 V or dual supplies up to ±15 V. AD824 FET inputs’ 2 pA
bias currents minimize offset errors caused by high unbalanced
source impedances.

An array of precision thin-film resistors sets the in amp gain to
be either 10 or 100. These resistors are laser-trimmed to ratio
match to 0.01% and have a maximum differential TC of 5 ppm/°C.

Table I. AD824 In Amp Performance

Parameters VS = 3 V, 0 V VS = 5 V

CMRR 74 dB 80 dB
Common-Mode

Voltage Range –0.2 V to +2 V –5.2 V to +4 V

3 dB BW, G = 10 180 kHz 180 kHz

G = 100 18 kHz 18 kHz

t

SETTLING

2 V Step (VS = 0 V, 3 V) 2 µs
5 V (V

= ±5 V) 5 µs

S

Noise @ f = 1 kHz, G = 10 270 nV/√Hz 270 nV/√Hz

G = 100 2.2 µV/√Hz 2.2 µV/√Hz

5µs

100

90

10

0%

1V

Figure 5a. Pulse Response of In Amp to a 500 mV p-p

Input Signal; V

V

REF

V

IN1

V

IN2

90kR29kR31kR41kR59kR690k

G = 10 G = 100 G = 10G = 100

R

P

1k

R

1k

(G = 10) V

(G = 100) V

FOR R1 = R6, R2 = R5 AND R3 = R4

R1

= 5 V, 0 V; Gain = 10

S

+V

S

0.1F

2

1

1/4

AD824

3

P

= (V

OUT

= (V

– V

IN1

IN1

OUT

) (1+ ) + V

IN2

– V

) (1+ ) + V

IN2

6

AD824

5

R6

R4 + R5

R5 + R6

R4

1/4

OHMTEK
PART # 1043

7

V

11

REF

REF

OUT

Figure 5b. A Single Supply Programmable
Instrumentation Amplifier

–12–

REV. B

AD824

3.3/5V

3.3/5V

R1

50k

R2

50k

A1

3

2

4

1

11

0.1F

FALSE GROUND (FG)

A4

12

13

14

SAMPLE/

HOLD

A3

10

9

8

A2

5

6

7

15

14

16

10

9

11

AD824B

3.3/5V

ADG513

R5

2k

AD824C

+

–

V

OUT

CH

C
500pF

FG

4

5

8

6

7

2

3

1

AD824A

AD824D

R4

2k

FG

13

500pF

FG

A1

A2

A3

A4

3 Volt, Single Supply Stereo Headphone Driver

The AD824 exhibits good current drive and THD+N perfor­mance, even at 3 V single supplies. At 1 kHz, total harmonic
distortion plus noise (THD+N) equals –62 dB (0.079%) for a
300 mV p-p output signal. This is comparable to other single
supply op amps that consume more power and cannot run on 3 V
power supplies.

In Figure 6, each channel’s input signal is coupled via a 1 µF
Mylar capacitor. Resistor dividers set the dc voltage at the
noninverting inputs so that the output voltage is midway between
the power supplies (1.5 V). The gain is 1.5. Each half of the
AD824 can then be used to drive a headphone channel. A 5 Hz
high-pass filter is realized by the 500 µF capacitors and the
headphones, which can be modeled as 32 ohm load resistors to
ground. This ensures that all signals in the audio frequency
range (20 Hz–20 kHz) are delivered to the headphones.

3V

0.1F

L

R

CHANNEL 1

CHANNEL 2

1F

MYLAR

95.3k

1F

MYLAR

95.3k

47.5k

47.5k

AD824

AD824

10k

10k

AD824

AD824

1/4

1/4

1/4

1/4

4.99k

4.99k

0.1F

500F

HEADPHONES

32 IMPEDANCE

500F

of 4.5 V can be used to drive an A/D converter front end. The
other half of the AD824 is configured as a unity-gain inverter
and generates the other bridge input of –4.5 V. Resistors R1 and
R2 provide a constant current for bridge excitation. The AD620
low power instrumentation amplifier is used to condition the
differential output voltage of the bridge. The gain of the AD620
is programmed using an external resistor R

49.4 kΩ

G =

R

G

and determined by:

G

+ 1

A 3.3 V/5 V Precision Sample-and-Hold Amplifier

In battery-powered applications, low supply voltage operational
amplifiers are required for low power consumption. Also, low
supply voltage applications limit the signal range in precision
analog circuitry. Circuits like the sample-and-hold circuit shown
in Figure 8, illustrate techniques for designing precision analog
circuitry in low supply voltage applications. To maintain high
signal-to-noise ratios (SNRs) in a low supply voltage application
requires the use of rail-to-rail, input/output operational amplifi­ers. This design highlights the ability of the AD824 to operate
rail-to-rail from a single 3 V/5 V supply, with the advantages of
high input impedance. The AD824, a quad JFET-input op amp,
is well suited to S/H circuits due to its low input bias currents
(3 pA, typical) and high input impedances (3 × 10

13

Ω, typical).

The AD824 also exhibits very low supply currents so the total
supply current in this circuit is less than 2.5 mA.

Figure 6. 3 Volt Single Supply Stereo Headphone Driver

Low Dropout Bipolar Bridge Driver

The AD824 can be used for driving a 350 ohm Wheatstone
bridge. Figure 7 shows one half of the AD824 being used to
buffer the AD589—a 1.235 V low power reference. The output

+V

S

REV. B

49.9k

+1.235V

AD589

10k

1%

10k

1%

1/4
1/4

AD824

AD824

26.4k, 1%

350 350

10k

1%

1/4

1/4

AD824

AD824

Figure 7. Low Dropout Bipolar Bridge Driver

R1
20

350 350

–4.5V

R2
20

TO A/D CONVERTER
REFERENCE INPUT

3

AD824

R

G

2

+V

S

–V

S

0.1F

GND

0.1F

–V

S

+V

AD620

4

–V

S

7

5

V

REF

S

6

Figure 8. 3.3 V/5.5 V Precision Sample and Hold

In many single supply applications, the use of a false ground
generator is required. In this circuit, R1 and R2 divide the

+5V

1F

1F

–5V

supply voltage symmetrically, creating the false ground voltage
at one-half the supply. Amplifier A1 then buffers this voltage
creating a low impedance output drive. The S/H circuit is con­figured in an inverting topology centered around this false
ground level.

–13–

AD824

A design consideration in sample-and-hold circuits is voltage
droop at the output caused by op amp bias and switch leakage
currents. By choosing a JFET op amp and a low leakage CMOS
switch, this design minimizes droop rate error to better than

0.1 µV/µs in this circuit. Higher values of CH will yield a lower
droop rate. For best performance, C

and C2 should be poly-

H

styrene, polypropylene or Teflon capacitors. These types of
capacitors exhibit low leakage and low dielectric absorption. Addi­tionally, 1% metal film resistors were used throughout the design.

In the sample mode, SW1 and SW4 are closed, and the output

= –VIN. The purpose of SW4, which operates in parallel

is V

OUT

with SW1, is to reduce the pedestal, or hold step, error by
injecting the same amount of charge into the noninverting input
of A3 that SW1 injects into the inverting input of A3. This
creates a common-mode voltage across the inputs of A3 and is
then rejected by the CMR of A3; otherwise, the charge injection
from SW1 would create a differential voltage step error that
would appear at V

. The pedestal error for this circuit is

OUT

less than 2 mV over the entire 0 V to 3.3 V/5 V signal range.
Another method of reducing pedestal error is to reduce the pulse
amplitude applied to the control pins. In order to control the
ADG513, only 2.4 V are required for the “ON” state and

0.8 V for the “OFF” state. If possible, use an input control
signal whose amplitude ranges from 0.8 V to 2.4 V instead of a
full range 0 V to 3.3 V/5 V for minimum pedestal error.

Other circuit features include an acquisition time of less than
3 µs to 1%; reducing C

and C2 will speed up the acquisition

H

time further, but an increased pedestal error will result. Settling
time is less than 300 ns to 1%, and the sample-mode signal BW
is 80 kHz.

The ADG513 was chosen for its ability to work with 3 V/5 V
supplies and for having normallyopen and normallyclosed preci­sion CMOS switches on a dielectrically isolated process. SW2 is
not required in this circuit; however, it was used in parallel with
SW3 to provide a lower R

analog switch.

ON

–14–

REV. B

AD824

* AD824 SPICE Macro-model 9/94, Rev. A *

ARG/ADI

*
* Copyright 1994 by Analog Devices, Inc.
*
* Refer to “README.DOC” file for License Statement.

Use of this model indicates your acceptance with
the terms and provisions in the License Statement. *

* Node assignments
* noninverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | |

.SUBCKT AD824
1 2 99 50 25

*
* INPUT STAGE & POLE AT 3.1 MHz
*

R3 5 99

1.193E3
R4 6 99

1.193E3
CIN 1 2
4E-12
C2 5 6

19.229E-12
I1 4 50 108E-6
IOS 1 2
1E-12
EOS 7 1
POLY(1) (12,98) 100E-6 1
J1 4 2 5

JX

J2 4 7 6

JX

*
* GAIN STAGE & DOMINANT POLE
*

EREF 98
0 (30,0) 1
R5 9 98

2.205E6
C3 9 25
54E-12
G1 98 9
(6,5) 0.838E-3
V1 8 98

-1
V2 98 10

-1
D1 9 10
DX
D2 8 9
DX

*
* COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHz *

R21 11 12
1E6
R22 12 98
100
C14 11 12
159E-12
E13 11 98
POLY(2) (2,98) (1,98) 0 0.5 0.5

*
* POLE AT 10 MHz
*

R23 18 98
1E6
C15 18 98

15.9E-15

G15 98 18
(9,98) 1E-6

*
* OUTPUT STAGE
*

ES 26 98
(18,98) 1
RS 26 22
500
IB1 98 21

2.404E-3
IB2 23 98

2.404E-3
D10 21 98
DY
D11 98 23
DY
C16 20 25
2E-12
C17 24 25
2E-12
DQ197 20
DQ
Q2 20 21
22 NPN
Q3 24 23
22 PNP
DQ224 51
DQ
Q5 25 20
97 PNP 20
Q6 25 24
51 NPN 20
VP 96 97
0
VN 51 52
0
EP 96 0
(99,0) 1
EN 52 0
(50,0) 1
R25 30 99
5E6
R26 30 50
5E6
FSY1 99
0 VP 1
FSY2 0
50VN 1
DC1 25 99
DX
DC2 50 25
DX

*
* MODELS USED
*

.MODEL JX NJF(BETA=3.2526E-3 VTO=-2.000 IS=2E-12) .MODEL
NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3
+ RE=4 RC=550 IS=1E-16)
.MODEL PNP PNP(BF=120 VAF=150 VAR=15 RB=2E3 + RE=4
RC=750 IS=1E-16)
.MODEL DX D(IS=1E-15)
.MODEL DY D()
.MODEL DQ D(IS=1E-16)
.ENDS AD824

REV. B

–15–

AD824

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

PIN 1

0.210 (5.33)
MAX

0.160 (4.06)

0.115 (2.93)

14-Pin Plastic (N) Package

(N-14)

0.795 (20.19)

0.725 (18.42)

14

1

0.100 (2.54)

0.022 (0.558)

0.014 (0.356)

BSC

0.070 (1.77)

0.045 (1.15)

8

0.280 (7.11)

0.240 (6.10)

7

0.060 (1.52)

0.015 (0.38)

0.130
(3.30)
MIN

SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

16

1

PIN 1

0.195 (4.95)

0.115 (2.93)

0.4133 (10.50)

0.3977 (10.00)

0.050 (1.27)
BSC

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.0098 (0.25)

0.0040 (0.10)

16-Pin SOIC Package

(R-16)

9

0.2992 (7.60)

0.2914 (7.40)

8

0.1043 (2.65)

0.0926 (2.35)

0.4193 (10.65)

0.3937 (10.00)

0.3444 (8.75)

0.3367 (8.55)

14

1

0.050 (1.27)
BSC

0.0291 (0.74)

0.0098 (0.25)

14-Pin SOIC (R) Package

(R-14)

8

0.2440 (6.20)

0.2284 (5.80)

7

0.0688 (1.75)

0.0532 (1.35)

0.0192 (0.49)

0.0138 (0.35)

 45

SEATING
PLANE

0.0099 (0.25)

0.0075 (0.19)

0.0196 (0.50)

0.0099 (0.25)

8



0



0.0500 (1.27)

0.0160 (0.41)



45



C00875–0–1/02(B)

0.0118 (0.30)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

SEATING
PLANE

0.0125 (0.32)

0.0091 (0.23)

8
0

0.0500 (1.27)

0.0157 (0.40)

Revision History

Location Page

Data Sheet changed from REV. A to REV. B.

Edits to ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PRINTED IN U.S.A.

–16–

REV. B