Datasheet AD8227 Datasheet (ANALOG DEVICES)

Wide Supply Range, Rail-to-Rail

FEATURES

Gain set with 1 external resistor

Gain range: 5 to 1000
Input voltage goes below ground
Inputs protected beyond supplies
Very wide power supply range

Single supply: 2.2 V to 36 V

Dual supply: ±1.5 V to ±18 V
Bandwidth (G = 5): 250 kHz
CMRR (G = 5): 100 dB minimum (B Grade)
Input noise: 24 nV/√Hz
Typical supply current: 350 μA
Specified temperature: −40°C to +125°C
8-lead SOIC and MSOP packages

APPLICATIONS

Industrial process controls
Bridge amplifiers
Medical instrumentation
Portable data acquisition
Multichannel systems

Output Instrumentation Amplifier

AD8227

PIN CONFIGURATION

AD8227

1

–IN

2

R

G

3

R

G

4

+IN

TOP VIEW

(Not to Scale)

Figure 1.

Table 1. Instrumentation Amplifiers by Category

General
Purpose

Zero
Drift

Military
Grade

AD8220 AD8231 AD620 AD627 AD8250
AD8221 AD8290 AD621 AD623 AD8251
AD8222 AD8293 AD524 AD8223 AD8253
AD8224 AD8553 AD526 AD8226
AD8228 AD8556 AD624 AD8227
AD8295 AD8557

1

See www.analog.com for the latest selection of instrumentation amplifiers.

8

+V

S

7

V

OUT

6

REF

5

–V

S

Low
Power

07759-001

1

High Speed
PGA

GENERAL DESCRIPTION

The AD8227 is a low cost, wide supply range instrumentation
amplifier that requires only one external resistor to set any gain
between 5 and 1000.

The AD8227 is designed to work with a variety of signal voltages.
A wide input range and rail-to-rail output allow the signal to
make full use of the supply rails. Because the input range can
also go below the negative supply, small signals near ground can
be amplified without requiring dual supplies. The AD8227
operates on supplies ranging from ±1.5 V to ±18 V (2.2 V to
36 V single supply).

The robust AD8227 inputs are designed to connect to real­world sensors. In addition to its wide operating range, the
AD8227 can handle voltages beyond the rails. For example,
with a ±5 V supply, the part is guaranteed to withstand ±35 V
at the input with no damage. Minimum as well as maximum
input bias currents are specified to facilitate open wire detection.

The AD8227 is ideal for multichannel, space-constrained
applications. With its MSOP package and 125°C temperature
rating, the AD8227 thrives in tightly packed, zero airflow designs.

The AD8227 is available in 8-pin MSOP and SOIC packages.
It is fully specified for −40°C to +125°C operation.

For a similar instrumentation amplifier with a gain range of 1 to
1000, see the AD8226.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

AD8227

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Pin Configuration ............................................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 19

Architecture ................................................................................. 19

REVISION HISTORY

5/09—Revision 0: Initial Version

Gain Selection ............................................................................. 19

Reference Terminal .................................................................... 20

Input Voltage Range ................................................................... 20

Layout .......................................................................................... 20

Input Bias Current Return Path ............................................... 21

Input Protection ......................................................................... 21

Radio Frequency Interference (RFI) ........................................ 21

Applications Information .............................................................. 22

Differential Drive ....................................................................... 22

Precision Strain Gage ................................................................. 22

Driving an ADC ......................................................................... 23

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

Rev. 0 | Page 2 of 24

AD8227

SPECIFICATIONS

+VS = +15 V, −VS = −15 V, V

Table 2.

Test Conditions/ A Grade B Grade
Parameter Comments Min Typ Max Min Typ Max Unit

COMMON-MODE REJECTION RATIO VCM = −10 V to +10 V

DC to 60 Hz

G = 5 90 100 dB
G = 10 96 105 dB
G = 100 105 110 dB
G = 1000 105 110 dB

5 kHz

G = 5 80 80 dB
G = 10 86 86 dB
G = 100 86 86 dB
G = 1000 86 86 dB

NOISE

Voltage Noise, 1 kHz

Input Voltage Noise, eNI 24 25 24 25 nV/√Hz
Output Voltage Noise, eNO 310 315 310 315 nV/√Hz

RTI f = 0.1 Hz to 10 Hz

G = 5 1.5 1.5 μV p-p
G = 10 0.9 0.9 μV p-p

G = 100 to 1000 0.5 0.5 μV p-p
Current Noise f = 1 kHz 100 100 fA/√Hz
f = 0.1 Hz to 10 Hz 3 3 pA p-p

VOLTAGE OFFSET

Input Offset, V

V

OSI

Average Temperature Drift TA = −40°C to +125°C 0.2 2 0.2 1 μV/°C
Output Offset, V

V

OSO

Average Temperature Drift TA = −40°C to +125°C 2 10 2 5 μV/°C
Offset RTI vs. Supply (PSR) VS = ±5 V to ±15 V

G = 5 90 100 dB

G = 10 96 105 dB

G = 100 105 110 dB

G = 1000 105 110 dB

INPUT CURRENT

Input Bias Current

1

T

T

T

Average Temperature Drift TA = −40°C to +125°C 70 70 pA/°C
Input Offset Current TA = +25°C 1.5 1.5 nA
T
T

Average Temperature Drift TA = −40°C to +125°C 5 5 pA/°C

REFERENCE INPUT

RIN 60 60 kΩ
IIN 12 12 μA
Voltage Range −VS +VS −VS +VS V
Reference Gain to Output 1 1 V/V
Reference Gain Error 0.01 0.01 %

= 0 V, TA = 25°C, G = 5, RL = 10 k, specifications referred to input, unless otherwise noted.

REF

Tot al noise:

eN = √(e

2

+ (eNO/G)2)

NI

Total offset voltage:
VOS = V

+ (V

OSO

/G)

OSI

= ±5 V to ±15 V 200 100 μV

S

= ±5 V to ±15 V 1000 500 μV

S

= +25°C 5 20 27 5 20 27 nA

A

= +125°C 5 15 25 5 15 25 nA

A

= −40°C 5 30 35 5 30 35 nA

A

= +125°C 1.5 1.5 nA

A

= −40°C 2 2 nA

A

Rev. 0 | Page 3 of 24

AD8227

Test Conditions/ A Grade B Grade
Parameter Comments Min Typ Max Min Typ Max Unit

DYNAMIC RESPONSE

Small Signal −3 dB Bandwidth

G = 5 250 250 kHz
G = 10 200 200 kHz
G = 100 50 50 kHz
G = 1000 5 5 kHz

Settling Time 0.01% 10 V step

G = 5 14 14 μs
G = 10 15 15 μs
G = 100 35 35 μs
G = 1000 275 275 μs

Slew Rate

GAIN

Gain Range 5 1000 5 1000 V/V
Gain Error V

Gain Nonlinearity V

Gain vs. Temperature TA = −40°C to +125°C

INPUT VS = ±1.5 V to +36 V

Impedance

Operating Voltage Range
T
T
Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40 V

OUTPUT

Output Swing

Short-Circuit Current 13 13 mA

POWER SUPPLY

Operating Range Dual-supply operation ±1.5 ±18 ±1.5 ±18 V
Quiescent Current TA = +25°C 350 425 350 425 μA
T
T
T

TEMPERATURE RANGE −40 +125 −40 +125 °C

1

The input stage uses pnp transistors, so input bias current always flows into the part.

2

At high gains, the part is bandwidth limited rather than slew rate limited.

3

For G > 5, gain error specifications do not include the effects of External Resistor RG.

4

Input voltage range of the AD8227 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference voltage. See the

2

G = 5 to 100 0.8 0.8 V/μs

3

G = 5 + (80 kΩ/R

= −10 V to +10 V

OUT

)

G

G = 5 0.04 0.02 %
G = 10 to 1000 0.3 0.15 %

= −10 V to +10 V

OUT

G = 5 RL ≥ 2 kΩ 10 10 ppm
G = 10 RL ≥ 2 kΩ 15 15 ppm
G = 100 RL ≥ 2 kΩ 15 50 ppm
G = 1000 RL ≥ 2 kΩ 750 150 ppm

G = 5 5 5 ppm/°C
G > 5 −100 −100 ppm/°C

Differential 0.8||2 0.8||2 GΩ||pF
Common Mode 0.4||2 0.4||2 GΩ||pF

4

TA = +25°C −VS − 0.1 +VS − 0.8 −VS − 0.1 +VS − 0.8 V

= +125°C −VS − 0.05 +VS − 0.6 −VS − 0.05 +VS − 0.6 V

A

= −40°C −VS − 0.15 +VS − 0.9 −VS − 0.15 +VS − 0.9 V

A

RL = 10 kΩ to ground TA = −40°C to +85°C −VS + 0.2 +VS − 0.2 −VS + 0.2 +VS − 0.2 V
T

= +85°C to +125°C −VS + 0.2 +VS − 0.3 −VS + 0.2 +VS − 0.3 V

A

RL = 100 kΩ to ground TA = −40°C to +125°C −VS + 0.1 +VS − 0.1 −VS + 0.1 +VS − 0.1 V

= −40°C 250 325 250 325 μA

A

= +85°C 450 525 450 525 μA

A

= +125°C 525 600 525 600 μA

A

section for more information. Input Voltage Range

Rev. 0 | Page 4 of 24

AD8227

+VS = 2.7 V, −VS = 0 V, V

Table 3.

Test Conditions/ A Grade B Grade
Parameter Comments Min Typ Max Min Typ Max Unit

COMMON-MODE REJECTION RATIO VCM = 0 V to 1.7 V

DC to 60 Hz

G = 5 90 100 dB

G = 10 96 105 dB

G = 100 105 110 dB

G = 1000 105 110 dB
5 kHz

G = 5 80 80 dB

G = 10 86 86 dB

G = 100 86 86 dB

G = 1000 86 86 dB

NOISE

Voltage Noise, 1 kHz

Input Voltage Noise, eNI 25 28 25 28 nV/√Hz

Output Voltage Noise, eNO 310 330 310 330 nV/√Hz
RTI f = 0.1 Hz to 10 Hz

G = 5 1.5 1.5 μV p-p

G = 10 0.8 0.8 μV p-p

G = 100 to 1000 0.5 0.5 μV p-p
Current Noise f = 1 kHz 100 100 fA/√Hz
f = 0.1 Hz to 10 Hz 3 3 pA p-p

VOLTAGE OFFSET

Input Offset, V

V

OSI

Average Temperature Drift TA = −40°C to +125°C 0.2 2 0.2 1 μV/°C
Output Offset, V

OSO

Average Temperature Drift TA = −40°C to +125°C 2 10 2 5 μV/°C
Offset RTI vs. Supply (PSR) VS = 0 V to 1.7 V

G = 5 90 100 dB

G = 10 96 105 dB

G = 100 105 110 dB

G = 1000 105 110 dB

INPUT CURRENT

Input Bias Current

1

T
T

Average Temperature Drift TA = −40°C to +125°C 70 70 pA/°C
Input Offset Current TA = +25°C 1.5 1.5 nA
T
T

Average Temperature Drift TA = −40°C to +125°C 5 5 pA/°C

REFERENCE INPUT

RIN 60 60 kΩ
IIN 12 12 μA
Voltage Range −VS +VS −VS +VS V
Reference Gain to Output 1 1 V/V
Reference Gain Error 0.01 0.01 %

= 0 V, TA = 25°C, G = 5, RL = 10 k, specifications referred to input, unless otherwise noted.

REF

Tot al noise:

e

= √(e

N

2

+ (eNO/G)2)

NI

Total offset voltage:

= V

V

V

T

+ (V

OS

OSI

OSO

= 0 V to 1.7 V 200 100 μV

S

= 0 V to 1.7 V 1000 500 μV

S

= +25°C 5 20 27 5 20 27 nA

A

= +125°C 5 15 25 5 15 25 nA

A

= −40°C 5 30 35 5 30 35 nA

A

= +125°C 1.5 1.5 nA

A

= −40°C 2 2 nA

A

/G)

Rev. 0 | Page 5 of 24

AD8227

Test Conditions/ A Grade B Grade
Parameter Comments Min Typ Max Min Typ Max Unit

DYNAMIC RESPONSE

Small Signal −3 dB Bandwidth

G = 5 250 250 kHz
G = 10 200 200 kHz
G = 100 50 50 kHz
G = 1000 5 5 kHz

Settling Time 0.01% 2 V step

G = 5 6 6 μs
G = 10 6 6 μs
G = 100 30 30 μs
G = 1000 275 275 μs

Slew Rate

GAIN

Gain Range 5 1000 5 1000 V/V
Gain Error

Gain vs. Temperature TA = −40°C to +125°C

INPUT

Impedance

Operating Voltage Range
T
T
Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40 V

OUTPUT

Output Swing TA = −40°C to +125°C

Short-Circuit Current 13 13 mA

POWER SUPPLY

Operating Range Single-supply operation 2.2 36 2.2 36 V
Quiescent Current +VS = 2.7 V
T
T
T
T

TEMPERATURE RANGE −40 +125 −40 +125 °C

1

Input stage uses pnp transistors, so input bias current always flows into the part.

2

At high gains, the part is bandwidth limited rather than slew rate limited.

3

For G > 5, gain error specifications do not include the effects of External Resistor RG.

4

Input voltage range of the AD8227 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference voltage. See the

2

G = 5 to 10 0.6 0.6 V/μs

3

G = 5 + (80 kΩ/R

G = 5 V
G = 10 to 1000 V

= 0.8 V to 1.8 V 0.04 0.04 %

OUT

= 0.2 V to 2.5 V 0.3 0.3 %

OUT

)

G

G = 5 5 5 ppm/°C
G > 5 −100 −100 ppm/°C

= 0 V; +VS = 2.7 V to

−V

S

36 V

Differential 0.8||2 0.8||2 GΩ||pF
Common Mode 0.4||2 0.4||2 GΩ||pF

4

TA = +25°C −0.1 +VS − 0.7 −0.1 +VS − 0.7 V

= −40°C −0.15 +VS − 0.9 −0.15 +VS − 0.9 V

A

= +125°C −0.05 +VS − 0.6 −0.05 +VS − 0.6 V

A

RL = 2 kΩ to 1.35 V 0.2 +VS − 0.2 0.2 +VS − 0.2 V
RL = 10 kΩ to 1.35 V 0.1 +VS − 0.1 0.1 +VS − 0.1 V

= +25°C 325 400 325 400 μA

A

= −40°C 250 325 250 325 μA

A

= +85°C 425 500 425 500 μA

A

= +125°C 475 550 475 550 μA

A

section for more information. Input Voltage Range

Rev. 0 | Page 6 of 24

AD8227

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage ±18 V
Output Short-Circuit Current Indefinite
Maximum Voltage at −IN or +IN −VS + 40 V
Minimum Voltage at −IN or +IN +VS − 40 V
REF Voltage ±VS
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Maximum Junction Temperature 140°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for a device in free air.

Table 5.

Package θJA Unit

8-Lead MSOP, 4-Layer JEDEC Board 135 °C/W
8-Lead SOIC, 4-Layer JEDEC Board 121 °C/W

ESD CAUTION

Rev. 0 | Page 7 of 24

AD8227

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD8227

1

–IN

2

R

G

3

R

G

4

+IN

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 −IN Negative Input.
2, 3 RG Gain Setting Pins. Place a gain resistor between these two pins.
4 +IN Positive Input.
5 −VS Negative Supply.
6 REF Reference. This pin must be driven by low impedance.
7 V

Output.

OUT

8 +VS Positive Supply.

8

+V

S

7

V

OUT

6

REF

5

–V

S

07759-002

Rev. 0 | Page 8 of 24

AD8227

TYPICAL PERFORMANCE CHARACTERISTICS

T = 25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted.

500

400

300

HITS

200

100

0

–900 –600 –300 0 300 600 900

OUTPUT V

(µV)

OS

Figure 3. Typical Distribution of Output Offset Voltage

700

600

500

400

HITS

300

200

100

MEAN: 15.9
SD: 196.50

MEAN: –0.701
SD: 0.676912

MEAN: 0.0668

1000

800

600

HITS

400

200

0

–0.9 –0.6 –0.3 0 0.3 0.6 0.9

07759-003

INPUT V

DRIFT (µV)

OS

SD: 0.065827

07759-006

Figure 6. Typical Distribution of Input Offset Voltage Drift, G = 100

1000

800

600

HITS

400

200

MEAN: 20.4
SD: 0.5893

0

–6 –4 –2 0 2 4 6

OUTPUT V

DRIFT (µV)

OS

Figure 4. Typical Distribution of Output Offset Voltage Drift

1000

800

600

HITS

400

200

0

–200 –150 –100 –50 0 50 100 150 200

INPUT V

(µV)

OS

MEAN: –5.90
SD: 15.8825

Figure 5. Typical Distribution of Input Offset Voltage

07759-004

07759-005

Rev. 0 | Page 9 of 24

0

16 18 20 22 24 26

POSITIVE I

BIAS

(nA)

Figure 7. Typical Distribution of Input Bias Current

MEAN: –0.027

1000

800

600

HITS

400

200

0

–0.9 –0.6 –0.3 0 0.3 0.6 0.9

(nA)

I

OS

SD: 0.079173

Figure 8. Typical Distribution of Input Offset Current

07759-007

07759-008

AD8227

1.6
+0.02V, +1.5V

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

COMMON-MODE VOLTAGE ( V)

–0.2

–0.4

–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0

+0.02V, +1.35V

+0.02V, –0.15V

+0.02V, –0.3V

V

= 1.35V

REF

OUTPUT VOLTAGE (V)

V

REF

+2.7V, +1.1V

+1.35V, –0.3V

= 0V

+2.67V, +1.2V

+2.7V, 0V

+2.67V, –0.15V

Figure 9. Input Common-Mode Voltage vs. Output Voltage,

Single Supply, V

= 2.7 V, G = 5

s

07759-009

1.6
+0.02V, +1.5V

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

COMMON-MODE VOLTAGE (V)

–0.2

–0.4

–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0

+0.02V, +1.35V

+0.02V, –0.25V

+0.02V, –0. 3V

V

= 1.35V

REF

+1.35V, –0.3V

OUTPUT VOLTAGE (V)

V

= 0V

REF

+2.67V, +1.2V

+2.67V, +1.1V

+2.67V, –0.25V

+2.67V, –0.25V

Figure 12. Input Common-Mode Voltage vs. Output Voltage,

Single Supply, V

= 2.7 V, G = 100

s

07759-012

5

+0.02V, +4.25V

4

+0.02V, +4V

3

2

1

COMMON-MO DE VO LTAGE (V)

+0.01V, –0. 05V

0

+0.02V, –0.3V

–1

–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

V

= 0V

REF

V

= 2.5V

REF

+2.5V, –0.3V

OUTPUT VO LTAGE (V)

+4.96V, +3.75V

+4.96V, +3.5V

+4.96V, +0.2V

+4.96V, –0.05V

Figure 10. Input Common-Mode Voltage vs. Output Voltage,

= 5 V, G = 5

s

0V, +4.2V

+4.96V, +3.7V

6

–4.98V, +3.7V

4

2

0

Single Supply, V

5

+0.02V, +4.25V

4

+0.02V, +4V

3

2

1

COMMON-MODE VOLTAGE (V)

0

+0.02V, –0.25V

+0.02V, –0.3V

–1

–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

07759-010

V

OUTPUT VOLTAGE (V)

= 2.5V

REF

+2.5V, –0.3V

V

= 0V

REF

+4.96V, +3.75V

+4.96V, +3.5V

+4.96V, –0. 2V

+4.96V, –0.25V

07759-013

Figure 13. Input Common-Mode Voltage vs. Output Voltage,

= 5 V, G = 100

s

0V, +4.2V

+4.96V, +3.25V

6

–4.96V, +3.75V

4

2

0

Single Supply, V

–2

COMMON-MODE VOLTAGE (V)

–4

–4.97V, –4. 8V

–6

–6 –4 –2 0 2 4 6

0V, –5.3V

OUTPUT VOLTAGE (V)

+4.96V, –4.8V

Figure 11. Input Common-Mode Voltage vs. Output Voltage,

Dual Supply, V

= ±5 V, G = 5

s

07759-011

Rev. 0 | Page 10 of 24

–2

COMMON-MODE VOLTAGE (V)

–4

–4.96V, –5. 1V

–6

–6–4–20246

0V, –5.3V

+4.96V, –5.1V

OUTPUT VOLTAGE (V)

Figure 14. Input Common-Mode Voltage vs. Output Voltage,

Dual Supply, V

= ±5 V, G = 100

s

07759-014

AD8227

20

15

–14.96V, +12. 7V

10

5

0

–5

–10

COMMON-MODE VOLTAGE (V)

–15

–14.96V, –13.8V +14.94V, –13.8V

–20

–20 –15 –10 –5 0 5 10 15 20

–11.96V,
+10V

–11.96V,
–11.1V

0V, +14.2V

0V, +11.2V

VS = ±12V

0V, –12.3V

0V, –15.3V

OUTPUT VOL TAGE (V)

VS = ±15V

+14.94V, +12 .7V

+11.94V,
+10V

+11.94V,
–11.1V

Figure 15. Input Common-Mode Voltage vs. Output Voltage,

Dual Supply, V

= ±15 V, G = 5

s

59-015
077

16

VS = ±15V, G = 5

14

12
10

8

6
4
2

0

–2

–4

–6

OUTPUT VOL TAGE (V)

–8
–10

–12

–14
–16

–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40

I

IN

V

OUT

INPUT VOLTAGE (V)

Figure 18. Input Overvoltage Performance, G = 5, Vs = ±15 V

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

INPUT CURRENT (mA)

07759-018

20

15

–14.96V, +12.7V

10

5

0

–5

–10

COMMON-MODE VOLTAGE (V)

–15

–14.96V, –14V +14.94V, –14V

–20

–20 –15 –10 –5 0 5 10 15 20

–11.96V,
+10V

–11.96V,
–11.3V

0V, +14.2V

0V, +11.2V

VS = ±12V

0V, –12.3V

0V, –15.3V

OUTPUT VOL TAGE (V)

VS = ±15V

+14.94V, +12. 7V

+11.94V,
+10V

+11.94V,
–11.3V

Figure 16. Input Common-Mode Voltage vs. Output Voltage,

Dual Supply, V

3.00
VS = 2.7V, G = 5

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

OUTPUT VOLTAGE (V)

0.75

0.50

0.25

0

–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40

= ±15 V, G = 100

s

V

OUT

I

IN

INPUT VOLTAGE (V)

Figure 17. Input Overvoltage Performance, G = 5, Vs = 2.7 V

0.6

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

3.00
VS = 2.7V, G = 100

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

OUTPUT VOL TAGE (V)

0.75

0.50

0.25

0

59-016
077

–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40

V

OUT

I

IN

INPUT VOLTAGE (V)

0.6

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

INPUT CURRENT (mA)

07759-019

Figure 19. Input Overvoltage Performance, G = 100, Vs = 2.7 V

16

VS = ±15V, G = 100

14

12
10

8

6
4
2

0

–2

–4

INPUT CURRENT (mA)

07759-017

–6

OUTPUT VOLTAGE (V)

–8
–10

–12

–14
–16 –0.5

–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40

V

OUT

I

IN

INPUT VOLTAGE (V)

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

INPUT CURRENT (mA)

07759-020

Figure 20. Input Overvoltage Performance, G = 100, Vs = ±15 V

Rev. 0 | Page 11

of 24

AD8227

33

31

29

27

25

23

21

INPUT BIAS CURRENT (nA)

19

17

15

–0.14V

+4.23V

–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4. 5

COMMON-MODE VOLTAGE (V)

Figure 21. Input Bias Current vs. Common-Mode Voltage, Vs = 5 V

759-021
07

140

120

100

80

60

NEGATIVE PSRR (dB)

40

20

0

0.1 1 10 100 1k 10k 100k

FREQUENCY (Hz)

G = 1000

G = 100

G = 10

G = 5

Figure 24. Negative PSRR vs. Frequency

07759-024

40

–15.01V

35

30

25

20

15

10

INPUT BIAS CURRENT (n A)

5

0
–16 –12 –8 –4 0 4 8 12 16

COMMON-MODE VOLTAGE (V)

+14.03V

Figure 22. Input Bias Current vs. Common-Mode Voltage, Vs = ±15 V

160

G = 1000

G = 100

140

G = 10

120

G = 5

100

80

60

POSITIVE PSRR (dB)

40

20

0

0.1 1 10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 23. Positive PSRR vs. Frequency, RTI

70

G = 1000

60

50

G = 100

40

30

G = 10

20

GAIN (dB)

G = 5

10

0

–10

–20

–30

9-022
0775

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

07759-025

Figure 25. Gain vs. Frequency, VS = ±15 V

70

G = 1000

60

50

G = 100

40

30

G = 10

20

G = 5

GAIN (dB)

10

0

–10

–20

–30

07759-023

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

07759-026

Figure 26. Gain vs. Frequency, VS = 2.7 V

Rev. 0 | Page 12 of 24

AD8227

160

140

120

100

G = 1000

G = 100

G = 10

G = 5

35

30

25

–IN BIAS CURRENT
+IN BIAS CURRENT
OFFSET CURRENT

VS = ±15V
V

REF

150

= 0V

125

100

80

CMRR (dB)

60

40

20

0

0.1 1 10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 27. CMRR vs. Frequency, RTI

160

140

G = 1000

G = 100

120

100

80

CMRR (dB)

60

40

20

0

0.1 1 10 100 1k 10k 100k

G = 10

G = 5

FREQUENCY (Hz)

Figure 28. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance

20

15

INPUT BIAS CURRENT (nA)

10

5

9-027
0775

–45 –30 – 15 0 15 30 45 60 75 90 105 120 135

TEMPERATURE ( °C)

75

50

INPUT OFFSET CURRENT ( pA)

25

0

07759-030

Figure 30. Input Bias Current and Offset Current vs. Temperature

300

200

100

0

–100

GAIN ERROR (µV/V)

–200

–300

759-028
07

–40

–20

0 20 40 60 80 100 120

TEMPERATURE (° C)

07759-031

Figure 31. Gain Error vs. Temperature, G = 5

0.3

0.2

0.1

0

–0.1

CHANGE IN INPUT OFFSET (µV)

–0.2

–0.3

0 10 20 30 40 50 60 70 80 90 100 110 120

WARM-UP TIME (s)

Figure 29. Change in Input Offset Voltage vs. Warm-Up Time

07759-029

Rev. 0 | Page 13

10

8

6

4

2

0

–2

CMRR (µV/V)

–4

–6

–8

–10

–40 –20 0 20 40 60 80 100 120

TEMPERATURE (° C)

Figure 32. CMRR vs. Temperature, G = 5

of 24

07759-032

AD8227

+V

S

–0.2

–0.4

–0.6

–0.8

–V

S

INPUT VOLTAGE (V)

–0.2

–0.4

REFERRED TO SUPPLY VOLTAGES

–0.6

–0.8

2 4 6 8 10 12 14 16 18

SUPPLY VOLTAGE (±V

)

S

Figure 33. Input Voltage Limit vs. Supply Voltage

–40°C
+25°C
+85°C
+105°C
+125°C

759-033
07

15

10

5

0

–5

OUTPUT VO LTAGE SW ING (V)

–10

–15

100 1k 10k 100k

LOAD (Ω)

–40°C
+25°C
+85°C
+105°C
+125°C

Figure 36. Output Voltage Swing vs. Load Resistance

07759-036

+V

S

–0.1

–0.2

–0.3

–0.4

+0.4

+0.3

OUTPUT VO LTAGE SWING (V)

+0.2

REFERRED TO SUPPLY VOLTAGES

+0.1

–V

S

Figure 34. Output Voltage Swing vs. Supply Voltage, R

+V

S

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

+1.2

+1.0

+0.8

OUTPUT VO LTAGE SWING (V)

+0.6

REFERRED TO SUPPLY VOLTAGES

+0.4

+0.2

–V

S

–40°C
+25°C
+85°C
+105°C
+125°C

2 4 6 8 10 12 14 16 18

2 4 6 8 10 12 14 16 18

SUPPLY VOLTAGE (±V

–40°C
+25°C
+85°C
+105°C
+125°C

SUPPLY VOLTAGE (±V

)

S

= 10 kΩ

L

)

S

Figure 35. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ

+V

S

–0.2

–0.4

–0.6

–0.8

+0.8

+0.6

OUTPUT VOLTAGE SWING (V)

+0.4

REFERRED TO SUPPLY VOLTAGES

+0.2

–V

759-034
07

–40°C
+25°C
+85°C
+105°C
+125°C

S

0.01 0.1 1 10

OUTPUT CURRENT (mA)

07759-037

Figure 37. Output Voltage Swing vs. Output Current

40

G = 5

30

20

10

0

–10

–20

NONLINEARITY (10ppm/DIV)

–30

–40

–10 –8 –6 –4 –2 0 2 4 6 8 10

07759-035

Figure 38. Gain Nonlinearity, G = 5, R

OUTPUT VOLTAGE (V)

≥ 2 kΩ

L

07759-038

Rev. 0 | Page 14 of 24

AD8227

40

G = 10

30

20

1k

10

0

–10

–20

NONLINEARITY (10ppm/DIV)

–30

–40

–10 –8 –6 –4 –2 0 2 4 6 8 10

OUTPUT VOLTAGE (V)

Figure 39. Gain Nonlinearity, G = 10, RL ≥ 2 kΩ

160

G = 100

120

80

40

0

–40

–80

NONLINEARITY (40ppm/DIV)

–120

–160

–10–8–6–4–2 0 2 4 6 8 10

OUTPUT VOLTAGE (V)

Figure 40. Gain Nonlinearity, G = 100, RL ≥ 2 kΩ

Hz)

100

NOISE (n V/

10

9-039
0775

1 10 100 1k 10k 100k

G = 5 (67nV/ Hz)

G = 10 (40nV/ Hz)

G = 100 (26nV/ Hz)

G = 1000 (25nV/ Hz)

BANDWIDTH

LIMITED

FREQUENCY (Hz)

07759-042

Figure 42. Voltage Noise Spectral Density vs. Frequency

G = 1000, 200n V/DIV

G = 5, 1µV/DIV

7759-0430

9-040
0775

Figure 43. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 5, G = 1000

400

G = 1000

300

200

100

0

–100

–200

NONLINEARIT Y (100ppm/ DIV)

–300

–400

–10–8–6–4–2 0 2 4 6 8 10

OUTPUT VOLTAGE (V)

Figure 41. Gain Nonlinearity, G = 1000, RL ≥ 2 kΩ

07759-041

Rev. 0 | Page 15 of 24

1k

Hz)

100

NOISE (fA/

10

1 10 100 1k 10k

FREQUENCY (Hz)

Figure 44. Current Noise Spectral Density vs. Frequency

07759-044

AD8227

5V/DIV

13.8µs TO 0. 01%

16.8µs TO 0 .001%

0.002%/DIV

1s/DIV1.5pA/DIV

Figure 45. 0.1 Hz to 10 Hz Current Noise

30

25

20

15

10

OUTPUT VOLTAGE (V p-p)

5

0

100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 46. Large-Signal Frequency Response

7759-0450

40µs/DIV

07759-048

Figure 48. Large-Signal Pulse Response and Settling Time, G = 10,

10 V Step, V

5V/DIV

35µs TO 0.01%

50µs TO 0. 001%

0.002%/DIV

07759-046

= ±15 V

S

40µs/DIV

07759-049

Figure 49. Large-Signal Pulse Response and Settling Time, G = 100,

10 V Step, V

= ±15 V

S

5V/DIV

13.4µs TO 0. 01%

16.6µs TO 0.001%

0.002%/DIV

40µs/DIV

07759-047

Figure 47. Large-Signal Pulse Response and Settling Time, G = 5,

10 V Step, V

= ±15 V

S

Figure 50. Large-Signal Pulse Response and Settling Time, G = 1000,

Rev. 0 | Page 16 of 24

5V/DIV

0.002%/DIV

275µs TO 0. 01%

350µs TO 0. 001%

10 V Step, V

= ±15 V

S

200µs/DIV

07759-050

AD8227

20mV/DIV 4µs/DIV 20mV/DIV 20µs/DIV

Figure 51. Small-Signal Pulse Response, G = 5, R

20mV/DIV 4µs/DIV

Figure 52. Small-Signal Pulse Response, G = 10, R

= 10 kΩ, CL = 100 pF

L

= 10 kΩ, CL = 100 pF

L

759-05107

Figure 53. Small-Signal Pulse Response, G = 100, R

07759-052

20mV/DIV 100µs/DIV

Figure 54. Small-Signal Pulse Response, G = 1000, R

07759-053

= 10 kΩ, CL = 100 pF

L

07759-054

= 10 kΩ, CL = 100 pF

L

Rev. 0 | Page 17 of 24

AD8227

340

330

CL = 47pF

NO LOAD

CL = 100pF

320

CL = 147pF

20mV/DIV 4µs/ DIV

07759-055

Figure 55. Small-Signal Pulse Response with Various Capacitive Loads,

= Infinity

G = 5, R

L

35

30

25

20

15

SETTLING TIME (µs)

10

5

0

2 4 6 8 10 12 14 16 18 20

Figure 56. Settling Time vs. Step Size, V

SETTL ED TO 0.001%

SETTLED TO 0.01%

STEP SIZE (V)

= ±15 V, Dual Supply

S

07759-056

310

SUPPLY CURRENT (µA)

300

290

0 2 4 6 8 1012 141618

SUPPLY VOLTAGE (±V

)

S

Figure 57. Supply Current vs. Supply Voltage

07759-057

Rev. 0 | Page 18 of 24

AD8227

THEORY OF OPERATION

+V

S

–V

S

R1

8kΩ

NODE 1

ESD AND

OVERVOLTAGE

+IN

PROTECTION

R

A1 A2

B

+V

S

R

G

–V

V

BIAS

S

–V

NODE 4NODE 3

R2
8kΩ

NODE 2

S

Q2Q1

R

B

Figure 58. Simplified Schematic

ESD AND

OVERVOLTAGE

PROTECTION

R4

10kΩ

R5

10kΩ

–IN

R3

50kΩ

A3

+V

R6

50kΩ

–V

DIFFERENCE

AMPLIFI ER STAGEGAIN STAGE

+V

S

V

OUT

S

–V

S

REF

S

07759-058

ARCHITECTURE

The AD8227 is based on the classic three op amp topology. This
topology has two stages: a preamplifier to provide differential
amplification followed by a difference amplifier that removes
the common-mode voltage and provides additional amplifica­tion. Figure 58 shows a simplified schematic of the AD8227.

The first stage works as follows. To maintain a constant voltage
across the bias resistor, R
constant diode drop above the positive input voltage. Similarly,
Amplifier A2 keeps Node 4 at a constant diode drop above the
negative input voltage. Therefore, a replica of the differential
input voltage is placed across the gain setting resistor, R
current that flows across this resistance must also flow through
the R1 and R2 resistors, creating a gained differential signal
between the A2 and A1 outputs. Note that, in addition to a
gained differential signal, the original common-mode signal,
shifted a diode drop up, is also still present.

The second stage is a difference amplifier, composed of
Amplifier A3 and the R3 through R6 resistors. This stage
removes the common-mode signal from the amplified
differential signal and gains it by 5.

The transfer function of the AD8227 is

V

= G × (V

OUT

where:

G

k80

5 +=

GR

, Amplifier A1 must keep Node 3 at a

B

− V

) + V

IN+

IN−

REF

. The

G

GAIN SELECTION

Placing a resistor across the R
AD8227. The gain can be calculated by referring to Tab le 7 or
by using the following gain equation:

k80

R

G

5

−=G

Table 7. Gains Achieved Using Common Resistor Values

Standard Table Value of RG Calculated Gain

No resistor 5
100 kΩ 5.8

49.9 kΩ 6.6

26.7 kΩ 8
20 kΩ 9
16 kΩ 10
10 kΩ 13

5.36 kΩ 19.9
2 kΩ 45

1.78 kΩ 49.9
1 kΩ 85
845 Ω 99.7
412 Ω 199
162 Ω 499

80.6 Ω 998

The AD8227 defaults to G = 5 when no gain resistor is used.
The tolerance and gain drift of the R
to the specifications of the AD8227 to determine the total gain
accuracy of the system. When the gain resistor is not used, gain
error and gain drift are minimal.

terminals sets the gain of the

G

resistor should be added

G

Rev. 0 | Page 19 of 24

AD8227

REFERENCE TERMINAL

The output voltage of the AD8227 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF pin to level­shift the output so that the AD8227 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +V

or −VS by more than 0.3 V.

S

For best performance, source impedance to the REF terminal
should be kept below 2 Ω. As shown in Figure 58, the reference
terminal, REF, is at one end of a 50 k resistor. Additional imped­ance at the REF terminal adds to this 50 k resistor and results
in amplification of the signal connected to the positive input.
The amplification from the additional R

can be calculated as

REF

follows:

6(50 k + R

)/(60 k + R

REF

REF

)

Only the positive signal path is amplified; the negative path
is unaffected. This uneven amplification degrades CMRR.

INCORRECT

AD8227

REF

V

Figure 59. Driving the Reference Pin

V

CORRECT

+

OP1177

–

AD8227

REF

07759-059

INPUT VOLTAGE RANGE

Most instrumentation amplifiers have a very limited output
voltage swing when the common-mode voltage is near the
upper or lower limit of the part’s input range. The AD8227 has
very little of this limitation. See Figure 9 through Figure 16 for
the input common-mode range vs. output voltage of the part.

LAYOUT

To ensure optimum performance of the AD8227 at the PCB
level, care must be taken in the design of the board layout. The
pins of the AD8227 are arranged in a logical manner to aid in
this task.

1

–IN

2

R

G

3

R

G

4

+IN

AD8227

TOP VIEW

(Not to Scale)

Figure 60. Pinout Diagram

8

+V

S

7

V

OUT

6

REF

5

–V

S

07759-060

Common-Mode Rejection Ratio over Frequency

Poor layout can cause some of the common-mode signals to be
converted to differential signals before reaching the in-amp.
Such conversions occur when one input path has a frequency
response that is different from the other. To keep CMRR over
frequency high, the input source impedance and capacitance of
each path should be closely matched. Additional source resis­tance in the input path (for example, for input protection) should
be placed close to the in-amp inputs, which minimizes the
interaction of the source resistance with parasitic capacitance
from the PCB traces.

Parasitic capacitance at the gain setting pins can also affect CMRR
over frequency. If the board design has a component at the gain
setting pins (for example, a switch or jumper), the component
should be chosen so that the parasitic capacitance is as small as
possible.

Power Supplies

A stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect perfor­mance. See the PSRR performance curves in Figure 23 and
Figure 24 for more information.

A 0.1 µF capacitor should be placed as close as possible to each
supply pin. As shown in Figure 61, a 10 µF tantalum capacitor
can be used farther away from the part. In most cases, it can be
shared by other precision integrated circuits.

+V

S

REF

10µF

LOAD

V

OUT

07759-061

0.1µF

+IN

R

G

AD8227

–IN

0.1µF 10µF

–V

S

Figure 61. Supply Decoupling, REF, and Output Referred to Local Ground

References

The output voltage of the AD8227 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground.

Rev. 0 | Page 20 of 24

AD8227

INPUT BIAS CURRENT RETURN PATH

The input bias current of the AD8227 must have a return path to
ground. When the source, such as a thermocouple, cannot provide
a return current path, one should be created, as shown in Figure 62.

INCORRECT

+V

S

AD8227

REF

–V

S

TRANSFORMER

+V

S

AD8227

REF

–V

S

THERMOCOUPL E

+V

S

C

AD8227

C

CAPACITIVEL Y COUPLED

REF

–V

S

f

HIGH-PASS

=

2πRC

CAPACIT IVEL Y COUPL ED

Figure 62. Creating an Input Bias Current Return Path

10MΩ

1

CORRECT

TRANSFORMER

THERMOCOUPL E

C

R

C

R

+V

S

AD8227

–V

S

+V

S

AD8227

–V

S

+V

S

AD8227

–V

S

REF

REF

REF

INPUT PROTECTION

The AD8227 has very robust inputs and typically does not need
additional input protection. Input voltages can be up to 40 V
from the opposite supply rail. For example, with a +5 V positive
supply and a −8 V negative supply, the part can safely withstand
voltages from −35 V to +32 V. Unlike some other instrumentation
amplifiers, the part can handle large differential input voltages
even when the part is in high gain. Figure 17 through Figure 20
show the behavior of the part under overvoltage conditions.

07759-062

The other AD8227 terminals should be kept within the supplies.
All terminals of the AD8227 are protected against ESD.

For applications where the AD8227 encounters voltages beyond
the allowed limits, external current limiting resistors and low
leakage diode clamps such as the BAV199L, the FJH1100s, or
the SP720 should be used.

RADIO FREQUENCY INTERFERENCE (RFI)

RF rectification is often a problem when amplifiers are used in
applications that have strong RF signals. The disturbance can
appear as a small dc offset voltage. High frequency signals can
be filtered with a low-pass RC network placed at the input of
the instrumentation amplifier, as shown in Figure 63. The filter
limits the input signal bandwidth, according to the following
relationship:

1

)2(π2

CCR

+

D

C

1

RC

π2

C

+V

S

0.1µF

+IN

R

AD8227

G

–IN

0.1µF

–V

should be chosen to minimize

C

at the positive input and

C

10µF

REF

10µF

S

where C

≥ 10 CC.

D

R

4.02kΩ

R

4.02kΩ

uencyFilterFreq

uencyFilterFreq

=

DIFF

=

CM

C

C

1nF

C

D

10nF

C

C

1nF

Figure 63. RFI Suppression

CD affects the differential signal and CC affects the common­mode signal. Values of R and C
RFI. A mismatch between R × C

at the negative input degrades the CMRR of the AD8227.

R × C

C

By using a value of C

one magnitude larger than CC, the effect

D

of the mismatch is reduced, and performance is improved.

V

OUT

07759-063

Rev. 0 | Page 21 of 24

AD8227

APPLICATIONS INFORMATION

DIFFERENTIAL DRIVE

Figure 64 shows how to configure the AD8227 for differential
output.

+IN

AD8227

–IN

REF

RECOMMENDED O P AMPS: AD8515, AD8641, AD820.
RECOMMENDED R VALUES: 5kΩ to 20kΩ.

R

–

R

OP AMP

Figure 64. Differential Output Using an Op Amp

The differential output is set by the following equation:

V

DIFF_OUT

= V

OUT+

− V

= Gain × (V

OUT−

The common-mode output is set by the following equation:

V

CM_OUT

= (V

OUT+

− V

OUT−

)/2 = V

BIAS

The advantage of this circuit is that the dc differential accuracy
depends on the AD8227 and not on the op amp or the resistors.
This circuit takes advantage of the AD8227’s precise control of
its output voltage relative to the reference voltage. Op amp dc
performance and resistor matching affect the dc common-mode
output accuracy. However, because common-mode errors are
likely to be rejected by the next device in the signal chain, these
errors typically have little effect on overall system accuracy.

+OUT

V

BIAS

+

–OUT

06407759-

− V

IN−

)

IN+

Tips for Best Differential Output Performance

For best ac performance, an op amp with at least 2 MHz gain
bandwidth and 1 V/µs slew rate is recommended. Good choices
for op amps are the AD8641, AD8515, or AD820.

Keep trace lengths from resistors to the inverting terminal of
the op amp as short as possible. Excessive capacitance at this
node can cause the circuit to be unstable. If capacitance cannot
be avoided, use lower value resistors.

PRECISION STRAIN GAGE

The low offset and high CMRR over frequency of the AD8227
make it an excellent choice for bridge measurements. The
bridge can be connected directly to the inputs of the amplifier
(see Figure 65).

5V

1µF

+IN

+

R

AD8227

G

–

–IN

2.5V

07759-065

350Ω

10µF 0.

350Ω

350Ω350Ω

Figure 65. Precision Strain Gage

Rev. 0 | Page 22 of 24

AD8227

DRIVING AN ADC

Figure 66 shows several different methods for driving an ADC.
The ADC in the ADuC7026 microcontroller was chosen for
this example because it has an unbuffered charge sampling
architecture that is typical of most modern ADCs. This type of
architecture typically requires an RC buffer stage between the
ADC and the amplifier to work correctly.

Option 1 shows the minimum configuration required to drive
a charge sampling ADC. The capacitor provides charge to the
ADC sampling capacitor, and the resistor shields the AD8227
from the capacitance. To keep the AD8227 stable, the RC time
constant of the resistor and capacitor needs to stay above 5 µs.
This circuit is mainly useful for lower frequency signals.

OPTION 1: DRIVING LOW FREQUENCY SIGNALS

3.3V

AD8227

REF

100Ω

100nF

Option 2 shows a circuit for driving higher frequency signals.
It uses a precision op amp (AD8616) with relatively high band­width and output drive. This amplifier can drive a resistor and
capacitor with a much higher time constant and is, therefore,
suited for higher frequency applications.

Option 3 is useful for applications where the AD8227 needs to
run off a large voltage supply but drives a single-supply ADC.
In normal operation, the AD8227 output stays within the ADC
range, and the AD8616 simply buffers it. However, in a fault
condition, the output of the AD8227 may go outside the supply
range of both the AD8616 and the ADC. This is not an issue in
the circuit, because the 10 k resistor between the two amplifiers
limits the current into the AD8616 to a safe level.

3.3V

AV

DD

ADC0

ADuC7026

OPTIO N 2: DRIVING HIGH FREQ UENCY SIGNALS

3.3V

3.3V

AD8227

AD8227

REF

OPTIO N 3: PROTECT ING ADC FROM LARGE VOLTAGES

+15V

REF

–15V

AD8616

3.3V

10kΩ

AD8616

10Ω

10Ω

10nF

10nF

ADC1

ADC2

AGND

07759-066

Figure 66. Driving an ADC

Rev. 0 | Page 23 of 24

AD8227

0

0

0

OUTLINE DIMENSIONS

3.20

3.00

2.80

8

5

4

SEATING
PLANE

5.15

4.90

4.65

1.10 MAX

0.23

0.08

8°
0°

3.20

3.00

1

2.80

PIN 1

0.65 BSC

.95
.85
.75

0.15

0.38

0.00

0.22

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO -187-AA

Figure 67. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

0.80

0.60

0.40

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLL ING DIMENSI ONS ARE IN MILLIMETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

Figure 68. 8-Lead Standard Small Outline Package [SOIC_N]

5.00 (0.1968)

4.80 (0.1890)

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-A A

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD8227ARMZ
AD8227ARMZ-RL
AD8227ARMZ-R7
AD8227ARZ
AD8227ARZ-RL
AD8227ARZ-R7
AD8227BRMZ
AD8227BRMZ-RL
AD8227BRMZ-R7
AD8227BRZ
AD8227BRZ-RL
AD8227BRZ-R7

1

Z = RoHS Compliant Part.

1

−40°C to +125°C 8-Lead MSOP RM-8 Y1S

1

−40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y1S

1

−40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y1S

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8

1

−40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8

1

−40°C to +125°C 8-Lead MSOP RM-8 Y1U

1

−40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y1U

1

−40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y1U

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8

1

−40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8

©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07759-0-5/09(0)

Rev. 0 | Page 24 of 24