Datasheet AD8221 Datasheet (Analog Devices)

+

Precision Instrumentation Amplifier

FEATURES

Available in space-saving MSOP package
Gain set with 1 external resistor (gain range 1 to 1000)

Wide power supply range: ±2.3 V to ±18 V
Temperature range for specified performance:

–40°C to +85°C
Operational up to 125°C
EXCELLENT AC SPECIFICATONS

80 dB min CMRR to 10 kHz ( G = 1)
825 kHz –3 dB bandwidth (G = 1)
2 V/µs slew rate

LOW NOISE

8 nV/√Hz, @ 1 kHz, max input voltage noise

0.25 µV p-p input noise (0.1 Hz to 10 Hz)

HIGH ACCURACY DC PERFORMANCE (AD8221BR)

90 dB min CMRR (G = 1)
25 µV max input offset voltage

0.3 µV/°C max input offset drift

0.4 nA max input bias current

APPLICATIONS

Weigh scales
Industrial process controls
Bridge amplifiers
Precision data acquisition systems
Medical instrumentation
Strain gages
Transducer interfaces

GENERAL DESCRIPTION

The AD8221 is a gain programmable, high performance instru­mentation amplifier that delivers the industry’s highest CMRR
over frequency. The CMRR of instrumentation amplifiers on
the market today falls off at 200 Hz. In contrast, the AD8221
maintains a minimum CMRR of 80 dB to 10 kHz for all grades
at G = 1. High CMRR over frequency allows the AD8221 to
reject wideband interference and line harmonics, greatly
simplifying filter requirements. Possible applications include
precision data acquisition, biomedical analysis, and aerospace
instrumentation.

Low voltage offset, low offset drift, low gain drift, high gain
accuracy, and high CMRR make this part an excellent choice in
applications that demand the best dc performance possible,
such as bridge signal conditioning.

1

AD8221

CONNECTION DIAGRAM

1

–IN

2

R

G

3

R

G

4

IN

AD8221

TOP VIEW

Figure 1. SOIC and MSOP Connection Diagram

120

110

100

90

80

CMRR (dB)

70

60

50

40

10010 1k 10k 100k

FREQUENCY (Hz)

Figure 2. Typical CMRR vs. Frequency for G = 1

Programmable gain affords the user design flexibility. A single
resistor sets the gain from 1 to 1000. The AD8221 operates on
both single and dual supplies, and is well suited for applications
where ±10 V input voltages are encountered.

The AD8221 is available in low cost 8-lead SOIC and MSOP
packages, both of which offer the industry’s best performance.
The MSOP requires half the board space of the SOIC, making it
ideal for multichannel or space-constrained applications.

Performance is specified over the entire industrial temperature
range of –40°C to +85°C for all grades. Furthermore, the
AD8221 is operational from –40°C to +125°C

1

See Typical Performance Curves for expected operation from 85°C to 125°C.

8

+V

S

7

V

OUT

6

REF

5

–V

S

AD8221

COMPETITOR 1

COMPETITOR 2

03149-0-001

1

.

03149-0-002

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD8221

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Typical Performance Characteristics............................................. 6

Theory of Operation ......................................................................13

Gain Selection............................................................................. 14

Layout........................................................................................... 14

Reference Terminal ....................................................................15

Power Supply Regulation and Bypassing ................................15

Input Bias Current Return Path................................................15

Input Protection ......................................................................... 15

RF Interference........................................................................... 16

Precision Strain Gage................................................................. 16

Conditioning ±10 V Signals for a +5 V Differential Input

ADC ............................................................................................. 17

AC-Coupled Instrumentation Amplifier ................................ 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

REVISION HISTORY

Revision A
11/03—Data Sheet Changed from Rev. 0 to Rev. A

Change Page

Changes to Features...............................................................................1

Changes to Specifications section .......................................................4

Change to Theory of Operation section...........................................13

Change to Gain Selection section......................................................14

Rev. A | Page 2 of 20

AD8221

SPECIFICATIONS

Table 1. VS = ±15 V, V

Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit

COMMON-MODE
REJECTION RATIO (CMRR)

CMRR DC to 60 Hz with
1 kΩ Source Imbalance

G = 1 80 90 80 dB
G = 10 100 110 100 dB
G = 100 120 130 120 dB
G = 1000 130 140 130 dB

CMRR at 10 kHz VCM = –10 V to +10 V

G = 1 80 80 80 dB
G = 10 90 100 90 dB
G = 100 100 110 100 dB
G = 1000 100 110 100 dB

NOISE

Voltage Noise, 1 kHz

Input Voltage Noise, eNI V
Output Voltage Noise, eNO 75 75 75 nV/√Hz

RTI f = 0.1 Hz to 10 Hz

G = 1 2 2 2 µV p-p
G = 10 0.5 0.5 0.5 µV p-p
G = 100 to 1000 0.25 0.25 0.25 µV p-p

Current Noise f = 1 kHz 40 40 40 fA/√Hz

f = 0.1 Hz to 10 Hz 6 6 6 pA p-p

VOLTAGE OFFSET1

Input Offset, V

V

OSI

Over Temperature T = –40°C to +85°C 86 45 135 µV
Average TC 0.4 0.3 0.9 µV/°C

Output Offset, V

OSO

Over Temperature T = –40°C to +85°C 0.66 0.45 1.00 mV
Average TC 6 5 9 µV/°C

Offset RTI vs. Supply (PSR) VS = ±2.3 V to ±18 V

G = 1 90 110 94 110 90 100 dB
G = 10 110 120 114 130 100 120 dB
G = 100 124 130 130 140 120 140 dB
G = 1000 130 140 140 150 120 140 dB

INPUT CURRENT

Input Bias Current 0.5 1.5 0.2 0.4 0.5 2 nA

Over Temperature T = –40°C to +85°C 2.0 1 3 nA
Average TC 1 1 3 pA/°C

Input Offset Current 0.2 0.6 0.1 0.4 0.3 1 nA

Over Temperature T = –40°C to +85°C 0.8 0.6 1.5 nA
Average TC 1 1 3 pA/°C

REFERENCE INPUT

RIN 20 20 20 kΩ
IIN V
Voltage Range –VS +VS –VS +VS –VS +VS V
Gain to Output

POWER SUPPLY

Operating Range VS = ±2.3 V to ±18 V ±2.3 ±18 ±2.3 ±18 ±2.3 ±18 V
Quiescent Current 0.9 1 0.9 1 0.9 1 mA

Over Temperature T = –40°C to +85°C 1 1.2 1 1.2 1 1.2 mA

= 0 V, TA = +25°C, G = 1, RL = 2 kΩ, unless otherwise noted

REF

AR Grade BR Grade ARM Grade

VCM = –10 V to +10 V

RTI noi se = √

, V

IN+

= ±5 V to ±15 V 60 25 70 µV

S

V

= ±5 V to ±15 V 300 200 600 µV

S

, V

IN+

e

NI

, V

= 0 8 8 8 nV/√Hz

IN–

REF

, V

= 0 50 60 50 60 50 60 µA

IN–

REF

2

+ (eNO/G)

2

1 ± 0.0001 1 ± 0.0001 1 ± 0.0001

V/V

Rev. A | Page 3 of 20

AD8221

AR Grade BR Grade ARM Grade

Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit

DYNAMIC RESPONSE

Small Signal –3 dB

Bandwidth
G = 1 825 825 825 kHz
G = 10 562 562 562 kHz
G = 100 100 100 100 kHz
G = 1000 14.7 14.7 14.7 kHz

Settling Time 0.01% 10 V Step

G = 1 to 100 10 10 10 µs
G = 1000 80 80 80 µs

Settling Time 0.001% 10 V Step

G = 1 to 100 13 13 13 µs
G = 1000 110 110 110 µs

Slew Rate G = 1 1.5 2 1.5 2 1.5 2 V/µs
G = 5–100 2 2.5 2 2.5 2 2.5 V/µs
GAIN G = 1 + (49.4 kΩ/RG)

Gain Range 1 1000 1 1000 1 1000 V/V

Gain Error V

G = 1 0.03 0.02 0.1 %
G = 10 0.3 0.15 0.3 %
G = 100 0.3 0.15 0.3 %
G = 1000 0.3 0.15 0.3 %

Gain Nonlinearity V

G = 1 to 10 RL = 10 kΩ 3 10 3 10 5 15 ppm
G = 100 RL = 10 kΩ 5 15 5 15 7 20 ppm
G = 1000 RL = 10 kΩ 10 40 10 40 10 50 ppm
G = 1 to 100 RL = 2 kΩ 10 95 10 95 15 100 ppm

Gain vs. Temperature

G = 1 3 10 2 5 3 10 ppm/°C

2

G > 1

INPUT

Input Impedance

Differential 100||2 100||2 100||2 GΩ||pF
Common Mode 100||2 100||2 100||2 GΩ||pF

Input Operating

Voltage Range

3

Over Temperature T = –40°C to +85°C –VS + 2.0 +VS – 1.2 –VS + 2.0 +VS – 1.2 –VS + 2.0 +VS – 1.2 V

Input Operating

Voltage Range

Over Temperature T = –40°C to +85°C –VS + 2.0 +VS – 1.2 –VS + 2.0 +VS – 1.2 –VS + 2.0 +VS – 1.2 V

OUTPUT RL = 10 kΩ

Output Swing VS = ±2.3 V to ±5 V –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 V

Over Temperature T = –40°C to +85°C –VS + 1.4 +Vs – 1.3 –VS + 1.4 +Vs – 1.3 –VS + 1.4 +Vs – 1.3 V

Output Swing VS = ±5 V to ±18 V –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 V

Over Temperature T = –40°C to +85°C –VS + 1.6 +VS – 1.5 –VS + 1.6 +VS – 1.5 –VS + 1.6 +VS – 1.5 V

Short-Circuit Current 18 18 18 mA
TEMPERATURE RANGE

Specified Performance –40 +85 –40 +85 –40 +85 °C

Operational

4

1

Total RTI VOS = (V

2

Does not include the effects of external resistor RG.

3

One input grounded. G = 1.

4

See Typical Performance Curves for expected operation between 85°C to 125°C.

OSI

) + (V

±10 V

OUT

= –10 V to +10 V

OUT

–50 –50 –50 ppm/°C

VS = ±2.3 V to ±5 V –VS + 1.9 +VS – 1.1 –VS + 1.9 +VS – 1.1 –VS + 1.9 +VS – 1.1 V

VS = ±5 V to ±18 V –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 V

–40 +125 –40 +125 –40 +125 °C

/G).

OSO

Rev. A | Page 4 of 20

AD8221

ABSOLUTE MAXIMUM RATINGS

Table 2. AD8221 Absolute Maximum Ratings

Parameter Rating

Supply Voltage ±18 V
Internal Power Dissipation 200 mW
Output Short Circuit Current Indefinite
Input Voltage (Common-Mode) ±V
Differential Input Voltage ±Vs
Storage Temperature –65°C to +150°C
Operational* Temperature Range –40°C to +125°C

*Temperature range for specified performance is –40°C to +85°C. See Typical

Performance Curves for expected operation from +85°C to +125°C.

S

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumu­late on the human body and test equipment and can discharge without detection. Although this
product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recom­mended to avoid performance degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions may affect device reliability.

Specification is for device in free air:

SOIC θ
MSOP θ

(4 Layer JEDEC Board) = 121°C/W.

JA

(4 Layer JEDEC Board) = 135°C/W.

JA

Rev. A | Page 5 of 20

AD8221

TYPICAL PERFORMANCE CHARACTERISTICS

(@+25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted.)

1600

3500

1400

1200

1000

800

UNITS

600

400

200

2400

2100

1800

1500

1200

UNITS

900

600

300

0

0–50–100–150 50 100 150

CMR (µV/V)

Figure 3. Typical Distribution for CMR (G = 1)

03149-0-003

3000

2500

2000

UNITS

1500

1000

500

0

INPUT OFFSET CURRENT (nA)

0–0.3–0.6–0.9 0.3 0.6 0.9

Figure 6. Typical Distribution of Input Offset Current

15

10

5

0

–5

–10

INPUT COMMON-MODE VOLTAGE (V)

VS = ±5V

VS = ±15V

03149-0-006

0

INPUT OFFSET VOLTAGE (µV)

0–20–40–60 204060

Figure 4. Typical Distribution of Input Offset Voltage

3000

2500

2000

1500

UNITS

1000

500

0

INPUT BIAS CURRENT (nA)

0–0.5–1.0–1.5 0.5 1.0 1.5

Figure 5. Typical Distribution of Input Bias Current

03149-0-004

03149-0-005

Rev. A | Page 6 of 20

–15

–5 0–15 –10 5 10 15
OUTPUT VOLTAGE (V)

Figure 7. Input Common-Mode Range vs. Output Voltage, G = 1

15

10

VS = ±15V

5

0

–5

–10

INPUT COMMON-MODE VOLTAGE (V)

–15

–5 0–15 –10 5 10 15

OUTPUT VOLTAGE (V)

VS = ±5V

Figure 8. Input Common-Mode Range vs. Output Voltage, G = 100

03149-0-007

03149-0-008

AD8221

0.80

180

0.75

0.70

0.65

0.60

0.55

0.50

INPUT BIAS CURRENT (nA)

0.45

0.40

2.00

1.75

1.50

1.25

1.00

0.75

VS = ±15V

VS = ±5V

–5 0–15 –10 5 10 15

COMMON-MODE VOLTAGE (V)

Figure 9. I

vs. CMV

BIAS

03149-0-009

160

GAIN = 1000

140

GAIN = 100

120

GAIN = 10

100

GAIN = 1

PSRR (dB)

80

60

40

20

0.1 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)

GAIN = 1000

Figure 12. Positive PSRR vs. Frequency, RTI (G = 1 to 1000)

180

160

GAIN = 1000

140

GAIN = 100

120

GAIN = 10

100

GAIN = 1

PSRR (dB)

80

03149-0-012

0.50

0.25

CHANGE IN INPUT OFFSET VOLTAGE (µV)

0

0.10.01 1 10
WARM-UP TIME (min)

Figure 10. Change in Input Offset Voltage vs. Warm-Up Time

5.0

4.0

3.0

2.0

1.0
INPUT OFFSET CURRENT

0

–1.0

INPUT CURRENT (nA)

–2.0

–3.0

–4.0

–5.0

–40 –20 0 20 40 60 80 100 120 140

VS = ±15V

INPUT BIAS CURRENT

TEMPERATURE (°C)

Figure 11. Input Bias Current and Offset Current vs. Temperature

03149-0-010

03149-0-011

60

40

20

0.1 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)

Figure 13. Negative PSRR vs. Frequency, RTI (G = 1 to 1000)

100k

10k

BEST AVAILABLE FET
INPUT IN-AMP GAIN = 1

1k

100

TOTAL DRIFT 25°C– 85°C RTI (µV)

10

BEST AVAILABLE FET

INPUT IN-AMP GAIN = 1000

AD8221 GAIN = 1

AD8221 GAIN = 1000

1k 10k10 100 100k 1M 10M

SOURCE RESISTANCE (Ω)

Figure 14. Total Drift vs. Source Resistance

03149-0-013

03149-0-014

Rev. A | Page 7 of 20

AD8221

70

GAIN = 1000

60

50

GAIN = 100

40

30

GAIN = 10

20

GAIN (dB)

10

GAIN = 1

0

–10

–20
–30

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 15. Gain vs. Frequency

160

GAIN = 1000

140

GAIN = 100

120

GAIN = 10

100

GAIN = 1

CMRR (dB)

80

60

40

0.1 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)

Figure 16. CMRR vs. Frequency, RTI

GAIN = 10

GAIN = 100

GAIN = 1000

03149-0-015

03149-0-016

100

80

60

40

20

0

CMR (µV/V)

–20

–40

–60

–80

–100

–40 –20 0 20 40 60 80 100 120 140

TEMPERATURE (°C)

03149-0-041

Figure 18. CMR vs. Temperature

–0.0

+V

S

–0.4
–0.8
–1.2
–1.6
–2.0
–2.4

+2.4
+2.0
+1.6

INPUT VOLTAGE LIMIT (V)

+1.2

REFERRED TO SUPPLY VOLTAGES

+0.8
+0.4

–VS+0.0

501015

± SUPPLY VOLTAGE (V)

20

03149-0-018

Figure 19. Input Voltage Limit vs. Supply Voltage, G = 1

160

GAIN = 1000
GAIN = 100

140

GAIN = 10

120

GAIN = 1

100

CMRR (dB)

80

60

40

0.1 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)

GAIN = 100

GAIN = 1000

GAIN = 10

Figure 17. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance

+V

–VS+0.0

03149-0-017

Rev. A | Page 8 of 20

–0.0

S

–0.4
–0.8
–1.2
–1.6
–2.0

+2.0
+1.6
+1.2

OUTPUT VOLTAGE SWING (V)

+0.8

REFERRED TO SUPPLY VOLTAGES

+0.4

501015

± SUPPLY VOLTAGE (V)

RL = 10kΩ

RL = 2kΩ

RL = 2kΩ

RL = 10kΩ

Figure 20. Output Voltage Swing vs. Supply Voltage, G = 1

20

03149-0-019

AD8221

30

VS = ±15V

20

VS = ±15V

10

OUTPUT VOLTAGE SWING (V p-p)

0

101 100 1k 10k

LOAD RESISTANCE (Ω)

Figure 21. Output Voltage Swing vs. Load Resistance

+V

–0

S

–1

–2

–3

+3

+2

OUTPUT VOLTAGE SWING (V)

REFERRED TO SUPPLY VOLTAGES

+1

–VS+0

0123456789101112

OUTPUT CURRENT (mA)

SOURCING

SINKING

Figure 22. Output Voltage Swing vs. Output Current, G = 1

V

S

= ±15V

03149-0-020

03149-0-021

ERROR (10ppm/DIV)

–10–8–6–4–2 0 2 4 6 810

Figure 24. Gain Nonlinearity, G = 100, R

OUTPUT VOLTAGE (V)

= 10 kΩ

L

VS = ±15V

ERROR (100ppm/DIV)

–10–8–6–4–2 0 2 4 6 810

Figure 25. Gain Nonlinearity, G = 1000, R

OUTPUT VOLTAGE (V)

= 10 kΩ

L

1k

03149-0-023

03149-0-024

ERROR (1ppm/DIV)

–10–8–6–4–2 0 2 4 6 810

Figure 23. Gain Nonlinearity, G = 1, R

OUTPUT VOLTAGE (V)

= 10 kΩ

L

03149-0-022

Rev. A | Page 9 of 20

GAIN = 1

100

GAIN = 10

GAIN = 100

10

VOLTAGE NOISE RTI (nV/ Hz)

GAIN = 1000

GAIN = 1000
BW LIMIT

1

1 10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 26. Voltage Noise Spectral Density vs. Frequency (G = 1 to 1000)

03149-0-025

AD8221

Figure 27. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)

Figure 28. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)

1k

1s/DIV2µV/DIV

03149-0-026

1s/DIV5pA/DIV

03149-0-029

Figure 30. 0.1 Hz to 10 Hz Current Noise

30

25

20

GAIN = 1 GAIN = 10, 100, 1000

15

10

OUTPUT VOLTAGE (V p-p)

5

0

1s/DIV0.1µV/DIV

03149-0-027

1k 100k10k 1M

FREQUENCY (Hz)

VS = ±15V

03149-0-030

Figure 31. Large Signal Frequency Response

100

CURRENT NOISE (fA/ Hz)

10

101 100 1k 10k

FREQUENCY (Hz)

Figure 29. Current Noise Spectral Density vs. Frequency

03149-0-028

Figure 32. Large Signal Pulse Response and Settling Time (G = 1), 0.002%/div

Rev. A | Page 10 of 20

5V/DIV

10mV/DIV

7.9µs TO 0.01%

8.5

µ

s TO 0.001%

20µs/DIV

03149-0-031

AD8221

5V/div

4.9µs TO 0.01%

5.6

µ

10mV/div

s TO 0.001%

20mV/DIV

20µs/div

Figure 33. Large Signal Pulse Response and Settling Time (G = 10),

0.002%/div

5V/DIV

10.3µs TO 0.01%

13.4

µ

10mV/DIV

s TO 0.001%

20µs/DIV

Figure 34. Large Signal Pulse Response and Settling Time (G = 100),

0.002%/div

03149-0-032

03149-0-033

4µs/DIV

Figure 36. Small Signal Response, G = 1, R

= 2 kΩ, CL = 100 pF

L

20mV/DIV

4µs/DIV

Figure 37. Small Signal Response, G = 10, RL = 2 kΩ, CL = 100 pF

03149-0-035

03149-0-036

5V/DIV

83µs TO 0.01%
112

µ

10mV/DIV

s TO 0.001%

20µs/DIV

Figure 35. Large Signal Pulse Response and Settling Time (G = 1000),

0.002%/div

03149-0-034

Rev. A | Page 11 of 20

20mV/DIV

Figure 38. Small Signal Response, G = 100, R

10µs/DIV

= 2 kΩ, CL = 100 pF

L

03149-0-037

AD8221

2

20mV/DIV

Figure 39. Small Signal Response, G = 1000, RL = 2 kΩ, CL = 100 pF

15

s)

10

µ

SETTLED TO 0.001%

100µs/DIV

03149-0-038

1k

100

10

SETTLING TIME (µs)

1

1 10010 1k

SETTLED TO 0.001%

SETTLED TO 0.01%

GAIN

Figure 41. Settling Time vs. Gain for a 10 V Step

03149-0-040

5

SETTLING TIME (

0

SETTLED TO 0.01%

501015

OUTPUT VOLTAGE STEP SIZE (V)

Figure 40. Settling Time vs. Step Size (G = 1)

20

03149-0-039

Rev. A | Page 12 of 20

AD8221

+

THEORY OF OPERATION

II

V

B

A2A1

C1 C2

+V

S

400Ω 400Ω

–V

Q1

S

R1 24.7kΩ 24.7kΩ

+V

S

–V

S

R2

+V

S

R

G

–V

S

Figure 42. Simplified Schematic

The AD8221 is a monolithic instrumentation amplifier based
on the classic 3-op amp topology. Input transistors Q1 and Q2
are biased at a fixed current, so that any differential input signal
will force the output voltages of A1 and A2 to change accor­dingly. A signal applied to the input creates a current through

, R1, and R2, such that the outputs of A1 and A2 deliver the

R

G

correct voltage. Topologically, Q1, A1, R1 and Q2, A2, R2 can be
viewed as precision current feedback amplifiers. The amplified
differential and common-mode signals are applied to a dif­ference amplifier that rejects the common-mode voltage but
amplifies the differential voltage. The difference amplifier
employs innovations that result in low output offset voltage as
well as low output offset voltage drift. Laser-trimmed resistors
allow for a highly accurate in-amp with gain error typically less
than 20 ppm and CMRR that exceeds 90 dB (G = 1).

Using superbeta input transistors and an I

compensation

B

scheme, the AD8221 offers extremely high input impedance,

, low IB drift, low IOS, low input bias current noise, and

low I

B

extremely low voltage noise of 8 nV/√Hz.

The transfer function of the AD8221 is

kΩ4.49

G

1+=

GR

Users can easily and accurately set the gain using a single,
standard resistor.

COMPENSATIONIB COMPENSATION

I

Q2

B

10kΩ

10kΩ

+V

S

+IN–IN

–V

S

10kΩ

10kΩ

A3

+V

S

OUTPUT

+V

–V

S

S

REF

–V

S

03149-0-042

Since the input amplifiers employ a current feedback architec­ture, the AD8221’s gain-bandwidth product increases with gain,
resulting in a system that does not suffer from the expected
bandwidth loss of voltage feedback architectures at higher gains.

In order to maintain precision even at low input levels, special
attention was given to the AD8221’s design and layout, resulting
in an in-amp whose performance satisfies the most demanding
applications.

A unique pinout enables the AD8221 to meet a CMRR
specification of 80 dB at 10 kHz (G = 1) and 110 dB at 1 kHz
(G = 1000). The balanced pinout, shown in Figure 43, reduces
the parasitics that had, in the past, adversely affected CMRR
performance. In addition, the new pinout simplifies board
layout because associated traces are grouped together. For
example, the gain setting resistor pins are adjacent to the inputs,
and the reference pin is next to the output.

1

–IN

2

R

G

3

R

G

4

IN

AD8221

TOP VIEW

Figure 43. Pinout Diagram

8

+V

S

7

V

OUT

6

REF

5

–V

S

03149-0-001

Rev. A | Page 13 of 20

AD8221

GAIN SELECTION

Placing a resistor across the RG terminals will set the AD8221’s
gain, which may be calculated by referring to Table 3 or by
using the gain equation

Grounding

The AD8221’s output voltage is developed with respect to the
potential on the reference terminal. Care should be taken to tie
REF to the appropriate “local ground.”

R

G

kΩ4.49

1

−=G

Table 3. Gains Achieved Using 1% Resistors

1% Std Table Value of RG (Ω) Calculated Gain

49.9 k 1.990

12.4 k 4.984

5.49 k 9.998

2.61 k 19.93

1.00 k 50.40
499 100.0
249 199.4
100 495.0

49.9 991.0

In mixed-signal environments, low level analog signals need to
be isolated from the noisy digital environment. Many ADCs
have separate analog and digital ground pins. Although it is
convenient to tie both grounds to a single ground plane, the
current traveling through the ground wires and PC board may
cause hundreds of millivolts of error. Therefore, separate analog
and digital ground returns should be used to minimize the
current flow from sensitive points to the system ground. An
example layout is shown in Figure 44 and Figure 45.

The AD8221 defaults to G = 1 when no gain resistor is used.
Gain accuracy is determined by the absolute tolerance of R

.

G

The TC of the external gain resistor will increase the gain drift
of the instrumentation amplifier. Gain error and gain drift are
kept to a minimum when the gain resistor is not used.

LAYOUT

Careful board layout maximizes system performance. Traces
from the gain setting resistor to the R
short as possible to minimize parasitic inductance. To ensure
the most accurate output, the trace from the REF pin should
either be connected to the AD8221’s local ground as shown in
Figure 47, or connected to a voltage that is referenced to the
AD8221’s local ground.

Common-Mode Rejection

One benefit of the AD8221’s high CMRR over frequency is that
it has greater immunity to disturbances such as line noise and
its associated harmonics than do typical in-amps. These,
typically, have CMRR fall-off at 200 Hz; common-mode filters
are often used to compensate for this shortcoming. The AD8221
is able to reject CMRR over a greater frequency range, reducing
the need for filtering.

pins should be kept as

G

Figure 44.Top Layer of the AD8221-EVAL

03149-0-051

A well implemented layout helps to maintain the AD8221’s high
CMRR over frequency. Input source impedance and capacitance
should be closely matched. In addition, source resistance and
capacitance should be placed as close to the inputs as
permissible.

Rev. A | Page 14 of 20

03149-0-052

Figure 45.Bottom Layer of the AD8221-EVAL

AD8221

f

REFERENCE TERMINAL

As shown in Figure 42, the reference terminal, REF, is at one end
of a 10 kΩ resistor. The instrumentation amplifier’s output is
referenced to the voltage on the REF terminal; this is useful
when the output signal needs to be offset to a precise midsupply
level. For example, a voltage source can be tied to the REF pin to
level-shift the output so that the AD8221 can interface with an
ADC. The allowable reference voltage range is a function of the
gain, input and supply voltage. The REF pin should not exceed
either +V

or –VS by more than 0.5 V.

S

For best performance, source impedance to the REF terminal
should be kept low, since parasitic resistance can adversely affect
CMRR and gain accuracy.

POWER SUPPLY REGULATION AND BYPASSING

A stable dc voltage should be used to power the instrumenta­tion amplifier. Noise on the supply pins may adversely affect
performance. Bypass capacitors should be used to decouple the
amplifier.

A 0.1 µF capacitor should be placed close to each supply pin. As
shown in Figure 47, a 10 µF tantalum capacitor may be used
further away from the part. In most cases, it may be shared by
other precision integrated circuits.

Figure 46

+V

S

0.1µF

+IN

AD8221

–IN

REF

0.1µF 10µ F

–V

S

Figure 47. Supply Decoupling,. REF and Output Referred to Local Ground

10µF

LOAD

V

OUT

03149-0-043

INPUT BIAS CURRENT RETURN PATH

The AD8221’s input bias current must have a return path to
common. When the source, such as a thermocouple, cannot
provide a return current path, one should be created, as shown
in Figure 48.

+V

S

AD8221

REF

–V

S

TRANSFORMER

+V

S

AD8221

REF

–V

S

THERMOCOUPLE

+V

S

C

HIGH-PASS

2πRC

1

=

Figure 48. Creating an I

R

C

CAPACITOR COUPLED

AD8221

R

–V

S

Path

BIAS

REF

03149-0-044

INPUT PROTECTION

All terminals of the AD8221 are protected against ESD1. In
addition, the input structure allows for dc overload conditions
below the negative supply, –Vs. The internal 400 Ω resistors
limit current in the event of a negative fault condition. However,
in the case of a dc overload voltage above the positive supply,
+Vs, a large current would flow directly through the ESD diode
to the positive rail. Therefore, an external resistor should be
used in series with the input to limit current for voltages above
+Vs. In either scenario, the AD8221 can safely handle a
continuous 6 mA current, I = V
and I = V

/(400 Ω + R

IN

) for negative overvoltage.

EXT

For applications where the AD8221 encounters extreme
overload voltages, as in cardiac defibrillators, external series
resistors and low leakage diode clamps such as BAV199Ls,
FJH1100s, or SP720s should be used.

for positive overvoltage

IN/REXT

1

1 kV—Human Body Model.

Rev. A | Page 15 of 20

AD8221

C

RF INTERFERENCE

RF rectification is often a problem when amplifiers are used in
applications where there are strong RF signals. The disturbance
may appear as a small dc offset voltage. High frequency signals
can be filtered with a low-pass R-C network placed at the input
of the instrumentation amplifier, as shown in Figure 49. The
filter limits the input signal bandwidth according to the
following relationship:

where

C

≥ 10CC.

D

R

4.02kΩ

R

4.02kΩ

Diff

R1

499Ω

=

CM

0.1µF

+IN

–IN

0.1µF

FilterFreq

FilterFreq

C

1nF

C

C

10nF

D

1nF

C

C

Figure 49. RFI Suppression

1

=

R

π2

+15V

AD8221

–15V

1

)2(π2

CD

CCR

+

C

10µF

V

OUT

REF

10µF

03149-0-045

CD affects the difference signal and CC affects the common­mode signal. Values of R and C
RFI. Mismatch between the R × C
R × C

at negative input will degrade the AD8221’s CMRR. By

C

using a value of C

one magnitude larger than CC, the effect of

D

should be chosen to minimize

C

at the positive input and the

C

the mismatch is reduced, and hence, performance is improved.

PRECISION STRAIN GAGE

The AD8221’s low offset and high CMRR over frequency make
it an excellent candidate for bridge measurements. As shown in
Figure 50, the bridge can be directly connected to the inputs of
the amplifier.

+5V

10µF 0.1µF

350Ω

350Ω

350Ω350Ω

Figure 50. Precision Strain Gage

R

+IN

–IN

+

AD8221

–

+2.5V

03149-0-049

Rev. A | Page 16 of 20

AD8221

10kΩ

10kΩ

+2.5V

R3 1kΩ

+12V

0.1µF

R1

R2

OP27

499Ω

0.1µF

–12V

R4 1kΩ

Figure 51. Interfacing to a Differential Input ADC

+12V

0.1µF

10µF

+IN

AD8221

–IN

0.1µF10µF

REF

–12V

CONDITIONING ±10 V SIGNALS FOR A +5 V DIFFERENTIAL INPUT ADC

There is a need in many applications to condition ±10 V signals.
However, many of today’s ADCs and digital ICs operate on
much lower, single-supply voltages. Furthermore, new ADCs
have differential inputs because they provide better common­mode rejection, noise immunity, and performance at low supply
voltages. Interfacing a
amplifier to a +5 V, differential ADC may be a challenge.
Interfacing the in-amp to the ADC requires attenuation and a
level shift. A solution is shown in Figure 51.

In this topology, an OP27 sets the AD8221’s reference voltage.
The in-amp’s output signal is taken across the OUT pin and the
REF pin. Two 1 kΩ resistors and a 499 Ω resistor attenuate the
±10 V signal to +4 V. An optional capacitor, C1, may serve as an
ant aliasing filter. An AD8022 is used to drive the ADC.

This topology has five benefits. In addition to level-shifting and
attenuation, very little noise is contributed to the system. Noise
from R1 and R2 is common to both of the ADC’s inputs and is
easily rejected. R5 adds a third of the dominant noise and there­fore makes a negligible contribution to the noise of the system.
The attenuator divides the noise from R3 and R4. Likewise, its
noise contribution is negligible. The fourth benefit of this inter­face circuit is that the AD8221’s acquisition time is reduced by a
factor of 2. With the help of the OP27, the AD8221 only needs
to deliver one-half of the full swing; therefore, signals can settle
more quickly. Lastly, the AD8022 settles quickly, which is helpful
because the shorter the settling time, the more bits that can be
resolved when the ADC acquires data. This configuration pro­vides attenuation, a level-shift, and a convenient interface with a
differential input ADC while maintaining performance.

±10 V, single-ended instrumentation

+12V

0.1µF

C1

470pF

R5

AD8022

(½)

0.1µF

–12V
+12V

0.1µF

AD8022

(½)

0.1µF

–12V

R6 27.4Ω

C2

220µF

R7 27.4Ω

220nF 10nF

+5V

10µF 0.1µ F22µF

+5V +5V

10nF

AV

V

DD

IN+

AD7723

V

IN–

AGND VGND REF1 REF2

V

V

IN

OUT

AD780

GND

DV

2.5V

DD

03149-0-047

AC-COUPLED INSTRUMENTATION AMPLIFIER

Measuring small signals that are in the amplifier’s noise or offset
can be a challenge. Figure 52 shows a circuit that can improve
the resolution of small ac signals. The large gain reduces the
referred input noise of the amplifier to 8 nV/√Hz. Thus, smaller
signals can be measured since the noise floor is lower. DC
offsets that would have been gained by 100 are eliminated from
the AD8221’s output by the integrator feedback network.

At low frequencies, the OP1177 forces the AD8221’s output to
0 V. Once a signal exceeds f
amplified input signal.

+V

S

0.1µF

+IN

R

–IN

0.1µF

AD8221

REF

–V

S

–V

+V

S

10µF10µF

Figure 52. AC-Coupled Circuit

499Ω

S

, the AD8221 outputs the

HIGH-PASS

f

=

HIGH-PASS

C 1µF

+V

S

0.1µF

OP1177

0.1µF
–V

S

1

2

π

RC

R

15.8kΩ

03149-0-048

Rev. A | Page 17 of 20

AD8221

Y

OUTLINE DIMENSIONS

3.00

BSC

85

3.00

BSC

PIN 1

0.65 BSC

0.15

0.00

0.38

0.22

COPLANARITY

0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA

4

SEATING
PLANE

4.90
BSC

1.10 MAX

0.23

0.08

8°
0°

0.80

0.60

0.40

Figure 53. 8-Lead Mini Small Outline Package [MSOP] (RM-8)

Dimensions shown in millimeters

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARIT

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

85

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

BSC

6.20 (0.2440)

5.80 (0.2284)

41

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

Figure 54. 8-Lead Shrink Small Outline Package [SOIC] (R-8)

× 45°

ORDERING GUIDE

1

Temperature

Rev. A | Page 18 of 20

Package
Option Branding

Model

Temperature Range for
Specified Performance

Operational
Range Package Description

AD8221AR –40°C to +85°C –40°C to 125°C 8-Lead SOIC R-8
AD8221AR-REEL –40°C to +85°C –40°C to 125°C 13" Tape and Reel R-8
AD8221AR-REEL7 –40°C to +85°C –40°C to 125°C 7" Tape and Reel R-8
AD8221ARM –40°C to +85°C –40°C to 125°C 8-Lead MSOP RM-8 JLA
AD8221ARM-REEL –40°C to +85°C –40°C to 125°C 13" Tape and Reel RM-8 JLA
AD8221ARM-REEL7 –40°C to +85°C –40°C to 125°C 7" Tape and Reel RM-8 JLA
AD8221BR –40°C to +85°C –40°C to 125°C 8-Lead SOIC R-8
AD8221BR-REEL –40°C to +85°C –40°C to 125°C 13" Tape and Reel R-8
AD8221BR-REEL7 –40°C to +85°C –40°C to 125°C 7" Tape and Reel R-8
AD8221-EVAL Evaluation Board

1

See Typical Performance Curves for expected operation from 85°C to 125°C.

AD8221

NOTES

Rev. A | Page 19 of 20

AD8221

NOTES

© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C03149–0–11/03(A)

Rev. A | Page 20 of 20